1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 39 #include <machine/pmc_mdep.h> 40 #include <machine/cpu.h> 41 42 static int armv7_npmcs; 43 44 struct armv7_event_code_map { 45 enum pmc_event pe_ev; 46 uint8_t pe_code; 47 }; 48 49 #define PMC_EV_CPU_CYCLES 0xFF 50 51 /* 52 * Per-processor information. 53 */ 54 struct armv7_cpu { 55 struct pmc_hw *pc_armv7pmcs; 56 }; 57 58 static struct armv7_cpu **armv7_pcpu; 59 60 /* 61 * Interrupt Enable Set Register 62 */ 63 static __inline void 64 armv7_interrupt_enable(uint32_t pmc) 65 { 66 uint32_t reg; 67 68 reg = (1 << pmc); 69 cp15_pminten_set(reg); 70 } 71 72 /* 73 * Interrupt Clear Set Register 74 */ 75 static __inline void 76 armv7_interrupt_disable(uint32_t pmc) 77 { 78 uint32_t reg; 79 80 reg = (1 << pmc); 81 cp15_pminten_clr(reg); 82 } 83 84 /* 85 * Counter Set Enable Register 86 */ 87 static __inline void 88 armv7_counter_enable(unsigned int pmc) 89 { 90 uint32_t reg; 91 92 reg = (1 << pmc); 93 cp15_pmcnten_set(reg); 94 } 95 96 /* 97 * Counter Clear Enable Register 98 */ 99 static __inline void 100 armv7_counter_disable(unsigned int pmc) 101 { 102 uint32_t reg; 103 104 reg = (1 << pmc); 105 cp15_pmcnten_clr(reg); 106 } 107 108 /* 109 * Performance Count Register N 110 */ 111 static uint32_t 112 armv7_pmcn_read(unsigned int pmc) 113 { 114 115 KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 116 117 cp15_pmselr_set(pmc); 118 return (cp15_pmxevcntr_get()); 119 } 120 121 static uint32_t 122 armv7_pmcn_write(unsigned int pmc, uint32_t reg) 123 { 124 125 KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 126 127 cp15_pmselr_set(pmc); 128 cp15_pmxevcntr_set(reg); 129 130 return (reg); 131 } 132 133 static int 134 armv7_allocate_pmc(int cpu, int ri, struct pmc *pm, 135 const struct pmc_op_pmcallocate *a) 136 { 137 struct armv7_cpu *pac; 138 enum pmc_event pe; 139 uint32_t config; 140 uint32_t caps; 141 142 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 143 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 144 KASSERT(ri >= 0 && ri < armv7_npmcs, 145 ("[armv7,%d] illegal row index %d", __LINE__, ri)); 146 147 pac = armv7_pcpu[cpu]; 148 149 caps = a->pm_caps; 150 if (a->pm_class != PMC_CLASS_ARMV7) 151 return (EINVAL); 152 pe = a->pm_ev; 153 154 config = (pe & EVENT_ID_MASK); 155 pm->pm_md.pm_armv7.pm_armv7_evsel = config; 156 157 PMCDBG2(MDP, ALL, 2, "armv7-allocate ri=%d -> config=0x%x", ri, config); 158 159 return 0; 160 } 161 162 163 static int 164 armv7_read_pmc(int cpu, int ri, pmc_value_t *v) 165 { 166 pmc_value_t tmp; 167 struct pmc *pm; 168 169 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 170 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 171 KASSERT(ri >= 0 && ri < armv7_npmcs, 172 ("[armv7,%d] illegal row index %d", __LINE__, ri)); 173 174 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 175 176 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 177 tmp = (uint32_t)cp15_pmccntr_get(); 178 else 179 tmp = armv7_pmcn_read(ri); 180 tmp += 0x100000000llu * pm->pm_overflowcnt; 181 182 PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp); 183 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 184 *v = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 185 else 186 *v = tmp; 187 188 return 0; 189 } 190 191 static int 192 armv7_write_pmc(int cpu, int ri, pmc_value_t v) 193 { 194 struct pmc *pm; 195 196 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 197 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 198 KASSERT(ri >= 0 && ri < armv7_npmcs, 199 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 200 201 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 202 203 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 204 v = ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 205 206 PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v); 207 208 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 209 cp15_pmccntr_set(v); 210 else 211 armv7_pmcn_write(ri, v); 212 213 return 0; 214 } 215 216 static int 217 armv7_config_pmc(int cpu, int ri, struct pmc *pm) 218 { 219 struct pmc_hw *phw; 220 221 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 222 223 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 224 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 225 KASSERT(ri >= 0 && ri < armv7_npmcs, 226 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 227 228 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 229 230 KASSERT(pm == NULL || phw->phw_pmc == NULL, 231 ("[armv7,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 232 __LINE__, pm, phw->phw_pmc)); 233 234 phw->phw_pmc = pm; 235 236 return 0; 237 } 238 239 static int 240 armv7_start_pmc(int cpu, int ri) 241 { 242 struct pmc_hw *phw; 243 uint32_t config; 244 struct pmc *pm; 245 246 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 247 pm = phw->phw_pmc; 248 config = pm->pm_md.pm_armv7.pm_armv7_evsel; 249 250 pm->pm_overflowcnt = 0; 251 252 /* 253 * Configure the event selection. 254 */ 255 if (config != PMC_EV_CPU_CYCLES) { 256 cp15_pmselr_set(ri); 257 cp15_pmxevtyper_set(config); 258 } else 259 ri = 31; 260 261 /* 262 * Enable the PMC. 263 */ 264 armv7_interrupt_enable(ri); 265 armv7_counter_enable(ri); 266 267 return 0; 268 } 269 270 static int 271 armv7_stop_pmc(int cpu, int ri) 272 { 273 struct pmc_hw *phw; 274 struct pmc *pm; 275 uint32_t config; 276 277 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 278 pm = phw->phw_pmc; 279 config = pm->pm_md.pm_armv7.pm_armv7_evsel; 280 if (config == PMC_EV_CPU_CYCLES) 281 ri = 31; 282 283 /* 284 * Disable the PMCs. 285 */ 286 armv7_counter_disable(ri); 287 armv7_interrupt_disable(ri); 288 289 return 0; 290 } 291 292 static int 293 armv7_release_pmc(int cpu, int ri, struct pmc *pmc) 294 { 295 struct pmc_hw *phw; 296 297 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 298 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 299 KASSERT(ri >= 0 && ri < armv7_npmcs, 300 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 301 302 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 303 KASSERT(phw->phw_pmc == NULL, 304 ("[armv7,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 305 306 return 0; 307 } 308 309 static int 310 armv7_intr(struct trapframe *tf) 311 { 312 struct armv7_cpu *pc; 313 int retval, ri; 314 struct pmc *pm; 315 int error; 316 int reg, cpu; 317 318 cpu = curcpu; 319 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 320 ("[armv7,%d] CPU %d out of range", __LINE__, cpu)); 321 322 retval = 0; 323 pc = armv7_pcpu[cpu]; 324 325 for (ri = 0; ri < armv7_npmcs; ri++) { 326 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 327 if (pm == NULL) 328 continue; 329 330 /* Check if counter has overflowed */ 331 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 332 reg = (1 << 31); 333 else 334 reg = (1 << ri); 335 336 if ((cp15_pmovsr_get() & reg) == 0) { 337 continue; 338 } 339 340 /* Clear Overflow Flag */ 341 cp15_pmovsr_set(reg); 342 343 retval = 1; /* Found an interrupting PMC. */ 344 345 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 346 pm->pm_overflowcnt += 1; 347 continue; 348 } 349 if (pm->pm_state != PMC_STATE_RUNNING) 350 continue; 351 352 error = pmc_process_interrupt(PMC_HR, pm, tf); 353 if (error) 354 armv7_stop_pmc(cpu, ri); 355 356 /* Reload sampling count */ 357 armv7_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount); 358 } 359 360 return (retval); 361 } 362 363 static int 364 armv7_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 365 { 366 char armv7_name[PMC_NAME_MAX]; 367 struct pmc_hw *phw; 368 int error; 369 370 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 371 ("[armv7,%d], illegal CPU %d", __LINE__, cpu)); 372 KASSERT(ri >= 0 && ri < armv7_npmcs, 373 ("[armv7,%d] row-index %d out of range", __LINE__, ri)); 374 375 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 376 snprintf(armv7_name, sizeof(armv7_name), "ARMV7-%d", ri); 377 if ((error = copystr(armv7_name, pi->pm_name, PMC_NAME_MAX, 378 NULL)) != 0) 379 return error; 380 pi->pm_class = PMC_CLASS_ARMV7; 381 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 382 pi->pm_enabled = TRUE; 383 *ppmc = phw->phw_pmc; 384 } else { 385 pi->pm_enabled = FALSE; 386 *ppmc = NULL; 387 } 388 389 return (0); 390 } 391 392 static int 393 armv7_get_config(int cpu, int ri, struct pmc **ppm) 394 { 395 396 *ppm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 397 398 return 0; 399 } 400 401 /* 402 * XXX don't know what we should do here. 403 */ 404 static int 405 armv7_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 406 { 407 408 return 0; 409 } 410 411 static int 412 armv7_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 413 { 414 415 return 0; 416 } 417 418 static int 419 armv7_pcpu_init(struct pmc_mdep *md, int cpu) 420 { 421 struct armv7_cpu *pac; 422 struct pmc_hw *phw; 423 struct pmc_cpu *pc; 424 uint32_t pmnc; 425 int first_ri; 426 int i; 427 428 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 429 ("[armv7,%d] wrong cpu number %d", __LINE__, cpu)); 430 PMCDBG1(MDP, INI, 1, "armv7-init cpu=%d", cpu); 431 432 armv7_pcpu[cpu] = pac = malloc(sizeof(struct armv7_cpu), M_PMC, 433 M_WAITOK|M_ZERO); 434 435 pac->pc_armv7pmcs = malloc(sizeof(struct pmc_hw) * armv7_npmcs, 436 M_PMC, M_WAITOK|M_ZERO); 437 pc = pmc_pcpu[cpu]; 438 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7].pcd_ri; 439 KASSERT(pc != NULL, ("[armv7,%d] NULL per-cpu pointer", __LINE__)); 440 441 for (i = 0, phw = pac->pc_armv7pmcs; i < armv7_npmcs; i++, phw++) { 442 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 443 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 444 phw->phw_pmc = NULL; 445 pc->pc_hwpmcs[i + first_ri] = phw; 446 } 447 448 pmnc = 0xffffffff; 449 cp15_pmcnten_clr(pmnc); 450 cp15_pminten_clr(pmnc); 451 cp15_pmovsr_set(pmnc); 452 453 /* Enable unit */ 454 pmnc = cp15_pmcr_get(); 455 pmnc |= ARMV7_PMNC_ENABLE; 456 cp15_pmcr_set(pmnc); 457 458 return 0; 459 } 460 461 static int 462 armv7_pcpu_fini(struct pmc_mdep *md, int cpu) 463 { 464 uint32_t pmnc; 465 466 pmnc = cp15_pmcr_get(); 467 pmnc &= ~ARMV7_PMNC_ENABLE; 468 cp15_pmcr_set(pmnc); 469 470 pmnc = 0xffffffff; 471 cp15_pmcnten_clr(pmnc); 472 cp15_pminten_clr(pmnc); 473 cp15_pmovsr_set(pmnc); 474 475 return 0; 476 } 477 478 struct pmc_mdep * 479 pmc_armv7_initialize() 480 { 481 struct pmc_mdep *pmc_mdep; 482 struct pmc_classdep *pcd; 483 int idcode; 484 int reg; 485 486 reg = cp15_pmcr_get(); 487 armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \ 488 ARMV7_PMNC_N_MASK; 489 idcode = (reg & ARMV7_IDCODE_MASK) >> ARMV7_IDCODE_SHIFT; 490 491 PMCDBG1(MDP, INI, 1, "armv7-init npmcs=%d", armv7_npmcs); 492 493 /* 494 * Allocate space for pointers to PMC HW descriptors and for 495 * the MDEP structure used by MI code. 496 */ 497 armv7_pcpu = malloc(sizeof(struct armv7_cpu *) * pmc_cpu_max(), 498 M_PMC, M_WAITOK | M_ZERO); 499 500 /* Just one class */ 501 pmc_mdep = pmc_mdep_alloc(1); 502 503 switch (idcode) { 504 case ARMV7_IDCODE_CORTEX_A9: 505 pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A9; 506 break; 507 default: 508 case ARMV7_IDCODE_CORTEX_A8: 509 /* 510 * On A8 we implemented common events only, 511 * so use it for the rest of machines. 512 */ 513 pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A8; 514 break; 515 } 516 517 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7]; 518 pcd->pcd_caps = ARMV7_PMC_CAPS; 519 pcd->pcd_class = PMC_CLASS_ARMV7; 520 pcd->pcd_num = armv7_npmcs; 521 pcd->pcd_ri = pmc_mdep->pmd_npmc; 522 pcd->pcd_width = 32; 523 524 pcd->pcd_allocate_pmc = armv7_allocate_pmc; 525 pcd->pcd_config_pmc = armv7_config_pmc; 526 pcd->pcd_pcpu_fini = armv7_pcpu_fini; 527 pcd->pcd_pcpu_init = armv7_pcpu_init; 528 pcd->pcd_describe = armv7_describe; 529 pcd->pcd_get_config = armv7_get_config; 530 pcd->pcd_read_pmc = armv7_read_pmc; 531 pcd->pcd_release_pmc = armv7_release_pmc; 532 pcd->pcd_start_pmc = armv7_start_pmc; 533 pcd->pcd_stop_pmc = armv7_stop_pmc; 534 pcd->pcd_write_pmc = armv7_write_pmc; 535 536 pmc_mdep->pmd_intr = armv7_intr; 537 pmc_mdep->pmd_switch_in = armv7_switch_in; 538 pmc_mdep->pmd_switch_out = armv7_switch_out; 539 540 pmc_mdep->pmd_npmc += armv7_npmcs; 541 542 return (pmc_mdep); 543 } 544 545 void 546 pmc_armv7_finalize(struct pmc_mdep *md) 547 { 548 549 } 550