1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #if (__FreeBSD_version >= 1100000) 42 #include <x86/apicvar.h> 43 #else 44 #include <machine/apicvar.h> 45 #endif 46 #include <machine/cpu.h> 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #define CORE_CPUID_REQUEST 0xA 52 #define CORE_CPUID_REQUEST_SIZE 0x4 53 #define CORE_CPUID_EAX 0x0 54 #define CORE_CPUID_EBX 0x1 55 #define CORE_CPUID_ECX 0x2 56 #define CORE_CPUID_EDX 0x3 57 58 #define IAF_PMC_CAPS \ 59 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 60 PMC_CAP_USER | PMC_CAP_SYSTEM) 61 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 62 63 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 64 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 65 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 66 67 #define EV_IS_NOTARCH 0 68 #define EV_IS_ARCH_SUPP 1 69 #define EV_IS_ARCH_NOTSUPP -1 70 71 /* 72 * "Architectural" events defined by Intel. The values of these 73 * symbols correspond to positions in the bitmask returned by 74 * the CPUID.0AH instruction. 75 */ 76 enum core_arch_events { 77 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 78 CORE_AE_BRANCH_MISSES_RETIRED = 6, 79 CORE_AE_INSTRUCTION_RETIRED = 1, 80 CORE_AE_LLC_MISSES = 4, 81 CORE_AE_LLC_REFERENCE = 3, 82 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 83 CORE_AE_UNHALTED_CORE_CYCLES = 0 84 }; 85 86 static enum pmc_cputype core_cputype; 87 88 struct core_cpu { 89 volatile uint32_t pc_resync; 90 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 91 volatile uint64_t pc_globalctrl; /* Global control register. */ 92 struct pmc_hw pc_corepmcs[]; 93 }; 94 95 static struct core_cpu **core_pcpu; 96 97 static uint32_t core_architectural_events; 98 static uint64_t core_pmcmask; 99 100 static int core_iaf_ri; /* relative index of fixed counters */ 101 static int core_iaf_width; 102 static int core_iaf_npmc; 103 104 static int core_iap_width; 105 static int core_iap_npmc; 106 107 static int 108 core_pcpu_noop(struct pmc_mdep *md, int cpu) 109 { 110 (void) md; 111 (void) cpu; 112 return (0); 113 } 114 115 static int 116 core_pcpu_init(struct pmc_mdep *md, int cpu) 117 { 118 struct pmc_cpu *pc; 119 struct core_cpu *cc; 120 struct pmc_hw *phw; 121 int core_ri, n, npmc; 122 123 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 124 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 125 126 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 127 128 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 129 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 130 131 if (core_cputype != PMC_CPU_INTEL_CORE) 132 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 133 134 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 135 M_PMC, M_WAITOK | M_ZERO); 136 137 core_pcpu[cpu] = cc; 138 pc = pmc_pcpu[cpu]; 139 140 KASSERT(pc != NULL && cc != NULL, 141 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 142 143 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 144 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 145 PMC_PHW_CPU_TO_STATE(cpu) | 146 PMC_PHW_INDEX_TO_STATE(n + core_ri); 147 phw->phw_pmc = NULL; 148 pc->pc_hwpmcs[n + core_ri] = phw; 149 } 150 151 return (0); 152 } 153 154 static int 155 core_pcpu_fini(struct pmc_mdep *md, int cpu) 156 { 157 int core_ri, n, npmc; 158 struct pmc_cpu *pc; 159 struct core_cpu *cc; 160 uint64_t msr = 0; 161 162 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 163 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 164 165 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 166 167 if ((cc = core_pcpu[cpu]) == NULL) 168 return (0); 169 170 core_pcpu[cpu] = NULL; 171 172 pc = pmc_pcpu[cpu]; 173 174 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 175 cpu)); 176 177 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 178 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 179 180 for (n = 0; n < npmc; n++) { 181 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 182 wrmsr(IAP_EVSEL0 + n, msr); 183 } 184 185 if (core_cputype != PMC_CPU_INTEL_CORE) { 186 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 187 wrmsr(IAF_CTRL, msr); 188 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 189 } 190 191 for (n = 0; n < npmc; n++) 192 pc->pc_hwpmcs[n + core_ri] = NULL; 193 194 free(cc, M_PMC); 195 196 return (0); 197 } 198 199 /* 200 * Fixed function counters. 201 */ 202 203 static pmc_value_t 204 iaf_perfctr_value_to_reload_count(pmc_value_t v) 205 { 206 v &= (1ULL << core_iaf_width) - 1; 207 return (1ULL << core_iaf_width) - v; 208 } 209 210 static pmc_value_t 211 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 212 { 213 return (1ULL << core_iaf_width) - rlc; 214 } 215 216 static int 217 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 218 const struct pmc_op_pmcallocate *a) 219 { 220 enum pmc_event ev; 221 uint32_t caps, flags, validflags; 222 223 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 224 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 225 226 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 227 228 if (ri < 0 || ri > core_iaf_npmc) 229 return (EINVAL); 230 231 caps = a->pm_caps; 232 233 if (a->pm_class != PMC_CLASS_IAF || 234 (caps & IAF_PMC_CAPS) != caps) 235 return (EINVAL); 236 237 ev = pm->pm_event; 238 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 239 return (EINVAL); 240 241 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 242 return (EINVAL); 243 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 244 return (EINVAL); 245 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 246 return (EINVAL); 247 248 flags = a->pm_md.pm_iaf.pm_iaf_flags; 249 250 validflags = IAF_MASK; 251 252 if (core_cputype != PMC_CPU_INTEL_ATOM && 253 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 254 validflags &= ~IAF_ANY; 255 256 if ((flags & ~validflags) != 0) 257 return (EINVAL); 258 259 if (caps & PMC_CAP_INTERRUPT) 260 flags |= IAF_PMI; 261 if (caps & PMC_CAP_SYSTEM) 262 flags |= IAF_OS; 263 if (caps & PMC_CAP_USER) 264 flags |= IAF_USR; 265 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 266 flags |= (IAF_OS | IAF_USR); 267 268 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 269 270 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 271 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 272 273 return (0); 274 } 275 276 static int 277 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 278 { 279 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 280 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 281 282 KASSERT(ri >= 0 && ri < core_iaf_npmc, 283 ("[core,%d] illegal row-index %d", __LINE__, ri)); 284 285 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 286 287 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 288 cpu)); 289 290 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 291 292 return (0); 293 } 294 295 static int 296 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 297 { 298 int error; 299 struct pmc_hw *phw; 300 char iaf_name[PMC_NAME_MAX]; 301 302 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 303 304 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 305 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 306 NULL)) != 0) 307 return (error); 308 309 pi->pm_class = PMC_CLASS_IAF; 310 311 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 312 pi->pm_enabled = TRUE; 313 *ppmc = phw->phw_pmc; 314 } else { 315 pi->pm_enabled = FALSE; 316 *ppmc = NULL; 317 } 318 319 return (0); 320 } 321 322 static int 323 iaf_get_config(int cpu, int ri, struct pmc **ppm) 324 { 325 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 326 327 return (0); 328 } 329 330 static int 331 iaf_get_msr(int ri, uint32_t *msr) 332 { 333 KASSERT(ri >= 0 && ri < core_iaf_npmc, 334 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 335 336 *msr = IAF_RI_TO_MSR(ri); 337 338 return (0); 339 } 340 341 static int 342 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 343 { 344 struct pmc *pm; 345 pmc_value_t tmp; 346 347 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 348 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 349 KASSERT(ri >= 0 && ri < core_iaf_npmc, 350 ("[core,%d] illegal row-index %d", __LINE__, ri)); 351 352 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 353 354 KASSERT(pm, 355 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 356 ri, ri + core_iaf_ri)); 357 358 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 359 360 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 361 *v = iaf_perfctr_value_to_reload_count(tmp); 362 else 363 *v = tmp; 364 365 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 366 IAF_RI_TO_MSR(ri), *v); 367 368 return (0); 369 } 370 371 static int 372 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 373 { 374 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 375 376 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 377 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 378 KASSERT(ri >= 0 && ri < core_iaf_npmc, 379 ("[core,%d] illegal row-index %d", __LINE__, ri)); 380 381 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 382 ("[core,%d] PHW pmc non-NULL", __LINE__)); 383 384 return (0); 385 } 386 387 static int 388 iaf_start_pmc(int cpu, int ri) 389 { 390 struct pmc *pm; 391 struct core_cpu *iafc; 392 uint64_t msr = 0; 393 394 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 395 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 396 KASSERT(ri >= 0 && ri < core_iaf_npmc, 397 ("[core,%d] illegal row-index %d", __LINE__, ri)); 398 399 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 400 401 iafc = core_pcpu[cpu]; 402 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 403 404 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 405 406 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 407 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 408 409 do { 410 iafc->pc_resync = 0; 411 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 412 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 413 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 414 IAF_GLOBAL_CTRL_MASK)); 415 } while (iafc->pc_resync != 0); 416 417 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 418 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 419 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 420 421 return (0); 422 } 423 424 static int 425 iaf_stop_pmc(int cpu, int ri) 426 { 427 uint32_t fc; 428 struct core_cpu *iafc; 429 uint64_t msr = 0; 430 431 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 432 433 iafc = core_pcpu[cpu]; 434 435 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 436 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 437 KASSERT(ri >= 0 && ri < core_iaf_npmc, 438 ("[core,%d] illegal row-index %d", __LINE__, ri)); 439 440 fc = (IAF_MASK << (ri * 4)); 441 442 if (core_cputype != PMC_CPU_INTEL_ATOM && 443 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 444 fc &= ~IAF_ANY; 445 446 iafc->pc_iafctrl &= ~fc; 447 448 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 449 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 450 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 451 452 do { 453 iafc->pc_resync = 0; 454 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 455 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 456 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 457 IAF_GLOBAL_CTRL_MASK)); 458 } while (iafc->pc_resync != 0); 459 460 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 461 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 462 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 463 464 return (0); 465 } 466 467 static int 468 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 469 { 470 struct core_cpu *cc; 471 struct pmc *pm; 472 uint64_t msr; 473 474 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 475 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 476 KASSERT(ri >= 0 && ri < core_iaf_npmc, 477 ("[core,%d] illegal row-index %d", __LINE__, ri)); 478 479 cc = core_pcpu[cpu]; 480 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 481 482 KASSERT(pm, 483 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 484 485 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 486 v = iaf_reload_count_to_perfctr_value(v); 487 488 /* Turn off fixed counters */ 489 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 490 wrmsr(IAF_CTRL, msr); 491 492 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 493 494 /* Turn on fixed counters */ 495 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 496 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 497 498 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 499 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 500 (uintmax_t) rdmsr(IAF_CTRL), 501 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 502 503 return (0); 504 } 505 506 507 static void 508 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 509 { 510 struct pmc_classdep *pcd; 511 512 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 513 514 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 515 516 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 517 518 pcd->pcd_caps = IAF_PMC_CAPS; 519 pcd->pcd_class = PMC_CLASS_IAF; 520 pcd->pcd_num = npmc; 521 pcd->pcd_ri = md->pmd_npmc; 522 pcd->pcd_width = pmcwidth; 523 524 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 525 pcd->pcd_config_pmc = iaf_config_pmc; 526 pcd->pcd_describe = iaf_describe; 527 pcd->pcd_get_config = iaf_get_config; 528 pcd->pcd_get_msr = iaf_get_msr; 529 pcd->pcd_pcpu_fini = core_pcpu_noop; 530 pcd->pcd_pcpu_init = core_pcpu_noop; 531 pcd->pcd_read_pmc = iaf_read_pmc; 532 pcd->pcd_release_pmc = iaf_release_pmc; 533 pcd->pcd_start_pmc = iaf_start_pmc; 534 pcd->pcd_stop_pmc = iaf_stop_pmc; 535 pcd->pcd_write_pmc = iaf_write_pmc; 536 537 md->pmd_npmc += npmc; 538 } 539 540 /* 541 * Intel programmable PMCs. 542 */ 543 544 /* 545 * Event descriptor tables. 546 * 547 * For each event id, we track: 548 * 549 * 1. The CPUs that the event is valid for. 550 * 551 * 2. If the event uses a fixed UMASK, the value of the umask field. 552 * If the event doesn't use a fixed UMASK, a mask of legal bits 553 * to check against. 554 */ 555 556 struct iap_event_descr { 557 enum pmc_event iap_ev; 558 unsigned char iap_evcode; 559 unsigned char iap_umask; 560 unsigned int iap_flags; 561 }; 562 563 #define IAP_F_CC (1 << 0) /* CPU: Core */ 564 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 565 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 566 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 567 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 568 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 569 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 570 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 571 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 572 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 573 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 574 #define IAP_F_HW (1 << 10) /* CPU: Haswell */ 575 #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 576 #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ 577 #define IAP_F_BW (1 << 13) /* CPU: Broadwell */ 578 #define IAP_F_FM (1 << 14) /* Fixed mask */ 579 580 #define IAP_F_ALLCPUSCORE2 \ 581 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 582 583 /* Sub fields of UMASK that this event supports. */ 584 #define IAP_M_CORE (1 << 0) /* Core specificity */ 585 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 586 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 587 #define IAP_M_MESI (1 << 3) /* MESI */ 588 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 589 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 590 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 591 592 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 593 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 594 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 595 #define IAP_F_MESI (0xF << 8) /* MESI */ 596 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 597 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 598 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 599 600 #define IAP_PREFETCH_RESERVED (0x2 << 12) 601 #define IAP_CORE_THIS (0x1 << 14) 602 #define IAP_CORE_ALL (0x3 << 14) 603 #define IAP_F_CMASK 0xFF000000 604 605 static struct iap_event_descr iap_events[] = { 606 #undef IAPDESCR 607 #define IAPDESCR(N,EV,UM,FLAGS) { \ 608 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 609 .iap_evcode = (EV), \ 610 .iap_umask = (UM), \ 611 .iap_flags = (FLAGS) \ 612 } 613 614 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 615 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 616 617 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 618 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 619 IAP_F_SBX | IAP_F_CAS), 620 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 621 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 622 IAP_F_CAS | IAP_F_HWX), 623 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 624 IAP_F_CAS), 625 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 626 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 627 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 628 IAP_F_SBX | IAP_F_CAS), 629 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 630 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_CAS), 631 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_CAS), 632 633 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 634 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 635 IAP_F_CAS), 636 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 637 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_CAS), 638 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 639 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 640 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_CAS), 641 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_CAS), 642 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_CAS), 643 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_CAS), 644 645 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 646 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 647 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 648 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 649 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 650 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 651 652 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 653 IAP_F_CC2E | IAP_F_CA), 654 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 655 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 656 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 657 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 658 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 659 660 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 661 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 662 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 663 IAP_F_HW | IAP_F_HWX), 664 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 665 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 666 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 667 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 668 IAP_F_SBX), 669 670 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 671 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 672 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 673 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 674 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 675 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 676 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 677 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 678 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 679 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 680 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 681 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 682 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 683 IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 684 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 685 IAP_F_HWX), 686 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 687 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 688 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 689 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 690 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 691 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 692 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_IB | IAP_F_IBX), 693 694 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 695 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 696 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 697 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 698 699 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 700 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 701 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 702 703 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 704 IAP_F_WM), 705 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 706 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 707 708 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | 709 IAP_F_IB | IAP_F_IBX | IAP_F_HWX), 710 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 711 712 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 713 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 714 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 715 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 716 IAP_F_HWX), 717 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 718 IAP_F_HWX), 719 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 720 IAP_F_HWX), 721 722 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 723 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 724 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 725 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 726 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 727 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 728 729 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 730 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 731 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), 732 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 733 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 734 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 735 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 736 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 737 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 738 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 739 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 740 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 741 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 742 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 743 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 744 745 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 746 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 747 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 748 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 749 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 750 751 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 752 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 754 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 755 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 756 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 757 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 759 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 760 761 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 762 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 763 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 764 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 765 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 766 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 767 768 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 769 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 770 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 771 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 772 773 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 774 IAP_F_SBX), 775 776 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 777 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 778 779 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 780 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 781 IAP_F_I7 | IAP_F_WM), 782 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 783 784 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 785 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 786 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 787 788 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 789 790 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 791 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 792 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 793 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 794 795 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 796 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 797 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 798 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 799 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 800 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 801 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 802 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 803 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 804 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 805 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 806 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 807 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 808 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 809 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 810 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 811 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 812 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 813 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 814 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 815 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 816 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 817 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 818 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 819 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 820 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 821 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 822 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 823 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 824 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 825 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 826 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 827 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 828 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 829 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 830 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 831 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 832 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 833 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 834 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 835 IAP_F_HWX), 836 837 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 838 839 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 840 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 841 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 842 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 843 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 844 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 845 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 846 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 847 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 848 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 849 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 850 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 851 852 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 853 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 854 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 855 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 856 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 857 IAP_F_SBX), 858 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 859 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 860 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 861 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 862 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 863 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 864 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 865 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 866 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 867 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 868 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 869 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 870 871 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 872 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 873 IAP_F_SBX | IAP_F_IBX), 874 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 875 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 876 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 877 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 878 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 879 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 880 IAP_F_SBX | IAP_F_IBX), 881 882 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 883 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 884 IAP_F_CA | IAP_F_CC2), 885 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 886 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 887 888 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 889 IAP_F_ALLCPUSCORE2), 890 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 891 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 892 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 893 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 894 IAP_F_CAS | IAP_F_HWX), 895 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 896 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 897 IAP_F_CAS | IAP_F_HWX), 898 899 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 900 IAP_F_ALLCPUSCORE2), 901 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_CAS), 902 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_CAS), 903 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 904 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 905 906 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 907 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 908 909 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 910 911 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 912 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 913 IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 914 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 915 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 916 IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 917 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 918 919 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 920 921 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 922 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 923 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 924 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 925 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 926 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 927 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 928 929 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 930 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 931 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 932 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 933 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 934 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 935 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 936 937 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 938 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 939 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 940 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 941 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 942 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 943 944 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 945 IAP_F_I7), 946 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 947 IAP_F_CC2 | IAP_F_I7), 948 949 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 950 951 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 952 953 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 954 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 955 956 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 957 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 958 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 959 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 960 961 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 962 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 963 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 964 IAP_F_HW | IAP_F_HWX), 965 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 966 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 967 IAP_F_HW | IAP_F_HWX), 968 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 969 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 970 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 971 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 972 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 973 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 974 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 975 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 976 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | 977 IAP_F_HWX), 978 979 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 980 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 981 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 982 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 983 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 984 985 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 986 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 987 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 988 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 989 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 990 991 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 992 993 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 994 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 995 IAP_F_SB | IAP_F_SBX), 996 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 997 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 998 999 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 1000 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 1001 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 1002 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 1003 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 1004 1005 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1006 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1007 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1008 IAP_F_SB | IAP_F_SBX), 1009 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1010 IAP_F_SB | IAP_F_SBX), 1011 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1012 IAP_F_SB | IAP_F_SBX), 1013 1014 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1015 1016 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1017 1018 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1019 IAP_F_HWX), 1020 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1021 IAP_F_HWX), 1022 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1023 IAP_F_HWX), 1024 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1025 IAP_F_HWX), 1026 1027 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1028 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1029 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1030 1031 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1032 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1033 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1034 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1035 1036 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1037 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1038 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1039 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1040 1041 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1042 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1043 1044 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ 1045 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX | IAP_F_IB), 1046 1047 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1048 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1049 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1050 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1051 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1052 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1053 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1054 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1055 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1056 1057 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1058 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1059 1060 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1061 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1062 1063 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1064 IAP_F_CA | IAP_F_CC2), 1065 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1066 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1067 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1068 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1069 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1070 1071 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1072 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1073 1074 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1075 IAP_F_CA | IAP_F_CC2), 1076 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1077 1078 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1079 1080 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1081 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1082 1083 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1084 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1085 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1086 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1087 1088 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1089 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1090 1091 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1092 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1093 1094 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1095 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1096 1097 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1098 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1099 1100 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1101 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1102 1103 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1104 IAP_F_CA | IAP_F_CC2), 1105 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1106 1107 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1108 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1109 1110 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1111 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1112 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1113 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1114 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1115 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1116 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1117 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1118 1119 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1120 1121 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1122 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1123 1124 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1125 1126 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1127 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1128 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1129 IAP_F_HWX), 1130 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1131 IAP_F_HWX), 1132 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1133 IAP_F_HWX), 1134 1135 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1136 1137 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1138 1139 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1140 1141 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1142 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1143 1144 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1145 1146 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1147 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1148 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1149 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1150 IAP_F_CAS | IAP_F_HWX), 1151 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1152 IAP_F_WM | IAP_F_CAS), 1153 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX), 1154 1155 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1156 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1157 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1158 1159 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1160 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1161 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1162 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1163 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1164 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1165 1166 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1167 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1168 1169 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1170 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1171 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1172 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1173 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1174 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1175 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1176 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1177 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1178 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1179 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1180 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1181 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1182 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1183 1184 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1185 1186 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1187 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1188 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1189 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1190 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1191 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1192 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1193 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1194 1195 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1196 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1197 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1198 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1199 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1200 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1201 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1202 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1203 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1204 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1205 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1206 IAPDESCR(88H_41H, 0x88, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1207 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1208 IAPDESCR(88H_81H, 0x88, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1209 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1210 IAPDESCR(88H_82H, 0x88, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1211 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1212 IAPDESCR(88H_84H, 0x88, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1213 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1214 IAPDESCR(88H_88H, 0x88, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1215 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1216 IAPDESCR(88H_90H, 0x88, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1217 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1218 IAPDESCR(88H_A0H, 0x88, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1219 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1220 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1221 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1222 1223 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1224 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1225 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1226 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1227 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1228 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1229 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1230 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1231 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1232 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1233 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1234 IAPDESCR(89H_41H, 0x89, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1235 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1236 IAPDESCR(89H_81H, 0x89, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1237 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1238 IAPDESCR(89H_82H, 0x89, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1239 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1240 IAPDESCR(89H_84H, 0x89, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1241 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1242 IAPDESCR(89H_88H, 0x89, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1243 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1244 IAPDESCR(89H_90H, 0x89, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1245 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1246 IAPDESCR(89H_A0H, 0x89, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1247 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1248 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1249 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1250 1251 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1252 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1253 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1254 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1255 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1256 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1257 1258 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1259 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1260 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1261 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1262 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1263 1264 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1265 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1266 1267 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1268 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1269 1270 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1271 1272 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1273 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1274 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1275 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1276 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1277 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1278 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1279 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1280 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1281 IAP_F_SBX | IAP_F_IBX), 1282 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1283 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1284 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1285 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1286 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1287 IAP_F_SBX | IAP_F_IBX), 1288 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1289 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1290 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1291 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1292 1293 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1294 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1295 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1296 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1297 IAP_F_SB | IAP_F_SBX), 1298 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1299 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1300 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1301 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1302 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1303 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1304 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1305 IAP_F_SB | IAP_F_SBX), 1306 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1307 IAP_F_SB | IAP_F_SBX), 1308 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1309 IAP_F_SB | IAP_F_SBX), 1310 1311 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), 1312 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), 1313 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB), 1314 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1315 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | IAP_F_HWX), 1316 IAPDESCR(A3H_0CH, 0xA3, 0x08, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1317 1318 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1319 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1320 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | 1321 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 1322 1323 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1324 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1325 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1326 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1327 1328 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1329 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1330 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1331 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1332 1333 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1334 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1335 IAP_F_SBX | IAP_F_IBX), 1336 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1337 1338 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1339 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1340 1341 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1342 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1343 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1344 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1345 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1346 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1347 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1348 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1349 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1350 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1351 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1352 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1353 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1354 1355 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1356 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1357 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1358 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1359 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1360 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1361 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1362 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1363 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1364 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1365 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1366 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1367 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1368 IAP_F_WM), 1369 1370 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1371 IAP_F_SB | IAP_F_SBX), 1372 1373 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1374 IAP_F_WM | IAP_F_I7O), 1375 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1376 IAP_F_WM | IAP_F_I7O), 1377 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1378 IAP_F_WM | IAP_F_I7O), 1379 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1380 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1381 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1382 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1383 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1384 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1385 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1386 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1387 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1388 1389 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1390 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1391 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1392 1393 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1394 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_CAS), 1395 1396 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1397 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | 1398 IAP_F_HWX), 1399 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1400 1401 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1402 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1403 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1404 1405 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1406 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1407 1408 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1409 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1410 1411 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1412 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1413 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1414 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1415 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1416 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1417 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1418 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1419 1420 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1421 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1422 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1423 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1424 1425 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1426 1427 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1428 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1429 IAP_F_CAS | IAP_F_HWX), 1430 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1431 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1432 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1433 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1434 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1435 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1436 IAP_F_I7 | IAP_F_WM), 1437 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1438 1439 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1440 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1441 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1442 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1443 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1444 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1445 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1446 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1447 IAP_F_SBX | IAP_F_IBX), 1448 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1449 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_IB | IAP_F_IBX), 1450 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1451 1452 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1453 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1454 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1455 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1456 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1457 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1458 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1459 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1460 IAP_F_I7 | IAP_F_WM), 1461 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1462 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1463 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1464 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1465 1466 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1467 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1468 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1469 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1470 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1471 IAP_F_CAS | IAP_F_HWX), 1472 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1473 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1474 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1475 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_CAS), 1476 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1477 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1478 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1479 1480 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1481 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1482 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1483 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1484 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1485 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1486 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1487 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1488 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1489 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1490 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1491 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1492 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1493 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1494 IAP_F_HWX), 1495 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1496 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1497 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1498 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1499 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1500 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1501 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1502 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1503 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_CAS), 1504 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_CAS), 1505 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_CAS), 1506 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_CAS), 1507 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_CAS), 1508 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_CAS), 1509 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_CAS), 1510 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_CAS), 1511 1512 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1513 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1514 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1515 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1516 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1517 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1518 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1519 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1520 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1521 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1522 IAP_F_SBX | IAP_F_IBX), 1523 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1524 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1525 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_CAS), 1526 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_CAS), 1527 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_CAS), 1528 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_CAS), 1529 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_CAS), 1530 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_CAS), 1531 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_CAS), 1532 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_CAS), 1533 1534 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1535 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1536 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1537 1538 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1539 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1540 IAP_F_I7 | IAP_F_WM), 1541 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1542 IAP_F_I7 | IAP_F_WM), 1543 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1544 IAP_F_I7 | IAP_F_WM), 1545 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1546 IAP_F_I7 | IAP_F_WM), 1547 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1548 IAP_F_I7 | IAP_F_WM), 1549 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1550 1551 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1552 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1553 1554 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1555 1556 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1557 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1558 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1559 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1560 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1561 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1562 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1563 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1564 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1565 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1566 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1567 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1568 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_CAS), 1569 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_CAS), 1570 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_CAS), 1571 1572 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1573 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1574 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1575 IAP_F_I7 | IAP_F_WM), 1576 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1577 IAP_F_I7 | IAP_F_WM), 1578 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1579 IAP_F_I7 | IAP_F_WM), 1580 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1581 IAP_F_WM), 1582 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_CAS), 1583 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1584 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1585 1586 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1587 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1588 IAP_F_I7 | IAP_F_WM), 1589 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1590 IAP_F_I7 | IAP_F_WM), 1591 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1592 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1593 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1594 1595 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1596 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1597 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1598 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1599 IAP_F_SBX | IAP_F_IBX), 1600 1601 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1602 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1603 1604 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1605 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1606 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1607 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1608 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1609 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1610 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1611 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1612 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1613 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1614 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1615 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1616 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1617 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1618 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1619 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1620 1621 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1622 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1623 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1624 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1625 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1626 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1627 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1628 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1629 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX), 1630 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1631 IAP_F_HW | IAP_F_HWX), 1632 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1633 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1634 1635 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1636 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1637 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1638 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1639 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1640 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1641 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1642 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1643 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1644 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1645 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1646 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1647 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1648 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1649 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1650 1651 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1652 1653 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1654 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1655 IAPDESCR(D3H_03H, 0xD3, 0x03, IAP_F_IBX), 1656 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), /* Not defined for IBX */ 1657 IAPDESCR(D3H_0CH, 0xD3, 0x0C, IAP_F_IBX), 1658 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX ), 1659 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX ), 1660 1661 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1662 IAP_F_I7 | IAP_F_WM), 1663 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1664 IAP_F_SB | IAP_F_SBX), 1665 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1666 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1667 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1668 1669 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1670 IAP_F_I7 | IAP_F_WM), 1671 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1672 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1673 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1674 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1675 1676 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1677 1678 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1679 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1680 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1681 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1682 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1683 1684 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1685 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1686 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1687 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1688 1689 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1690 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1691 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1692 1693 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1694 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1695 1696 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1697 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1698 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1699 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1700 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1701 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1702 1703 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1704 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1705 IAP_F_WM), 1706 1707 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1708 1709 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1710 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1711 1712 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1713 1714 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1715 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1716 IAP_F_WM | IAP_F_SBX | IAP_F_CAS), 1717 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1718 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_CAS), 1719 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_CAS), 1720 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | 1721 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1722 1723 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_CAS), 1724 1725 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1726 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1727 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1728 1729 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1730 1731 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1732 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1733 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1734 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1735 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1736 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1737 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1738 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1739 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1740 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1741 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1742 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1743 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1744 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1745 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1746 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1747 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1748 1749 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1750 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1751 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1752 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1753 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1754 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1755 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1756 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1757 1758 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1759 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1760 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1761 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1762 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1763 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1764 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1765 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1766 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1767 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1768 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1769 IAP_F_IBX), 1770 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1771 1772 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1773 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1774 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1775 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1776 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1777 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1778 1779 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1780 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1781 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1782 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1783 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1784 IAP_F_SB | IAP_F_SBX), 1785 1786 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1787 1788 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1789 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1790 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1791 1792 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1793 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1794 1795 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1796 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1797 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1798 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1799 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1800 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1801 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1802 }; 1803 1804 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1805 1806 static pmc_value_t 1807 iap_perfctr_value_to_reload_count(pmc_value_t v) 1808 { 1809 v &= (1ULL << core_iap_width) - 1; 1810 return (1ULL << core_iap_width) - v; 1811 } 1812 1813 static pmc_value_t 1814 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1815 { 1816 return (1ULL << core_iap_width) - rlc; 1817 } 1818 1819 static int 1820 iap_pmc_has_overflowed(int ri) 1821 { 1822 uint64_t v; 1823 1824 /* 1825 * We treat a Core (i.e., Intel architecture v1) PMC as has 1826 * having overflowed if its MSB is zero. 1827 */ 1828 v = rdpmc(ri); 1829 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1830 } 1831 1832 /* 1833 * Check an event against the set of supported architectural events. 1834 * 1835 * If the event is not architectural EV_IS_NOTARCH is returned. 1836 * If the event is architectural and supported on this CPU, the correct 1837 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 1838 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 1839 */ 1840 1841 static int 1842 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 1843 { 1844 enum core_arch_events ae; 1845 1846 switch (pe) { 1847 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 1848 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1849 *map = PMC_EV_IAP_EVENT_3CH_00H; 1850 break; 1851 case PMC_EV_IAP_ARCH_INS_RET: 1852 ae = CORE_AE_INSTRUCTION_RETIRED; 1853 *map = PMC_EV_IAP_EVENT_C0H_00H; 1854 break; 1855 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 1856 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1857 *map = PMC_EV_IAP_EVENT_3CH_01H; 1858 break; 1859 case PMC_EV_IAP_ARCH_LLC_REF: 1860 ae = CORE_AE_LLC_REFERENCE; 1861 *map = PMC_EV_IAP_EVENT_2EH_4FH; 1862 break; 1863 case PMC_EV_IAP_ARCH_LLC_MIS: 1864 ae = CORE_AE_LLC_MISSES; 1865 *map = PMC_EV_IAP_EVENT_2EH_41H; 1866 break; 1867 case PMC_EV_IAP_ARCH_BR_INS_RET: 1868 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1869 *map = PMC_EV_IAP_EVENT_C4H_00H; 1870 break; 1871 case PMC_EV_IAP_ARCH_BR_MIS_RET: 1872 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1873 *map = PMC_EV_IAP_EVENT_C5H_00H; 1874 break; 1875 1876 default: /* Non architectural event. */ 1877 return (EV_IS_NOTARCH); 1878 } 1879 1880 return (((core_architectural_events & (1 << ae)) == 0) ? 1881 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 1882 } 1883 1884 static int 1885 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1886 { 1887 uint32_t mask; 1888 1889 switch (pe) { 1890 /* 1891 * Events valid only on counter 0, 1. 1892 */ 1893 case PMC_EV_IAP_EVENT_40H_01H: 1894 case PMC_EV_IAP_EVENT_40H_02H: 1895 case PMC_EV_IAP_EVENT_40H_04H: 1896 case PMC_EV_IAP_EVENT_40H_08H: 1897 case PMC_EV_IAP_EVENT_40H_0FH: 1898 case PMC_EV_IAP_EVENT_41H_02H: 1899 case PMC_EV_IAP_EVENT_41H_04H: 1900 case PMC_EV_IAP_EVENT_41H_08H: 1901 case PMC_EV_IAP_EVENT_42H_01H: 1902 case PMC_EV_IAP_EVENT_42H_02H: 1903 case PMC_EV_IAP_EVENT_42H_04H: 1904 case PMC_EV_IAP_EVENT_42H_08H: 1905 case PMC_EV_IAP_EVENT_43H_01H: 1906 case PMC_EV_IAP_EVENT_43H_02H: 1907 case PMC_EV_IAP_EVENT_51H_01H: 1908 case PMC_EV_IAP_EVENT_51H_02H: 1909 case PMC_EV_IAP_EVENT_51H_04H: 1910 case PMC_EV_IAP_EVENT_51H_08H: 1911 case PMC_EV_IAP_EVENT_63H_01H: 1912 case PMC_EV_IAP_EVENT_63H_02H: 1913 mask = 0x3; 1914 break; 1915 1916 default: 1917 mask = ~0; /* Any row index is ok. */ 1918 } 1919 1920 return (mask & (1 << ri)); 1921 } 1922 1923 static int 1924 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1925 { 1926 uint32_t mask; 1927 1928 switch (pe) { 1929 /* 1930 * Events valid only on counter 0. 1931 */ 1932 case PMC_EV_IAP_EVENT_60H_01H: 1933 case PMC_EV_IAP_EVENT_60H_02H: 1934 case PMC_EV_IAP_EVENT_60H_04H: 1935 case PMC_EV_IAP_EVENT_60H_08H: 1936 case PMC_EV_IAP_EVENT_B3H_01H: 1937 case PMC_EV_IAP_EVENT_B3H_02H: 1938 case PMC_EV_IAP_EVENT_B3H_04H: 1939 mask = 0x1; 1940 break; 1941 1942 /* 1943 * Events valid only on counter 0, 1. 1944 */ 1945 case PMC_EV_IAP_EVENT_4CH_01H: 1946 case PMC_EV_IAP_EVENT_4EH_01H: 1947 case PMC_EV_IAP_EVENT_4EH_02H: 1948 case PMC_EV_IAP_EVENT_4EH_04H: 1949 case PMC_EV_IAP_EVENT_51H_01H: 1950 case PMC_EV_IAP_EVENT_51H_02H: 1951 case PMC_EV_IAP_EVENT_51H_04H: 1952 case PMC_EV_IAP_EVENT_51H_08H: 1953 case PMC_EV_IAP_EVENT_63H_01H: 1954 case PMC_EV_IAP_EVENT_63H_02H: 1955 mask = 0x3; 1956 break; 1957 1958 default: 1959 mask = ~0; /* Any row index is ok. */ 1960 } 1961 1962 return (mask & (1 << ri)); 1963 } 1964 1965 static int 1966 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 1967 { 1968 uint32_t mask; 1969 1970 switch (pe) { 1971 /* Events valid only on counter 0. */ 1972 case PMC_EV_IAP_EVENT_B7H_01H: 1973 mask = 0x1; 1974 break; 1975 /* Events valid only on counter 1. */ 1976 case PMC_EV_IAP_EVENT_C0H_01H: 1977 mask = 0x2; 1978 break; 1979 /* Events valid only on counter 2. */ 1980 case PMC_EV_IAP_EVENT_48H_01H: 1981 case PMC_EV_IAP_EVENT_A2H_02H: 1982 case PMC_EV_IAP_EVENT_A3H_08H: 1983 mask = 0x4; 1984 break; 1985 /* Events valid only on counter 3. */ 1986 case PMC_EV_IAP_EVENT_BBH_01H: 1987 case PMC_EV_IAP_EVENT_CDH_01H: 1988 case PMC_EV_IAP_EVENT_CDH_02H: 1989 mask = 0x8; 1990 break; 1991 default: 1992 mask = ~0; /* Any row index is ok. */ 1993 } 1994 1995 return (mask & (1 << ri)); 1996 } 1997 1998 static int 1999 iap_event_ok_on_counter(enum pmc_event pe, int ri) 2000 { 2001 uint32_t mask; 2002 2003 switch (pe) { 2004 /* 2005 * Events valid only on counter 0. 2006 */ 2007 case PMC_EV_IAP_EVENT_10H_00H: 2008 case PMC_EV_IAP_EVENT_14H_00H: 2009 case PMC_EV_IAP_EVENT_18H_00H: 2010 case PMC_EV_IAP_EVENT_B3H_01H: 2011 case PMC_EV_IAP_EVENT_B3H_02H: 2012 case PMC_EV_IAP_EVENT_B3H_04H: 2013 case PMC_EV_IAP_EVENT_C1H_00H: 2014 case PMC_EV_IAP_EVENT_CBH_01H: 2015 case PMC_EV_IAP_EVENT_CBH_02H: 2016 mask = (1 << 0); 2017 break; 2018 2019 /* 2020 * Events valid only on counter 1. 2021 */ 2022 case PMC_EV_IAP_EVENT_11H_00H: 2023 case PMC_EV_IAP_EVENT_12H_00H: 2024 case PMC_EV_IAP_EVENT_13H_00H: 2025 mask = (1 << 1); 2026 break; 2027 2028 default: 2029 mask = ~0; /* Any row index is ok. */ 2030 } 2031 2032 return (mask & (1 << ri)); 2033 } 2034 2035 static int 2036 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 2037 const struct pmc_op_pmcallocate *a) 2038 { 2039 int arch, n, model; 2040 enum pmc_event ev, map; 2041 struct iap_event_descr *ie; 2042 uint32_t c, caps, config, cpuflag, evsel, mask; 2043 2044 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2045 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2046 KASSERT(ri >= 0 && ri < core_iap_npmc, 2047 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 2048 2049 /* check requested capabilities */ 2050 caps = a->pm_caps; 2051 if ((IAP_PMC_CAPS & caps) != caps) 2052 return (EPERM); 2053 map = 0; /* XXX: silent GCC warning */ 2054 arch = iap_is_event_architectural(pm->pm_event, &map); 2055 if (arch == EV_IS_ARCH_NOTSUPP) 2056 return (EOPNOTSUPP); 2057 else if (arch == EV_IS_ARCH_SUPP) 2058 ev = map; 2059 else 2060 ev = pm->pm_event; 2061 2062 /* 2063 * A small number of events are not supported in all the 2064 * processors based on a given microarchitecture. 2065 */ 2066 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2067 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2068 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2069 return (EINVAL); 2070 } 2071 2072 switch (core_cputype) { 2073 case PMC_CPU_INTEL_COREI7: 2074 case PMC_CPU_INTEL_NEHALEM_EX: 2075 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2076 return (EINVAL); 2077 break; 2078 case PMC_CPU_INTEL_BROADWELL: 2079 case PMC_CPU_INTEL_SANDYBRIDGE: 2080 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2081 case PMC_CPU_INTEL_IVYBRIDGE: 2082 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2083 case PMC_CPU_INTEL_HASWELL: 2084 case PMC_CPU_INTEL_HASWELL_XEON: 2085 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2086 return (EINVAL); 2087 break; 2088 case PMC_CPU_INTEL_WESTMERE: 2089 case PMC_CPU_INTEL_WESTMERE_EX: 2090 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2091 return (EINVAL); 2092 break; 2093 default: 2094 if (iap_event_ok_on_counter(ev, ri) == 0) 2095 return (EINVAL); 2096 } 2097 2098 /* 2099 * Look for an event descriptor with matching CPU and event id 2100 * fields. 2101 */ 2102 2103 switch (core_cputype) { 2104 default: 2105 case PMC_CPU_INTEL_ATOM: 2106 cpuflag = IAP_F_CA; 2107 break; 2108 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2109 cpuflag = IAP_F_CAS; 2110 break; 2111 case PMC_CPU_INTEL_BROADWELL: 2112 cpuflag = IAP_F_BW; 2113 break; 2114 case PMC_CPU_INTEL_CORE: 2115 cpuflag = IAP_F_CC; 2116 break; 2117 case PMC_CPU_INTEL_CORE2: 2118 cpuflag = IAP_F_CC2; 2119 break; 2120 case PMC_CPU_INTEL_CORE2EXTREME: 2121 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2122 break; 2123 case PMC_CPU_INTEL_COREI7: 2124 cpuflag = IAP_F_I7; 2125 break; 2126 case PMC_CPU_INTEL_HASWELL: 2127 cpuflag = IAP_F_HW; 2128 break; 2129 case PMC_CPU_INTEL_HASWELL_XEON: 2130 cpuflag = IAP_F_HWX; 2131 break; 2132 case PMC_CPU_INTEL_IVYBRIDGE: 2133 cpuflag = IAP_F_IB; 2134 break; 2135 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2136 cpuflag = IAP_F_IBX; 2137 break; 2138 case PMC_CPU_INTEL_SANDYBRIDGE: 2139 cpuflag = IAP_F_SB; 2140 break; 2141 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2142 cpuflag = IAP_F_SBX; 2143 break; 2144 case PMC_CPU_INTEL_WESTMERE: 2145 cpuflag = IAP_F_WM; 2146 break; 2147 } 2148 2149 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 2150 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2151 break; 2152 2153 if (n == niap_events) 2154 return (EINVAL); 2155 2156 /* 2157 * A matching event descriptor has been found, so start 2158 * assembling the contents of the event select register. 2159 */ 2160 evsel = ie->iap_evcode; 2161 2162 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2163 2164 /* 2165 * If the event uses a fixed umask value, reject any umask 2166 * bits set by the user. 2167 */ 2168 if (ie->iap_flags & IAP_F_FM) { 2169 2170 if (IAP_UMASK(config) != 0) 2171 return (EINVAL); 2172 2173 evsel |= (ie->iap_umask << 8); 2174 2175 } else { 2176 2177 /* 2178 * Otherwise, the UMASK value needs to be taken from 2179 * the MD fields of the allocation request. Reject 2180 * requests that specify reserved bits. 2181 */ 2182 2183 mask = 0; 2184 2185 if (ie->iap_umask & IAP_M_CORE) { 2186 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2187 c != IAP_CORE_THIS) 2188 return (EINVAL); 2189 mask |= IAP_F_CORE; 2190 } 2191 2192 if (ie->iap_umask & IAP_M_AGENT) 2193 mask |= IAP_F_AGENT; 2194 2195 if (ie->iap_umask & IAP_M_PREFETCH) { 2196 2197 if ((c = (config & IAP_F_PREFETCH)) == 2198 IAP_PREFETCH_RESERVED) 2199 return (EINVAL); 2200 2201 mask |= IAP_F_PREFETCH; 2202 } 2203 2204 if (ie->iap_umask & IAP_M_MESI) 2205 mask |= IAP_F_MESI; 2206 2207 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2208 mask |= IAP_F_SNOOPRESPONSE; 2209 2210 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2211 mask |= IAP_F_SNOOPTYPE; 2212 2213 if (ie->iap_umask & IAP_M_TRANSITION) 2214 mask |= IAP_F_TRANSITION; 2215 2216 /* 2217 * If bits outside of the allowed set of umask bits 2218 * are set, reject the request. 2219 */ 2220 if (config & ~mask) 2221 return (EINVAL); 2222 2223 evsel |= (config & mask); 2224 2225 } 2226 2227 /* 2228 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2229 */ 2230 if (core_cputype == PMC_CPU_INTEL_ATOM || 2231 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2232 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2233 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2234 evsel |= (config & IAP_ANY); 2235 else if (config & IAP_ANY) 2236 return (EINVAL); 2237 2238 /* 2239 * Check offcore response configuration. 2240 */ 2241 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2242 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2243 ev != PMC_EV_IAP_EVENT_BBH_01H) 2244 return (EINVAL); 2245 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2246 ev == PMC_EV_IAP_EVENT_BBH_01H) 2247 return (EINVAL); 2248 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2249 core_cputype == PMC_CPU_INTEL_WESTMERE || 2250 core_cputype == PMC_CPU_INTEL_NEHALEM_EX || 2251 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && 2252 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2253 return (EINVAL); 2254 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2255 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2256 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2257 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2258 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2259 return (EINVAL); 2260 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2261 } 2262 2263 if (caps & PMC_CAP_THRESHOLD) 2264 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2265 if (caps & PMC_CAP_USER) 2266 evsel |= IAP_USR; 2267 if (caps & PMC_CAP_SYSTEM) 2268 evsel |= IAP_OS; 2269 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2270 evsel |= (IAP_OS | IAP_USR); 2271 if (caps & PMC_CAP_EDGE) 2272 evsel |= IAP_EDGE; 2273 if (caps & PMC_CAP_INVERT) 2274 evsel |= IAP_INV; 2275 if (caps & PMC_CAP_INTERRUPT) 2276 evsel |= IAP_INT; 2277 2278 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2279 2280 return (0); 2281 } 2282 2283 static int 2284 iap_config_pmc(int cpu, int ri, struct pmc *pm) 2285 { 2286 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2287 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2288 2289 KASSERT(ri >= 0 && ri < core_iap_npmc, 2290 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2291 2292 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2293 2294 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2295 cpu)); 2296 2297 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2298 2299 return (0); 2300 } 2301 2302 static int 2303 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2304 { 2305 int error; 2306 struct pmc_hw *phw; 2307 char iap_name[PMC_NAME_MAX]; 2308 2309 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2310 2311 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2312 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2313 NULL)) != 0) 2314 return (error); 2315 2316 pi->pm_class = PMC_CLASS_IAP; 2317 2318 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2319 pi->pm_enabled = TRUE; 2320 *ppmc = phw->phw_pmc; 2321 } else { 2322 pi->pm_enabled = FALSE; 2323 *ppmc = NULL; 2324 } 2325 2326 return (0); 2327 } 2328 2329 static int 2330 iap_get_config(int cpu, int ri, struct pmc **ppm) 2331 { 2332 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2333 2334 return (0); 2335 } 2336 2337 static int 2338 iap_get_msr(int ri, uint32_t *msr) 2339 { 2340 KASSERT(ri >= 0 && ri < core_iap_npmc, 2341 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2342 2343 *msr = ri; 2344 2345 return (0); 2346 } 2347 2348 static int 2349 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2350 { 2351 struct pmc *pm; 2352 pmc_value_t tmp; 2353 2354 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2355 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2356 KASSERT(ri >= 0 && ri < core_iap_npmc, 2357 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2358 2359 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2360 2361 KASSERT(pm, 2362 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2363 ri)); 2364 2365 tmp = rdpmc(ri); 2366 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2367 *v = iap_perfctr_value_to_reload_count(tmp); 2368 else 2369 *v = tmp & ((1ULL << core_iap_width) - 1); 2370 2371 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2372 ri, *v); 2373 2374 return (0); 2375 } 2376 2377 static int 2378 iap_release_pmc(int cpu, int ri, struct pmc *pm) 2379 { 2380 (void) pm; 2381 2382 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2383 pm); 2384 2385 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2386 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2387 KASSERT(ri >= 0 && ri < core_iap_npmc, 2388 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2389 2390 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2391 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2392 2393 return (0); 2394 } 2395 2396 static int 2397 iap_start_pmc(int cpu, int ri) 2398 { 2399 struct pmc *pm; 2400 uint32_t evsel; 2401 struct core_cpu *cc; 2402 2403 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2404 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2405 KASSERT(ri >= 0 && ri < core_iap_npmc, 2406 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2407 2408 cc = core_pcpu[cpu]; 2409 pm = cc->pc_corepmcs[ri].phw_pmc; 2410 2411 KASSERT(pm, 2412 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2413 __LINE__, cpu, ri)); 2414 2415 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2416 2417 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2418 2419 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2420 cpu, ri, IAP_EVSEL0 + ri, evsel); 2421 2422 /* Event specific configuration. */ 2423 switch (pm->pm_event) { 2424 case PMC_EV_IAP_EVENT_B7H_01H: 2425 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2426 break; 2427 case PMC_EV_IAP_EVENT_BBH_01H: 2428 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2429 break; 2430 default: 2431 break; 2432 } 2433 2434 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2435 2436 if (core_cputype == PMC_CPU_INTEL_CORE) 2437 return (0); 2438 2439 do { 2440 cc->pc_resync = 0; 2441 cc->pc_globalctrl |= (1ULL << ri); 2442 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2443 } while (cc->pc_resync != 0); 2444 2445 return (0); 2446 } 2447 2448 static int 2449 iap_stop_pmc(int cpu, int ri) 2450 { 2451 struct pmc *pm; 2452 struct core_cpu *cc; 2453 uint64_t msr; 2454 2455 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2456 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2457 KASSERT(ri >= 0 && ri < core_iap_npmc, 2458 ("[core,%d] illegal row index %d", __LINE__, ri)); 2459 2460 cc = core_pcpu[cpu]; 2461 pm = cc->pc_corepmcs[ri].phw_pmc; 2462 2463 KASSERT(pm, 2464 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2465 cpu, ri)); 2466 2467 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2468 2469 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2470 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2471 2472 if (core_cputype == PMC_CPU_INTEL_CORE) 2473 return (0); 2474 2475 msr = 0; 2476 do { 2477 cc->pc_resync = 0; 2478 cc->pc_globalctrl &= ~(1ULL << ri); 2479 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2480 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2481 } while (cc->pc_resync != 0); 2482 2483 return (0); 2484 } 2485 2486 static int 2487 iap_write_pmc(int cpu, int ri, pmc_value_t v) 2488 { 2489 struct pmc *pm; 2490 struct core_cpu *cc; 2491 2492 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2493 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2494 KASSERT(ri >= 0 && ri < core_iap_npmc, 2495 ("[core,%d] illegal row index %d", __LINE__, ri)); 2496 2497 cc = core_pcpu[cpu]; 2498 pm = cc->pc_corepmcs[ri].phw_pmc; 2499 2500 KASSERT(pm, 2501 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2502 cpu, ri)); 2503 2504 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2505 IAP_PMC0 + ri, v); 2506 2507 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2508 v = iap_reload_count_to_perfctr_value(v); 2509 2510 /* 2511 * Write the new value to the counter. The counter will be in 2512 * a stopped state when the pcd_write() entry point is called. 2513 */ 2514 2515 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2516 2517 return (0); 2518 } 2519 2520 2521 static void 2522 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2523 int flags) 2524 { 2525 struct pmc_classdep *pcd; 2526 2527 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2528 2529 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2530 2531 /* Remember the set of architectural events supported. */ 2532 core_architectural_events = ~flags; 2533 2534 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2535 2536 pcd->pcd_caps = IAP_PMC_CAPS; 2537 pcd->pcd_class = PMC_CLASS_IAP; 2538 pcd->pcd_num = npmc; 2539 pcd->pcd_ri = md->pmd_npmc; 2540 pcd->pcd_width = pmcwidth; 2541 2542 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2543 pcd->pcd_config_pmc = iap_config_pmc; 2544 pcd->pcd_describe = iap_describe; 2545 pcd->pcd_get_config = iap_get_config; 2546 pcd->pcd_get_msr = iap_get_msr; 2547 pcd->pcd_pcpu_fini = core_pcpu_fini; 2548 pcd->pcd_pcpu_init = core_pcpu_init; 2549 pcd->pcd_read_pmc = iap_read_pmc; 2550 pcd->pcd_release_pmc = iap_release_pmc; 2551 pcd->pcd_start_pmc = iap_start_pmc; 2552 pcd->pcd_stop_pmc = iap_stop_pmc; 2553 pcd->pcd_write_pmc = iap_write_pmc; 2554 2555 md->pmd_npmc += npmc; 2556 } 2557 2558 static int 2559 core_intr(int cpu, struct trapframe *tf) 2560 { 2561 pmc_value_t v; 2562 struct pmc *pm; 2563 struct core_cpu *cc; 2564 int error, found_interrupt, ri; 2565 uint64_t msr; 2566 2567 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2568 TRAPF_USERMODE(tf)); 2569 2570 found_interrupt = 0; 2571 cc = core_pcpu[cpu]; 2572 2573 for (ri = 0; ri < core_iap_npmc; ri++) { 2574 2575 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2576 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2577 continue; 2578 2579 if (!iap_pmc_has_overflowed(ri)) 2580 continue; 2581 2582 found_interrupt = 1; 2583 2584 if (pm->pm_state != PMC_STATE_RUNNING) 2585 continue; 2586 2587 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2588 TRAPF_USERMODE(tf)); 2589 2590 v = pm->pm_sc.pm_reloadcount; 2591 v = iaf_reload_count_to_perfctr_value(v); 2592 2593 /* 2594 * Stop the counter, reload it but only restart it if 2595 * the PMC is not stalled. 2596 */ 2597 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2598 wrmsr(IAP_EVSEL0 + ri, msr); 2599 wrmsr(IAP_PMC0 + ri, v); 2600 2601 if (error) 2602 continue; 2603 2604 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2605 IAP_EN)); 2606 } 2607 2608 if (found_interrupt) 2609 lapic_reenable_pmc(); 2610 2611 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2612 &pmc_stats.pm_intr_ignored, 1); 2613 2614 return (found_interrupt); 2615 } 2616 2617 static int 2618 core2_intr(int cpu, struct trapframe *tf) 2619 { 2620 int error, found_interrupt, n; 2621 uint64_t flag, intrstatus, intrenable, msr; 2622 struct pmc *pm; 2623 struct core_cpu *cc; 2624 pmc_value_t v; 2625 2626 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2627 TRAPF_USERMODE(tf)); 2628 2629 /* 2630 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2631 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2632 * the current set of interrupting PMCs and process these 2633 * after stopping them. 2634 */ 2635 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2636 intrenable = intrstatus & core_pmcmask; 2637 2638 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2639 (uintmax_t) intrstatus); 2640 2641 found_interrupt = 0; 2642 cc = core_pcpu[cpu]; 2643 2644 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2645 2646 cc->pc_globalctrl &= ~intrenable; 2647 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2648 2649 /* 2650 * Stop PMCs and clear overflow status bits. 2651 */ 2652 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2653 wrmsr(IA_GLOBAL_CTRL, msr); 2654 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2655 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2656 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2657 2658 /* 2659 * Look for interrupts from fixed function PMCs. 2660 */ 2661 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2662 n++, flag <<= 1) { 2663 2664 if ((intrstatus & flag) == 0) 2665 continue; 2666 2667 found_interrupt = 1; 2668 2669 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2670 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2671 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2672 continue; 2673 2674 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2675 TRAPF_USERMODE(tf)); 2676 if (error) 2677 intrenable &= ~flag; 2678 2679 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2680 2681 /* Reload sampling count. */ 2682 wrmsr(IAF_CTR0 + n, v); 2683 2684 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2685 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2686 } 2687 2688 /* 2689 * Process interrupts from the programmable counters. 2690 */ 2691 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2692 if ((intrstatus & flag) == 0) 2693 continue; 2694 2695 found_interrupt = 1; 2696 2697 pm = cc->pc_corepmcs[n].phw_pmc; 2698 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2699 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2700 continue; 2701 2702 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2703 TRAPF_USERMODE(tf)); 2704 if (error) 2705 intrenable &= ~flag; 2706 2707 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2708 2709 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2710 (uintmax_t) v); 2711 2712 /* Reload sampling count. */ 2713 wrmsr(IAP_PMC0 + n, v); 2714 } 2715 2716 /* 2717 * Reenable all non-stalled PMCs. 2718 */ 2719 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2720 (uintmax_t) intrenable); 2721 2722 cc->pc_globalctrl |= intrenable; 2723 2724 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2725 2726 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2727 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2728 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2729 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2730 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2731 2732 if (found_interrupt) 2733 lapic_reenable_pmc(); 2734 2735 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2736 &pmc_stats.pm_intr_ignored, 1); 2737 2738 return (found_interrupt); 2739 } 2740 2741 int 2742 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 2743 { 2744 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2745 int ipa_version, flags, nflags; 2746 2747 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2748 2749 ipa_version = (version_override > 0) ? version_override : 2750 cpuid[CORE_CPUID_EAX] & 0xFF; 2751 core_cputype = md->pmd_cputype; 2752 2753 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2754 core_cputype, maxcpu, ipa_version); 2755 2756 if (ipa_version < 1 || ipa_version > 3 || 2757 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 2758 /* Unknown PMC architecture. */ 2759 printf("hwpc_core: unknown PMC architecture: %d\n", 2760 ipa_version); 2761 return (EPROGMISMATCH); 2762 } 2763 2764 core_pmcmask = 0; 2765 2766 /* 2767 * Initialize programmable counters. 2768 */ 2769 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2770 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2771 2772 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2773 2774 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2775 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2776 2777 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2778 2779 /* 2780 * Initialize fixed function counters, if present. 2781 */ 2782 if (core_cputype != PMC_CPU_INTEL_CORE) { 2783 core_iaf_ri = core_iap_npmc; 2784 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2785 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2786 2787 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2788 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2789 } 2790 2791 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2792 core_iaf_ri); 2793 2794 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 2795 M_ZERO | M_WAITOK); 2796 2797 /* 2798 * Choose the appropriate interrupt handler. 2799 */ 2800 if (ipa_version == 1) 2801 md->pmd_intr = core_intr; 2802 else 2803 md->pmd_intr = core2_intr; 2804 2805 md->pmd_pcpu_fini = NULL; 2806 md->pmd_pcpu_init = NULL; 2807 2808 return (0); 2809 } 2810 2811 void 2812 pmc_core_finalize(struct pmc_mdep *md) 2813 { 2814 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2815 2816 free(core_pcpu, M_PMC); 2817 core_pcpu = NULL; 2818 } 2819