1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_ADMINQ_CMD_H_ 34 #define _ICE_ADMINQ_CMD_H_ 35 36 /* This header file defines the Admin Queue commands, error codes and 37 * descriptor format. It is shared between Firmware and Software. 38 */ 39 40 #define ICE_MAX_VSI 768 41 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 42 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 43 44 struct ice_aqc_generic { 45 __le32 param0; 46 __le32 param1; 47 __le32 addr_high; 48 __le32 addr_low; 49 }; 50 51 /* Get version (direct 0x0001) */ 52 struct ice_aqc_get_ver { 53 __le32 rom_ver; 54 __le32 fw_build; 55 u8 fw_branch; 56 u8 fw_major; 57 u8 fw_minor; 58 u8 fw_patch; 59 u8 api_branch; 60 u8 api_major; 61 u8 api_minor; 62 u8 api_patch; 63 }; 64 65 /* Send driver version (indirect 0x0002) */ 66 struct ice_aqc_driver_ver { 67 u8 major_ver; 68 u8 minor_ver; 69 u8 build_ver; 70 u8 subbuild_ver; 71 u8 reserved[4]; 72 __le32 addr_high; 73 __le32 addr_low; 74 }; 75 76 /* Queue Shutdown (direct 0x0003) */ 77 struct ice_aqc_q_shutdown { 78 u8 driver_unloading; 79 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 80 u8 reserved[15]; 81 }; 82 83 /* Get Expanded Error Code (0x0005, direct) */ 84 struct ice_aqc_get_exp_err { 85 __le32 reason; 86 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 87 __le32 identifier; 88 u8 rsvd[8]; 89 }; 90 91 /* Request resource ownership (direct 0x0008) 92 * Release resource ownership (direct 0x0009) 93 */ 94 struct ice_aqc_req_res { 95 __le16 res_id; 96 #define ICE_AQC_RES_ID_NVM 1 97 #define ICE_AQC_RES_ID_SDP 2 98 #define ICE_AQC_RES_ID_CHNG_LOCK 3 99 #define ICE_AQC_RES_ID_GLBL_LOCK 4 100 __le16 access_type; 101 #define ICE_AQC_RES_ACCESS_READ 1 102 #define ICE_AQC_RES_ACCESS_WRITE 2 103 104 /* Upon successful completion, FW writes this value and driver is 105 * expected to release resource before timeout. This value is provided 106 * in milliseconds. 107 */ 108 __le32 timeout; 109 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 110 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 111 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 112 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 113 /* For SDP: pin ID of the SDP */ 114 __le32 res_number; 115 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 116 __le16 status; 117 #define ICE_AQ_RES_GLBL_SUCCESS 0 118 #define ICE_AQ_RES_GLBL_IN_PROG 1 119 #define ICE_AQ_RES_GLBL_DONE 2 120 u8 reserved[2]; 121 }; 122 123 /* Get function capabilities (indirect 0x000A) 124 * Get device capabilities (indirect 0x000B) 125 */ 126 struct ice_aqc_list_caps { 127 u8 cmd_flags; 128 u8 pf_index; 129 u8 reserved[2]; 130 __le32 count; 131 __le32 addr_high; 132 __le32 addr_low; 133 }; 134 135 /* Device/Function buffer entry, repeated per reported capability */ 136 struct ice_aqc_list_caps_elem { 137 __le16 cap; 138 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001 139 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002 140 #define ICE_AQC_CAPS_OS2BMC 0x0004 141 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 142 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 143 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006 144 #define ICE_AQC_CAPS_WOL_PROXY 0x0008 145 #define ICE_AQC_CAPS_SRIOV 0x0012 146 #define ICE_AQC_CAPS_VF 0x0013 147 #define ICE_AQC_CAPS_802_1QBG 0x0015 148 #define ICE_AQC_CAPS_802_1BR 0x0016 149 #define ICE_AQC_CAPS_VSI 0x0017 150 #define ICE_AQC_CAPS_DCB 0x0018 151 #define ICE_AQC_CAPS_RSVD 0x0021 152 #define ICE_AQC_CAPS_ISCSI 0x0022 153 #define ICE_AQC_CAPS_RSS 0x0040 154 #define ICE_AQC_CAPS_RXQS 0x0041 155 #define ICE_AQC_CAPS_TXQS 0x0042 156 #define ICE_AQC_CAPS_MSIX 0x0043 157 #define ICE_AQC_CAPS_MAX_MTU 0x0047 158 #define ICE_AQC_CAPS_NVM_VER 0x0048 159 #define ICE_AQC_CAPS_OROM_VER 0x004A 160 #define ICE_AQC_CAPS_NET_VER 0x004C 161 #define ICE_AQC_CAPS_CEM 0x00F2 162 #define ICE_AQC_CAPS_IWARP 0x0051 163 #define ICE_AQC_CAPS_LED 0x0061 164 #define ICE_AQC_CAPS_SDP 0x0062 165 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 166 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 167 #define ICE_AQC_CAPS_SKU 0x0074 168 #define ICE_AQC_CAPS_PORT_MAP 0x0075 169 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 170 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 171 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 172 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081 173 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082 174 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083 175 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084 176 177 u8 major_ver; 178 u8 minor_ver; 179 /* Number of resources described by this capability */ 180 __le32 number; 181 /* Only meaningful for some types of resources */ 182 __le32 logical_id; 183 /* Only meaningful for some types of resources */ 184 __le32 phys_id; 185 __le64 rsvd1; 186 __le64 rsvd2; 187 }; 188 189 /* Manage MAC address, read command - indirect (0x0107) 190 * This struct is also used for the response 191 */ 192 struct ice_aqc_manage_mac_read { 193 __le16 flags; /* Zeroed by device driver */ 194 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 195 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 196 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 197 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 198 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 199 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 200 #define ICE_AQC_MAN_MAC_READ_S 4 201 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 202 u8 rsvd[2]; 203 u8 num_addr; /* Used in response */ 204 u8 rsvd1[3]; 205 __le32 addr_high; 206 __le32 addr_low; 207 }; 208 209 /* Response buffer format for manage MAC read command */ 210 struct ice_aqc_manage_mac_read_resp { 211 u8 lport_num; 212 u8 addr_type; 213 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 214 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 215 u8 mac_addr[ETH_ALEN]; 216 }; 217 218 /* Manage MAC address, write command - direct (0x0108) */ 219 struct ice_aqc_manage_mac_write { 220 u8 rsvd; 221 u8 flags; 222 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 223 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 224 #define ICE_AQC_MAN_MAC_WR_S 6 225 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 226 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 227 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 228 /* byte stream in network order */ 229 u8 mac_addr[ETH_ALEN]; 230 __le32 addr_high; 231 __le32 addr_low; 232 }; 233 234 /* Clear PXE Command and response (direct 0x0110) */ 235 struct ice_aqc_clear_pxe { 236 u8 rx_cnt; 237 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 238 u8 reserved[15]; 239 }; 240 241 /* Configure No-Drop Policy Command (direct 0x0112) */ 242 struct ice_aqc_config_no_drop_policy { 243 u8 opts; 244 #define ICE_AQC_FORCE_NO_DROP BIT(0) 245 u8 rsvd[15]; 246 }; 247 248 /* Get switch configuration (0x0200) */ 249 struct ice_aqc_get_sw_cfg { 250 /* Reserved for command and copy of request flags for response */ 251 __le16 flags; 252 /* First desc in case of command and next_elem in case of response 253 * In case of response, if it is not zero, means all the configuration 254 * was not returned and new command shall be sent with this value in 255 * the 'first desc' field 256 */ 257 __le16 element; 258 /* Reserved for command, only used for response */ 259 __le16 num_elems; 260 __le16 rsvd; 261 __le32 addr_high; 262 __le32 addr_low; 263 }; 264 265 /* Each entry in the response buffer is of the following type: */ 266 struct ice_aqc_get_sw_cfg_resp_elem { 267 /* VSI/Port Number */ 268 __le16 vsi_port_num; 269 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 270 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 271 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 272 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 273 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 274 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 275 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 276 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 277 278 /* SWID VSI/Port belongs to */ 279 __le16 swid; 280 281 /* Bit 14..0 : PF/VF number VSI belongs to 282 * Bit 15 : VF indication bit 283 */ 284 __le16 pf_vf_num; 285 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 286 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 287 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 288 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 289 }; 290 291 /* Set Port parameters, (direct, 0x0203) */ 292 struct ice_aqc_set_port_params { 293 __le16 cmd_flags; 294 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 295 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 296 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 297 __le16 bad_frame_vsi; 298 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 299 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 300 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 301 __le16 swid; 302 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 303 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 304 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 305 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 306 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 307 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 308 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 309 u8 reserved[10]; 310 }; 311 312 /* These resource type defines are used for all switch resource 313 * commands where a resource type is required, such as: 314 * Get Resource Allocation command (indirect 0x0204) 315 * Allocate Resources command (indirect 0x0208) 316 * Free Resources command (indirect 0x0209) 317 * Get Allocated Resource Descriptors Command (indirect 0x020A) 318 */ 319 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 320 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 321 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 322 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 323 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 324 #define ICE_AQC_RES_TYPE_RECIPE 0x05 325 #define ICE_AQC_RES_TYPE_PROFILE 0x06 326 #define ICE_AQC_RES_TYPE_SWID 0x07 327 #define ICE_AQC_RES_TYPE_VSI 0x08 328 #define ICE_AQC_RES_TYPE_FLU 0x09 329 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 330 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 331 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 332 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 333 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 334 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 335 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 336 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 337 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 338 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 339 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 340 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 341 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 342 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 343 /* Resource types 0x62-67 are reserved for Hash profile builder */ 344 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 345 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 346 347 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 348 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 349 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 350 351 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 352 353 #define ICE_AQC_RES_TYPE_S 0 354 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 355 356 /* Get Resource Allocation command (indirect 0x0204) */ 357 struct ice_aqc_get_res_alloc { 358 __le16 resp_elem_num; /* Used in response, reserved in command */ 359 u8 reserved[6]; 360 __le32 addr_high; 361 __le32 addr_low; 362 }; 363 364 /* Get Resource Allocation Response Buffer per response */ 365 struct ice_aqc_get_res_resp_elem { 366 __le16 res_type; /* Types defined above cmd 0x0204 */ 367 __le16 total_capacity; /* Resources available to all PF's */ 368 __le16 total_function; /* Resources allocated for a PF */ 369 __le16 total_shared; /* Resources allocated as shared */ 370 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 371 }; 372 373 /* Allocate Resources command (indirect 0x0208) 374 * Free Resources command (indirect 0x0209) 375 */ 376 struct ice_aqc_alloc_free_res_cmd { 377 __le16 num_entries; /* Number of Resource entries */ 378 u8 reserved[6]; 379 __le32 addr_high; 380 __le32 addr_low; 381 }; 382 383 /* Resource descriptor */ 384 struct ice_aqc_res_elem { 385 union { 386 __le16 sw_resp; 387 __le16 flu_resp; 388 } e; 389 }; 390 391 /* Buffer for Allocate/Free Resources commands */ 392 struct ice_aqc_alloc_free_res_elem { 393 __le16 res_type; /* Types defined above cmd 0x0204 */ 394 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 395 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 396 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 397 __le16 num_elems; 398 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 399 }; 400 401 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 402 struct ice_aqc_get_allocd_res_desc { 403 union { 404 struct { 405 __le16 res; /* Types defined above cmd 0x0204 */ 406 __le16 first_desc; 407 __le32 reserved; 408 } cmd; 409 struct { 410 __le16 res; 411 __le16 next_desc; 412 __le16 num_desc; 413 __le16 reserved; 414 } resp; 415 } ops; 416 __le32 addr_high; 417 __le32 addr_low; 418 }; 419 420 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 421 struct ice_aqc_set_vlan_mode { 422 u8 reserved; 423 u8 l2tag_prio_tagging; 424 #define ICE_AQ_VLAN_PRIO_TAG_S 0 425 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 426 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 427 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 428 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 429 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 430 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 431 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 432 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 433 u8 l2tag_reserved[64]; 434 u8 rdma_packet; 435 #define ICE_AQ_VLAN_RDMA_TAG_S 0 436 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 437 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 438 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 439 u8 rdma_reserved[2]; 440 u8 mng_vlan_prot_id; 441 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 442 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 443 u8 prot_id_reserved[30]; 444 }; 445 446 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 447 struct ice_aqc_get_vlan_mode { 448 u8 vlan_mode; 449 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 450 u8 l2tag_prio_tagging; 451 u8 reserved[98]; 452 }; 453 454 /* Add VSI (indirect 0x0210) 455 * Update VSI (indirect 0x0211) 456 * Get VSI (indirect 0x0212) 457 * Free VSI (indirect 0x0213) 458 */ 459 struct ice_aqc_add_get_update_free_vsi { 460 __le16 vsi_num; 461 #define ICE_AQ_VSI_NUM_S 0 462 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 463 #define ICE_AQ_VSI_IS_VALID BIT(15) 464 __le16 cmd_flags; 465 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 466 u8 vf_id; 467 u8 reserved; 468 __le16 vsi_flags; 469 #define ICE_AQ_VSI_TYPE_S 0 470 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 471 #define ICE_AQ_VSI_TYPE_VF 0x0 472 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 473 #define ICE_AQ_VSI_TYPE_PF 0x2 474 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 475 __le32 addr_high; 476 __le32 addr_low; 477 }; 478 479 /* Response descriptor for: 480 * Add VSI (indirect 0x0210) 481 * Update VSI (indirect 0x0211) 482 * Free VSI (indirect 0x0213) 483 */ 484 struct ice_aqc_add_update_free_vsi_resp { 485 __le16 vsi_num; 486 __le16 ext_status; 487 __le16 vsi_used; 488 __le16 vsi_free; 489 __le32 addr_high; 490 __le32 addr_low; 491 }; 492 493 struct ice_aqc_get_vsi_resp { 494 __le16 vsi_num; 495 u8 vf_id; 496 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 497 * These are found above in struct ice_aqc_add_get_update_free_vsi. 498 */ 499 u8 vsi_flags; 500 __le16 vsi_used; 501 __le16 vsi_free; 502 __le32 addr_high; 503 __le32 addr_low; 504 }; 505 506 struct ice_aqc_vsi_props { 507 __le16 valid_sections; 508 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 509 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 510 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 511 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 512 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 513 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 514 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 515 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 516 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 517 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 518 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 519 /* switch section */ 520 u8 sw_id; 521 u8 sw_flags; 522 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 523 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 524 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 525 u8 sw_flags2; 526 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 527 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 528 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 529 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 530 u8 veb_stat_id; 531 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 532 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 533 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 534 /* security section */ 535 u8 sec_flags; 536 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 537 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 538 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 539 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 540 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 541 u8 sec_reserved; 542 /* VLAN section */ 543 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 544 u8 inner_vlan_reserved[2]; 545 u8 inner_vlan_flags; 546 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 547 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 548 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 549 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 550 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 551 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 552 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 553 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 554 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 555 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 556 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 557 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 558 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 559 u8 inner_vlan_reserved2[3]; 560 /* ingress egress up sections */ 561 __le32 ingress_table; /* bitmap, 3 bits per up */ 562 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 563 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 564 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 565 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 566 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 567 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 568 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 569 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 570 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 571 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 572 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 573 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 574 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 575 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 576 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 577 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 578 __le32 egress_table; /* same defines as for ingress table */ 579 /* outer tags section */ 580 __le16 port_based_outer_vlan; 581 u8 outer_vlan_flags; 582 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 583 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 584 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 585 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 586 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 587 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 588 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 589 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 590 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 591 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 592 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 593 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 594 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 595 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 596 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 597 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 598 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 599 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 600 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 601 u8 outer_vlan_reserved; 602 /* queue mapping section */ 603 __le16 mapping_flags; 604 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 605 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 606 __le16 q_mapping[16]; 607 #define ICE_AQ_VSI_Q_S 0 608 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 609 __le16 tc_mapping[8]; 610 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 611 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 612 #define ICE_AQ_VSI_TC_Q_NUM_S 11 613 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 614 /* queueing option section */ 615 u8 q_opt_rss; 616 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 617 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 618 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 619 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 620 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 621 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 622 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 623 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 624 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 625 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 626 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 627 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 628 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 629 u8 q_opt_tc; 630 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 631 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 632 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 633 u8 q_opt_flags; 634 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 635 u8 q_opt_reserved[3]; 636 /* outer up section */ 637 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 638 /* section 10 */ 639 __le16 sect_10_reserved; 640 /* flow director section */ 641 __le16 fd_options; 642 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 643 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 644 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 645 __le16 max_fd_fltr_dedicated; 646 __le16 max_fd_fltr_shared; 647 __le16 fd_def_q; 648 #define ICE_AQ_VSI_FD_DEF_Q_S 0 649 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 650 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 651 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 652 __le16 fd_report_opt; 653 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 654 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 655 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 656 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 657 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 658 /* PASID section */ 659 __le32 pasid_id; 660 #define ICE_AQ_VSI_PASID_ID_S 0 661 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 662 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 663 u8 reserved[24]; 664 }; 665 666 /* Add/update mirror rule - direct (0x0260) */ 667 #define ICE_AQC_RULE_ID_VALID_S 7 668 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 669 #define ICE_AQC_RULE_ID_S 0 670 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 671 672 /* Following defines to be used while processing caller specified mirror list 673 * of VSI indexes. 674 */ 675 /* Action: Byte.bit (1.7) 676 * 0 = Remove VSI from mirror rule 677 * 1 = Add VSI to mirror rule 678 */ 679 #define ICE_AQC_RULE_ACT_S 15 680 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 681 /* Action: 1.2:0.0 = Mirrored VSI */ 682 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 683 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 684 685 /* This is to be used by add/update mirror rule Admin Queue command. 686 * In case of add mirror rule - if rule ID is specified as 687 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 688 * If specified rule_id is valid, then it is used. If specified rule_id 689 * is in use then new mirroring rule is added. 690 */ 691 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 692 693 struct ice_aqc_add_update_mir_rule { 694 __le16 rule_id; 695 696 __le16 rule_type; 697 #define ICE_AQC_RULE_TYPE_S 0 698 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 699 /* VPORT ingress/egress */ 700 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 701 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 702 /* Physical port ingress mirroring. 703 * All traffic received by this port 704 */ 705 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 706 /* Physical port egress mirroring. All traffic sent by this port */ 707 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 708 709 /* Number of mirrored entries. 710 * The values are in the command buffer 711 */ 712 __le16 num_entries; 713 714 /* Destination VSI */ 715 __le16 dest; 716 __le32 addr_high; 717 __le32 addr_low; 718 }; 719 720 /* Delete mirror rule - direct(0x0261) */ 721 struct ice_aqc_delete_mir_rule { 722 __le16 rule_id; 723 __le16 rsvd; 724 725 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 726 * the PF allocated resources, otherwise it is returned to the 727 * shared pool 728 */ 729 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 730 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 731 __le16 flags; 732 733 u8 reserved[10]; 734 }; 735 736 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 737 /* This structure holds get storm configuration response and same structure 738 * is used to perform set_storm_cfg 739 */ 740 struct ice_aqc_storm_cfg { 741 __le32 bcast_thresh_size; 742 __le32 mcast_thresh_size; 743 /* Bit 18:0 - Traffic upper threshold size 744 * Bit 31:19 - Reserved 745 */ 746 #define ICE_AQ_THRESHOLD_S 0 747 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 748 749 __le32 storm_ctrl_ctrl; 750 /* Bit 0: MDIPW - Drop Multicast packets in previous window 751 * Bit 1: MDICW - Drop multicast packets in current window 752 * Bit 2: BDIPW - Drop broadcast packets in previous window 753 * Bit 3: BDICW - Drop broadcast packets in current window 754 */ 755 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 756 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 757 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 758 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 759 /* Bit 7:5 : Reserved */ 760 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 761 * interval size for applying ingress broadcast or multicast storm 762 * control. 763 */ 764 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 765 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 766 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 767 __le32 reserved; 768 }; 769 770 #define ICE_MAX_NUM_RECIPES 64 771 772 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 773 */ 774 struct ice_aqc_sw_rules { 775 /* ops: add switch rules, referring the number of rules. 776 * ops: update switch rules, referring the number of filters 777 * ops: remove switch rules, referring the entry index. 778 * ops: get switch rules, referring to the number of filters. 779 */ 780 __le16 num_rules_fltr_entry_index; 781 u8 reserved[6]; 782 __le32 addr_high; 783 __le32 addr_low; 784 }; 785 786 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 787 * This structures describes the lookup rules and associated actions. "index" 788 * is returned as part of a response to a successful Add command, and can be 789 * used to identify the rule for Update/Get/Remove commands. 790 */ 791 struct ice_sw_rule_lkup_rx_tx { 792 __le16 recipe_id; 793 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 794 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 795 __le16 src; 796 __le32 act; 797 798 /* Bit 0:1 - Action type */ 799 #define ICE_SINGLE_ACT_TYPE_S 0x00 800 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 801 802 /* Bit 2 - Loop back enable 803 * Bit 3 - LAN enable 804 */ 805 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 806 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 807 808 /* Action type = 0 - Forward to VSI or VSI list */ 809 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 810 811 #define ICE_SINGLE_ACT_VSI_ID_S 4 812 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 813 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 814 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 815 /* This bit needs to be set if action is forward to VSI list */ 816 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 817 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 818 #define ICE_SINGLE_ACT_DROP BIT(18) 819 820 /* Action type = 1 - Forward to Queue of Queue group */ 821 #define ICE_SINGLE_ACT_TO_Q 0x1 822 #define ICE_SINGLE_ACT_Q_INDEX_S 4 823 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 824 #define ICE_SINGLE_ACT_Q_REGION_S 15 825 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 826 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 827 828 /* Action type = 2 - Prune */ 829 #define ICE_SINGLE_ACT_PRUNE 0x2 830 #define ICE_SINGLE_ACT_EGRESS BIT(15) 831 #define ICE_SINGLE_ACT_INGRESS BIT(16) 832 #define ICE_SINGLE_ACT_PRUNET BIT(17) 833 /* Bit 18 should be set to 0 for this action */ 834 835 /* Action type = 2 - Pointer */ 836 #define ICE_SINGLE_ACT_PTR 0x2 837 #define ICE_SINGLE_ACT_PTR_VAL_S 4 838 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 839 /* Bit 18 should be set to 1 */ 840 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 841 842 /* Action type = 3 - Other actions. Last two bits 843 * are other action identifier 844 */ 845 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 846 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 847 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 848 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 849 850 /* Bit 17:18 - Defines other actions */ 851 /* Other action = 0 - Mirror VSI */ 852 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 853 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 854 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 855 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 856 857 /* Other action = 3 - Set Stat count */ 858 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 859 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 860 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 861 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 862 863 __le16 index; /* The index of the rule in the lookup table */ 864 /* Length and values of the header to be matched per recipe or 865 * lookup-type 866 */ 867 __le16 hdr_len; 868 u8 hdr[STRUCT_HACK_VAR_LEN]; 869 }; 870 871 /* Add/Update/Remove large action command/response entry 872 * "index" is returned as part of a response to a successful Add command, and 873 * can be used to identify the action for Update/Get/Remove commands. 874 */ 875 struct ice_sw_rule_lg_act { 876 __le16 index; /* Index in large action table */ 877 __le16 size; 878 /* Max number of large actions */ 879 #define ICE_MAX_LG_ACT 4 880 /* Bit 0:1 - Action type */ 881 #define ICE_LG_ACT_TYPE_S 0 882 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 883 884 /* Action type = 0 - Forward to VSI or VSI list */ 885 #define ICE_LG_ACT_VSI_FORWARDING 0 886 #define ICE_LG_ACT_VSI_ID_S 3 887 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 888 #define ICE_LG_ACT_VSI_LIST_ID_S 3 889 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 890 /* This bit needs to be set if action is forward to VSI list */ 891 #define ICE_LG_ACT_VSI_LIST BIT(13) 892 893 #define ICE_LG_ACT_VALID_BIT BIT(16) 894 895 /* Action type = 1 - Forward to Queue of Queue group */ 896 #define ICE_LG_ACT_TO_Q 0x1 897 #define ICE_LG_ACT_Q_INDEX_S 3 898 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 899 #define ICE_LG_ACT_Q_REGION_S 14 900 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 901 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 902 903 /* Action type = 2 - Prune */ 904 #define ICE_LG_ACT_PRUNE 0x2 905 #define ICE_LG_ACT_EGRESS BIT(14) 906 #define ICE_LG_ACT_INGRESS BIT(15) 907 #define ICE_LG_ACT_PRUNET BIT(16) 908 909 /* Action type = 3 - Mirror VSI */ 910 #define ICE_LG_OTHER_ACT_MIRROR 0x3 911 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 912 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 913 914 /* Action type = 5 - Generic Value */ 915 #define ICE_LG_ACT_GENERIC 0x5 916 #define ICE_LG_ACT_GENERIC_VALUE_S 3 917 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 918 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 919 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 920 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 921 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 922 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 923 924 /* Action = 7 - Set Stat count */ 925 #define ICE_LG_ACT_STAT_COUNT 0x7 926 #define ICE_LG_ACT_STAT_COUNT_S 3 927 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 928 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 929 }; 930 931 /* Add/Update/Remove VSI list command/response entry 932 * "index" is returned as part of a response to a successful Add command, and 933 * can be used to identify the VSI list for Update/Get/Remove commands. 934 */ 935 struct ice_sw_rule_vsi_list { 936 __le16 index; /* Index of VSI/Prune list */ 937 __le16 number_vsi; 938 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 939 }; 940 941 #pragma pack(1) 942 /* Query VSI list command/response entry */ 943 struct ice_sw_rule_vsi_list_query { 944 __le16 index; 945 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 946 }; 947 #pragma pack() 948 949 #pragma pack(1) 950 /* Add switch rule response: 951 * Content of return buffer is same as the input buffer. The status field and 952 * LUT index are updated as part of the response 953 */ 954 struct ice_aqc_sw_rules_elem { 955 __le16 type; /* Switch rule type, one of T_... */ 956 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 957 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 958 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 959 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 960 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 961 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 962 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 963 __le16 status; 964 union { 965 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 966 struct ice_sw_rule_lg_act lg_act; 967 struct ice_sw_rule_vsi_list vsi_list; 968 struct ice_sw_rule_vsi_list_query vsi_list_query; 969 } pdata; 970 }; 971 972 #pragma pack() 973 974 /* PFC Ignore (direct 0x0301) 975 * The command and response use the same descriptor structure 976 */ 977 struct ice_aqc_pfc_ignore { 978 u8 tc_bitmap; 979 u8 cmd_flags; /* unused in response */ 980 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 981 #define ICE_AQC_PFC_IGNORE_CLEAR 0 982 u8 reserved[14]; 983 }; 984 985 /* Set PFC Mode (direct 0x0303) 986 * Query PFC Mode (direct 0x0302) 987 */ 988 struct ice_aqc_set_query_pfc_mode { 989 u8 pfc_mode; 990 /* For Set Command response, reserved in all other cases */ 991 #define ICE_AQC_PFC_NOT_CONFIGURED 0 992 /* For Query Command response, reserved in all other cases */ 993 #define ICE_AQC_DCB_DIS 0 994 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 995 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 996 u8 rsvd[15]; 997 }; 998 999 /* Set DCB Parameters (direct 0x0306) */ 1000 struct ice_aqc_set_dcb_params { 1001 u8 cmd_flags; /* unused in response */ 1002 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 1003 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 1004 u8 valid_flags; /* unused in response */ 1005 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1006 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 1007 u8 rsvd[14]; 1008 }; 1009 1010 /* Get Default Topology (indirect 0x0400) */ 1011 struct ice_aqc_get_topo { 1012 u8 port_num; 1013 u8 num_branches; 1014 __le16 reserved1; 1015 __le32 reserved2; 1016 __le32 addr_high; 1017 __le32 addr_low; 1018 }; 1019 1020 /* Update TSE (indirect 0x0403) 1021 * Get TSE (indirect 0x0404) 1022 * Add TSE (indirect 0x0401) 1023 * Delete TSE (indirect 0x040F) 1024 * Move TSE (indirect 0x0408) 1025 * Suspend Nodes (indirect 0x0409) 1026 * Resume Nodes (indirect 0x040A) 1027 */ 1028 struct ice_aqc_sched_elem_cmd { 1029 __le16 num_elem_req; /* Used by commands */ 1030 __le16 num_elem_resp; /* Used by responses */ 1031 __le32 reserved; 1032 __le32 addr_high; 1033 __le32 addr_low; 1034 }; 1035 1036 struct ice_aqc_txsched_move_grp_info_hdr { 1037 __le32 src_parent_teid; 1038 __le32 dest_parent_teid; 1039 __le16 num_elems; 1040 u8 flags; 1041 u8 reserved; 1042 }; 1043 1044 struct ice_aqc_move_elem { 1045 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1046 __le32 teid[STRUCT_HACK_VAR_LEN]; 1047 }; 1048 1049 struct ice_aqc_elem_info_bw { 1050 __le16 bw_profile_idx; 1051 __le16 bw_alloc; 1052 }; 1053 1054 struct ice_aqc_txsched_elem { 1055 u8 elem_type; /* Special field, reserved for some aq calls */ 1056 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1057 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1058 #define ICE_AQC_ELEM_TYPE_TC 0x2 1059 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1060 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1061 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1062 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1063 u8 valid_sections; 1064 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1065 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1066 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1067 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1068 u8 generic; 1069 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1070 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1071 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1072 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1073 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1074 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1075 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1076 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1077 u8 flags; /* Special field, reserved for some aq calls */ 1078 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1079 struct ice_aqc_elem_info_bw cir_bw; 1080 struct ice_aqc_elem_info_bw eir_bw; 1081 __le16 srl_id; 1082 __le16 reserved2; 1083 }; 1084 1085 struct ice_aqc_txsched_elem_data { 1086 __le32 parent_teid; 1087 __le32 node_teid; 1088 struct ice_aqc_txsched_elem data; 1089 }; 1090 1091 struct ice_aqc_txsched_topo_grp_info_hdr { 1092 __le32 parent_teid; 1093 __le16 num_elems; 1094 __le16 reserved2; 1095 }; 1096 1097 struct ice_aqc_add_elem { 1098 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1099 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1100 }; 1101 1102 struct ice_aqc_get_topo_elem { 1103 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1104 struct ice_aqc_txsched_elem_data 1105 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1106 }; 1107 1108 struct ice_aqc_delete_elem { 1109 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1110 __le32 teid[STRUCT_HACK_VAR_LEN]; 1111 }; 1112 1113 /* Query Port ETS (indirect 0x040E) 1114 * 1115 * This indirect command is used to query port TC node configuration. 1116 */ 1117 struct ice_aqc_query_port_ets { 1118 __le32 port_teid; 1119 __le32 reserved; 1120 __le32 addr_high; 1121 __le32 addr_low; 1122 }; 1123 1124 struct ice_aqc_port_ets_elem { 1125 u8 tc_valid_bits; 1126 u8 reserved[3]; 1127 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1128 __le32 up2tc; 1129 u8 tc_bw_share[8]; 1130 __le32 port_eir_prof_id; 1131 __le32 port_cir_prof_id; 1132 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1133 __le32 tc_node_prio; 1134 #define ICE_TC_NODE_PRIO_S 0x4 1135 u8 reserved1[4]; 1136 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1137 }; 1138 1139 /* Rate limiting profile for 1140 * Add RL profile (indirect 0x0410) 1141 * Query RL profile (indirect 0x0411) 1142 * Remove RL profile (indirect 0x0415) 1143 * These indirect commands acts on single or multiple 1144 * RL profiles with specified data. 1145 */ 1146 struct ice_aqc_rl_profile { 1147 __le16 num_profiles; 1148 __le16 num_processed; /* Only for response. Reserved in Command. */ 1149 u8 reserved[4]; 1150 __le32 addr_high; 1151 __le32 addr_low; 1152 }; 1153 1154 struct ice_aqc_rl_profile_elem { 1155 u8 level; 1156 u8 flags; 1157 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1158 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1159 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1160 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1161 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1162 /* The following flag is used for Query RL Profile Data */ 1163 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1164 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1165 1166 __le16 profile_id; 1167 __le16 max_burst_size; 1168 __le16 rl_multiply; 1169 __le16 wake_up_calc; 1170 __le16 rl_encode; 1171 }; 1172 1173 /* Configure L2 Node CGD (indirect 0x0414) 1174 * This indirect command allows configuring a congestion domain for given L2 1175 * node TEIDs in the scheduler topology. 1176 */ 1177 struct ice_aqc_cfg_l2_node_cgd { 1178 __le16 num_l2_nodes; 1179 u8 reserved[6]; 1180 __le32 addr_high; 1181 __le32 addr_low; 1182 }; 1183 1184 struct ice_aqc_cfg_l2_node_cgd_elem { 1185 __le32 node_teid; 1186 u8 cgd; 1187 u8 reserved[3]; 1188 }; 1189 1190 /* Query Scheduler Resource Allocation (indirect 0x0412) 1191 * This indirect command retrieves the scheduler resources allocated by 1192 * EMP Firmware to the given PF. 1193 */ 1194 struct ice_aqc_query_txsched_res { 1195 u8 reserved[8]; 1196 __le32 addr_high; 1197 __le32 addr_low; 1198 }; 1199 1200 struct ice_aqc_generic_sched_props { 1201 __le16 phys_levels; 1202 __le16 logical_levels; 1203 u8 flattening_bitmap; 1204 u8 max_device_cgds; 1205 u8 max_pf_cgds; 1206 u8 rsvd0; 1207 __le16 rdma_qsets; 1208 u8 rsvd1[22]; 1209 }; 1210 1211 struct ice_aqc_layer_props { 1212 u8 logical_layer; 1213 u8 chunk_size; 1214 __le16 max_device_nodes; 1215 __le16 max_pf_nodes; 1216 u8 rsvd0[4]; 1217 __le16 max_sibl_grp_sz; 1218 __le16 max_cir_rl_profiles; 1219 __le16 max_eir_rl_profiles; 1220 __le16 max_srl_profiles; 1221 u8 rsvd1[14]; 1222 }; 1223 1224 struct ice_aqc_query_txsched_res_resp { 1225 struct ice_aqc_generic_sched_props sched_props; 1226 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1227 }; 1228 1229 /* Query Node to Root Topology (indirect 0x0413) 1230 * This command uses ice_aqc_get_elem as its data buffer. 1231 */ 1232 struct ice_aqc_query_node_to_root { 1233 __le32 teid; 1234 __le32 num_nodes; /* Response only */ 1235 __le32 addr_high; 1236 __le32 addr_low; 1237 }; 1238 1239 /* Get PHY capabilities (indirect 0x0600) */ 1240 struct ice_aqc_get_phy_caps { 1241 u8 lport_num; 1242 u8 reserved; 1243 __le16 param0; 1244 /* 18.0 - Report qualified modules */ 1245 #define ICE_AQC_GET_PHY_RQM BIT(0) 1246 /* 18.1 - 18.3 : Report mode 1247 * 000b - Report topology capabilities, without media 1248 * 001b - Report topology capabilities, with media 1249 * 010b - Report Active configuration 1250 * 011b - Report PHY Type and FEC mode capabilities 1251 * 100b - Report Default capabilities 1252 */ 1253 #define ICE_AQC_REPORT_MODE_S 1 1254 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1255 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1256 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1257 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1258 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1259 __le32 reserved1; 1260 __le32 addr_high; 1261 __le32 addr_low; 1262 }; 1263 1264 /* This is #define of PHY type (Extended): 1265 * The first set of defines is for phy_type_low. 1266 */ 1267 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1268 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1269 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1270 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1271 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1272 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1273 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1274 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1275 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1276 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1277 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1278 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1279 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1280 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1281 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1282 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1283 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1284 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1285 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1286 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1287 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1288 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1289 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1290 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1291 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1292 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1293 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1294 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1295 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1296 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1297 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1298 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1299 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1300 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1301 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1302 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1303 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1304 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1305 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1306 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1307 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1308 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1309 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1310 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1311 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1312 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1313 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1314 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1315 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1316 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1317 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1318 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1319 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1320 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1321 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1322 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1323 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1324 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1325 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1326 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1327 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1328 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1329 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1330 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1331 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1332 /* The second set of defines is for phy_type_high. */ 1333 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1334 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1335 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1336 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1337 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1338 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1339 1340 struct ice_aqc_get_phy_caps_data { 1341 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1342 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1343 u8 caps; 1344 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1345 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1346 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1347 #define ICE_AQC_PHY_EN_LINK BIT(3) 1348 #define ICE_AQC_PHY_AN_MODE BIT(4) 1349 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1350 #define ICE_AQC_PHY_EN_LESM BIT(6) 1351 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1352 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1353 u8 low_power_ctrl_an; 1354 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1355 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1356 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1357 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1358 __le16 eee_cap; 1359 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1360 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1361 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1362 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1363 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1364 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1365 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1366 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1367 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1368 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1369 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1370 __le16 eeer_value; 1371 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1372 u8 phy_fw_ver[8]; 1373 u8 link_fec_options; 1374 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1375 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1376 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1377 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1378 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1379 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1380 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1381 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1382 u8 module_compliance_enforcement; 1383 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1384 u8 extended_compliance_code; 1385 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1386 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1387 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1388 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1389 #define ICE_AQC_MOD_TYPE_IDENT 1 1390 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1391 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1392 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1393 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1394 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1395 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1396 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1397 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1398 u8 qualified_module_count; 1399 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1400 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1401 struct { 1402 u8 v_oui[3]; 1403 u8 rsvd3; 1404 u8 v_part[16]; 1405 __le32 v_rev; 1406 __le64 rsvd4; 1407 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1408 }; 1409 1410 /* Set PHY capabilities (direct 0x0601) 1411 * NOTE: This command must be followed by setup link and restart auto-neg 1412 */ 1413 struct ice_aqc_set_phy_cfg { 1414 u8 lport_num; 1415 u8 reserved[7]; 1416 __le32 addr_high; 1417 __le32 addr_low; 1418 }; 1419 1420 /* Set PHY config command data structure */ 1421 struct ice_aqc_set_phy_cfg_data { 1422 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1423 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1424 u8 caps; 1425 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1426 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1427 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1428 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1429 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1430 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1431 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1432 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1433 u8 low_power_ctrl_an; 1434 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1435 __le16 eeer_value; 1436 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1437 u8 module_compliance_enforcement; 1438 }; 1439 1440 /* Set MAC Config command data structure (direct 0x0603) */ 1441 struct ice_aqc_set_mac_cfg { 1442 __le16 max_frame_size; 1443 u8 params; 1444 #define ICE_AQ_SET_MAC_PACE_S 3 1445 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1446 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1447 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1448 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1449 u8 tx_tmr_priority; 1450 __le16 tx_tmr_value; 1451 __le16 fc_refresh_threshold; 1452 u8 drop_opts; 1453 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1454 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1455 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1456 u8 reserved[7]; 1457 }; 1458 1459 /* Restart AN command data structure (direct 0x0605) 1460 * Also used for response, with only the lport_num field present. 1461 */ 1462 struct ice_aqc_restart_an { 1463 u8 lport_num; 1464 u8 reserved; 1465 u8 cmd_flags; 1466 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1467 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1468 u8 reserved2[13]; 1469 }; 1470 1471 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1472 struct ice_aqc_get_link_status { 1473 u8 lport_num; 1474 u8 reserved; 1475 __le16 cmd_flags; 1476 #define ICE_AQ_LSE_M 0x3 1477 #define ICE_AQ_LSE_NOP 0x0 1478 #define ICE_AQ_LSE_DIS 0x2 1479 #define ICE_AQ_LSE_ENA 0x3 1480 /* only response uses this flag */ 1481 #define ICE_AQ_LSE_IS_ENABLED 0x1 1482 __le32 reserved2; 1483 __le32 addr_high; 1484 __le32 addr_low; 1485 }; 1486 1487 /* Get link status response data structure, also used for Link Status Event */ 1488 struct ice_aqc_get_link_status_data { 1489 u8 topo_media_conflict; 1490 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1491 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1492 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1493 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1494 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1495 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1496 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1497 u8 link_cfg_err; 1498 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1499 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1500 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1501 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1502 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1503 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1504 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1505 u8 link_info; 1506 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1507 #define ICE_AQ_LINK_FAULT BIT(1) 1508 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1509 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1510 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1511 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1512 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1513 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1514 u8 an_info; 1515 #define ICE_AQ_AN_COMPLETED BIT(0) 1516 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1517 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1518 #define ICE_AQ_FEC_EN BIT(3) 1519 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1520 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1521 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1522 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1523 u8 ext_info; 1524 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1525 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1526 /* Port Tx Suspended */ 1527 #define ICE_AQ_LINK_TX_S 2 1528 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1529 #define ICE_AQ_LINK_TX_ACTIVE 0 1530 #define ICE_AQ_LINK_TX_DRAINED 1 1531 #define ICE_AQ_LINK_TX_FLUSHED 3 1532 u8 lb_status; 1533 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1534 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1535 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1536 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1537 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1538 __le16 max_frame_size; 1539 u8 cfg; 1540 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1541 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1542 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1543 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1544 /* Pacing Config */ 1545 #define ICE_AQ_CFG_PACING_S 3 1546 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1547 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1548 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1549 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1550 /* External Device Power Ability */ 1551 u8 power_desc; 1552 #define ICE_AQ_PWR_CLASS_M 0x3F 1553 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1554 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1555 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1556 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1557 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1558 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1559 __le16 link_speed; 1560 #define ICE_AQ_LINK_SPEED_M 0x7FF 1561 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1562 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1563 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1564 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1565 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1566 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1567 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1568 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1569 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1570 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1571 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1572 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1573 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1574 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1575 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1576 }; 1577 1578 /* Set event mask command (direct 0x0613) */ 1579 struct ice_aqc_set_event_mask { 1580 u8 lport_num; 1581 u8 reserved[7]; 1582 __le16 event_mask; 1583 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1584 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1585 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1586 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1587 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1588 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1589 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1590 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1591 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1592 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1593 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1594 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1595 u8 reserved1[6]; 1596 }; 1597 1598 /* Set PHY Loopback command (direct 0x0619) */ 1599 struct ice_aqc_set_phy_lb { 1600 u8 lport_num; 1601 u8 lport_num_valid; 1602 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0) 1603 u8 phy_index; 1604 u8 lb_mode; 1605 #define ICE_AQ_PHY_LB_EN BIT(0) 1606 #define ICE_AQ_PHY_LB_TYPE_M BIT(1) 1607 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0 1608 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M 1609 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2) 1610 #define ICE_AQ_PHY_LB_LEVEL_PMD 0 1611 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M 1612 u8 reserved2[12]; 1613 }; 1614 1615 /* Set MAC Loopback command (direct 0x0620) */ 1616 struct ice_aqc_set_mac_lb { 1617 u8 lb_mode; 1618 #define ICE_AQ_MAC_LB_EN BIT(0) 1619 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1620 u8 reserved[15]; 1621 }; 1622 1623 /* DNL Get Status command (indirect 0x0680) 1624 * Structure used for the response, the command uses the generic 1625 * ice_aqc_generic struct to pass a buffer address to the FW. 1626 */ 1627 struct ice_aqc_dnl_get_status { 1628 u8 ctx; 1629 u8 status; 1630 #define ICE_AQ_DNL_STATUS_IDLE 0x0 1631 #define ICE_AQ_DNL_STATUS_RESERVED 0x1 1632 #define ICE_AQ_DNL_STATUS_STOPPED 0x2 1633 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */ 1634 #define ICE_AQ_DNL_SRC_S 3 1635 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S) 1636 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S) 1637 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S) 1638 u8 stack_ptr; 1639 #define ICE_AQ_DNL_ST_PTR_S 0x0 1640 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S) 1641 u8 engine_flags; 1642 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2) 1643 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3) 1644 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4) 1645 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5) 1646 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6) 1647 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7) 1648 __le16 pc; 1649 __le16 activity_id; 1650 __le32 addr_high; 1651 __le32 addr_low; 1652 }; 1653 1654 struct ice_aqc_dnl_get_status_data { 1655 __le16 activity_err_code; 1656 __le16 act_err_code; 1657 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */ 1658 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */ 1659 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */ 1660 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */ 1661 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */ 1662 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */ 1663 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */ 1664 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */ 1665 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */ 1666 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */ 1667 __le32 execution_time; /* in nanoseconds */ 1668 __le16 lib_ver; 1669 u8 psto_local_sz; 1670 u8 psto_global_sz; 1671 u8 stack_sz; 1672 #define ICE_AQ_DNL_STACK_SZ_S 0 1673 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S) 1674 u8 port_count; 1675 #define ICE_AQ_DNL_PORT_CNT_S 0 1676 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S) 1677 __le16 act_cache_cntr; 1678 u32 i2c_clk_cntr; 1679 u32 mdio_clk_cntr; 1680 u32 sb_iosf_clk_cntr; 1681 }; 1682 1683 /* DNL run command (direct 0x0681) */ 1684 struct ice_aqc_dnl_run_command { 1685 u8 reserved0; 1686 u8 command; 1687 #define ICE_AQ_DNL_CMD_S 0 1688 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S) 1689 #define ICE_AQ_DNL_CMD_RESET 0x0 1690 #define ICE_AQ_DNL_CMD_RUN 0x1 1691 #define ICE_AQ_DNL_CMD_STEP 0x3 1692 #define ICE_AQ_DNL_CMD_ABORT 0x4 1693 #define ICE_AQ_DNL_CMD_SET_PC 0x7 1694 #define ICE_AQ_DNL_CMD_SRC_S 3 1695 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S) 1696 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0 1697 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1 1698 __le16 new_pc; 1699 u8 reserved1[12]; 1700 }; 1701 1702 /* DNL call command (indirect 0x0682) 1703 * Struct is used for both command and response 1704 */ 1705 struct ice_aqc_dnl_call_command { 1706 u8 ctx; /* Used in command, reserved in response */ 1707 u8 reserved; 1708 __le16 activity_id; 1709 __le32 reserved1; 1710 __le32 addr_high; 1711 __le32 addr_low; 1712 }; 1713 1714 /* DNL call command/response buffer (indirect 0x0682) */ 1715 struct ice_aqc_dnl_call { 1716 __le32 stores[4]; 1717 }; 1718 1719 /* Used for both commands: 1720 * DNL read sto command (indirect 0x0683) 1721 * DNL write sto command (indirect 0x0684) 1722 */ 1723 struct ice_aqc_dnl_read_write_command { 1724 u8 ctx; 1725 u8 sto_sel; /* STORE select */ 1726 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0 1727 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1 1728 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2 1729 __le16 offset; 1730 __le32 data; /* Used for write sto only */ 1731 __le32 addr_high; /* Used for read sto only */ 1732 __le32 addr_low; /* Used for read sto only */ 1733 }; 1734 1735 /* Used for both command responses: 1736 * DNL read sto response (indirect 0x0683) 1737 * DNL write sto response (indirect 0x0684) 1738 */ 1739 struct ice_aqc_dnl_read_write_response { 1740 u8 reserved; 1741 u8 status; /* Reserved for read command */ 1742 __le16 size; /* Reserved for write command */ 1743 __le32 data; /* Reserved for write command */ 1744 __le32 addr_high; /* Reserved for write command */ 1745 __le32 addr_low; /* Reserved for write command */ 1746 }; 1747 1748 /* DNL set breakpoints command (indirect 0x0686) */ 1749 struct ice_aqc_dnl_set_breakpoints_command { 1750 __le32 reserved[2]; 1751 __le32 addr_high; 1752 __le32 addr_low; 1753 }; 1754 1755 /* DNL set breakpoints data buffer structure (indirect 0x0686) */ 1756 struct ice_aqc_dnl_set_breakpoints { 1757 u8 ctx; 1758 u8 ena; /* 0- disabled, 1- enabled */ 1759 __le16 offset; 1760 __le16 activity_id; 1761 }; 1762 1763 /* DNL read log data command(indirect 0x0687) */ 1764 struct ice_aqc_dnl_read_log_command { 1765 __le16 reserved0; 1766 __le16 offset; 1767 __le32 reserved1; 1768 __le32 addr_high; 1769 __le32 addr_low; 1770 1771 }; 1772 1773 /* DNL read log data response(indirect 0x0687) */ 1774 struct ice_aqc_dnl_read_log_response { 1775 __le16 reserved; 1776 __le16 size; 1777 __le32 data; 1778 __le32 addr_high; 1779 __le32 addr_low; 1780 1781 }; 1782 1783 struct ice_aqc_link_topo_params { 1784 u8 lport_num; 1785 u8 lport_num_valid; 1786 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1787 u8 node_type_ctx; 1788 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1789 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1790 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1791 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1792 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1793 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1794 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1795 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1796 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1797 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1798 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1799 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1800 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1801 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1802 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1803 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1804 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1805 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1806 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1807 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1808 u8 index; 1809 }; 1810 1811 struct ice_aqc_link_topo_addr { 1812 struct ice_aqc_link_topo_params topo_params; 1813 __le16 handle; 1814 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1815 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1816 /* Used to decode the handle field */ 1817 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1818 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1819 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1820 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1821 /* In case of a Mezzanine type */ 1822 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1823 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1824 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1825 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1826 /* In case of a LOM type */ 1827 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1828 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1829 }; 1830 1831 /* Get Link Topology Handle (direct, 0x06E0) */ 1832 struct ice_aqc_get_link_topo { 1833 struct ice_aqc_link_topo_addr addr; 1834 u8 node_part_num; 1835 #define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1836 u8 rsvd[9]; 1837 }; 1838 1839 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1840 struct ice_aqc_i2c { 1841 struct ice_aqc_link_topo_addr topo_addr; 1842 __le16 i2c_addr; 1843 u8 i2c_params; 1844 #define ICE_AQC_I2C_DATA_SIZE_S 0 1845 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 1846 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 1847 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 1848 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 1849 #define ICE_AQC_I2C_DATA_OFFSET_S 5 1850 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 1851 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1852 u8 rsvd; 1853 __le16 i2c_bus_addr; 1854 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 1855 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 1856 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1857 }; 1858 1859 /* Read I2C Response (direct, 0x06E2) */ 1860 struct ice_aqc_read_i2c_resp { 1861 u8 i2c_data[16]; 1862 }; 1863 1864 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 1865 struct ice_aqc_mdio { 1866 struct ice_aqc_link_topo_addr topo_addr; 1867 u8 mdio_device_addr; 1868 #define ICE_AQC_MDIO_DEV_S 0 1869 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S) 1870 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5) 1871 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6) 1872 u8 mdio_bus_address; 1873 #define ICE_AQC_MDIO_BUS_ADDR_S 0 1874 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S) 1875 __le16 offset; 1876 __le16 data; /* Input in write cmd, output in read cmd. */ 1877 u8 rsvd1[4]; 1878 }; 1879 1880 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 1881 struct ice_aqc_gpio_by_func { 1882 struct ice_aqc_link_topo_addr topo_addr; 1883 u8 io_func_num; 1884 #define ICE_AQC_GPIO_FUNC_S 0 1885 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S) 1886 u8 io_value; /* Input in write cmd, output in read cmd. */ 1887 #define ICE_AQC_GPIO_ON BIT(0) 1888 #define ICE_AQC_GPIO_OFF 0 1889 u8 rsvd[8]; 1890 }; 1891 1892 /* Set LED (direct, 0x06E8) */ 1893 struct ice_aqc_set_led { 1894 struct ice_aqc_link_topo_addr topo_addr; 1895 u8 color_and_blink; 1896 #define ICE_AQC_LED_COLOR_S 0 1897 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S) 1898 #define ICE_AQC_LED_COLOR_SKIP 0 1899 #define ICE_AQC_LED_COLOR_RED 1 1900 #define ICE_AQC_LED_COLOR_ORANGE 2 1901 #define ICE_AQC_LED_COLOR_YELLOW 3 1902 #define ICE_AQC_LED_COLOR_GREEN 4 1903 #define ICE_AQC_LED_COLOR_BLUE 5 1904 #define ICE_AQC_LED_COLOR_PURPLE 6 1905 #define ICE_AQC_LED_BLINK_S 3 1906 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S) 1907 #define ICE_AQC_LED_BLINK_NONE 0 1908 #define ICE_AQC_LED_BLINK_SLOW 1 1909 #define ICE_AQC_LED_BLINK_SLOW_MAC 2 1910 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3 1911 #define ICE_AQC_LED_BLINK_FAST 5 1912 #define ICE_AQC_LED_BLINK_FAST_MAC 6 1913 #define ICE_AQC_LED_BLINK_FAST_FLTR 7 1914 u8 rsvd[9]; 1915 }; 1916 1917 /* Set Port Identification LED (direct, 0x06E9) */ 1918 struct ice_aqc_set_port_id_led { 1919 u8 lport_num; 1920 u8 lport_num_valid; 1921 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1922 u8 ident_mode; 1923 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1924 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1925 u8 rsvd[13]; 1926 }; 1927 1928 /* Get Port Options (indirect, 0x06EA) */ 1929 struct ice_aqc_get_port_options { 1930 u8 lport_num; 1931 u8 lport_num_valid; 1932 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0) 1933 u8 port_options_count; 1934 #define ICE_AQC_PORT_OPT_COUNT_S 0 1935 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) 1936 u8 innermost_phy_index; 1937 u8 port_options; 1938 #define ICE_AQC_PORT_OPT_ACTIVE_S 0 1939 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) 1940 #define ICE_AQC_PORT_OPT_FORCED BIT(6) 1941 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1942 u8 pending_port_option_status; 1943 #define ICE_AQC_PENDING_PORT_OPT_IDX_S 0 1944 #define ICE_AQC_PENDING_PORT_OPT_IDX_M (0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S) 1945 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1946 u8 rsvd[2]; 1947 __le32 addr_high; 1948 __le32 addr_low; 1949 }; 1950 1951 struct ice_aqc_get_port_options_elem { 1952 u8 pmd; 1953 #define ICE_AQC_PORT_INV_PORT_OPT 4 1954 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 1955 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) 1956 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 1957 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) 1958 u8 max_lane_speed; 1959 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 1960 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) 1961 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1962 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1963 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1964 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1965 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1966 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1967 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1968 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1969 u8 global_scid[2]; 1970 u8 phy_scid[2]; 1971 u8 pf2port_cid[2]; 1972 }; 1973 1974 /* Set Port Option (direct, 0x06EB) */ 1975 struct ice_aqc_set_port_option { 1976 u8 lport_num; 1977 u8 lport_num_valid; 1978 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) 1979 u8 selected_port_option; 1980 u8 rsvd[13]; 1981 }; 1982 1983 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1984 struct ice_aqc_gpio { 1985 __le16 gpio_ctrl_handle; 1986 #define ICE_AQC_GPIO_HANDLE_S 0 1987 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1988 u8 gpio_num; 1989 u8 gpio_val; 1990 u8 rsvd[12]; 1991 }; 1992 1993 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1994 struct ice_aqc_sff_eeprom { 1995 u8 lport_num; 1996 u8 lport_num_valid; 1997 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1998 __le16 i2c_bus_addr; 1999 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 2000 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 2001 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 2002 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 2003 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 2004 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 2005 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 2006 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 2007 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 2008 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 2009 #define ICE_AQC_SFF_IS_WRITE BIT(15) 2010 __le16 i2c_mem_addr; 2011 __le16 eeprom_page; 2012 #define ICE_AQC_SFF_EEPROM_BANK_S 0 2013 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 2014 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 2015 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 2016 __le32 addr_high; 2017 __le32 addr_low; 2018 }; 2019 2020 /* SW Set GPIO command (indirect 0x6EF) 2021 * SW Get GPIO command (indirect 0x6F0) 2022 */ 2023 struct ice_aqc_sw_gpio { 2024 __le16 gpio_ctrl_handle; 2025 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 2026 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 2027 u8 gpio_num; 2028 #define ICE_AQC_SW_GPIO_NUMBER_S 0 2029 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 2030 u8 gpio_params; 2031 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 2032 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 2033 u8 rsvd[12]; 2034 }; 2035 2036 /* Program Topology Device NVM (direct, 0x06F2) */ 2037 struct ice_aqc_prog_topo_dev_nvm { 2038 struct ice_aqc_link_topo_params topo_params; 2039 u8 rsvd[12]; 2040 }; 2041 2042 /* Read Topology Device NVM (direct, 0x06F3) */ 2043 struct ice_aqc_read_topo_dev_nvm { 2044 struct ice_aqc_link_topo_params topo_params; 2045 __le32 start_address; 2046 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8 2047 u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE]; 2048 }; 2049 2050 /* NVM Read command (indirect 0x0701) 2051 * NVM Erase commands (direct 0x0702) 2052 * NVM Write commands (indirect 0x0703) 2053 * NVM Write Activate commands (direct 0x0707) 2054 * NVM Shadow RAM Dump commands (direct 0x0707) 2055 */ 2056 struct ice_aqc_nvm { 2057 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 2058 __le16 offset_low; 2059 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 2060 u8 cmd_flags; 2061 #define ICE_AQC_NVM_LAST_CMD BIT(0) 2062 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 2063 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 2064 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 2065 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 2066 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 2067 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 2068 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 2069 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 2070 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 2071 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 2072 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 2073 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 2074 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 2075 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 2076 #define ICE_AQC_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */ 2077 #define ICE_AQC_NVM_POR_FLAG 0 2078 #define ICE_AQC_NVM_PERST_FLAG 1 2079 #define ICE_AQC_NVM_EMPR_FLAG 2 2080 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 2081 __le16 module_typeid; 2082 __le16 length; 2083 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 2084 __le32 addr_high; 2085 __le32 addr_low; 2086 }; 2087 2088 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 2089 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 2090 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 2091 2092 #define ICE_AQC_NVM_START_POINT 0 2093 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 2094 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 2095 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 2096 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 2097 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 2098 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 2099 2100 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 2101 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 2102 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2103 2104 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 2105 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 2106 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 2107 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 2108 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 2109 2110 #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130 2111 2112 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the 2113 * type field is excluded from the section when reading and writing from 2114 * a module using the module_typeid field with these AQ commands. 2115 */ 2116 struct ice_aqc_nvm_minsrev { 2117 __le16 length; 2118 __le16 validity; 2119 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0) 2120 #define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1) 2121 __le16 nvm_minsrev_l; 2122 __le16 nvm_minsrev_h; 2123 __le16 orom_minsrev_l; 2124 __le16 orom_minsrev_h; 2125 }; 2126 2127 /* Used for 0x0704 as well as for 0x0705 commands */ 2128 struct ice_aqc_nvm_cfg { 2129 u8 cmd_flags; 2130 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 2131 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 2132 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 2133 u8 reserved; 2134 __le16 count; 2135 __le16 id; 2136 u8 reserved1[2]; 2137 __le32 addr_high; 2138 __le32 addr_low; 2139 }; 2140 2141 struct ice_aqc_nvm_cfg_data { 2142 __le16 field_id; 2143 __le16 field_options; 2144 __le16 field_value; 2145 }; 2146 2147 /* NVM Checksum Command (direct, 0x0706) */ 2148 struct ice_aqc_nvm_checksum { 2149 u8 flags; 2150 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 2151 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 2152 u8 rsvd; 2153 __le16 checksum; /* Used only by response */ 2154 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 2155 u8 rsvd2[12]; 2156 }; 2157 2158 /* 2159 * Send to PF command (indirect 0x0801) ID is only used by PF 2160 * 2161 * Send to VF command (indirect 0x0802) ID is only used by PF 2162 * 2163 */ 2164 struct ice_aqc_pf_vf_msg { 2165 __le32 id; 2166 u32 reserved; 2167 __le32 addr_high; 2168 __le32 addr_low; 2169 }; 2170 2171 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 2172 struct ice_aqc_read_write_alt_direct { 2173 __le32 dword0_addr; 2174 __le32 dword0_value; 2175 __le32 dword1_addr; 2176 __le32 dword1_value; 2177 }; 2178 2179 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 2180 struct ice_aqc_read_write_alt_indirect { 2181 __le32 base_dword_addr; 2182 __le32 num_dwords; 2183 __le32 addr_high; 2184 __le32 addr_low; 2185 }; 2186 2187 /* Done Alternate Write (direct 0x0904) */ 2188 struct ice_aqc_done_alt_write { 2189 u8 flags; 2190 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0) 2191 #define ICE_AQC_RESP_RESET_NEEDED BIT(1) 2192 u8 reserved[15]; 2193 }; 2194 2195 /* Clear Port Alternate Write (direct 0x0906) */ 2196 struct ice_aqc_clear_port_alt_write { 2197 u8 reserved[16]; 2198 }; 2199 2200 /* Get LLDP MIB (indirect 0x0A00) 2201 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 2202 * as the format is the same. 2203 */ 2204 struct ice_aqc_lldp_get_mib { 2205 u8 type; 2206 #define ICE_AQ_LLDP_MIB_TYPE_S 0 2207 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 2208 #define ICE_AQ_LLDP_MIB_LOCAL 0 2209 #define ICE_AQ_LLDP_MIB_REMOTE 1 2210 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 2211 #define ICE_AQ_LLDP_BRID_TYPE_S 2 2212 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 2213 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 2214 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 2215 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 2216 #define ICE_AQ_LLDP_TX_S 0x4 2217 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 2218 #define ICE_AQ_LLDP_TX_ACTIVE 0 2219 #define ICE_AQ_LLDP_TX_SUSPENDED 1 2220 #define ICE_AQ_LLDP_TX_FLUSHED 3 2221 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 2222 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 2223 * Get LLDP MIB (0x0A00) response only. 2224 */ 2225 u8 reserved1; 2226 __le16 local_len; 2227 __le16 remote_len; 2228 u8 reserved2[2]; 2229 __le32 addr_high; 2230 __le32 addr_low; 2231 }; 2232 2233 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 2234 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 2235 struct ice_aqc_lldp_set_mib_change { 2236 u8 command; 2237 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2238 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 2239 u8 reserved[15]; 2240 }; 2241 2242 /* Add LLDP TLV (indirect 0x0A02) 2243 * Delete LLDP TLV (indirect 0x0A04) 2244 */ 2245 struct ice_aqc_lldp_add_delete_tlv { 2246 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2247 u8 reserved1[1]; 2248 __le16 len; 2249 u8 reserved2[4]; 2250 __le32 addr_high; 2251 __le32 addr_low; 2252 }; 2253 2254 /* Update LLDP TLV (indirect 0x0A03) */ 2255 struct ice_aqc_lldp_update_tlv { 2256 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2257 u8 reserved; 2258 __le16 old_len; 2259 __le16 new_offset; 2260 __le16 new_len; 2261 __le32 addr_high; 2262 __le32 addr_low; 2263 }; 2264 2265 /* Stop LLDP (direct 0x0A05) */ 2266 struct ice_aqc_lldp_stop { 2267 u8 command; 2268 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 2269 #define ICE_AQ_LLDP_AGENT_STOP 0x0 2270 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 2271 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 2272 u8 reserved[15]; 2273 }; 2274 2275 /* Start LLDP (direct 0x0A06) */ 2276 struct ice_aqc_lldp_start { 2277 u8 command; 2278 #define ICE_AQ_LLDP_AGENT_START BIT(0) 2279 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 2280 u8 reserved[15]; 2281 }; 2282 2283 /* Get CEE DCBX Oper Config (0x0A07) 2284 * The command uses the generic descriptor struct and 2285 * returns the struct below as an indirect response. 2286 */ 2287 struct ice_aqc_get_cee_dcb_cfg_resp { 2288 u8 oper_num_tc; 2289 u8 oper_prio_tc[4]; 2290 u8 oper_tc_bw[8]; 2291 u8 oper_pfc_en; 2292 __le16 oper_app_prio; 2293 #define ICE_AQC_CEE_APP_FCOE_S 0 2294 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 2295 #define ICE_AQC_CEE_APP_ISCSI_S 3 2296 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 2297 #define ICE_AQC_CEE_APP_FIP_S 8 2298 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 2299 __le32 tlv_status; 2300 #define ICE_AQC_CEE_PG_STATUS_S 0 2301 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 2302 #define ICE_AQC_CEE_PFC_STATUS_S 3 2303 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 2304 #define ICE_AQC_CEE_FCOE_STATUS_S 8 2305 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 2306 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 2307 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 2308 #define ICE_AQC_CEE_FIP_STATUS_S 16 2309 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 2310 u8 reserved[12]; 2311 }; 2312 2313 /* Set Local LLDP MIB (indirect 0x0A08) 2314 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 2315 */ 2316 struct ice_aqc_lldp_set_local_mib { 2317 u8 type; 2318 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 2319 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 2320 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 2321 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 2322 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 2323 u8 reserved0; 2324 __le16 length; 2325 u8 reserved1[4]; 2326 __le32 addr_high; 2327 __le32 addr_low; 2328 }; 2329 2330 struct ice_aqc_lldp_set_local_mib_resp { 2331 u8 status; 2332 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2333 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2334 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2335 u8 reserved[15]; 2336 }; 2337 2338 /* Stop/Start LLDP Agent (direct 0x0A09) 2339 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2340 * The same structure is used for the response, with the command field 2341 * being used as the status field. 2342 */ 2343 struct ice_aqc_lldp_stop_start_specific_agent { 2344 u8 command; 2345 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2346 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2347 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2348 u8 reserved[15]; 2349 }; 2350 2351 /* LLDP Filter Control (direct 0x0A0A) */ 2352 struct ice_aqc_lldp_filter_ctrl { 2353 u8 cmd_flags; 2354 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 2355 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2356 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2357 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 2358 u8 reserved1; 2359 __le16 vsi_num; 2360 u8 reserved2[12]; 2361 }; 2362 2363 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2364 struct ice_aqc_get_set_rss_key { 2365 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2366 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2367 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2368 __le16 vsi_id; 2369 u8 reserved[6]; 2370 __le32 addr_high; 2371 __le32 addr_low; 2372 }; 2373 2374 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2375 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2376 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2377 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2378 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2379 2380 /** 2381 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2382 * @standard_rss_key: 40 most significant bytes of hash key 2383 * @extended_hash_key: 12 least significant bytes of hash key 2384 * 2385 * Set/Get 40 byte hash key using standard_rss_key field, and set 2386 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2387 * standard_rss_key field for 40 most significant bytes and the 2388 * extended_hash_key field for the 12 least significant bytes of hash key. 2389 */ 2390 struct ice_aqc_get_set_rss_keys { 2391 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2392 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2393 }; 2394 2395 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2396 struct ice_aqc_get_set_rss_lut { 2397 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2398 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2399 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2400 __le16 vsi_id; 2401 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2402 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2403 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2404 2405 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2406 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2407 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2408 2409 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2410 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2411 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2412 2413 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2414 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2415 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2416 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2417 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2418 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2419 2420 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2421 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2422 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2423 2424 __le16 flags; 2425 __le32 reserved; 2426 __le32 addr_high; 2427 __le32 addr_low; 2428 }; 2429 2430 /* Add Tx LAN Queues (indirect 0x0C30) */ 2431 struct ice_aqc_add_txqs { 2432 u8 num_qgrps; 2433 u8 reserved[3]; 2434 __le32 reserved1; 2435 __le32 addr_high; 2436 __le32 addr_low; 2437 }; 2438 2439 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2440 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2441 */ 2442 struct ice_aqc_add_txqs_perq { 2443 __le16 txq_id; 2444 u8 rsvd[2]; 2445 __le32 q_teid; 2446 u8 txq_ctx[22]; 2447 u8 rsvd2[2]; 2448 struct ice_aqc_txsched_elem info; 2449 }; 2450 2451 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2452 * is an array of the following structs. Please note that the length of 2453 * each struct ice_aqc_add_tx_qgrp is variable due 2454 * to the variable number of queues in each group! 2455 */ 2456 struct ice_aqc_add_tx_qgrp { 2457 __le32 parent_teid; 2458 u8 num_txqs; 2459 u8 rsvd[3]; 2460 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2461 }; 2462 2463 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2464 struct ice_aqc_dis_txqs { 2465 u8 cmd_type; 2466 #define ICE_AQC_Q_DIS_CMD_S 0 2467 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2468 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2469 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2470 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2471 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2472 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2473 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2474 u8 num_entries; 2475 __le16 vmvf_and_timeout; 2476 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2477 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2478 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2479 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2480 __le32 blocked_cgds; 2481 __le32 addr_high; 2482 __le32 addr_low; 2483 }; 2484 2485 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2486 * contains the following structures, arrayed one after the 2487 * other. 2488 * Note: Since the q_id is 16 bits wide, if the 2489 * number of queues is even, then 2 bytes of alignment MUST be 2490 * added before the start of the next group, to allow correct 2491 * alignment of the parent_teid field. 2492 */ 2493 #pragma pack(1) 2494 struct ice_aqc_dis_txq_item { 2495 __le32 parent_teid; 2496 u8 num_qs; 2497 u8 rsvd; 2498 /* The length of the q_id array varies according to num_qs */ 2499 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2500 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2501 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2502 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2503 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2504 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2505 }; 2506 #pragma pack() 2507 2508 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2509 struct ice_aqc_txqs_cleanup { 2510 __le16 caller_opc; 2511 __le16 cmd_tag; 2512 u8 reserved[12]; 2513 }; 2514 2515 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2516 struct ice_aqc_move_txqs { 2517 u8 cmd_type; 2518 #define ICE_AQC_Q_CMD_TYPE_S 0 2519 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2520 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2521 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2522 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2523 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2524 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2525 u8 num_qs; 2526 u8 rsvd; 2527 u8 timeout; 2528 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2529 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2530 __le32 blocked_cgds; 2531 __le32 addr_high; 2532 __le32 addr_low; 2533 }; 2534 2535 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2536 struct ice_aqc_move_txqs_elem { 2537 __le16 txq_id; 2538 u8 q_cgd; 2539 u8 rsvd; 2540 __le32 q_teid; 2541 }; 2542 2543 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2544 struct ice_aqc_move_txqs_data { 2545 __le32 src_teid; 2546 __le32 dest_teid; 2547 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2548 }; 2549 2550 /* Download Package (indirect 0x0C40) */ 2551 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2552 struct ice_aqc_download_pkg { 2553 u8 flags; 2554 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2555 u8 reserved[3]; 2556 __le32 reserved1; 2557 __le32 addr_high; 2558 __le32 addr_low; 2559 }; 2560 2561 struct ice_aqc_download_pkg_resp { 2562 __le32 error_offset; 2563 __le32 error_info; 2564 __le32 addr_high; 2565 __le32 addr_low; 2566 }; 2567 2568 /* Get Package Info List (indirect 0x0C43) */ 2569 struct ice_aqc_get_pkg_info_list { 2570 __le32 reserved1; 2571 __le32 reserved2; 2572 __le32 addr_high; 2573 __le32 addr_low; 2574 }; 2575 2576 /* Version format for packages */ 2577 struct ice_pkg_ver { 2578 u8 major; 2579 u8 minor; 2580 u8 update; 2581 u8 draft; 2582 }; 2583 2584 #define ICE_PKG_NAME_SIZE 32 2585 #define ICE_SEG_ID_SIZE 28 2586 #define ICE_SEG_NAME_SIZE 28 2587 2588 struct ice_aqc_get_pkg_info { 2589 struct ice_pkg_ver ver; 2590 char name[ICE_SEG_NAME_SIZE]; 2591 __le32 track_id; 2592 u8 is_in_nvm; 2593 u8 is_active; 2594 u8 is_active_at_boot; 2595 u8 is_modified; 2596 }; 2597 2598 /* Get Package Info List response buffer format (0x0C43) */ 2599 struct ice_aqc_get_pkg_info_resp { 2600 __le32 count; 2601 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2602 }; 2603 2604 /* Driver Shared Parameters (direct, 0x0C90) */ 2605 struct ice_aqc_driver_shared_params { 2606 u8 set_or_get_op; 2607 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2608 #define ICE_AQC_DRIVER_PARAM_SET 0 2609 #define ICE_AQC_DRIVER_PARAM_GET 1 2610 u8 param_indx; 2611 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2612 u8 rsvd[2]; 2613 __le32 param_val; 2614 __le32 addr_high; 2615 __le32 addr_low; 2616 }; 2617 2618 /* Lan Queue Overflow Event (direct, 0x1001) */ 2619 struct ice_aqc_event_lan_overflow { 2620 __le32 prtdcb_ruptq; 2621 __le32 qtx_ctl; 2622 u8 reserved[8]; 2623 }; 2624 2625 /* Debug Dump Internal Data (indirect 0xFF08) */ 2626 struct ice_aqc_debug_dump_internals { 2627 u8 cluster_id; 2628 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 2629 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 2630 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 2631 /* EMP_DRAM only dumpable in device debug mode */ 2632 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 2633 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 2634 /* AUX_REGS only dumpable in device debug mode */ 2635 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 2636 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 2637 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 2638 u8 reserved; 2639 __le16 table_id; /* Used only for non-memory clusters */ 2640 __le32 idx; /* In table entries for tables, in bytes for memory */ 2641 __le32 addr_high; 2642 __le32 addr_low; 2643 }; 2644 2645 enum ice_aqc_fw_logging_mod { 2646 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2647 ICE_AQC_FW_LOG_ID_CTRL, 2648 ICE_AQC_FW_LOG_ID_LINK, 2649 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2650 ICE_AQC_FW_LOG_ID_DNL, 2651 ICE_AQC_FW_LOG_ID_I2C, 2652 ICE_AQC_FW_LOG_ID_SDP, 2653 ICE_AQC_FW_LOG_ID_MDIO, 2654 ICE_AQC_FW_LOG_ID_ADMINQ, 2655 ICE_AQC_FW_LOG_ID_HDMA, 2656 ICE_AQC_FW_LOG_ID_LLDP, 2657 ICE_AQC_FW_LOG_ID_DCBX, 2658 ICE_AQC_FW_LOG_ID_DCB, 2659 ICE_AQC_FW_LOG_ID_XLR, 2660 ICE_AQC_FW_LOG_ID_NVM, 2661 ICE_AQC_FW_LOG_ID_AUTH, 2662 ICE_AQC_FW_LOG_ID_VPD, 2663 ICE_AQC_FW_LOG_ID_IOSF, 2664 ICE_AQC_FW_LOG_ID_PARSER, 2665 ICE_AQC_FW_LOG_ID_SW, 2666 ICE_AQC_FW_LOG_ID_SCHEDULER, 2667 ICE_AQC_FW_LOG_ID_TXQ, 2668 ICE_AQC_FW_LOG_ID_RSVD, 2669 ICE_AQC_FW_LOG_ID_POST, 2670 ICE_AQC_FW_LOG_ID_WATCHDOG, 2671 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2672 ICE_AQC_FW_LOG_ID_MNG, 2673 ICE_AQC_FW_LOG_ID_SYNCE, 2674 ICE_AQC_FW_LOG_ID_HEALTH, 2675 ICE_AQC_FW_LOG_ID_TSDRV, 2676 ICE_AQC_FW_LOG_ID_PFREG, 2677 ICE_AQC_FW_LOG_ID_MDLVER, 2678 ICE_AQC_FW_LOG_ID_MAX, 2679 }; 2680 2681 2682 /* Set Health Status (direct 0xFF20) */ 2683 struct ice_aqc_set_health_status_config { 2684 u8 event_source; 2685 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2686 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2687 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2688 u8 reserved[15]; 2689 }; 2690 2691 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2692 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2693 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2694 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2695 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2696 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2697 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2698 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2699 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2700 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2701 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2702 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2703 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2704 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2705 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2706 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2707 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2708 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2709 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2710 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2711 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120 2712 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121 2713 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2714 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2715 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2716 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2717 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2718 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2719 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2720 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2721 2722 /* Get Health Status codes (indirect 0xFF21) */ 2723 struct ice_aqc_get_supported_health_status_codes { 2724 __le16 health_code_count; 2725 u8 reserved[6]; 2726 __le32 addr_high; 2727 __le32 addr_low; 2728 }; 2729 2730 /* Get Health Status (indirect 0xFF22) */ 2731 struct ice_aqc_get_health_status { 2732 __le16 health_status_count; 2733 u8 reserved[6]; 2734 __le32 addr_high; 2735 __le32 addr_low; 2736 }; 2737 2738 /* Get Health Status event buffer entry, (0xFF22) 2739 * repeated per reported health status 2740 */ 2741 struct ice_aqc_health_status_elem { 2742 __le16 health_status_code; 2743 __le16 event_source; 2744 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2745 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2746 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2747 __le32 internal_data1; 2748 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2749 __le32 internal_data2; 2750 }; 2751 2752 /* Clear Health Status (direct 0xFF23) */ 2753 struct ice_aqc_clear_health_status { 2754 __le32 reserved[4]; 2755 }; 2756 2757 /* Set FW Logging configuration (indirect 0xFF30) 2758 * Register for FW Logging (indirect 0xFF31) 2759 * Query FW Logging (indirect 0xFF32) 2760 * FW Log Event (indirect 0xFF33) 2761 * Get FW Log (indirect 0xFF34) 2762 * Clear FW Log (indirect 0xFF35) 2763 */ 2764 struct ice_aqc_fw_log { 2765 u8 cmd_flags; 2766 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2767 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2768 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 2769 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2770 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2771 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2772 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0) 2773 u8 rsp_flag; 2774 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1) 2775 __le16 fw_rt_msb; 2776 union { 2777 struct { 2778 __le32 fw_rt_lsb; 2779 } sync; 2780 struct { 2781 __le16 log_resolution; 2782 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2783 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2784 __le16 mdl_cnt; 2785 } cfg; 2786 } ops; 2787 __le32 addr_high; 2788 __le32 addr_low; 2789 }; 2790 2791 /* Response Buffer for: 2792 * Set Firmware Logging Configuration (0xFF30) 2793 * Query FW Logging (0xFF32) 2794 */ 2795 struct ice_aqc_fw_log_cfg_resp { 2796 __le16 module_identifier; 2797 u8 log_level; 2798 u8 rsvd0; 2799 }; 2800 2801 /** 2802 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2803 * @flags: ICE_AQ_FLAG_* flags 2804 * @opcode: AQ command opcode 2805 * @datalen: length in bytes of indirect/external data buffer 2806 * @retval: return value from firmware 2807 * @cookie_high: opaque data high-half 2808 * @cookie_low: opaque data low-half 2809 * @params: command-specific parameters 2810 * 2811 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2812 * (ATQ). The firmware writes back onto the command descriptor and returns 2813 * the result of the command. Asynchronous events that are not an immediate 2814 * result of the command are written to the Admin Receive Queue (ARQ) using 2815 * the same descriptor format. Descriptors are in little-endian notation with 2816 * 32-bit words. 2817 */ 2818 struct ice_aq_desc { 2819 __le16 flags; 2820 __le16 opcode; 2821 __le16 datalen; 2822 __le16 retval; 2823 __le32 cookie_high; 2824 __le32 cookie_low; 2825 union { 2826 u8 raw[16]; 2827 struct ice_aqc_generic generic; 2828 struct ice_aqc_get_ver get_ver; 2829 struct ice_aqc_driver_ver driver_ver; 2830 struct ice_aqc_q_shutdown q_shutdown; 2831 struct ice_aqc_get_exp_err exp_err; 2832 struct ice_aqc_req_res res_owner; 2833 struct ice_aqc_manage_mac_read mac_read; 2834 struct ice_aqc_manage_mac_write mac_write; 2835 struct ice_aqc_clear_pxe clear_pxe; 2836 struct ice_aqc_config_no_drop_policy no_drop; 2837 struct ice_aqc_add_update_mir_rule add_update_rule; 2838 struct ice_aqc_delete_mir_rule del_rule; 2839 struct ice_aqc_list_caps get_cap; 2840 struct ice_aqc_get_phy_caps get_phy; 2841 struct ice_aqc_set_phy_cfg set_phy; 2842 struct ice_aqc_restart_an restart_an; 2843 struct ice_aqc_dnl_get_status get_status; 2844 struct ice_aqc_dnl_run_command dnl_run; 2845 struct ice_aqc_dnl_call_command dnl_call; 2846 struct ice_aqc_dnl_read_write_command dnl_read_write; 2847 struct ice_aqc_dnl_read_write_response dnl_read_write_resp; 2848 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; 2849 struct ice_aqc_dnl_read_log_command dnl_read_log; 2850 struct ice_aqc_dnl_read_log_response dnl_read_log_resp; 2851 struct ice_aqc_i2c read_write_i2c; 2852 struct ice_aqc_read_i2c_resp read_i2c_resp; 2853 struct ice_aqc_mdio read_write_mdio; 2854 struct ice_aqc_gpio_by_func read_write_gpio_by_func; 2855 struct ice_aqc_gpio read_write_gpio; 2856 struct ice_aqc_sw_gpio sw_read_write_gpio; 2857 struct ice_aqc_set_led set_led; 2858 struct ice_aqc_mdio read_mdio; 2859 struct ice_aqc_mdio write_mdio; 2860 struct ice_aqc_sff_eeprom read_write_sff_param; 2861 struct ice_aqc_set_port_id_led set_port_id_led; 2862 struct ice_aqc_get_port_options get_port_options; 2863 struct ice_aqc_set_port_option set_port_option; 2864 struct ice_aqc_get_sw_cfg get_sw_conf; 2865 struct ice_aqc_set_port_params set_port_params; 2866 struct ice_aqc_sw_rules sw_rules; 2867 struct ice_aqc_storm_cfg storm_conf; 2868 struct ice_aqc_get_topo get_topo; 2869 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2870 struct ice_aqc_query_txsched_res query_sched_res; 2871 struct ice_aqc_query_node_to_root query_node_to_root; 2872 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2873 struct ice_aqc_query_port_ets port_ets; 2874 struct ice_aqc_rl_profile rl_profile; 2875 struct ice_aqc_nvm nvm; 2876 struct ice_aqc_nvm_cfg nvm_cfg; 2877 struct ice_aqc_nvm_checksum nvm_checksum; 2878 struct ice_aqc_pf_vf_msg virt; 2879 struct ice_aqc_read_write_alt_direct read_write_alt_direct; 2880 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; 2881 struct ice_aqc_done_alt_write done_alt_write; 2882 struct ice_aqc_clear_port_alt_write clear_port_alt_write; 2883 struct ice_aqc_pfc_ignore pfc_ignore; 2884 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2885 struct ice_aqc_set_dcb_params set_dcb_params; 2886 struct ice_aqc_lldp_get_mib lldp_get_mib; 2887 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2888 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2889 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2890 struct ice_aqc_lldp_stop lldp_stop; 2891 struct ice_aqc_lldp_start lldp_start; 2892 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2893 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2894 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2895 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2896 struct ice_aqc_get_set_rss_key get_set_rss_key; 2897 struct ice_aqc_add_txqs add_txqs; 2898 struct ice_aqc_dis_txqs dis_txqs; 2899 struct ice_aqc_move_txqs move_txqs; 2900 struct ice_aqc_txqs_cleanup txqs_cleanup; 2901 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2902 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2903 struct ice_aqc_get_vsi_resp get_vsi_resp; 2904 struct ice_aqc_download_pkg download_pkg; 2905 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2906 struct ice_aqc_driver_shared_params drv_shared_params; 2907 struct ice_aqc_fw_log fw_log; 2908 struct ice_aqc_debug_dump_internals debug_dump; 2909 struct ice_aqc_set_mac_lb set_mac_lb; 2910 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2911 struct ice_aqc_get_res_alloc get_res; 2912 struct ice_aqc_get_allocd_res_desc get_res_desc; 2913 struct ice_aqc_set_mac_cfg set_mac_cfg; 2914 struct ice_aqc_set_event_mask set_event_mask; 2915 struct ice_aqc_get_link_status get_link_status; 2916 struct ice_aqc_event_lan_overflow lan_overflow; 2917 struct ice_aqc_get_link_topo get_link_topo; 2918 struct ice_aqc_set_health_status_config 2919 set_health_status_config; 2920 struct ice_aqc_get_supported_health_status_codes 2921 get_supported_health_status_codes; 2922 struct ice_aqc_get_health_status get_health_status; 2923 struct ice_aqc_clear_health_status clear_health_status; 2924 struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm; 2925 struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm; 2926 } params; 2927 }; 2928 2929 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2930 #define ICE_AQ_LG_BUF 512 2931 2932 /* Flags sub-structure 2933 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2934 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2935 */ 2936 2937 /* command flags and offsets */ 2938 #define ICE_AQ_FLAG_DD_S 0 2939 #define ICE_AQ_FLAG_CMP_S 1 2940 #define ICE_AQ_FLAG_ERR_S 2 2941 #define ICE_AQ_FLAG_VFE_S 3 2942 #define ICE_AQ_FLAG_LB_S 9 2943 #define ICE_AQ_FLAG_RD_S 10 2944 #define ICE_AQ_FLAG_VFC_S 11 2945 #define ICE_AQ_FLAG_BUF_S 12 2946 #define ICE_AQ_FLAG_SI_S 13 2947 #define ICE_AQ_FLAG_EI_S 14 2948 #define ICE_AQ_FLAG_FE_S 15 2949 2950 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2951 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2952 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2953 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2954 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2955 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2956 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2957 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2958 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2959 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2960 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2961 2962 /* error codes */ 2963 enum ice_aq_err { 2964 ICE_AQ_RC_OK = 0, /* Success */ 2965 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2966 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2967 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2968 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2969 ICE_AQ_RC_EIO = 5, /* I/O error */ 2970 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2971 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2972 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2973 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2974 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2975 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2976 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2977 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2978 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2979 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2980 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2981 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2982 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2983 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2984 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2985 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2986 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2987 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2988 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2989 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2990 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2991 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2992 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2993 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2994 }; 2995 2996 /* Admin Queue command opcodes */ 2997 enum ice_adminq_opc { 2998 /* AQ commands */ 2999 ice_aqc_opc_get_ver = 0x0001, 3000 ice_aqc_opc_driver_ver = 0x0002, 3001 ice_aqc_opc_q_shutdown = 0x0003, 3002 ice_aqc_opc_get_exp_err = 0x0005, 3003 3004 /* resource ownership */ 3005 ice_aqc_opc_req_res = 0x0008, 3006 ice_aqc_opc_release_res = 0x0009, 3007 3008 /* device/function capabilities */ 3009 ice_aqc_opc_list_func_caps = 0x000A, 3010 ice_aqc_opc_list_dev_caps = 0x000B, 3011 3012 /* manage MAC address */ 3013 ice_aqc_opc_manage_mac_read = 0x0107, 3014 ice_aqc_opc_manage_mac_write = 0x0108, 3015 3016 /* PXE */ 3017 ice_aqc_opc_clear_pxe_mode = 0x0110, 3018 3019 ice_aqc_opc_config_no_drop_policy = 0x0112, 3020 3021 /* internal switch commands */ 3022 ice_aqc_opc_get_sw_cfg = 0x0200, 3023 ice_aqc_opc_set_port_params = 0x0203, 3024 3025 /* Alloc/Free/Get Resources */ 3026 ice_aqc_opc_get_res_alloc = 0x0204, 3027 ice_aqc_opc_alloc_res = 0x0208, 3028 ice_aqc_opc_free_res = 0x0209, 3029 ice_aqc_opc_get_allocd_res_desc = 0x020A, 3030 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 3031 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 3032 3033 /* VSI commands */ 3034 ice_aqc_opc_add_vsi = 0x0210, 3035 ice_aqc_opc_update_vsi = 0x0211, 3036 ice_aqc_opc_get_vsi_params = 0x0212, 3037 ice_aqc_opc_free_vsi = 0x0213, 3038 3039 /* Mirroring rules - add/update, delete */ 3040 ice_aqc_opc_add_update_mir_rule = 0x0260, 3041 ice_aqc_opc_del_mir_rule = 0x0261, 3042 3043 /* storm configuration */ 3044 ice_aqc_opc_set_storm_cfg = 0x0280, 3045 ice_aqc_opc_get_storm_cfg = 0x0281, 3046 3047 /* switch rules population commands */ 3048 ice_aqc_opc_add_sw_rules = 0x02A0, 3049 ice_aqc_opc_update_sw_rules = 0x02A1, 3050 ice_aqc_opc_remove_sw_rules = 0x02A2, 3051 ice_aqc_opc_get_sw_rules = 0x02A3, 3052 ice_aqc_opc_clear_pf_cfg = 0x02A4, 3053 3054 /* DCB commands */ 3055 ice_aqc_opc_pfc_ignore = 0x0301, 3056 ice_aqc_opc_query_pfc_mode = 0x0302, 3057 ice_aqc_opc_set_pfc_mode = 0x0303, 3058 ice_aqc_opc_set_dcb_params = 0x0306, 3059 3060 /* transmit scheduler commands */ 3061 ice_aqc_opc_get_dflt_topo = 0x0400, 3062 ice_aqc_opc_add_sched_elems = 0x0401, 3063 ice_aqc_opc_cfg_sched_elems = 0x0403, 3064 ice_aqc_opc_get_sched_elems = 0x0404, 3065 ice_aqc_opc_move_sched_elems = 0x0408, 3066 ice_aqc_opc_suspend_sched_elems = 0x0409, 3067 ice_aqc_opc_resume_sched_elems = 0x040A, 3068 ice_aqc_opc_query_port_ets = 0x040E, 3069 ice_aqc_opc_delete_sched_elems = 0x040F, 3070 ice_aqc_opc_add_rl_profiles = 0x0410, 3071 ice_aqc_opc_query_rl_profiles = 0x0411, 3072 ice_aqc_opc_query_sched_res = 0x0412, 3073 ice_aqc_opc_query_node_to_root = 0x0413, 3074 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 3075 ice_aqc_opc_remove_rl_profiles = 0x0415, 3076 3077 /* PHY commands */ 3078 ice_aqc_opc_get_phy_caps = 0x0600, 3079 ice_aqc_opc_set_phy_cfg = 0x0601, 3080 ice_aqc_opc_set_mac_cfg = 0x0603, 3081 ice_aqc_opc_restart_an = 0x0605, 3082 ice_aqc_opc_get_link_status = 0x0607, 3083 ice_aqc_opc_set_event_mask = 0x0613, 3084 ice_aqc_opc_set_mac_lb = 0x0620, 3085 ice_aqc_opc_dnl_get_status = 0x0680, 3086 ice_aqc_opc_dnl_run = 0x0681, 3087 ice_aqc_opc_dnl_call = 0x0682, 3088 ice_aqc_opc_dnl_read_sto = 0x0683, 3089 ice_aqc_opc_dnl_write_sto = 0x0684, 3090 ice_aqc_opc_dnl_set_breakpoints = 0x0686, 3091 ice_aqc_opc_dnl_read_log = 0x0687, 3092 ice_aqc_opc_get_link_topo = 0x06E0, 3093 ice_aqc_opc_read_i2c = 0x06E2, 3094 ice_aqc_opc_write_i2c = 0x06E3, 3095 ice_aqc_opc_read_mdio = 0x06E4, 3096 ice_aqc_opc_write_mdio = 0x06E5, 3097 ice_aqc_opc_set_gpio_by_func = 0x06E6, 3098 ice_aqc_opc_get_gpio_by_func = 0x06E7, 3099 ice_aqc_opc_set_led = 0x06E8, 3100 ice_aqc_opc_set_port_id_led = 0x06E9, 3101 ice_aqc_opc_get_port_options = 0x06EA, 3102 ice_aqc_opc_set_port_option = 0x06EB, 3103 ice_aqc_opc_set_gpio = 0x06EC, 3104 ice_aqc_opc_get_gpio = 0x06ED, 3105 ice_aqc_opc_sff_eeprom = 0x06EE, 3106 ice_aqc_opc_sw_set_gpio = 0x06EF, 3107 ice_aqc_opc_sw_get_gpio = 0x06F0, 3108 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2, 3109 ice_aqc_opc_read_topo_dev_nvm = 0x06F3, 3110 3111 /* NVM commands */ 3112 ice_aqc_opc_nvm_read = 0x0701, 3113 ice_aqc_opc_nvm_erase = 0x0702, 3114 ice_aqc_opc_nvm_write = 0x0703, 3115 ice_aqc_opc_nvm_cfg_read = 0x0704, 3116 ice_aqc_opc_nvm_cfg_write = 0x0705, 3117 ice_aqc_opc_nvm_checksum = 0x0706, 3118 ice_aqc_opc_nvm_write_activate = 0x0707, 3119 ice_aqc_opc_nvm_sr_dump = 0x0707, 3120 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 3121 ice_aqc_opc_nvm_update_empr = 0x0709, 3122 ice_aqc_opc_nvm_pkg_data = 0x070A, 3123 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 3124 3125 /* PF/VF mailbox commands */ 3126 ice_mbx_opc_send_msg_to_pf = 0x0801, 3127 ice_mbx_opc_send_msg_to_vf = 0x0802, 3128 /* Alternate Structure Commands */ 3129 ice_aqc_opc_write_alt_direct = 0x0900, 3130 ice_aqc_opc_write_alt_indirect = 0x0901, 3131 ice_aqc_opc_read_alt_direct = 0x0902, 3132 ice_aqc_opc_read_alt_indirect = 0x0903, 3133 ice_aqc_opc_done_alt_write = 0x0904, 3134 ice_aqc_opc_clear_port_alt_write = 0x0906, 3135 /* LLDP commands */ 3136 ice_aqc_opc_lldp_get_mib = 0x0A00, 3137 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 3138 ice_aqc_opc_lldp_add_tlv = 0x0A02, 3139 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3140 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3141 ice_aqc_opc_lldp_stop = 0x0A05, 3142 ice_aqc_opc_lldp_start = 0x0A06, 3143 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3144 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3145 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3146 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3147 3148 /* RSS commands */ 3149 ice_aqc_opc_set_rss_key = 0x0B02, 3150 ice_aqc_opc_set_rss_lut = 0x0B03, 3151 ice_aqc_opc_get_rss_key = 0x0B04, 3152 ice_aqc_opc_get_rss_lut = 0x0B05, 3153 3154 /* Tx queue handling commands/events */ 3155 ice_aqc_opc_add_txqs = 0x0C30, 3156 ice_aqc_opc_dis_txqs = 0x0C31, 3157 ice_aqc_opc_txqs_cleanup = 0x0C31, 3158 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3159 3160 /* package commands */ 3161 ice_aqc_opc_download_pkg = 0x0C40, 3162 ice_aqc_opc_upload_section = 0x0C41, 3163 ice_aqc_opc_update_pkg = 0x0C42, 3164 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3165 3166 ice_aqc_opc_driver_shared_params = 0x0C90, 3167 3168 /* Standalone Commands/Events */ 3169 ice_aqc_opc_event_lan_overflow = 0x1001, 3170 3171 /* debug commands */ 3172 ice_aqc_opc_debug_dump_internals = 0xFF08, 3173 3174 /* SystemDiagnostic commands */ 3175 ice_aqc_opc_set_health_status_config = 0xFF20, 3176 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3177 ice_aqc_opc_get_health_status = 0xFF22, 3178 ice_aqc_opc_clear_health_status = 0xFF23, 3179 3180 /* FW Logging Commands */ 3181 ice_aqc_opc_fw_logs_config = 0xFF30, 3182 ice_aqc_opc_fw_logs_register = 0xFF31, 3183 ice_aqc_opc_fw_logs_query = 0xFF32, 3184 ice_aqc_opc_fw_logs_event = 0xFF33, 3185 ice_aqc_opc_fw_logs_get = 0xFF34, 3186 ice_aqc_opc_fw_logs_clear = 0xFF35 3187 }; 3188 3189 #endif /* _ICE_ADMINQ_CMD_H_ */ 3190