1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2020, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_ADMINQ_CMD_H_ 34 #define _ICE_ADMINQ_CMD_H_ 35 36 /* This header file defines the Admin Queue commands, error codes and 37 * descriptor format. It is shared between Firmware and Software. 38 */ 39 40 #define ICE_MAX_VSI 768 41 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 42 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 43 44 struct ice_aqc_generic { 45 __le32 param0; 46 __le32 param1; 47 __le32 addr_high; 48 __le32 addr_low; 49 }; 50 51 /* Get version (direct 0x0001) */ 52 struct ice_aqc_get_ver { 53 __le32 rom_ver; 54 __le32 fw_build; 55 u8 fw_branch; 56 u8 fw_major; 57 u8 fw_minor; 58 u8 fw_patch; 59 u8 api_branch; 60 u8 api_major; 61 u8 api_minor; 62 u8 api_patch; 63 }; 64 65 /* Send driver version (indirect 0x0002) */ 66 struct ice_aqc_driver_ver { 67 u8 major_ver; 68 u8 minor_ver; 69 u8 build_ver; 70 u8 subbuild_ver; 71 u8 reserved[4]; 72 __le32 addr_high; 73 __le32 addr_low; 74 }; 75 76 /* Queue Shutdown (direct 0x0003) */ 77 struct ice_aqc_q_shutdown { 78 u8 driver_unloading; 79 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 80 u8 reserved[15]; 81 }; 82 83 /* Get Expanded Error Code (0x0005, direct) */ 84 struct ice_aqc_get_exp_err { 85 __le32 reason; 86 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 87 __le32 identifier; 88 u8 rsvd[8]; 89 }; 90 91 /* Request resource ownership (direct 0x0008) 92 * Release resource ownership (direct 0x0009) 93 */ 94 struct ice_aqc_req_res { 95 __le16 res_id; 96 #define ICE_AQC_RES_ID_NVM 1 97 #define ICE_AQC_RES_ID_SDP 2 98 #define ICE_AQC_RES_ID_CHNG_LOCK 3 99 #define ICE_AQC_RES_ID_GLBL_LOCK 4 100 __le16 access_type; 101 #define ICE_AQC_RES_ACCESS_READ 1 102 #define ICE_AQC_RES_ACCESS_WRITE 2 103 104 /* Upon successful completion, FW writes this value and driver is 105 * expected to release resource before timeout. This value is provided 106 * in milliseconds. 107 */ 108 __le32 timeout; 109 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 110 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 111 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 112 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 113 /* For SDP: pin ID of the SDP */ 114 __le32 res_number; 115 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 116 __le16 status; 117 #define ICE_AQ_RES_GLBL_SUCCESS 0 118 #define ICE_AQ_RES_GLBL_IN_PROG 1 119 #define ICE_AQ_RES_GLBL_DONE 2 120 u8 reserved[2]; 121 }; 122 123 /* Get function capabilities (indirect 0x000A) 124 * Get device capabilities (indirect 0x000B) 125 */ 126 struct ice_aqc_list_caps { 127 u8 cmd_flags; 128 u8 pf_index; 129 u8 reserved[2]; 130 __le32 count; 131 __le32 addr_high; 132 __le32 addr_low; 133 }; 134 135 /* Device/Function buffer entry, repeated per reported capability */ 136 struct ice_aqc_list_caps_elem { 137 __le16 cap; 138 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001 139 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002 140 #define ICE_AQC_CAPS_OS2BMC 0x0004 141 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 142 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 143 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006 144 #define ICE_AQC_CAPS_WOL_PROXY 0x0008 145 #define ICE_AQC_CAPS_SRIOV 0x0012 146 #define ICE_AQC_CAPS_VF 0x0013 147 #define ICE_AQC_CAPS_802_1QBG 0x0015 148 #define ICE_AQC_CAPS_802_1BR 0x0016 149 #define ICE_AQC_CAPS_VSI 0x0017 150 #define ICE_AQC_CAPS_DCB 0x0018 151 #define ICE_AQC_CAPS_RSVD 0x0021 152 #define ICE_AQC_CAPS_ISCSI 0x0022 153 #define ICE_AQC_CAPS_RSS 0x0040 154 #define ICE_AQC_CAPS_RXQS 0x0041 155 #define ICE_AQC_CAPS_TXQS 0x0042 156 #define ICE_AQC_CAPS_MSIX 0x0043 157 #define ICE_AQC_CAPS_MAX_MTU 0x0047 158 #define ICE_AQC_CAPS_NVM_VER 0x0048 159 #define ICE_AQC_CAPS_CEM 0x00F2 160 #define ICE_AQC_CAPS_IWARP 0x0051 161 #define ICE_AQC_CAPS_LED 0x0061 162 #define ICE_AQC_CAPS_SDP 0x0062 163 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 164 #define ICE_AQC_CAPS_NO_DROP_POLICY 0x0065 165 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 166 #define ICE_AQC_CAPS_SKU 0x0074 167 #define ICE_AQC_CAPS_PORT_MAP 0x0075 168 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 169 170 u8 major_ver; 171 u8 minor_ver; 172 /* Number of resources described by this capability */ 173 __le32 number; 174 /* Only meaningful for some types of resources */ 175 __le32 logical_id; 176 /* Only meaningful for some types of resources */ 177 __le32 phys_id; 178 __le64 rsvd1; 179 __le64 rsvd2; 180 }; 181 182 /* Manage MAC address, read command - indirect (0x0107) 183 * This struct is also used for the response 184 */ 185 struct ice_aqc_manage_mac_read { 186 __le16 flags; /* Zeroed by device driver */ 187 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 188 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 189 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 190 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 191 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 192 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 193 #define ICE_AQC_MAN_MAC_READ_S 4 194 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 195 u8 rsvd[2]; 196 u8 num_addr; /* Used in response */ 197 u8 rsvd1[3]; 198 __le32 addr_high; 199 __le32 addr_low; 200 }; 201 202 /* Response buffer format for manage MAC read command */ 203 struct ice_aqc_manage_mac_read_resp { 204 u8 lport_num; 205 u8 addr_type; 206 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 207 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 208 u8 mac_addr[ETH_ALEN]; 209 }; 210 211 /* Manage MAC address, write command - direct (0x0108) */ 212 struct ice_aqc_manage_mac_write { 213 u8 rsvd; 214 u8 flags; 215 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 216 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 217 #define ICE_AQC_MAN_MAC_WR_S 6 218 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 219 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 220 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 221 /* byte stream in network order */ 222 u8 mac_addr[ETH_ALEN]; 223 __le32 addr_high; 224 __le32 addr_low; 225 }; 226 227 /* Clear PXE Command and response (direct 0x0110) */ 228 struct ice_aqc_clear_pxe { 229 u8 rx_cnt; 230 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 231 u8 reserved[15]; 232 }; 233 234 /* Configure No-Drop Policy Command (direct 0x0112) */ 235 struct ice_aqc_config_no_drop_policy { 236 u8 opts; 237 #define ICE_AQC_FORCE_NO_DROP BIT(0) 238 u8 rsvd[15]; 239 }; 240 241 /* Get switch configuration (0x0200) */ 242 struct ice_aqc_get_sw_cfg { 243 /* Reserved for command and copy of request flags for response */ 244 __le16 flags; 245 /* First desc in case of command and next_elem in case of response 246 * In case of response, if it is not zero, means all the configuration 247 * was not returned and new command shall be sent with this value in 248 * the 'first desc' field 249 */ 250 __le16 element; 251 /* Reserved for command, only used for response */ 252 __le16 num_elems; 253 __le16 rsvd; 254 __le32 addr_high; 255 __le32 addr_low; 256 }; 257 258 /* Each entry in the response buffer is of the following type: */ 259 struct ice_aqc_get_sw_cfg_resp_elem { 260 /* VSI/Port Number */ 261 __le16 vsi_port_num; 262 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 263 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 264 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 265 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 266 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 267 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 268 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 269 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 270 271 /* SWID VSI/Port belongs to */ 272 __le16 swid; 273 274 /* Bit 14..0 : PF/VF number VSI belongs to 275 * Bit 15 : VF indication bit 276 */ 277 __le16 pf_vf_num; 278 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 279 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 280 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 281 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 282 }; 283 284 /* The response buffer is as follows. Note that the length of the 285 * elements array varies with the length of the command response. 286 */ 287 struct ice_aqc_get_sw_cfg_resp { 288 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 289 }; 290 291 /* Set Port parameters, (direct, 0x0203) */ 292 struct ice_aqc_set_port_params { 293 __le16 cmd_flags; 294 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 295 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 296 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 297 __le16 bad_frame_vsi; 298 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 299 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 300 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 301 __le16 swid; 302 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 303 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 304 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 305 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 306 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 307 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 308 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 309 u8 reserved[10]; 310 }; 311 312 /* These resource type defines are used for all switch resource 313 * commands where a resource type is required, such as: 314 * Get Resource Allocation command (indirect 0x0204) 315 * Allocate Resources command (indirect 0x0208) 316 * Free Resources command (indirect 0x0209) 317 * Get Allocated Resource Descriptors Command (indirect 0x020A) 318 */ 319 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 320 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 321 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 322 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 323 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 324 #define ICE_AQC_RES_TYPE_RECIPE 0x05 325 #define ICE_AQC_RES_TYPE_PROFILE 0x06 326 #define ICE_AQC_RES_TYPE_SWID 0x07 327 #define ICE_AQC_RES_TYPE_VSI 0x08 328 #define ICE_AQC_RES_TYPE_FLU 0x09 329 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 330 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 331 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 332 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 333 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 334 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 335 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 336 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 337 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 338 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 339 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 340 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 341 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 342 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 343 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 344 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 345 /* Resource types 0x62-67 are reserved for Hash profile builder */ 346 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 347 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 348 349 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 350 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 351 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 352 353 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 354 355 #define ICE_AQC_RES_TYPE_S 0 356 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 357 358 /* Get Resource Allocation command (indirect 0x0204) */ 359 struct ice_aqc_get_res_alloc { 360 __le16 resp_elem_num; /* Used in response, reserved in command */ 361 u8 reserved[6]; 362 __le32 addr_high; 363 __le32 addr_low; 364 }; 365 366 /* Get Resource Allocation Response Buffer per response */ 367 struct ice_aqc_get_res_resp_elem { 368 __le16 res_type; /* Types defined above cmd 0x0204 */ 369 __le16 total_capacity; /* Resources available to all PF's */ 370 __le16 total_function; /* Resources allocated for a PF */ 371 __le16 total_shared; /* Resources allocated as shared */ 372 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 373 }; 374 375 /* Buffer for Get Resource command */ 376 struct ice_aqc_get_res_resp { 377 /* Number of resource entries to be calculated using 378 * datalen/sizeof(struct ice_aqc_cmd_resp)). 379 * Value of 'datalen' gets updated as part of response. 380 */ 381 struct ice_aqc_get_res_resp_elem elem[1]; 382 }; 383 384 /* Allocate Resources command (indirect 0x0208) 385 * Free Resources command (indirect 0x0209) 386 */ 387 struct ice_aqc_alloc_free_res_cmd { 388 __le16 num_entries; /* Number of Resource entries */ 389 u8 reserved[6]; 390 __le32 addr_high; 391 __le32 addr_low; 392 }; 393 394 /* Resource descriptor */ 395 struct ice_aqc_res_elem { 396 union { 397 __le16 sw_resp; 398 __le16 flu_resp; 399 } e; 400 }; 401 402 /* Buffer for Allocate/Free Resources commands */ 403 struct ice_aqc_alloc_free_res_elem { 404 __le16 res_type; /* Types defined above cmd 0x0204 */ 405 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 406 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 407 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 408 __le16 num_elems; 409 struct ice_aqc_res_elem elem[1]; 410 }; 411 412 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 413 struct ice_aqc_get_allocd_res_desc { 414 union { 415 struct { 416 __le16 res; /* Types defined above cmd 0x0204 */ 417 __le16 first_desc; 418 __le32 reserved; 419 } cmd; 420 struct { 421 __le16 res; 422 __le16 next_desc; 423 __le16 num_desc; 424 __le16 reserved; 425 } resp; 426 } ops; 427 __le32 addr_high; 428 __le32 addr_low; 429 }; 430 431 struct ice_aqc_get_allocd_res_desc_resp { 432 struct ice_aqc_res_elem elem[1]; 433 }; 434 435 /* Add VSI (indirect 0x0210) 436 * Update VSI (indirect 0x0211) 437 * Get VSI (indirect 0x0212) 438 * Free VSI (indirect 0x0213) 439 */ 440 struct ice_aqc_add_get_update_free_vsi { 441 __le16 vsi_num; 442 #define ICE_AQ_VSI_NUM_S 0 443 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 444 #define ICE_AQ_VSI_IS_VALID BIT(15) 445 __le16 cmd_flags; 446 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 447 u8 vf_id; 448 u8 reserved; 449 __le16 vsi_flags; 450 #define ICE_AQ_VSI_TYPE_S 0 451 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 452 #define ICE_AQ_VSI_TYPE_VF 0x0 453 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 454 #define ICE_AQ_VSI_TYPE_PF 0x2 455 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 456 __le32 addr_high; 457 __le32 addr_low; 458 }; 459 460 /* Response descriptor for: 461 * Add VSI (indirect 0x0210) 462 * Update VSI (indirect 0x0211) 463 * Free VSI (indirect 0x0213) 464 */ 465 struct ice_aqc_add_update_free_vsi_resp { 466 __le16 vsi_num; 467 __le16 ext_status; 468 __le16 vsi_used; 469 __le16 vsi_free; 470 __le32 addr_high; 471 __le32 addr_low; 472 }; 473 474 struct ice_aqc_get_vsi_resp { 475 __le16 vsi_num; 476 u8 vf_id; 477 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 478 * These are found above in struct ice_aqc_add_get_update_free_vsi. 479 */ 480 u8 vsi_flags; 481 __le16 vsi_used; 482 __le16 vsi_free; 483 __le32 addr_high; 484 __le32 addr_low; 485 }; 486 487 struct ice_aqc_vsi_props { 488 __le16 valid_sections; 489 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 490 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 491 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 492 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 493 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 494 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 495 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 496 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 497 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 498 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 499 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 500 /* switch section */ 501 u8 sw_id; 502 u8 sw_flags; 503 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 504 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 505 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 506 u8 sw_flags2; 507 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 508 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 509 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 510 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 511 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 512 u8 veb_stat_id; 513 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 514 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 515 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 516 /* security section */ 517 u8 sec_flags; 518 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 519 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 520 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 521 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 522 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 523 u8 sec_reserved; 524 /* VLAN section */ 525 __le16 pvid; /* VLANS include priority bits */ 526 u8 pvlan_reserved[2]; 527 u8 vlan_flags; 528 #define ICE_AQ_VSI_VLAN_MODE_S 0 529 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 530 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 531 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 532 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 533 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 534 #define ICE_AQ_VSI_VLAN_EMOD_S 3 535 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 536 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 537 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 538 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 539 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 540 u8 pvlan_reserved2[3]; 541 /* ingress egress up sections */ 542 __le32 ingress_table; /* bitmap, 3 bits per up */ 543 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 544 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 545 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 546 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 547 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 548 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 549 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 550 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 551 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 552 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 553 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 554 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 555 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 556 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 557 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 558 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 559 __le32 egress_table; /* same defines as for ingress table */ 560 /* outer tags section */ 561 __le16 outer_tag; 562 u8 outer_tag_flags; 563 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 564 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 565 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 566 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 567 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 568 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 569 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 570 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 571 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 572 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 573 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 574 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 575 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 576 u8 outer_tag_reserved; 577 /* queue mapping section */ 578 __le16 mapping_flags; 579 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 580 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 581 __le16 q_mapping[16]; 582 #define ICE_AQ_VSI_Q_S 0 583 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 584 __le16 tc_mapping[8]; 585 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 586 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 587 #define ICE_AQ_VSI_TC_Q_NUM_S 11 588 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 589 /* queueing option section */ 590 u8 q_opt_rss; 591 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 592 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 593 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 594 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 595 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 596 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 597 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 598 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 599 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 600 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 601 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 602 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 603 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 604 u8 q_opt_tc; 605 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 606 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 607 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 608 u8 q_opt_flags; 609 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 610 u8 q_opt_reserved[3]; 611 /* outer up section */ 612 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 613 /* section 10 */ 614 __le16 sect_10_reserved; 615 /* flow director section */ 616 __le16 fd_options; 617 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 618 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 619 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 620 __le16 max_fd_fltr_dedicated; 621 __le16 max_fd_fltr_shared; 622 __le16 fd_def_q; 623 #define ICE_AQ_VSI_FD_DEF_Q_S 0 624 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 625 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 626 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 627 __le16 fd_report_opt; 628 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 629 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 630 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 631 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 632 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 633 /* PASID section */ 634 __le32 pasid_id; 635 #define ICE_AQ_VSI_PASID_ID_S 0 636 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 637 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 638 u8 reserved[24]; 639 }; 640 641 /* Add/update mirror rule - direct (0x0260) */ 642 #define ICE_AQC_RULE_ID_VALID_S 7 643 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 644 #define ICE_AQC_RULE_ID_S 0 645 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 646 647 /* Following defines to be used while processing caller specified mirror list 648 * of VSI indexes. 649 */ 650 /* Action: Byte.bit (1.7) 651 * 0 = Remove VSI from mirror rule 652 * 1 = Add VSI to mirror rule 653 */ 654 #define ICE_AQC_RULE_ACT_S 15 655 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 656 /* Action: 1.2:0.0 = Mirrored VSI */ 657 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 658 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 659 660 /* This is to be used by add/update mirror rule Admin Queue command. 661 * In case of add mirror rule - if rule ID is specified as 662 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 663 * If specified rule_id is valid, then it is used. If specified rule_id 664 * is in use then new mirroring rule is added. 665 */ 666 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 667 668 struct ice_aqc_add_update_mir_rule { 669 __le16 rule_id; 670 671 __le16 rule_type; 672 #define ICE_AQC_RULE_TYPE_S 0 673 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 674 /* VPORT ingress/egress */ 675 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 676 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 677 /* Physical port ingress mirroring. 678 * All traffic received by this port 679 */ 680 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 681 /* Physical port egress mirroring. All traffic sent by this port */ 682 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 683 684 /* Number of mirrored entries. 685 * The values are in the command buffer 686 */ 687 __le16 num_entries; 688 689 /* Destination VSI */ 690 __le16 dest; 691 __le32 addr_high; 692 __le32 addr_low; 693 }; 694 695 /* Delete mirror rule - direct(0x0261) */ 696 struct ice_aqc_delete_mir_rule { 697 __le16 rule_id; 698 __le16 rsvd; 699 700 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 701 * the PF allocated resources, otherwise it is returned to the 702 * shared pool 703 */ 704 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 705 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 706 __le16 flags; 707 708 u8 reserved[10]; 709 }; 710 711 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 712 /* This structure holds get storm configuration response and same structure 713 * is used to perform set_storm_cfg 714 */ 715 struct ice_aqc_storm_cfg { 716 __le32 bcast_thresh_size; 717 __le32 mcast_thresh_size; 718 /* Bit 18:0 - Traffic upper threshold size 719 * Bit 31:19 - Reserved 720 */ 721 #define ICE_AQ_THRESHOLD_S 0 722 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 723 724 __le32 storm_ctrl_ctrl; 725 /* Bit 0: MDIPW - Drop Multicast packets in previous window 726 * Bit 1: MDICW - Drop multicast packets in current window 727 * Bit 2: BDIPW - Drop broadcast packets in previous window 728 * Bit 3: BDICW - Drop broadcast packets in current window 729 */ 730 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 731 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 732 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 733 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 734 /* Bit 7:5 : Reserved */ 735 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 736 * interval size for applying ingress broadcast or multicast storm 737 * control. 738 */ 739 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 740 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 741 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 742 __le32 reserved; 743 }; 744 745 #define ICE_MAX_NUM_RECIPES 64 746 747 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 748 */ 749 struct ice_aqc_sw_rules { 750 /* ops: add switch rules, referring the number of rules. 751 * ops: update switch rules, referring the number of filters 752 * ops: remove switch rules, referring the entry index. 753 * ops: get switch rules, referring to the number of filters. 754 */ 755 __le16 num_rules_fltr_entry_index; 756 u8 reserved[6]; 757 __le32 addr_high; 758 __le32 addr_low; 759 }; 760 761 #pragma pack(1) 762 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 763 * This structures describes the lookup rules and associated actions. "index" 764 * is returned as part of a response to a successful Add command, and can be 765 * used to identify the rule for Update/Get/Remove commands. 766 */ 767 struct ice_sw_rule_lkup_rx_tx { 768 __le16 recipe_id; 769 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 770 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 771 __le16 src; 772 __le32 act; 773 774 /* Bit 0:1 - Action type */ 775 #define ICE_SINGLE_ACT_TYPE_S 0x00 776 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 777 778 /* Bit 2 - Loop back enable 779 * Bit 3 - LAN enable 780 */ 781 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 782 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 783 784 /* Action type = 0 - Forward to VSI or VSI list */ 785 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 786 787 #define ICE_SINGLE_ACT_VSI_ID_S 4 788 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 789 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 790 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 791 /* This bit needs to be set if action is forward to VSI list */ 792 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 793 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 794 #define ICE_SINGLE_ACT_DROP BIT(18) 795 796 /* Action type = 1 - Forward to Queue of Queue group */ 797 #define ICE_SINGLE_ACT_TO_Q 0x1 798 #define ICE_SINGLE_ACT_Q_INDEX_S 4 799 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 800 #define ICE_SINGLE_ACT_Q_REGION_S 15 801 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 802 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 803 804 /* Action type = 2 - Prune */ 805 #define ICE_SINGLE_ACT_PRUNE 0x2 806 #define ICE_SINGLE_ACT_EGRESS BIT(15) 807 #define ICE_SINGLE_ACT_INGRESS BIT(16) 808 #define ICE_SINGLE_ACT_PRUNET BIT(17) 809 /* Bit 18 should be set to 0 for this action */ 810 811 /* Action type = 2 - Pointer */ 812 #define ICE_SINGLE_ACT_PTR 0x2 813 #define ICE_SINGLE_ACT_PTR_VAL_S 4 814 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 815 /* Bit 18 should be set to 1 */ 816 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 817 818 /* Action type = 3 - Other actions. Last two bits 819 * are other action identifier 820 */ 821 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 822 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 823 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 824 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 825 826 /* Bit 17:18 - Defines other actions */ 827 /* Other action = 0 - Mirror VSI */ 828 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 829 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 830 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 831 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 832 833 /* Other action = 3 - Set Stat count */ 834 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 835 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 836 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 837 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 838 839 __le16 index; /* The index of the rule in the lookup table */ 840 /* Length and values of the header to be matched per recipe or 841 * lookup-type 842 */ 843 __le16 hdr_len; 844 u8 hdr[1]; 845 }; 846 #pragma pack() 847 848 /* Add/Update/Remove large action command/response entry 849 * "index" is returned as part of a response to a successful Add command, and 850 * can be used to identify the action for Update/Get/Remove commands. 851 */ 852 struct ice_sw_rule_lg_act { 853 __le16 index; /* Index in large action table */ 854 __le16 size; 855 __le32 act[1]; /* array of size for actions */ 856 /* Max number of large actions */ 857 #define ICE_MAX_LG_ACT 4 858 /* Bit 0:1 - Action type */ 859 #define ICE_LG_ACT_TYPE_S 0 860 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 861 862 /* Action type = 0 - Forward to VSI or VSI list */ 863 #define ICE_LG_ACT_VSI_FORWARDING 0 864 #define ICE_LG_ACT_VSI_ID_S 3 865 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 866 #define ICE_LG_ACT_VSI_LIST_ID_S 3 867 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 868 /* This bit needs to be set if action is forward to VSI list */ 869 #define ICE_LG_ACT_VSI_LIST BIT(13) 870 871 #define ICE_LG_ACT_VALID_BIT BIT(16) 872 873 /* Action type = 1 - Forward to Queue of Queue group */ 874 #define ICE_LG_ACT_TO_Q 0x1 875 #define ICE_LG_ACT_Q_INDEX_S 3 876 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 877 #define ICE_LG_ACT_Q_REGION_S 14 878 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 879 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 880 881 /* Action type = 2 - Prune */ 882 #define ICE_LG_ACT_PRUNE 0x2 883 #define ICE_LG_ACT_EGRESS BIT(14) 884 #define ICE_LG_ACT_INGRESS BIT(15) 885 #define ICE_LG_ACT_PRUNET BIT(16) 886 887 /* Action type = 3 - Mirror VSI */ 888 #define ICE_LG_OTHER_ACT_MIRROR 0x3 889 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 890 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 891 892 /* Action type = 5 - Generic Value */ 893 #define ICE_LG_ACT_GENERIC 0x5 894 #define ICE_LG_ACT_GENERIC_VALUE_S 3 895 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 896 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 897 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 898 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 899 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 900 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 901 902 /* Action = 7 - Set Stat count */ 903 #define ICE_LG_ACT_STAT_COUNT 0x7 904 #define ICE_LG_ACT_STAT_COUNT_S 3 905 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 906 }; 907 908 /* Add/Update/Remove VSI list command/response entry 909 * "index" is returned as part of a response to a successful Add command, and 910 * can be used to identify the VSI list for Update/Get/Remove commands. 911 */ 912 struct ice_sw_rule_vsi_list { 913 __le16 index; /* Index of VSI/Prune list */ 914 __le16 number_vsi; 915 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 916 }; 917 918 #pragma pack(1) 919 /* Query VSI list command/response entry */ 920 struct ice_sw_rule_vsi_list_query { 921 __le16 index; 922 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 923 }; 924 #pragma pack() 925 926 #pragma pack(1) 927 /* Add switch rule response: 928 * Content of return buffer is same as the input buffer. The status field and 929 * LUT index are updated as part of the response 930 */ 931 struct ice_aqc_sw_rules_elem { 932 __le16 type; /* Switch rule type, one of T_... */ 933 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 934 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 935 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 936 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 937 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 938 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 939 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 940 __le16 status; 941 union { 942 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 943 struct ice_sw_rule_lg_act lg_act; 944 struct ice_sw_rule_vsi_list vsi_list; 945 struct ice_sw_rule_vsi_list_query vsi_list_query; 946 } pdata; 947 }; 948 949 #pragma pack() 950 951 /* PFC Ignore (direct 0x0301) 952 * The command and response use the same descriptor structure 953 */ 954 struct ice_aqc_pfc_ignore { 955 u8 tc_bitmap; 956 u8 cmd_flags; /* unused in response */ 957 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 958 #define ICE_AQC_PFC_IGNORE_CLEAR 0 959 u8 reserved[14]; 960 }; 961 962 /* Set PFC Mode (direct 0x0303) 963 * Query PFC Mode (direct 0x0302) 964 */ 965 struct ice_aqc_set_query_pfc_mode { 966 u8 pfc_mode; 967 /* For Set Command response, reserved in all other cases */ 968 #define ICE_AQC_PFC_NOT_CONFIGURED 0 969 /* For Query Command response, reserved in all other cases */ 970 #define ICE_AQC_DCB_DIS 0 971 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 972 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 973 u8 rsvd[15]; 974 }; 975 976 /* Set DCB Parameters (direct 0x0306) */ 977 struct ice_aqc_set_dcb_params { 978 u8 cmd_flags; /* unused in response */ 979 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 980 u8 valid_flags; /* unused in response */ 981 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 982 u8 rsvd[14]; 983 }; 984 985 /* Get Default Topology (indirect 0x0400) */ 986 struct ice_aqc_get_topo { 987 u8 port_num; 988 u8 num_branches; 989 __le16 reserved1; 990 __le32 reserved2; 991 __le32 addr_high; 992 __le32 addr_low; 993 }; 994 995 /* Update TSE (indirect 0x0403) 996 * Get TSE (indirect 0x0404) 997 * Add TSE (indirect 0x0401) 998 * Delete TSE (indirect 0x040F) 999 * Move TSE (indirect 0x0408) 1000 * Suspend Nodes (indirect 0x0409) 1001 * Resume Nodes (indirect 0x040A) 1002 */ 1003 struct ice_aqc_sched_elem_cmd { 1004 __le16 num_elem_req; /* Used by commands */ 1005 __le16 num_elem_resp; /* Used by responses */ 1006 __le32 reserved; 1007 __le32 addr_high; 1008 __le32 addr_low; 1009 }; 1010 1011 /* This is the buffer for: 1012 * Suspend Nodes (indirect 0x0409) 1013 * Resume Nodes (indirect 0x040A) 1014 */ 1015 struct ice_aqc_suspend_resume_elem { 1016 __le32 teid[1]; 1017 }; 1018 1019 struct ice_aqc_txsched_move_grp_info_hdr { 1020 __le32 src_parent_teid; 1021 __le32 dest_parent_teid; 1022 __le16 num_elems; 1023 __le16 reserved; 1024 }; 1025 1026 struct ice_aqc_move_elem { 1027 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1028 __le32 teid[1]; 1029 }; 1030 1031 struct ice_aqc_elem_info_bw { 1032 __le16 bw_profile_idx; 1033 __le16 bw_alloc; 1034 }; 1035 1036 struct ice_aqc_txsched_elem { 1037 u8 elem_type; /* Special field, reserved for some aq calls */ 1038 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1039 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1040 #define ICE_AQC_ELEM_TYPE_TC 0x2 1041 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1042 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1043 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1044 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1045 u8 valid_sections; 1046 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1047 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1048 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1049 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1050 u8 generic; 1051 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1052 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1053 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1054 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1055 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1056 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1057 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1058 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1059 u8 flags; /* Special field, reserved for some aq calls */ 1060 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1061 struct ice_aqc_elem_info_bw cir_bw; 1062 struct ice_aqc_elem_info_bw eir_bw; 1063 __le16 srl_id; 1064 __le16 reserved2; 1065 }; 1066 1067 struct ice_aqc_txsched_elem_data { 1068 __le32 parent_teid; 1069 __le32 node_teid; 1070 struct ice_aqc_txsched_elem data; 1071 }; 1072 1073 struct ice_aqc_txsched_topo_grp_info_hdr { 1074 __le32 parent_teid; 1075 __le16 num_elems; 1076 __le16 reserved2; 1077 }; 1078 1079 struct ice_aqc_add_elem { 1080 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1081 struct ice_aqc_txsched_elem_data generic[1]; 1082 }; 1083 1084 struct ice_aqc_conf_elem { 1085 struct ice_aqc_txsched_elem_data generic[1]; 1086 }; 1087 1088 struct ice_aqc_get_elem { 1089 struct ice_aqc_txsched_elem_data generic[1]; 1090 }; 1091 1092 struct ice_aqc_get_topo_elem { 1093 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1094 struct ice_aqc_txsched_elem_data 1095 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1096 }; 1097 1098 struct ice_aqc_delete_elem { 1099 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1100 __le32 teid[1]; 1101 }; 1102 1103 /* Query Port ETS (indirect 0x040E) 1104 * 1105 * This indirect command is used to query port TC node configuration. 1106 */ 1107 struct ice_aqc_query_port_ets { 1108 __le32 port_teid; 1109 __le32 reserved; 1110 __le32 addr_high; 1111 __le32 addr_low; 1112 }; 1113 1114 struct ice_aqc_port_ets_elem { 1115 u8 tc_valid_bits; 1116 u8 reserved[3]; 1117 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1118 __le32 up2tc; 1119 u8 tc_bw_share[8]; 1120 __le32 port_eir_prof_id; 1121 __le32 port_cir_prof_id; 1122 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1123 __le32 tc_node_prio; 1124 #define ICE_TC_NODE_PRIO_S 0x4 1125 u8 reserved1[4]; 1126 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1127 }; 1128 1129 /* Rate limiting profile for 1130 * Add RL profile (indirect 0x0410) 1131 * Query RL profile (indirect 0x0411) 1132 * Remove RL profile (indirect 0x0415) 1133 * These indirect commands acts on single or multiple 1134 * RL profiles with specified data. 1135 */ 1136 struct ice_aqc_rl_profile { 1137 __le16 num_profiles; 1138 __le16 num_processed; /* Only for response. Reserved in Command. */ 1139 u8 reserved[4]; 1140 __le32 addr_high; 1141 __le32 addr_low; 1142 }; 1143 1144 struct ice_aqc_rl_profile_elem { 1145 u8 level; 1146 u8 flags; 1147 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1148 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1149 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1150 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1151 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1152 /* The following flag is used for Query RL Profile Data */ 1153 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1154 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1155 1156 __le16 profile_id; 1157 __le16 max_burst_size; 1158 __le16 rl_multiply; 1159 __le16 wake_up_calc; 1160 __le16 rl_encode; 1161 }; 1162 1163 struct ice_aqc_rl_profile_generic_elem { 1164 struct ice_aqc_rl_profile_elem generic[1]; 1165 }; 1166 1167 /* Configure L2 Node CGD (indirect 0x0414) 1168 * This indirect command allows configuring a congestion domain for given L2 1169 * node TEIDs in the scheduler topology. 1170 */ 1171 struct ice_aqc_cfg_l2_node_cgd { 1172 __le16 num_l2_nodes; 1173 u8 reserved[6]; 1174 __le32 addr_high; 1175 __le32 addr_low; 1176 }; 1177 1178 struct ice_aqc_cfg_l2_node_cgd_elem { 1179 __le32 node_teid; 1180 u8 cgd; 1181 u8 reserved[3]; 1182 }; 1183 1184 struct ice_aqc_cfg_l2_node_cgd_data { 1185 struct ice_aqc_cfg_l2_node_cgd_elem elem[1]; 1186 }; 1187 1188 /* Query Scheduler Resource Allocation (indirect 0x0412) 1189 * This indirect command retrieves the scheduler resources allocated by 1190 * EMP Firmware to the given PF. 1191 */ 1192 struct ice_aqc_query_txsched_res { 1193 u8 reserved[8]; 1194 __le32 addr_high; 1195 __le32 addr_low; 1196 }; 1197 1198 struct ice_aqc_generic_sched_props { 1199 __le16 phys_levels; 1200 __le16 logical_levels; 1201 u8 flattening_bitmap; 1202 u8 max_device_cgds; 1203 u8 max_pf_cgds; 1204 u8 rsvd0; 1205 __le16 rdma_qsets; 1206 u8 rsvd1[22]; 1207 }; 1208 1209 struct ice_aqc_layer_props { 1210 u8 logical_layer; 1211 u8 chunk_size; 1212 __le16 max_device_nodes; 1213 __le16 max_pf_nodes; 1214 u8 rsvd0[4]; 1215 __le16 max_sibl_grp_sz; 1216 __le16 max_cir_rl_profiles; 1217 __le16 max_eir_rl_profiles; 1218 __le16 max_srl_profiles; 1219 u8 rsvd1[14]; 1220 }; 1221 1222 struct ice_aqc_query_txsched_res_resp { 1223 struct ice_aqc_generic_sched_props sched_props; 1224 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1225 }; 1226 1227 /* Query Node to Root Topology (indirect 0x0413) 1228 * This command uses ice_aqc_get_elem as its data buffer. 1229 */ 1230 struct ice_aqc_query_node_to_root { 1231 __le32 teid; 1232 __le32 num_nodes; /* Response only */ 1233 __le32 addr_high; 1234 __le32 addr_low; 1235 }; 1236 1237 /* Get PHY capabilities (indirect 0x0600) */ 1238 struct ice_aqc_get_phy_caps { 1239 u8 lport_num; 1240 u8 reserved; 1241 __le16 param0; 1242 /* 18.0 - Report qualified modules */ 1243 #define ICE_AQC_GET_PHY_RQM BIT(0) 1244 /* 18.1 - 18.2 : Report mode 1245 * 00b - Report NVM capabilities 1246 * 01b - Report topology capabilities 1247 * 10b - Report SW configured 1248 */ 1249 #define ICE_AQC_REPORT_MODE_S 1 1250 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 1251 #define ICE_AQC_REPORT_NVM_CAP 0 1252 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 1253 #define ICE_AQC_REPORT_SW_CFG BIT(2) 1254 __le32 reserved1; 1255 __le32 addr_high; 1256 __le32 addr_low; 1257 }; 1258 1259 /* This is #define of PHY type (Extended): 1260 * The first set of defines is for phy_type_low. 1261 */ 1262 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1263 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1264 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1265 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1266 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1267 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1268 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1269 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1270 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1271 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1272 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1273 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1274 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1275 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1276 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1277 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1278 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1279 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1280 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1281 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1282 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1283 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1284 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1285 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1286 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1287 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1288 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1289 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1290 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1291 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1292 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1293 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1294 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1295 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1296 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1297 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1298 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1299 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1300 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1301 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1302 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1303 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1304 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1305 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1306 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1307 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1308 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1309 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1310 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1311 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1312 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1313 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1314 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1315 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1316 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1317 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1318 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1319 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1320 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1321 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1322 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1323 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1324 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1325 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1326 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1327 /* The second set of defines is for phy_type_high. */ 1328 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1329 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1330 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1331 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1332 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1333 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 1334 1335 struct ice_aqc_get_phy_caps_data { 1336 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1337 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1338 u8 caps; 1339 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1340 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1341 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1342 #define ICE_AQC_PHY_EN_LINK BIT(3) 1343 #define ICE_AQC_PHY_AN_MODE BIT(4) 1344 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1345 #define ICE_AQC_PHY_EN_LESM BIT(6) 1346 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1347 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1348 u8 low_power_ctrl_an; 1349 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1350 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1351 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1352 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1353 __le16 eee_cap; 1354 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1355 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1356 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1357 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1358 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1359 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1360 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1361 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1362 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1363 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1364 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1365 __le16 eeer_value; 1366 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1367 u8 phy_fw_ver[8]; 1368 u8 link_fec_options; 1369 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1370 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1371 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1372 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1373 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1374 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1375 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1376 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1377 u8 module_compliance_enforcement; 1378 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1379 u8 extended_compliance_code; 1380 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1381 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1382 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1383 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1384 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1385 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1386 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1387 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1388 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1389 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1390 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1391 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1392 u8 qualified_module_count; 1393 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1394 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1395 struct { 1396 u8 v_oui[3]; 1397 u8 rsvd3; 1398 u8 v_part[16]; 1399 __le32 v_rev; 1400 __le64 rsvd4; 1401 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1402 }; 1403 1404 /* Set PHY capabilities (direct 0x0601) 1405 * NOTE: This command must be followed by setup link and restart auto-neg 1406 */ 1407 struct ice_aqc_set_phy_cfg { 1408 u8 lport_num; 1409 u8 reserved[7]; 1410 __le32 addr_high; 1411 __le32 addr_low; 1412 }; 1413 1414 /* Set PHY config command data structure */ 1415 struct ice_aqc_set_phy_cfg_data { 1416 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1417 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1418 u8 caps; 1419 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1420 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1421 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1422 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1423 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1424 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1425 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1426 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1427 u8 low_power_ctrl_an; 1428 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1429 __le16 eeer_value; 1430 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1431 u8 module_compliance_enforcement; 1432 }; 1433 1434 /* Set MAC Config command data structure (direct 0x0603) */ 1435 struct ice_aqc_set_mac_cfg { 1436 __le16 max_frame_size; 1437 u8 params; 1438 #define ICE_AQ_SET_MAC_PACE_S 3 1439 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1440 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1441 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1442 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1443 u8 tx_tmr_priority; 1444 __le16 tx_tmr_value; 1445 __le16 fc_refresh_threshold; 1446 u8 drop_opts; 1447 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1448 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1449 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1450 u8 reserved[7]; 1451 }; 1452 1453 /* Restart AN command data structure (direct 0x0605) 1454 * Also used for response, with only the lport_num field present. 1455 */ 1456 struct ice_aqc_restart_an { 1457 u8 lport_num; 1458 u8 reserved; 1459 u8 cmd_flags; 1460 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1461 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1462 u8 reserved2[13]; 1463 }; 1464 1465 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1466 struct ice_aqc_get_link_status { 1467 u8 lport_num; 1468 u8 reserved; 1469 __le16 cmd_flags; 1470 #define ICE_AQ_LSE_M 0x3 1471 #define ICE_AQ_LSE_NOP 0x0 1472 #define ICE_AQ_LSE_DIS 0x2 1473 #define ICE_AQ_LSE_ENA 0x3 1474 /* only response uses this flag */ 1475 #define ICE_AQ_LSE_IS_ENABLED 0x1 1476 __le32 reserved2; 1477 __le32 addr_high; 1478 __le32 addr_low; 1479 }; 1480 1481 /* Get link status response data structure, also used for Link Status Event */ 1482 struct ice_aqc_get_link_status_data { 1483 u8 topo_media_conflict; 1484 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1485 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1486 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1487 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1488 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1489 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1490 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1491 u8 link_cfg_err; 1492 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1493 u8 link_info; 1494 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1495 #define ICE_AQ_LINK_FAULT BIT(1) 1496 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1497 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1498 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1499 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1500 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1501 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1502 u8 an_info; 1503 #define ICE_AQ_AN_COMPLETED BIT(0) 1504 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1505 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1506 #define ICE_AQ_FEC_EN BIT(3) 1507 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1508 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1509 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1510 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1511 u8 ext_info; 1512 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1513 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1514 /* Port Tx Suspended */ 1515 #define ICE_AQ_LINK_TX_S 2 1516 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1517 #define ICE_AQ_LINK_TX_ACTIVE 0 1518 #define ICE_AQ_LINK_TX_DRAINED 1 1519 #define ICE_AQ_LINK_TX_FLUSHED 3 1520 u8 lb_status; 1521 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1522 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1523 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1524 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1525 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1526 __le16 max_frame_size; 1527 u8 cfg; 1528 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1529 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1530 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1531 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1532 /* Pacing Config */ 1533 #define ICE_AQ_CFG_PACING_S 3 1534 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1535 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1536 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1537 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1538 /* External Device Power Ability */ 1539 u8 power_desc; 1540 #define ICE_AQ_PWR_CLASS_M 0x3 1541 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1542 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1543 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1544 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1545 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1546 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1547 __le16 link_speed; 1548 #define ICE_AQ_LINK_SPEED_M 0x7FF 1549 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1550 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1551 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1552 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1553 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1554 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1555 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1556 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1557 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1558 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1559 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1560 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1561 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1562 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1563 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1564 }; 1565 1566 /* Set event mask command (direct 0x0613) */ 1567 struct ice_aqc_set_event_mask { 1568 u8 lport_num; 1569 u8 reserved[7]; 1570 __le16 event_mask; 1571 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1572 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1573 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1574 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1575 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1576 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1577 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1578 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1579 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1580 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1581 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1582 u8 reserved1[6]; 1583 }; 1584 1585 /* Set PHY Loopback command (direct 0x0619) */ 1586 struct ice_aqc_set_phy_lb { 1587 u8 lport_num; 1588 u8 lport_num_valid; 1589 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0) 1590 u8 phy_index; 1591 u8 lb_mode; 1592 #define ICE_AQ_PHY_LB_EN BIT(0) 1593 #define ICE_AQ_PHY_LB_TYPE_M BIT(1) 1594 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0 1595 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M 1596 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2) 1597 #define ICE_AQ_PHY_LB_LEVEL_PMD 0 1598 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M 1599 u8 reserved2[12]; 1600 }; 1601 1602 /* Set MAC Loopback command (direct 0x0620) */ 1603 struct ice_aqc_set_mac_lb { 1604 u8 lb_mode; 1605 #define ICE_AQ_MAC_LB_EN BIT(0) 1606 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1607 u8 reserved[15]; 1608 }; 1609 1610 /* DNL Get Status command (indirect 0x680) 1611 * Structure used for the response, the command uses the generic 1612 * ice_aqc_generic struct to pass a buffer address to the FW. 1613 */ 1614 struct ice_aqc_dnl_get_status { 1615 u8 ctx; 1616 u8 status; 1617 #define ICE_AQ_DNL_STATUS_IDLE 0x0 1618 #define ICE_AQ_DNL_STATUS_RESERVED 0x1 1619 #define ICE_AQ_DNL_STATUS_STOPPED 0x2 1620 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */ 1621 #define ICE_AQ_DNL_SRC_S 3 1622 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S) 1623 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S) 1624 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S) 1625 u8 stack_ptr; 1626 #define ICE_AQ_DNL_ST_PTR_S 0x0 1627 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S) 1628 u8 engine_flags; 1629 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2) 1630 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3) 1631 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4) 1632 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5) 1633 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6) 1634 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7) 1635 __le16 pc; 1636 __le16 activity_id; 1637 __le32 addr_high; 1638 __le32 addr_low; 1639 }; 1640 1641 struct ice_aqc_dnl_get_status_data { 1642 __le16 activity_err_code; 1643 __le16 act_err_code; 1644 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */ 1645 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */ 1646 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */ 1647 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */ 1648 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */ 1649 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */ 1650 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */ 1651 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */ 1652 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */ 1653 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */ 1654 __le32 execution_time; /* in nanoseconds */ 1655 __le16 lib_ver; 1656 u8 psto_local_sz; 1657 u8 psto_global_sz; 1658 u8 stack_sz; 1659 #define ICE_AQ_DNL_STACK_SZ_S 0 1660 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S) 1661 u8 port_count; 1662 #define ICE_AQ_DNL_PORT_CNT_S 0 1663 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S) 1664 __le16 act_cache_cntr; 1665 u32 i2c_clk_cntr; 1666 u32 mdio_clk_cntr; 1667 u32 sb_iosf_clk_cntr; 1668 }; 1669 1670 /* DNL run command (direct 0x681) */ 1671 struct ice_aqc_dnl_run_command { 1672 u8 reserved0; 1673 u8 command; 1674 #define ICE_AQ_DNL_CMD_S 0 1675 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S) 1676 #define ICE_AQ_DNL_CMD_RESET 0x0 1677 #define ICE_AQ_DNL_CMD_RUN 0x1 1678 #define ICE_AQ_DNL_CMD_STEP 0x3 1679 #define ICE_AQ_DNL_CMD_ABORT 0x4 1680 #define ICE_AQ_DNL_CMD_SET_PC 0x7 1681 #define ICE_AQ_DNL_CMD_SRC_S 3 1682 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S) 1683 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0 1684 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1 1685 __le16 new_pc; 1686 u8 reserved1[12]; 1687 }; 1688 1689 /* DNL call command (indirect 0x682) 1690 * Struct is used for both command and response 1691 */ 1692 struct ice_aqc_dnl_call_command { 1693 u8 ctx; /* Used in command, reserved in response */ 1694 u8 reserved; 1695 __le16 activity_id; 1696 __le32 reserved1; 1697 __le32 addr_high; 1698 __le32 addr_low; 1699 }; 1700 1701 /* DNL call command/response buffer (indirect 0x682) */ 1702 struct ice_aqc_dnl_call { 1703 __le32 stores[4]; 1704 }; 1705 1706 /* Used for both commands: 1707 * DNL read sto command (indirect 0x683) 1708 * DNL write sto command (indirect 0x684) 1709 */ 1710 struct ice_aqc_dnl_read_write_command { 1711 u8 ctx; 1712 u8 sto_sel; /* STORE select */ 1713 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0 1714 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1 1715 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2 1716 __le16 offset; 1717 __le32 data; /* Used for write sto only */ 1718 __le32 addr_high; /* Used for read sto only */ 1719 __le32 addr_low; /* Used for read sto only */ 1720 }; 1721 1722 /* Used for both command responses: 1723 * DNL read sto response (indirect 0x683) 1724 * DNL write sto response (indirect 0x684) 1725 */ 1726 struct ice_aqc_dnl_read_write_response { 1727 u8 reserved; 1728 u8 status; /* Reserved for read command */ 1729 __le16 size; /* Reserved for write command */ 1730 __le32 data; /* Reserved for write command */ 1731 __le32 addr_high; /* Reserved for write command */ 1732 __le32 addr_low; /* Reserved for write command */ 1733 }; 1734 1735 /* DNL set breakpoints command (indirect 0x686) */ 1736 struct ice_aqc_dnl_set_breakpoints_command { 1737 __le32 reserved[2]; 1738 __le32 addr_high; 1739 __le32 addr_low; 1740 }; 1741 1742 /* DNL set breakpoints data buffer structure (indirect 0x686) */ 1743 struct ice_aqc_dnl_set_breakpoints { 1744 u8 ctx; 1745 u8 ena; /* 0- disabled, 1- enabled */ 1746 __le16 offset; 1747 __le16 activity_id; 1748 }; 1749 1750 /* DNL read log data command(indirect 0x687) */ 1751 struct ice_aqc_dnl_read_log_command { 1752 __le16 reserved0; 1753 __le16 offset; 1754 __le32 reserved1; 1755 __le32 addr_high; 1756 __le32 addr_low; 1757 1758 }; 1759 1760 /* DNL read log data response(indirect 0x687) */ 1761 struct ice_aqc_dnl_read_log_response { 1762 __le16 reserved; 1763 __le16 size; 1764 __le32 data; 1765 __le32 addr_high; 1766 __le32 addr_low; 1767 1768 }; 1769 1770 struct ice_aqc_link_topo_addr { 1771 u8 lport_num; 1772 u8 lport_num_valid; 1773 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1774 u8 node_type_ctx; 1775 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1776 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1777 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1778 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1779 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1780 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1781 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1782 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1783 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1784 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1785 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1786 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1787 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1788 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1789 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1790 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1791 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1792 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1793 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1794 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1795 u8 index; 1796 __le16 handle; 1797 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1798 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1799 /* Used to decode the handle field */ 1800 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1801 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1802 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1803 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1804 /* In case of a Mezzanine type */ 1805 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1806 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1807 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1808 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1809 /* In case of a LOM type */ 1810 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1811 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1812 }; 1813 1814 /* Get Link Topology Handle (direct, 0x06E0) */ 1815 struct ice_aqc_get_link_topo { 1816 struct ice_aqc_link_topo_addr addr; 1817 u8 node_part_num; 1818 u8 rsvd[9]; 1819 }; 1820 1821 /* Get Link Topology Pin (direct, 0x06E1) */ 1822 struct ice_aqc_get_link_topo_pin { 1823 struct ice_aqc_link_topo_addr addr; 1824 u8 input_io_params; 1825 #define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S 0 1826 #define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_M \ 1827 (0x1F << ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S) 1828 #define ICE_AQC_LINK_TOPO_IO_FUNC_GPIO 0 1829 #define ICE_AQC_LINK_TOPO_IO_FUNC_RESET_N 1 1830 #define ICE_AQC_LINK_TOPO_IO_FUNC_INT_N 2 1831 #define ICE_AQC_LINK_TOPO_IO_FUNC_PRESENT_N 3 1832 #define ICE_AQC_LINK_TOPO_IO_FUNC_TX_DIS 4 1833 #define ICE_AQC_LINK_TOPO_IO_FUNC_MODSEL_N 5 1834 #define ICE_AQC_LINK_TOPO_IO_FUNC_LPMODE 6 1835 #define ICE_AQC_LINK_TOPO_IO_FUNC_TX_FAULT 7 1836 #define ICE_AQC_LINK_TOPO_IO_FUNC_RX_LOSS 8 1837 #define ICE_AQC_LINK_TOPO_IO_FUNC_RS0 9 1838 #define ICE_AQC_LINK_TOPO_IO_FUNC_RS1 10 1839 #define ICE_AQC_LINK_TOPO_IO_FUNC_EEPROM_WP 11 1840 /* 12 repeats intentionally due to two different uses depending on context */ 1841 #define ICE_AQC_LINK_TOPO_IO_FUNC_LED 12 1842 #define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12 1843 #define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED 13 1844 #define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14 1845 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5 1846 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \ 1847 (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) 1848 /* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ 1849 u8 output_io_params; 1850 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_S 0 1851 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_M \ 1852 (0x1F << \ ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_NUM_S) 1853 /* Use ICE_AQC_LINK_TOPO_IO_FUNC_* for the non-numerical options */ 1854 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_S 5 1855 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_M \ 1856 (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) 1857 /* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ 1858 u8 output_io_flags; 1859 #define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S 0 1860 #define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_M \ 1861 (0x7 << ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S) 1862 #define ICE_AQC_LINK_TOPO_OUTPUT_INT_S 3 1863 #define ICE_AQC_LINK_TOPO_OUTPUT_INT_M \ 1864 (0x3 << ICE_AQC_LINK_TOPO_OUTPUT_INT_S) 1865 #define ICE_AQC_LINK_TOPO_OUTPUT_POLARITY BIT(5) 1866 #define ICE_AQC_LINK_TOPO_OUTPUT_VALUE BIT(6) 1867 #define ICE_AQC_LINK_TOPO_OUTPUT_DRIVEN BIT(7) 1868 u8 rsvd[7]; 1869 }; 1870 1871 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1872 struct ice_aqc_i2c { 1873 struct ice_aqc_link_topo_addr topo_addr; 1874 __le16 i2c_addr; 1875 u8 i2c_params; 1876 #define ICE_AQC_I2C_DATA_SIZE_S 0 1877 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 1878 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 1879 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 1880 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 1881 #define ICE_AQC_I2C_DATA_OFFSET_S 5 1882 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 1883 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1884 u8 rsvd; 1885 __le16 i2c_bus_addr; 1886 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 1887 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 1888 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1889 }; 1890 1891 /* Read I2C Response (direct, 0x06E2) */ 1892 struct ice_aqc_read_i2c_resp { 1893 u8 i2c_data[16]; 1894 }; 1895 1896 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 1897 struct ice_aqc_mdio { 1898 struct ice_aqc_link_topo_addr topo_addr; 1899 u8 mdio_device_addr; 1900 #define ICE_AQC_MDIO_DEV_S 0 1901 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S) 1902 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5) 1903 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6) 1904 u8 rsvd; 1905 __le16 offset; 1906 __le16 data; /* Input in write cmd, output in read cmd. */ 1907 u8 rsvd1[4]; 1908 }; 1909 1910 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 1911 struct ice_aqc_gpio_by_func { 1912 struct ice_aqc_link_topo_addr topo_addr; 1913 u8 io_func_num; 1914 #define ICE_AQC_GPIO_FUNC_S 0 1915 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S) 1916 u8 io_value; /* Input in write cmd, output in read cmd. */ 1917 #define ICE_AQC_GPIO_ON BIT(0) 1918 #define ICE_AQC_GPIO_OFF 0 1919 u8 rsvd[8]; 1920 }; 1921 1922 /* Set LED (direct, 0x06E8) */ 1923 struct ice_aqc_set_led { 1924 struct ice_aqc_link_topo_addr topo_addr; 1925 u8 color_and_blink; 1926 #define ICE_AQC_LED_COLOR_S 0 1927 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S) 1928 #define ICE_AQC_LED_COLOR_SKIP 0 1929 #define ICE_AQC_LED_COLOR_RED 1 1930 #define ICE_AQC_LED_COLOR_ORANGE 2 1931 #define ICE_AQC_LED_COLOR_YELLOW 3 1932 #define ICE_AQC_LED_COLOR_GREEN 4 1933 #define ICE_AQC_LED_COLOR_BLUE 5 1934 #define ICE_AQC_LED_COLOR_PURPLE 6 1935 #define ICE_AQC_LED_BLINK_S 3 1936 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S) 1937 #define ICE_AQC_LED_BLINK_NONE 0 1938 #define ICE_AQC_LED_BLINK_SLOW 1 1939 #define ICE_AQC_LED_BLINK_SLOW_MAC 2 1940 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3 1941 #define ICE_AQC_LED_BLINK_FAST 5 1942 #define ICE_AQC_LED_BLINK_FAST_MAC 6 1943 #define ICE_AQC_LED_BLINK_FAST_FLTR 7 1944 u8 rsvd[9]; 1945 }; 1946 1947 /* Set Port Identification LED (direct, 0x06E9) */ 1948 struct ice_aqc_set_port_id_led { 1949 u8 lport_num; 1950 u8 lport_num_valid; 1951 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1952 u8 ident_mode; 1953 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1954 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1955 u8 rsvd[13]; 1956 }; 1957 1958 /* Get Port Options (indirect, 0x06EA) */ 1959 struct ice_aqc_get_port_options { 1960 u8 lport_num; 1961 u8 lport_num_valid; 1962 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0) 1963 u8 port_options_count; 1964 #define ICE_AQC_PORT_OPT_COUNT_S 0 1965 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) 1966 u8 innermost_phy_index; 1967 u8 port_options; 1968 #define ICE_AQC_PORT_OPT_ACTIVE_S 0 1969 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) 1970 #define ICE_AQC_PORT_OPT_FORCED BIT(6) 1971 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1972 u8 rsvd[3]; 1973 __le32 addr_high; 1974 __le32 addr_low; 1975 }; 1976 1977 struct ice_aqc_get_port_options_elem { 1978 u8 pmd; 1979 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 1980 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) 1981 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 1982 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) 1983 u8 max_lane_speed; 1984 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 1985 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) 1986 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1987 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1988 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1989 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1990 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1991 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1992 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1993 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1994 u8 global_scid[2]; 1995 u8 phy_scid[2]; 1996 }; 1997 1998 /* The buffer for command 0x06EA contains port_options_count of options 1999 * in the option array. 2000 */ 2001 struct ice_aqc_get_port_options_data { 2002 struct ice_aqc_get_port_options_elem option[1]; 2003 }; 2004 2005 /* Set Port Option (direct, 0x06EB) */ 2006 struct ice_aqc_set_port_option { 2007 u8 lport_num; 2008 u8 lport_num_valid; 2009 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) 2010 u8 selected_port_option; 2011 u8 rsvd[13]; 2012 }; 2013 2014 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 2015 struct ice_aqc_gpio { 2016 __le16 gpio_ctrl_handle; 2017 #define ICE_AQC_GPIO_HANDLE_S 0 2018 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 2019 u8 gpio_num; 2020 u8 gpio_val; 2021 u8 rsvd[12]; 2022 }; 2023 2024 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 2025 struct ice_aqc_sff_eeprom { 2026 u8 lport_num; 2027 u8 lport_num_valid; 2028 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 2029 __le16 i2c_bus_addr; 2030 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 2031 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 2032 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 2033 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 2034 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 2035 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 2036 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 2037 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 2038 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 2039 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 2040 #define ICE_AQC_SFF_IS_WRITE BIT(15) 2041 __le16 i2c_mem_addr; 2042 __le16 eeprom_page; 2043 #define ICE_AQC_SFF_EEPROM_BANK_S 0 2044 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 2045 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 2046 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 2047 __le32 addr_high; 2048 __le32 addr_low; 2049 }; 2050 2051 /* NVM Read command (indirect 0x0701) 2052 * NVM Erase commands (direct 0x0702) 2053 * NVM Write commands (indirect 0x0703) 2054 * NVM Write Activate commands (direct 0x0707) 2055 * NVM Shadow RAM Dump commands (direct 0x0707) 2056 */ 2057 struct ice_aqc_nvm { 2058 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 2059 __le16 offset_low; 2060 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 2061 u8 cmd_flags; 2062 #define ICE_AQC_NVM_LAST_CMD BIT(0) 2063 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 2064 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 2065 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 2066 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 2067 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 2068 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 2069 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 2070 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 2071 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 2072 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 2073 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 2074 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 2075 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 2076 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 2077 __le16 module_typeid; 2078 __le16 length; 2079 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 2080 __le32 addr_high; 2081 __le32 addr_low; 2082 }; 2083 2084 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 2085 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 2086 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 2087 2088 #define ICE_AQC_NVM_START_POINT 0 2089 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 2090 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 2091 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 2092 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 2093 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 2094 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 2095 2096 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 2097 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 2098 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2099 2100 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 2101 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 2102 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 2103 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 2104 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 2105 2106 /* The result of netlist NVM read comes in a TLV format. The actual data 2107 * (netlist header) starts from word offset 1 (byte 2). The FW strips 2108 * out the type field from the TLV header so all the netlist fields 2109 * should adjust their offset value by 1 word (2 bytes) in order to map 2110 * their correct location. 2111 */ 2112 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B 2113 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 2114 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ 2115 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 2116 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ 2117 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 2118 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ 2119 2120 /* netlist ID block field offsets (word offsets) */ 2121 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 2122 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 2123 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 2124 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 2125 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 2126 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 2127 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 2128 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 2129 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA 2130 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F 2131 2132 /* Used for 0x0704 as well as for 0x0705 commands */ 2133 struct ice_aqc_nvm_cfg { 2134 u8 cmd_flags; 2135 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 2136 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 2137 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 2138 u8 reserved; 2139 __le16 count; 2140 __le16 id; 2141 u8 reserved1[2]; 2142 __le32 addr_high; 2143 __le32 addr_low; 2144 }; 2145 2146 struct ice_aqc_nvm_cfg_data { 2147 __le16 field_id; 2148 __le16 field_options; 2149 __le16 field_value; 2150 }; 2151 2152 /* NVM Checksum Command (direct, 0x0706) */ 2153 struct ice_aqc_nvm_checksum { 2154 u8 flags; 2155 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 2156 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 2157 u8 rsvd; 2158 __le16 checksum; /* Used only by response */ 2159 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 2160 u8 rsvd2[12]; 2161 }; 2162 2163 /** 2164 * Send to PF command (indirect 0x0801) ID is only used by PF 2165 * 2166 * Send to VF command (indirect 0x0802) ID is only used by PF 2167 * 2168 */ 2169 struct ice_aqc_pf_vf_msg { 2170 __le32 id; 2171 u32 reserved; 2172 __le32 addr_high; 2173 __le32 addr_low; 2174 }; 2175 2176 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 2177 struct ice_aqc_read_write_alt_direct { 2178 __le32 dword0_addr; 2179 __le32 dword0_value; 2180 __le32 dword1_addr; 2181 __le32 dword1_value; 2182 }; 2183 2184 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 2185 struct ice_aqc_read_write_alt_indirect { 2186 __le32 base_dword_addr; 2187 __le32 num_dwords; 2188 __le32 addr_high; 2189 __le32 addr_low; 2190 }; 2191 2192 /* Done Alternate Write (direct 0x0904) */ 2193 struct ice_aqc_done_alt_write { 2194 u8 flags; 2195 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0) 2196 #define ICE_AQC_RESP_RESET_NEEDED BIT(1) 2197 u8 reserved[15]; 2198 }; 2199 2200 /* Clear Port Alternate Write (direct 0x0906) */ 2201 struct ice_aqc_clear_port_alt_write { 2202 u8 reserved[16]; 2203 }; 2204 2205 /* Get LLDP MIB (indirect 0x0A00) 2206 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 2207 * as the format is the same. 2208 */ 2209 struct ice_aqc_lldp_get_mib { 2210 u8 type; 2211 #define ICE_AQ_LLDP_MIB_TYPE_S 0 2212 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 2213 #define ICE_AQ_LLDP_MIB_LOCAL 0 2214 #define ICE_AQ_LLDP_MIB_REMOTE 1 2215 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 2216 #define ICE_AQ_LLDP_BRID_TYPE_S 2 2217 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 2218 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 2219 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 2220 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 2221 #define ICE_AQ_LLDP_TX_S 0x4 2222 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 2223 #define ICE_AQ_LLDP_TX_ACTIVE 0 2224 #define ICE_AQ_LLDP_TX_SUSPENDED 1 2225 #define ICE_AQ_LLDP_TX_FLUSHED 3 2226 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 2227 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 2228 * Get LLDP MIB (0x0A00) response only. 2229 */ 2230 u8 reserved1; 2231 __le16 local_len; 2232 __le16 remote_len; 2233 u8 reserved2[2]; 2234 __le32 addr_high; 2235 __le32 addr_low; 2236 }; 2237 2238 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 2239 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 2240 struct ice_aqc_lldp_set_mib_change { 2241 u8 command; 2242 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2243 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 2244 u8 reserved[15]; 2245 }; 2246 2247 /* Add LLDP TLV (indirect 0x0A02) 2248 * Delete LLDP TLV (indirect 0x0A04) 2249 */ 2250 struct ice_aqc_lldp_add_delete_tlv { 2251 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2252 u8 reserved1[1]; 2253 __le16 len; 2254 u8 reserved2[4]; 2255 __le32 addr_high; 2256 __le32 addr_low; 2257 }; 2258 2259 /* Update LLDP TLV (indirect 0x0A03) */ 2260 struct ice_aqc_lldp_update_tlv { 2261 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2262 u8 reserved; 2263 __le16 old_len; 2264 __le16 new_offset; 2265 __le16 new_len; 2266 __le32 addr_high; 2267 __le32 addr_low; 2268 }; 2269 2270 /* Stop LLDP (direct 0x0A05) */ 2271 struct ice_aqc_lldp_stop { 2272 u8 command; 2273 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 2274 #define ICE_AQ_LLDP_AGENT_STOP 0x0 2275 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 2276 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 2277 u8 reserved[15]; 2278 }; 2279 2280 /* Start LLDP (direct 0x0A06) */ 2281 struct ice_aqc_lldp_start { 2282 u8 command; 2283 #define ICE_AQ_LLDP_AGENT_START BIT(0) 2284 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 2285 u8 reserved[15]; 2286 }; 2287 2288 /* Get CEE DCBX Oper Config (0x0A07) 2289 * The command uses the generic descriptor struct and 2290 * returns the struct below as an indirect response. 2291 */ 2292 struct ice_aqc_get_cee_dcb_cfg_resp { 2293 u8 oper_num_tc; 2294 u8 oper_prio_tc[4]; 2295 u8 oper_tc_bw[8]; 2296 u8 oper_pfc_en; 2297 __le16 oper_app_prio; 2298 #define ICE_AQC_CEE_APP_FCOE_S 0 2299 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 2300 #define ICE_AQC_CEE_APP_ISCSI_S 3 2301 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 2302 #define ICE_AQC_CEE_APP_FIP_S 8 2303 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 2304 __le32 tlv_status; 2305 #define ICE_AQC_CEE_PG_STATUS_S 0 2306 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 2307 #define ICE_AQC_CEE_PFC_STATUS_S 3 2308 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 2309 #define ICE_AQC_CEE_FCOE_STATUS_S 8 2310 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 2311 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 2312 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 2313 #define ICE_AQC_CEE_FIP_STATUS_S 16 2314 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 2315 u8 reserved[12]; 2316 }; 2317 2318 /* Set Local LLDP MIB (indirect 0x0A08) 2319 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 2320 */ 2321 struct ice_aqc_lldp_set_local_mib { 2322 u8 type; 2323 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 2324 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 2325 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 2326 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 2327 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 2328 u8 reserved0; 2329 __le16 length; 2330 u8 reserved1[4]; 2331 __le32 addr_high; 2332 __le32 addr_low; 2333 }; 2334 2335 struct ice_aqc_lldp_set_local_mib_resp { 2336 u8 status; 2337 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2338 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2339 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2340 u8 reserved[15]; 2341 }; 2342 2343 /* Stop/Start LLDP Agent (direct 0x0A09) 2344 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2345 * The same structure is used for the response, with the command field 2346 * being used as the status field. 2347 */ 2348 struct ice_aqc_lldp_stop_start_specific_agent { 2349 u8 command; 2350 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2351 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2352 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2353 u8 reserved[15]; 2354 }; 2355 2356 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2357 struct ice_aqc_get_set_rss_key { 2358 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2359 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2360 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2361 __le16 vsi_id; 2362 u8 reserved[6]; 2363 __le32 addr_high; 2364 __le32 addr_low; 2365 }; 2366 2367 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2368 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2369 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2370 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2371 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2372 2373 /** 2374 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2375 * @standard_rss_key: 40 most significant bytes of hash key 2376 * @extended_hash_key: 12 least significant bytes of hash key 2377 * 2378 * Set/Get 40 byte hash key using standard_rss_key field, and set 2379 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2380 * standard_rss_key field for 40 most significant bytes and the 2381 * extended_hash_key field for the 12 least significant bytes of hash key. 2382 */ 2383 struct ice_aqc_get_set_rss_keys { 2384 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2385 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2386 }; 2387 2388 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2389 struct ice_aqc_get_set_rss_lut { 2390 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2391 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2392 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2393 __le16 vsi_id; 2394 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2395 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2396 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2397 2398 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2399 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2400 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2401 2402 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2403 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2404 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2405 2406 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2407 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2408 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2409 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2410 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2411 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2412 2413 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2414 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2415 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2416 2417 __le16 flags; 2418 __le32 reserved; 2419 __le32 addr_high; 2420 __le32 addr_low; 2421 }; 2422 2423 /* Add Tx LAN Queues (indirect 0x0C30) */ 2424 struct ice_aqc_add_txqs { 2425 u8 num_qgrps; 2426 u8 reserved[3]; 2427 __le32 reserved1; 2428 __le32 addr_high; 2429 __le32 addr_low; 2430 }; 2431 2432 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2433 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2434 */ 2435 struct ice_aqc_add_txqs_perq { 2436 __le16 txq_id; 2437 u8 rsvd[2]; 2438 __le32 q_teid; 2439 u8 txq_ctx[22]; 2440 u8 rsvd2[2]; 2441 struct ice_aqc_txsched_elem info; 2442 }; 2443 2444 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2445 * is an array of the following structs. Please note that the length of 2446 * each struct ice_aqc_add_tx_qgrp is variable due 2447 * to the variable number of queues in each group! 2448 */ 2449 struct ice_aqc_add_tx_qgrp { 2450 __le32 parent_teid; 2451 u8 num_txqs; 2452 u8 rsvd[3]; 2453 struct ice_aqc_add_txqs_perq txqs[1]; 2454 }; 2455 2456 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2457 struct ice_aqc_dis_txqs { 2458 u8 cmd_type; 2459 #define ICE_AQC_Q_DIS_CMD_S 0 2460 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2461 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2462 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2463 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2464 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2465 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2466 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2467 u8 num_entries; 2468 __le16 vmvf_and_timeout; 2469 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2470 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2471 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2472 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2473 __le32 blocked_cgds; 2474 __le32 addr_high; 2475 __le32 addr_low; 2476 }; 2477 2478 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2479 * contains the following structures, arrayed one after the 2480 * other. 2481 * Note: Since the q_id is 16 bits wide, if the 2482 * number of queues is even, then 2 bytes of alignment MUST be 2483 * added before the start of the next group, to allow correct 2484 * alignment of the parent_teid field. 2485 */ 2486 struct ice_aqc_dis_txq_item { 2487 __le32 parent_teid; 2488 u8 num_qs; 2489 u8 rsvd; 2490 /* The length of the q_id array varies according to num_qs */ 2491 __le16 q_id[1]; 2492 /* This only applies from F8 onward */ 2493 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2494 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2495 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2496 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2497 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2498 }; 2499 2500 struct ice_aqc_dis_txq { 2501 struct ice_aqc_dis_txq_item qgrps[1]; 2502 }; 2503 2504 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2505 struct ice_aqc_txqs_cleanup { 2506 __le16 caller_opc; 2507 __le16 cmd_tag; 2508 u8 reserved[12]; 2509 }; 2510 2511 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2512 struct ice_aqc_move_txqs { 2513 u8 cmd_type; 2514 #define ICE_AQC_Q_CMD_TYPE_S 0 2515 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2516 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2517 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2518 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2519 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2520 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2521 u8 num_qs; 2522 u8 rsvd; 2523 u8 timeout; 2524 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2525 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2526 __le32 blocked_cgds; 2527 __le32 addr_high; 2528 __le32 addr_low; 2529 }; 2530 2531 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2532 struct ice_aqc_move_txqs_elem { 2533 __le16 txq_id; 2534 u8 q_cgd; 2535 u8 rsvd; 2536 __le32 q_teid; 2537 }; 2538 2539 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2540 struct ice_aqc_move_txqs_data { 2541 __le32 src_teid; 2542 __le32 dest_teid; 2543 struct ice_aqc_move_txqs_elem txqs[1]; 2544 }; 2545 2546 /* Download Package (indirect 0x0C40) */ 2547 /* Also used for Update Package (indirect 0x0C42) */ 2548 struct ice_aqc_download_pkg { 2549 u8 flags; 2550 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2551 u8 reserved[3]; 2552 __le32 reserved1; 2553 __le32 addr_high; 2554 __le32 addr_low; 2555 }; 2556 2557 struct ice_aqc_download_pkg_resp { 2558 __le32 error_offset; 2559 __le32 error_info; 2560 __le32 addr_high; 2561 __le32 addr_low; 2562 }; 2563 2564 /* Get Package Info List (indirect 0x0C43) */ 2565 struct ice_aqc_get_pkg_info_list { 2566 __le32 reserved1; 2567 __le32 reserved2; 2568 __le32 addr_high; 2569 __le32 addr_low; 2570 }; 2571 2572 /* Version format for packages */ 2573 struct ice_pkg_ver { 2574 u8 major; 2575 u8 minor; 2576 u8 update; 2577 u8 draft; 2578 }; 2579 2580 #define ICE_PKG_NAME_SIZE 32 2581 #define ICE_SEG_NAME_SIZE 28 2582 2583 struct ice_aqc_get_pkg_info { 2584 struct ice_pkg_ver ver; 2585 char name[ICE_SEG_NAME_SIZE]; 2586 __le32 track_id; 2587 u8 is_in_nvm; 2588 u8 is_active; 2589 u8 is_active_at_boot; 2590 u8 is_modified; 2591 }; 2592 2593 /* Get Package Info List response buffer format (0x0C43) */ 2594 struct ice_aqc_get_pkg_info_resp { 2595 __le32 count; 2596 struct ice_aqc_get_pkg_info pkg_info[1]; 2597 }; 2598 2599 /* Driver Shared Parameters (direct, 0x0C90) */ 2600 struct ice_aqc_driver_shared_params { 2601 u8 set_or_get_op; 2602 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2603 #define ICE_AQC_DRIVER_PARAM_SET 0 2604 #define ICE_AQC_DRIVER_PARAM_GET 1 2605 u8 param_indx; 2606 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2607 u8 rsvd[2]; 2608 __le32 param_val; 2609 __le32 addr_high; 2610 __le32 addr_low; 2611 }; 2612 2613 /* Lan Queue Overflow Event (direct, 0x1001) */ 2614 struct ice_aqc_event_lan_overflow { 2615 __le32 prtdcb_ruptq; 2616 __le32 qtx_ctl; 2617 u8 reserved[8]; 2618 }; 2619 2620 /** 2621 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2622 * @flags: ICE_AQ_FLAG_* flags 2623 * @opcode: AQ command opcode 2624 * @datalen: length in bytes of indirect/external data buffer 2625 * @retval: return value from firmware 2626 * @cookie_h: opaque data high-half 2627 * @cookie_l: opaque data low-half 2628 * @params: command-specific parameters 2629 * 2630 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2631 * (ATQ). The firmware writes back onto the command descriptor and returns 2632 * the result of the command. Asynchronous events that are not an immediate 2633 * result of the command are written to the Admin Receive Queue (ARQ) using 2634 * the same descriptor format. Descriptors are in little-endian notation with 2635 * 32-bit words. 2636 */ 2637 struct ice_aq_desc { 2638 __le16 flags; 2639 __le16 opcode; 2640 __le16 datalen; 2641 __le16 retval; 2642 __le32 cookie_high; 2643 __le32 cookie_low; 2644 union { 2645 u8 raw[16]; 2646 struct ice_aqc_generic generic; 2647 struct ice_aqc_get_ver get_ver; 2648 struct ice_aqc_driver_ver driver_ver; 2649 struct ice_aqc_q_shutdown q_shutdown; 2650 struct ice_aqc_get_exp_err exp_err; 2651 struct ice_aqc_req_res res_owner; 2652 struct ice_aqc_manage_mac_read mac_read; 2653 struct ice_aqc_manage_mac_write mac_write; 2654 struct ice_aqc_clear_pxe clear_pxe; 2655 struct ice_aqc_config_no_drop_policy no_drop; 2656 struct ice_aqc_add_update_mir_rule add_update_rule; 2657 struct ice_aqc_delete_mir_rule del_rule; 2658 struct ice_aqc_list_caps get_cap; 2659 struct ice_aqc_get_phy_caps get_phy; 2660 struct ice_aqc_set_phy_cfg set_phy; 2661 struct ice_aqc_restart_an restart_an; 2662 struct ice_aqc_dnl_get_status get_status; 2663 struct ice_aqc_dnl_run_command dnl_run; 2664 struct ice_aqc_dnl_call_command dnl_call; 2665 struct ice_aqc_dnl_read_write_command dnl_read_write; 2666 struct ice_aqc_dnl_read_write_response dnl_read_write_resp; 2667 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; 2668 struct ice_aqc_dnl_read_log_command dnl_read_log; 2669 struct ice_aqc_dnl_read_log_response dnl_read_log_resp; 2670 struct ice_aqc_i2c read_write_i2c; 2671 struct ice_aqc_mdio read_write_mdio; 2672 struct ice_aqc_gpio_by_func read_write_gpio_by_func; 2673 struct ice_aqc_gpio read_write_gpio; 2674 struct ice_aqc_set_led set_led; 2675 struct ice_aqc_sff_eeprom read_write_sff_param; 2676 struct ice_aqc_set_port_id_led set_port_id_led; 2677 struct ice_aqc_get_port_options get_port_options; 2678 struct ice_aqc_set_port_option set_port_option; 2679 struct ice_aqc_get_sw_cfg get_sw_conf; 2680 struct ice_aqc_set_port_params set_port_params; 2681 struct ice_aqc_sw_rules sw_rules; 2682 struct ice_aqc_storm_cfg storm_conf; 2683 struct ice_aqc_get_topo get_topo; 2684 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2685 struct ice_aqc_query_txsched_res query_sched_res; 2686 struct ice_aqc_query_node_to_root query_node_to_root; 2687 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2688 struct ice_aqc_query_port_ets port_ets; 2689 struct ice_aqc_rl_profile rl_profile; 2690 struct ice_aqc_nvm nvm; 2691 struct ice_aqc_nvm_cfg nvm_cfg; 2692 struct ice_aqc_nvm_checksum nvm_checksum; 2693 struct ice_aqc_pf_vf_msg virt; 2694 struct ice_aqc_read_write_alt_direct read_write_alt_direct; 2695 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; 2696 struct ice_aqc_done_alt_write done_alt_write; 2697 struct ice_aqc_clear_port_alt_write clear_port_alt_write; 2698 struct ice_aqc_pfc_ignore pfc_ignore; 2699 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2700 struct ice_aqc_set_dcb_params set_dcb_params; 2701 struct ice_aqc_lldp_get_mib lldp_get_mib; 2702 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2703 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2704 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2705 struct ice_aqc_lldp_stop lldp_stop; 2706 struct ice_aqc_lldp_start lldp_start; 2707 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2708 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2709 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2710 struct ice_aqc_get_set_rss_key get_set_rss_key; 2711 struct ice_aqc_add_txqs add_txqs; 2712 struct ice_aqc_dis_txqs dis_txqs; 2713 struct ice_aqc_move_txqs move_txqs; 2714 struct ice_aqc_txqs_cleanup txqs_cleanup; 2715 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2716 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2717 struct ice_aqc_get_vsi_resp get_vsi_resp; 2718 struct ice_aqc_download_pkg download_pkg; 2719 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2720 struct ice_aqc_driver_shared_params drv_shared_params; 2721 struct ice_aqc_set_mac_lb set_mac_lb; 2722 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2723 struct ice_aqc_get_res_alloc get_res; 2724 struct ice_aqc_get_allocd_res_desc get_res_desc; 2725 struct ice_aqc_set_mac_cfg set_mac_cfg; 2726 struct ice_aqc_set_event_mask set_event_mask; 2727 struct ice_aqc_get_link_status get_link_status; 2728 struct ice_aqc_event_lan_overflow lan_overflow; 2729 struct ice_aqc_get_link_topo get_link_topo; 2730 } params; 2731 }; 2732 2733 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2734 #define ICE_AQ_LG_BUF 512 2735 2736 /* Flags sub-structure 2737 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2738 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2739 */ 2740 2741 /* command flags and offsets */ 2742 #define ICE_AQ_FLAG_DD_S 0 2743 #define ICE_AQ_FLAG_CMP_S 1 2744 #define ICE_AQ_FLAG_ERR_S 2 2745 #define ICE_AQ_FLAG_VFE_S 3 2746 #define ICE_AQ_FLAG_LB_S 9 2747 #define ICE_AQ_FLAG_RD_S 10 2748 #define ICE_AQ_FLAG_VFC_S 11 2749 #define ICE_AQ_FLAG_BUF_S 12 2750 #define ICE_AQ_FLAG_SI_S 13 2751 #define ICE_AQ_FLAG_EI_S 14 2752 #define ICE_AQ_FLAG_FE_S 15 2753 2754 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2755 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2756 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2757 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2758 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2759 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2760 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2761 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2762 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2763 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2764 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2765 2766 /* error codes */ 2767 enum ice_aq_err { 2768 ICE_AQ_RC_OK = 0, /* Success */ 2769 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2770 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2771 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2772 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2773 ICE_AQ_RC_EIO = 5, /* I/O error */ 2774 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2775 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2776 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2777 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2778 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2779 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2780 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2781 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2782 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2783 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2784 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2785 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2786 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2787 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2788 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2789 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2790 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2791 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2792 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2793 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2794 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2795 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2796 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2797 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2798 }; 2799 2800 /* Admin Queue command opcodes */ 2801 enum ice_adminq_opc { 2802 /* AQ commands */ 2803 ice_aqc_opc_get_ver = 0x0001, 2804 ice_aqc_opc_driver_ver = 0x0002, 2805 ice_aqc_opc_q_shutdown = 0x0003, 2806 ice_aqc_opc_get_exp_err = 0x0005, 2807 2808 /* resource ownership */ 2809 ice_aqc_opc_req_res = 0x0008, 2810 ice_aqc_opc_release_res = 0x0009, 2811 2812 /* device/function capabilities */ 2813 ice_aqc_opc_list_func_caps = 0x000A, 2814 ice_aqc_opc_list_dev_caps = 0x000B, 2815 2816 /* manage MAC address */ 2817 ice_aqc_opc_manage_mac_read = 0x0107, 2818 ice_aqc_opc_manage_mac_write = 0x0108, 2819 2820 /* PXE */ 2821 ice_aqc_opc_clear_pxe_mode = 0x0110, 2822 2823 ice_aqc_opc_config_no_drop_policy = 0x0112, 2824 2825 /* internal switch commands */ 2826 ice_aqc_opc_get_sw_cfg = 0x0200, 2827 ice_aqc_opc_set_port_params = 0x0203, 2828 2829 /* Alloc/Free/Get Resources */ 2830 ice_aqc_opc_get_res_alloc = 0x0204, 2831 ice_aqc_opc_alloc_res = 0x0208, 2832 ice_aqc_opc_free_res = 0x0209, 2833 ice_aqc_opc_get_allocd_res_desc = 0x020A, 2834 2835 /* VSI commands */ 2836 ice_aqc_opc_add_vsi = 0x0210, 2837 ice_aqc_opc_update_vsi = 0x0211, 2838 ice_aqc_opc_get_vsi_params = 0x0212, 2839 ice_aqc_opc_free_vsi = 0x0213, 2840 2841 /* Mirroring rules - add/update, delete */ 2842 ice_aqc_opc_add_update_mir_rule = 0x0260, 2843 ice_aqc_opc_del_mir_rule = 0x0261, 2844 2845 /* storm configuration */ 2846 ice_aqc_opc_set_storm_cfg = 0x0280, 2847 ice_aqc_opc_get_storm_cfg = 0x0281, 2848 2849 /* switch rules population commands */ 2850 ice_aqc_opc_add_sw_rules = 0x02A0, 2851 ice_aqc_opc_update_sw_rules = 0x02A1, 2852 ice_aqc_opc_remove_sw_rules = 0x02A2, 2853 ice_aqc_opc_get_sw_rules = 0x02A3, 2854 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2855 2856 /* DCB commands */ 2857 ice_aqc_opc_pfc_ignore = 0x0301, 2858 ice_aqc_opc_query_pfc_mode = 0x0302, 2859 ice_aqc_opc_set_pfc_mode = 0x0303, 2860 ice_aqc_opc_set_dcb_params = 0x0306, 2861 2862 /* transmit scheduler commands */ 2863 ice_aqc_opc_get_dflt_topo = 0x0400, 2864 ice_aqc_opc_add_sched_elems = 0x0401, 2865 ice_aqc_opc_cfg_sched_elems = 0x0403, 2866 ice_aqc_opc_get_sched_elems = 0x0404, 2867 ice_aqc_opc_move_sched_elems = 0x0408, 2868 ice_aqc_opc_suspend_sched_elems = 0x0409, 2869 ice_aqc_opc_resume_sched_elems = 0x040A, 2870 ice_aqc_opc_query_port_ets = 0x040E, 2871 ice_aqc_opc_delete_sched_elems = 0x040F, 2872 ice_aqc_opc_add_rl_profiles = 0x0410, 2873 ice_aqc_opc_query_rl_profiles = 0x0411, 2874 ice_aqc_opc_query_sched_res = 0x0412, 2875 ice_aqc_opc_query_node_to_root = 0x0413, 2876 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 2877 ice_aqc_opc_remove_rl_profiles = 0x0415, 2878 2879 /* PHY commands */ 2880 ice_aqc_opc_get_phy_caps = 0x0600, 2881 ice_aqc_opc_set_phy_cfg = 0x0601, 2882 ice_aqc_opc_set_mac_cfg = 0x0603, 2883 ice_aqc_opc_restart_an = 0x0605, 2884 ice_aqc_opc_get_link_status = 0x0607, 2885 ice_aqc_opc_set_event_mask = 0x0613, 2886 ice_aqc_opc_set_mac_lb = 0x0620, 2887 ice_aqc_opc_dnl_get_status = 0x0680, 2888 ice_aqc_opc_dnl_run = 0x0681, 2889 ice_aqc_opc_dnl_call = 0x0682, 2890 ice_aqc_opc_dnl_read_sto = 0x0683, 2891 ice_aqc_opc_dnl_write_sto = 0x0684, 2892 ice_aqc_opc_dnl_set_breakpoints = 0x0686, 2893 ice_aqc_opc_dnl_read_log = 0x0687, 2894 ice_aqc_opc_get_link_topo = 0x06E0, 2895 ice_aqc_opc_get_link_topo_pin = 0x06E1, 2896 ice_aqc_opc_read_i2c = 0x06E2, 2897 ice_aqc_opc_write_i2c = 0x06E3, 2898 ice_aqc_opc_read_mdio = 0x06E4, 2899 ice_aqc_opc_write_mdio = 0x06E5, 2900 ice_aqc_opc_set_gpio_by_func = 0x06E6, 2901 ice_aqc_opc_get_gpio_by_func = 0x06E7, 2902 ice_aqc_opc_set_led = 0x06E8, 2903 ice_aqc_opc_set_port_id_led = 0x06E9, 2904 ice_aqc_opc_get_port_options = 0x06EA, 2905 ice_aqc_opc_set_port_option = 0x06EB, 2906 ice_aqc_opc_set_gpio = 0x06EC, 2907 ice_aqc_opc_get_gpio = 0x06ED, 2908 ice_aqc_opc_sff_eeprom = 0x06EE, 2909 2910 /* NVM commands */ 2911 ice_aqc_opc_nvm_read = 0x0701, 2912 ice_aqc_opc_nvm_erase = 0x0702, 2913 ice_aqc_opc_nvm_write = 0x0703, 2914 ice_aqc_opc_nvm_cfg_read = 0x0704, 2915 ice_aqc_opc_nvm_cfg_write = 0x0705, 2916 ice_aqc_opc_nvm_checksum = 0x0706, 2917 ice_aqc_opc_nvm_write_activate = 0x0707, 2918 ice_aqc_opc_nvm_sr_dump = 0x0707, 2919 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 2920 ice_aqc_opc_nvm_update_empr = 0x0709, 2921 2922 /* PF/VF mailbox commands */ 2923 ice_mbx_opc_send_msg_to_pf = 0x0801, 2924 ice_mbx_opc_send_msg_to_vf = 0x0802, 2925 /* Alternate Structure Commands */ 2926 ice_aqc_opc_write_alt_direct = 0x0900, 2927 ice_aqc_opc_write_alt_indirect = 0x0901, 2928 ice_aqc_opc_read_alt_direct = 0x0902, 2929 ice_aqc_opc_read_alt_indirect = 0x0903, 2930 ice_aqc_opc_done_alt_write = 0x0904, 2931 ice_aqc_opc_clear_port_alt_write = 0x0906, 2932 /* LLDP commands */ 2933 ice_aqc_opc_lldp_get_mib = 0x0A00, 2934 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2935 ice_aqc_opc_lldp_add_tlv = 0x0A02, 2936 ice_aqc_opc_lldp_update_tlv = 0x0A03, 2937 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 2938 ice_aqc_opc_lldp_stop = 0x0A05, 2939 ice_aqc_opc_lldp_start = 0x0A06, 2940 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2941 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2942 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2943 2944 /* RSS commands */ 2945 ice_aqc_opc_set_rss_key = 0x0B02, 2946 ice_aqc_opc_set_rss_lut = 0x0B03, 2947 ice_aqc_opc_get_rss_key = 0x0B04, 2948 ice_aqc_opc_get_rss_lut = 0x0B05, 2949 2950 /* Tx queue handling commands/events */ 2951 ice_aqc_opc_add_txqs = 0x0C30, 2952 ice_aqc_opc_dis_txqs = 0x0C31, 2953 ice_aqc_opc_txqs_cleanup = 0x0C31, 2954 ice_aqc_opc_move_recfg_txqs = 0x0C32, 2955 2956 /* package commands */ 2957 ice_aqc_opc_download_pkg = 0x0C40, 2958 ice_aqc_opc_upload_section = 0x0C41, 2959 ice_aqc_opc_update_pkg = 0x0C42, 2960 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2961 2962 ice_aqc_opc_driver_shared_params = 0x0C90, 2963 2964 /* Standalone Commands/Events */ 2965 ice_aqc_opc_event_lan_overflow = 0x1001, 2966 }; 2967 2968 #endif /* _ICE_ADMINQ_CMD_H_ */ 2969