1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2022, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_SCHED_H_ 34 #define _ICE_SCHED_H_ 35 36 #include "ice_common.h" 37 38 #define ICE_SCHED_5_LAYERS 5 39 #define ICE_SCHED_9_LAYERS 9 40 41 #define ICE_QGRP_LAYER_OFFSET 2 42 #define ICE_VSI_LAYER_OFFSET 4 43 #define ICE_AGG_LAYER_OFFSET 6 44 #define ICE_SCHED_INVAL_LAYER_NUM 0xFF 45 /* Burst size is a 12 bits register that is configured while creating the RL 46 * profile(s). MSB is a granularity bit and tells the granularity type 47 * 0 - LSB bits are in 64 bytes granularity 48 * 1 - LSB bits are in 1K bytes granularity 49 */ 50 #define ICE_64_BYTE_GRANULARITY 0 51 #define ICE_KBYTE_GRANULARITY BIT(11) 52 #define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */ 53 #define ICE_MAX_BURST_SIZE_ALLOWED \ 54 ((BIT(11) - 1) * 1024) /* In Bytes */ 55 #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \ 56 ((BIT(11) - 1) * 64) /* In Bytes */ 57 #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED 58 59 #define ICE_RL_PROF_ACCURACY_BYTES 128 60 #define ICE_RL_PROF_MULTIPLIER 10000 61 #define ICE_RL_PROF_TS_MULTIPLIER 32 62 #define ICE_RL_PROF_FRACTION 512 63 64 #define ICE_PSM_CLK_367MHZ_IN_HZ 367647059 65 #define ICE_PSM_CLK_416MHZ_IN_HZ 416666667 66 #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 67 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 68 69 struct rl_profile_params { 70 u32 bw; /* in Kbps */ 71 u16 rl_multiplier; 72 u16 wake_up_calc; 73 u16 rl_encode; 74 }; 75 76 /* BW rate limit profile parameters list entry along 77 * with bandwidth maintained per layer in port info 78 */ 79 struct ice_aqc_rl_profile_info { 80 struct ice_aqc_rl_profile_elem profile; 81 struct LIST_ENTRY_TYPE list_entry; 82 u32 bw; /* requested */ 83 u16 prof_id_ref; /* profile ID to node association ref count */ 84 }; 85 86 struct ice_sched_agg_vsi_info { 87 struct LIST_ENTRY_TYPE list_entry; 88 ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 89 u16 vsi_handle; 90 /* save aggregator VSI TC bitmap */ 91 ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 92 }; 93 94 struct ice_sched_agg_info { 95 struct LIST_HEAD_TYPE agg_vsi_list; 96 struct LIST_ENTRY_TYPE list_entry; 97 ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 98 u32 agg_id; 99 enum ice_agg_type agg_type; 100 /* bw_t_info saves aggregator BW information */ 101 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 102 /* save aggregator TC bitmap */ 103 ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 104 }; 105 106 /* FW AQ command calls */ 107 enum ice_status 108 ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles, 109 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 110 struct ice_sq_cd *cd); 111 enum ice_status 112 ice_aq_cfg_node_attr(struct ice_hw *hw, u16 num_nodes, 113 struct ice_aqc_node_attr_elem *buf, u16 buf_size, 114 struct ice_sq_cd *cd); 115 enum ice_status 116 ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes, 117 struct ice_aqc_cfg_l2_node_cgd_elem *buf, u16 buf_size, 118 struct ice_sq_cd *cd); 119 enum ice_status 120 ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, 121 struct ice_aqc_move_elem *buf, u16 buf_size, 122 u16 *grps_movd, struct ice_sq_cd *cd); 123 enum ice_status 124 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 125 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 126 u16 *elems_ret, struct ice_sq_cd *cd); 127 enum ice_status ice_sched_init_port(struct ice_port_info *pi); 128 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw); 129 void ice_sched_get_psm_clk_freq(struct ice_hw *hw); 130 131 /* Functions to cleanup scheduler SW DB */ 132 void ice_sched_clear_port(struct ice_port_info *pi); 133 void ice_sched_cleanup_all(struct ice_hw *hw); 134 void ice_sched_clear_agg(struct ice_hw *hw); 135 136 /* Get a scheduling node from SW DB for given TEID */ 137 struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid); 138 struct ice_sched_node * 139 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); 140 /* Add a scheduling node into SW DB for given info */ 141 enum ice_status 142 ice_sched_add_node(struct ice_port_info *pi, u8 layer, 143 struct ice_aqc_txsched_elem_data *info); 144 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); 145 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); 146 struct ice_sched_node * 147 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 148 u8 owner); 149 enum ice_status 150 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 151 u8 owner, bool enable); 152 enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle); 153 enum ice_status ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle); 154 struct ice_sched_node * 155 ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 156 u16 vsi_handle); 157 bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node); 158 enum ice_status 159 ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid, 160 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 161 struct ice_sq_cd *cd); 162 163 /* Tx scheduler rate limiter functions */ 164 enum ice_status 165 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, 166 enum ice_agg_type agg_type, u8 tc_bitmap); 167 enum ice_status 168 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 169 u8 tc_bitmap); 170 enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id); 171 enum ice_status 172 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 173 u16 q_handle, enum ice_rl_type rl_type, u32 bw); 174 enum ice_status 175 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 176 u16 q_handle, enum ice_rl_type rl_type); 177 enum ice_status 178 ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 179 enum ice_rl_type rl_type, u32 bw); 180 enum ice_status 181 ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc, 182 enum ice_rl_type rl_type); 183 enum ice_status 184 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 185 enum ice_rl_type rl_type, u32 bw); 186 enum ice_status 187 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 188 enum ice_rl_type rl_type); 189 enum ice_status 190 ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 191 enum ice_rl_type rl_type, u32 bw); 192 enum ice_status 193 ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 194 enum ice_rl_type rl_type); 195 enum ice_status 196 ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 min_bw, 197 u32 max_bw, u32 shared_bw); 198 enum ice_status 199 ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle); 200 enum ice_status 201 ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw, 202 u32 max_bw, u32 shared_bw); 203 enum ice_status 204 ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id); 205 enum ice_status 206 ice_cfg_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 207 u32 min_bw, u32 max_bw, u32 shared_bw); 208 enum ice_status 209 ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, 210 u8 tc); 211 enum ice_status 212 ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, 213 u8 *q_prio); 214 enum ice_status 215 ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap, 216 enum ice_rl_type rl_type, u8 *bw_alloc); 217 enum ice_status 218 ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id, 219 u16 num_vsis, u16 *vsi_handle_arr, 220 u8 *node_prio, u8 tc); 221 enum ice_status 222 ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap, 223 enum ice_rl_type rl_type, u8 *bw_alloc); 224 bool 225 ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base, 226 struct ice_sched_node *node); 227 enum ice_status 228 ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle); 229 enum ice_status 230 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id, 231 enum ice_agg_type agg_type, u8 tc, 232 enum ice_rl_type rl_type, u32 bw); 233 enum ice_status 234 ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, 235 u32 min_bw, u32 max_bw, u32 shared_bw); 236 enum ice_status 237 ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw, 238 u32 max_bw, u32 shared_bw); 239 enum ice_status 240 ice_sched_set_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, 241 u8 tc, u32 min_bw, u32 max_bw, 242 u32 shared_bw); 243 enum ice_status 244 ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi, 245 struct ice_sched_node *node, u8 priority); 246 enum ice_status 247 ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 248 enum ice_rl_type rl_type, u8 bw_alloc); 249 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes); 250 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw); 251 void ice_sched_replay_agg(struct ice_hw *hw); 252 enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi); 253 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); 254 enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi); 255 enum ice_status 256 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); 257 258 #endif /* _ICE_SCHED_H_ */ 259