1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_TYPE_H_ 33 #define _ICE_TYPE_H_ 34 35 #include "ice_defs.h" 36 #include "ice_status.h" 37 #include "ice_hw_autogen.h" 38 #include "ice_devids.h" 39 #include "ice_osdep.h" 40 #include "ice_bitops.h" /* Must come before ice_controlq.h */ 41 #include "ice_lan_tx_rx.h" 42 #include "ice_ddp_common.h" 43 #include "ice_controlq.h" 44 #include "ice_flex_type.h" 45 #include "ice_protocol_type.h" 46 #include "ice_vlan_mode.h" 47 #include "ice_fwlog.h" 48 49 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc) 50 { 51 return !!(bitmap & BIT(tc)); 52 } 53 54 /** 55 * DIV_S64 - Divide signed 64-bit value with signed 64-bit divisor 56 * @dividend: value to divide 57 * @divisor: value to divide by 58 * 59 * Use DIV_S64 for any 64-bit divide which operates on signed 64-bit dividends. 60 * Do not use this for unsigned 64-bit dividends as it will not produce 61 * correct results if the dividend is larger than S64_MAX. 62 */ 63 static inline s64 DIV_S64(s64 dividend, s64 divisor) 64 { 65 return dividend / divisor; 66 } 67 68 /** 69 * DIV_U64 - Divide unsigned 64-bit value by unsigned 64-bit divisor 70 * @dividend: value to divide 71 * @divisor: value to divide by 72 * 73 * Use DIV_U64 for any 64-bit divide which operates on unsigned 64-bit 74 * dividends. Do not use this for signed 64-bit dividends as it will not 75 * handle negative values correctly. 76 */ 77 static inline u64 DIV_U64(u64 dividend, u64 divisor) 78 { 79 return dividend / divisor; 80 } 81 82 static inline u64 round_up_64bit(u64 a, u32 b) 83 { 84 return DIV_U64(((a) + (b) / 2), (b)); 85 } 86 87 static inline u32 ice_round_to_num(u32 N, u32 R) 88 { 89 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 90 ((((N) + (R) - 1) / (R)) * (R))); 91 } 92 93 /* Driver always calls main vsi_handle first */ 94 #define ICE_MAIN_VSI_HANDLE 0 95 96 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 97 #define ICE_MS_TO_GTIME(time) ((time) * 1000) 98 99 /* Data type manipulation macros. */ 100 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 101 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 102 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 103 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF)) 104 #define ICE_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 105 #define ICE_LO_BYTE(x) ((u8)((x) & 0xFF)) 106 107 /* debug masks - set these bits in hw->debug_mask to control output */ 108 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */ 109 #define ICE_DBG_INIT BIT_ULL(1) 110 #define ICE_DBG_RELEASE BIT_ULL(2) 111 #define ICE_DBG_FW_LOG BIT_ULL(3) 112 #define ICE_DBG_LINK BIT_ULL(4) 113 #define ICE_DBG_PHY BIT_ULL(5) 114 #define ICE_DBG_QCTX BIT_ULL(6) 115 #define ICE_DBG_NVM BIT_ULL(7) 116 #define ICE_DBG_LAN BIT_ULL(8) 117 #define ICE_DBG_FLOW BIT_ULL(9) 118 #define ICE_DBG_DCB BIT_ULL(10) 119 #define ICE_DBG_DIAG BIT_ULL(11) 120 #define ICE_DBG_FD BIT_ULL(12) 121 #define ICE_DBG_SW BIT_ULL(13) 122 #define ICE_DBG_SCHED BIT_ULL(14) 123 124 #define ICE_DBG_RDMA BIT_ULL(15) 125 #define ICE_DBG_PKG BIT_ULL(16) 126 #define ICE_DBG_RES BIT_ULL(17) 127 #define ICE_DBG_AQ_MSG BIT_ULL(24) 128 #define ICE_DBG_AQ_DESC BIT_ULL(25) 129 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 130 #define ICE_DBG_AQ_CMD BIT_ULL(27) 131 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 132 ICE_DBG_AQ_DESC | \ 133 ICE_DBG_AQ_DESC_BUF | \ 134 ICE_DBG_AQ_CMD) 135 #define ICE_DBG_PARSER BIT_ULL(28) 136 137 #define ICE_DBG_USER BIT_ULL(31) 138 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL 139 140 #define IS_UNICAST_ETHER_ADDR(addr) \ 141 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0)) 142 143 #define IS_MULTICAST_ETHER_ADDR(addr) \ 144 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1)) 145 146 /* Check whether an address is broadcast. */ 147 #define IS_BROADCAST_ETHER_ADDR(addr) \ 148 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff)))) 149 150 #define IS_ZERO_ETHER_ADDR(addr) \ 151 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \ 152 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \ 153 ((bool)((((u16 *)(addr))[2] == ((u16)0x0))))) 154 155 #ifndef IS_ETHER_ADDR_EQUAL 156 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \ 157 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \ 158 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \ 159 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2])))) 160 #endif 161 162 enum ice_aq_res_ids { 163 ICE_NVM_RES_ID = 1, 164 ICE_SPD_RES_ID, 165 ICE_CHANGE_LOCK_RES_ID, 166 ICE_GLOBAL_CFG_LOCK_RES_ID 167 }; 168 169 /* FW update timeout definitions are in milliseconds */ 170 #define ICE_NVM_TIMEOUT 180000 171 #define ICE_CHANGE_LOCK_TIMEOUT 1000 172 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 173 174 struct ice_driver_ver { 175 u8 major_ver; 176 u8 minor_ver; 177 u8 build_ver; 178 u8 subbuild_ver; 179 u8 driver_string[32]; 180 }; 181 182 enum ice_fc_mode { 183 ICE_FC_NONE = 0, 184 ICE_FC_RX_PAUSE, 185 ICE_FC_TX_PAUSE, 186 ICE_FC_FULL, 187 ICE_FC_AUTO, 188 ICE_FC_PFC, 189 ICE_FC_DFLT 190 }; 191 192 enum ice_phy_cache_mode { 193 ICE_FC_MODE = 0, 194 ICE_SPEED_MODE, 195 ICE_FEC_MODE 196 }; 197 198 enum ice_fec_mode { 199 ICE_FEC_NONE = 0, 200 ICE_FEC_RS, 201 ICE_FEC_BASER, 202 ICE_FEC_AUTO, 203 ICE_FEC_DIS_AUTO 204 }; 205 206 struct ice_phy_cache_mode_data { 207 union { 208 enum ice_fec_mode curr_user_fec_req; 209 enum ice_fc_mode curr_user_fc_req; 210 u16 curr_user_speed_req; 211 } data; 212 }; 213 214 enum ice_set_fc_aq_failures { 215 ICE_SET_FC_AQ_FAIL_NONE = 0, 216 ICE_SET_FC_AQ_FAIL_GET, 217 ICE_SET_FC_AQ_FAIL_SET, 218 ICE_SET_FC_AQ_FAIL_UPDATE 219 }; 220 221 /* These are structs for managing the hardware information and the operations */ 222 /* MAC types */ 223 enum ice_mac_type { 224 ICE_MAC_UNKNOWN = 0, 225 ICE_MAC_VF, 226 ICE_MAC_E810, 227 ICE_MAC_GENERIC, 228 ICE_MAC_GENERIC_3K, 229 }; 230 231 /* Media Types */ 232 enum ice_media_type { 233 ICE_MEDIA_UNKNOWN = 0, 234 ICE_MEDIA_FIBER, 235 ICE_MEDIA_BASET, 236 ICE_MEDIA_BACKPLANE, 237 ICE_MEDIA_DA, 238 ICE_MEDIA_AUI, 239 }; 240 241 /* Software VSI types. */ 242 enum ice_vsi_type { 243 ICE_VSI_PF = 0, 244 ICE_VSI_VF = 1, 245 ICE_VSI_LB = 6, 246 }; 247 248 struct ice_link_status { 249 /* Refer to ice_aq_phy_type for bits definition */ 250 u64 phy_type_low; 251 u64 phy_type_high; 252 u8 topo_media_conflict; 253 u16 max_frame_size; 254 u16 link_speed; 255 u16 req_speeds; 256 u8 link_cfg_err; 257 u8 lse_ena; /* Link Status Event notification */ 258 u8 link_info; 259 u8 an_info; 260 u8 ext_info; 261 u8 fec_info; 262 u8 pacing; 263 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 264 * ice_aqc_get_phy_caps structure 265 */ 266 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 267 }; 268 269 /* Different data queue types: These are mainly for SW consumption. */ 270 enum ice_q { 271 ICE_DATA_Q_DOORBELL, 272 ICE_DATA_Q_CMPL, 273 ICE_DATA_Q_QUANTA, 274 ICE_DATA_Q_RX, 275 ICE_DATA_Q_TX, 276 }; 277 278 /* Different reset sources for which a disable queue AQ call has to be made in 279 * order to clean the Tx scheduler as a part of the reset 280 */ 281 enum ice_disq_rst_src { 282 ICE_NO_RESET = 0, 283 ICE_VM_RESET, 284 ICE_VF_RESET, 285 }; 286 287 /* PHY info such as phy_type, etc... */ 288 struct ice_phy_info { 289 struct ice_link_status link_info; 290 struct ice_link_status link_info_old; 291 u64 phy_type_low; 292 u64 phy_type_high; 293 enum ice_media_type media_type; 294 u8 get_link_info; 295 /* Please refer to struct ice_aqc_get_link_status_data to get 296 * detail of enable bit in curr_user_speed_req 297 */ 298 u16 curr_user_speed_req; 299 enum ice_fec_mode curr_user_fec_req; 300 enum ice_fc_mode curr_user_fc_req; 301 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 302 }; 303 304 #define ICE_MAX_NUM_MIRROR_RULES 64 305 306 #define ICE_L2TPV2_FLAGS_CTRL 0x8000 307 #define ICE_L2TPV2_FLAGS_LEN 0x4000 308 #define ICE_L2TPV2_FLAGS_SEQ 0x0800 309 #define ICE_L2TPV2_FLAGS_OFF 0x0200 310 #define ICE_L2TPV2_FLAGS_VER 0x0002 311 312 #define ICE_L2TPV2_PKT_LENGTH 6 313 #define ICE_PPP_PKT_LENGTH 4 314 315 /* Common HW capabilities for SW use */ 316 struct ice_hw_common_caps { 317 /* Write CSR protection */ 318 u64 wr_csr_prot; 319 u32 switching_mode; 320 /* switching mode supported - EVB switching (including cloud) */ 321 #define ICE_NVM_IMAGE_TYPE_EVB 0x0 322 323 /* Manageablity mode & supported protocols over MCTP */ 324 u32 mgmt_mode; 325 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF 326 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0 327 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00 328 329 u32 mgmt_protocols_mctp; 330 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0) 331 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1) 332 #define ICE_MGMT_MODE_PROTO_OEM BIT(2) 333 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3) 334 335 u32 os2bmc; 336 u32 valid_functions; 337 /* DCB capabilities */ 338 u32 active_tc_bitmap; 339 u32 maxtc; 340 341 /* RSS related capabilities */ 342 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 343 u32 rss_table_entry_width; /* RSS Entry width in bits */ 344 345 /* Tx/Rx queues */ 346 u32 num_rxq; /* Number/Total Rx queues */ 347 u32 rxq_first_id; /* First queue ID for Rx queues */ 348 u32 num_txq; /* Number/Total Tx queues */ 349 u32 txq_first_id; /* First queue ID for Tx queues */ 350 351 /* MSI-X vectors */ 352 u32 num_msix_vectors; 353 u32 msix_vector_first_id; 354 355 /* Max MTU for function or device */ 356 u32 max_mtu; 357 358 /* WOL related */ 359 u32 num_wol_proxy_fltr; 360 u32 wol_proxy_vsi_seid; 361 362 /* LED/SDP pin count */ 363 u32 led_pin_num; 364 u32 sdp_pin_num; 365 366 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 367 #define ICE_MAX_SUPPORTED_GPIO_LED 12 368 #define ICE_MAX_SUPPORTED_GPIO_SDP 8 369 u8 led[ICE_MAX_SUPPORTED_GPIO_LED]; 370 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP]; 371 372 /* SR-IOV virtualization */ 373 u8 sr_iov_1_1; /* SR-IOV enabled */ 374 375 /* EVB capabilities */ 376 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 377 u8 evb_802_1_qbh; /* Bridge Port Extension */ 378 379 u8 dcb; 380 u8 iscsi; 381 u8 mgmt_cem; 382 u8 iwarp; 383 u8 roce_lag; 384 385 /* WoL and APM support */ 386 #define ICE_WOL_SUPPORT_M BIT(0) 387 #define ICE_ACPI_PROG_MTHD_M BIT(1) 388 #define ICE_PROXY_SUPPORT_M BIT(2) 389 u8 apm_wol_support; 390 u8 acpi_prog_mthd; 391 u8 proxy_support; 392 bool sec_rev_disabled; 393 bool update_disabled; 394 bool nvm_unified_update; 395 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) 396 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) 397 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 398 /* PCIe reset avoidance */ 399 bool pcie_reset_avoidance; /* false: not supported, true: supported */ 400 /* Post update reset restriction */ 401 bool reset_restrict_support; /* false: not supported, true: supported */ 402 403 /* External topology device images within the NVM */ 404 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4 405 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT]; 406 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT]; 407 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT]; 408 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8 409 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \ 410 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S) 411 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; 412 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0) 413 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; 414 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1) 415 bool tx_sched_topo_comp_mode_en; 416 bool dyn_flattening_en; 417 }; 418 419 #define ICE_NAC_TOPO_PRIMARY_M BIT(0) 420 #define ICE_NAC_TOPO_DUAL_M BIT(1) 421 #define ICE_NAC_TOPO_ID_M MAKEMASK(0xf, 0) 422 423 struct ice_nac_topology { 424 u32 mode; 425 u8 id; 426 }; 427 428 /* Function specific capabilities */ 429 struct ice_hw_func_caps { 430 struct ice_hw_common_caps common_cap; 431 u32 num_allocd_vfs; /* Number of allocated VFs */ 432 u32 vf_base_id; /* Logical ID of the first VF */ 433 u32 guar_num_vsi; 434 }; 435 436 /* Device wide capabilities */ 437 struct ice_hw_dev_caps { 438 struct ice_hw_common_caps common_cap; 439 u32 num_vfs_exposed; /* Total number of VFs exposed */ 440 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 441 u32 num_funcs; 442 struct ice_nac_topology nac_topo; 443 }; 444 445 /* Information about MAC such as address, etc... */ 446 struct ice_mac_info { 447 u8 lan_addr[ETH_ALEN]; 448 u8 perm_addr[ETH_ALEN]; 449 u8 port_addr[ETH_ALEN]; 450 u8 wol_addr[ETH_ALEN]; 451 }; 452 453 /* PCI bus types */ 454 enum ice_bus_type { 455 ice_bus_unknown = 0, 456 ice_bus_pci_express, 457 ice_bus_embedded, /* Is device Embedded versus card */ 458 ice_bus_reserved 459 }; 460 461 /* PCI bus speeds */ 462 enum ice_pcie_bus_speed { 463 ice_pcie_speed_unknown = 0xff, 464 ice_pcie_speed_2_5GT = 0x14, 465 ice_pcie_speed_5_0GT = 0x15, 466 ice_pcie_speed_8_0GT = 0x16, 467 ice_pcie_speed_16_0GT = 0x17 468 }; 469 470 /* PCI bus widths */ 471 enum ice_pcie_link_width { 472 ice_pcie_lnk_width_resrv = 0x00, 473 ice_pcie_lnk_x1 = 0x01, 474 ice_pcie_lnk_x2 = 0x02, 475 ice_pcie_lnk_x4 = 0x04, 476 ice_pcie_lnk_x8 = 0x08, 477 ice_pcie_lnk_x12 = 0x0C, 478 ice_pcie_lnk_x16 = 0x10, 479 ice_pcie_lnk_x32 = 0x20, 480 ice_pcie_lnk_width_unknown = 0xff, 481 }; 482 483 /* Reset types used to determine which kind of reset was requested. These 484 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 485 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 486 * because its reset source is different than the other types listed. 487 */ 488 enum ice_reset_req { 489 ICE_RESET_POR = 0, 490 ICE_RESET_INVAL = 0, 491 ICE_RESET_CORER = 1, 492 ICE_RESET_GLOBR = 2, 493 ICE_RESET_EMPR = 3, 494 ICE_RESET_PFR = 4, 495 }; 496 497 /* Bus parameters */ 498 struct ice_bus_info { 499 enum ice_pcie_bus_speed speed; 500 enum ice_pcie_link_width width; 501 enum ice_bus_type type; 502 u16 domain_num; 503 u16 device; 504 u8 func; 505 u8 bus_num; 506 }; 507 508 /* Flow control (FC) parameters */ 509 struct ice_fc_info { 510 enum ice_fc_mode current_mode; /* FC mode in effect */ 511 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 512 }; 513 514 /* Option ROM version information */ 515 struct ice_orom_info { 516 u8 major; /* Major version of OROM */ 517 u8 patch; /* Patch version of OROM */ 518 u16 build; /* Build version of OROM */ 519 u32 srev; /* Security revision */ 520 }; 521 522 /* NVM version information */ 523 struct ice_nvm_info { 524 u32 eetrack; 525 u32 srev; 526 u8 major; 527 u8 minor; 528 }; 529 530 /* Minimum Security Revision information */ 531 struct ice_minsrev_info { 532 u32 nvm; 533 u32 orom; 534 u8 nvm_valid : 1; 535 u8 orom_valid : 1; 536 }; 537 538 /* netlist version information */ 539 struct ice_netlist_info { 540 u32 major; /* major high/low */ 541 u32 minor; /* minor high/low */ 542 u32 type; /* type high/low */ 543 u32 rev; /* revision high/low */ 544 u32 hash; /* SHA-1 hash word */ 545 u16 cust_ver; /* customer version */ 546 }; 547 548 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 549 * of the flash image. 550 */ 551 enum ice_flash_bank { 552 ICE_INVALID_FLASH_BANK, 553 ICE_1ST_FLASH_BANK, 554 ICE_2ND_FLASH_BANK, 555 }; 556 557 /* Enumeration of which flash bank is desired to read from, either the active 558 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 559 * code which just wants to read the active or inactive flash bank. 560 */ 561 enum ice_bank_select { 562 ICE_ACTIVE_FLASH_BANK, 563 ICE_INACTIVE_FLASH_BANK, 564 }; 565 566 /* information for accessing NVM, OROM, and Netlist flash banks */ 567 struct ice_bank_info { 568 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 569 u32 nvm_size; /* Size of NVM bank */ 570 u32 orom_ptr; /* Pointer to 1st OROM bank */ 571 u32 orom_size; /* Size of OROM bank */ 572 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 573 u32 netlist_size; /* Size of Netlist bank */ 574 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 575 enum ice_flash_bank orom_bank; /* Active OROM bank */ 576 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 577 }; 578 579 /* Flash Chip Information */ 580 struct ice_flash_info { 581 struct ice_orom_info orom; /* Option ROM version info */ 582 struct ice_nvm_info nvm; /* NVM version information */ 583 struct ice_netlist_info netlist;/* Netlist version info */ 584 struct ice_bank_info banks; /* Flash Bank information */ 585 u16 sr_words; /* Shadow RAM size in words */ 586 u32 flash_size; /* Size of available flash in bytes */ 587 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 588 }; 589 590 struct ice_link_default_override_tlv { 591 u8 options; 592 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 593 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 594 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 595 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 596 #define ICE_LINK_OVERRIDE_EN BIT(3) 597 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 598 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 599 u8 phy_config; 600 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 601 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 602 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 603 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 604 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 605 u8 fec_options; 606 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 607 u8 rsvd1; 608 u64 phy_type_low; 609 u64 phy_type_high; 610 }; 611 612 #define ICE_NVM_VER_LEN 32 613 614 /* Max number of port to queue branches w.r.t topology */ 615 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 616 617 #define ice_for_each_traffic_class(_i) \ 618 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 619 620 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 621 * to driver defined policy for default aggregator 622 */ 623 #define ICE_INVAL_TEID 0xFFFFFFFF 624 #define ICE_DFLT_AGG_ID 0 625 626 struct ice_sched_node { 627 struct ice_sched_node *parent; 628 struct ice_sched_node *sibling; /* next sibling in the same layer */ 629 struct ice_sched_node **children; 630 struct ice_aqc_txsched_elem_data info; 631 u32 agg_id; /* aggregator group ID */ 632 u16 vsi_handle; 633 u8 in_use; /* suspended or in use */ 634 u8 tx_sched_layer; /* Logical Layer (1-9) */ 635 u8 num_children; 636 u8 tc_num; 637 u8 owner; 638 #define ICE_SCHED_NODE_OWNER_LAN 0 639 #define ICE_SCHED_NODE_OWNER_AE 1 640 #define ICE_SCHED_NODE_OWNER_RDMA 2 641 }; 642 643 /* Access Macros for Tx Sched Elements data */ 644 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid) 645 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid) 646 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \ 647 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx) 648 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \ 649 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx) 650 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id) 651 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \ 652 LE16_TO_CPU((x)->info.cir_bw.bw_alloc) 653 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \ 654 LE16_TO_CPU((x)->info.eir_bw.bw_alloc) 655 656 struct ice_sched_rl_profile { 657 u32 rate; /* In Kbps */ 658 struct ice_aqc_rl_profile_elem info; 659 }; 660 661 /* The aggregator type determines if identifier is for a VSI group, 662 * aggregator group, aggregator of queues, or queue group. 663 */ 664 enum ice_agg_type { 665 ICE_AGG_TYPE_UNKNOWN = 0, 666 ICE_AGG_TYPE_TC, 667 ICE_AGG_TYPE_AGG, /* aggregator */ 668 ICE_AGG_TYPE_VSI, 669 ICE_AGG_TYPE_QG, 670 ICE_AGG_TYPE_Q 671 }; 672 673 /* Rate limit types */ 674 enum ice_rl_type { 675 ICE_UNKNOWN_BW = 0, 676 ICE_MIN_BW, /* for CIR profile */ 677 ICE_MAX_BW, /* for EIR profile */ 678 ICE_SHARED_BW /* for shared profile */ 679 }; 680 681 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 682 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 683 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 684 #define ICE_SCHED_NO_PRIORITY 0 685 #define ICE_SCHED_NO_BW_WT 0 686 #define ICE_SCHED_DFLT_RL_PROF_ID 0 687 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 688 #define ICE_SCHED_DFLT_BW_WT 4 689 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 690 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 691 692 /* Access Macros for Tx Sched RL Profile data */ 693 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id) 694 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size) 695 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply) 696 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc) 697 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode) 698 699 #define ICE_MAX_PORT_PER_PCI_DEV 8 700 701 /* The following tree example shows the naming conventions followed under 702 * ice_port_info struct for default scheduler tree topology. 703 * 704 * A tree on a port 705 * * ---> root node 706 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8) 707 * * * * * * * * * | 708 * / | 709 * * | 710 * / |-> num_elements (range:1 - 9) 711 * * | implies num_of_layers 712 * / | 713 * (a)* | 714 * 715 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under 716 * (a) as child node where queues get added, add Tx/Rx queue admin commands; 717 * need TEID of (a) to add queues. 718 * 719 * This tree 720 * -> has 8 branches (one for each TC) 721 * -> First branch (TC0) has 4 elements 722 * -> has 4 layers 723 * -> (a) is the topmost layer node created by firmware on branch 0 724 * 725 * Note: Above asterisk tree covers only basic terminology and scenario. 726 * Refer to the documentation for more info. 727 */ 728 729 /* Data structure for saving BW information */ 730 enum ice_bw_type { 731 ICE_BW_TYPE_PRIO, 732 ICE_BW_TYPE_CIR, 733 ICE_BW_TYPE_CIR_WT, 734 ICE_BW_TYPE_EIR, 735 ICE_BW_TYPE_EIR_WT, 736 ICE_BW_TYPE_SHARED, 737 ICE_BW_TYPE_CNT /* This must be last */ 738 }; 739 740 struct ice_bw { 741 u32 bw; 742 u16 bw_alloc; 743 }; 744 745 struct ice_bw_type_info { 746 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT); 747 u8 generic; 748 struct ice_bw cir_bw; 749 struct ice_bw eir_bw; 750 u32 shared_bw; 751 }; 752 753 /* VSI queue context structure for given TC */ 754 struct ice_q_ctx { 755 u16 q_handle; 756 u32 q_teid; 757 /* bw_t_info saves queue BW information */ 758 struct ice_bw_type_info bw_t_info; 759 }; 760 761 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 762 struct ice_sched_vsi_info { 763 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 764 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 765 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 766 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 767 /* bw_t_info saves VSI BW information */ 768 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 769 }; 770 771 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 772 struct ice_dcb_ets_cfg { 773 u8 willing; 774 u8 cbs; 775 u8 maxtcs; 776 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 777 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 778 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 779 }; 780 781 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 782 struct ice_dcb_pfc_cfg { 783 u8 willing; 784 u8 mbc; 785 u8 pfccap; 786 u8 pfcena; 787 }; 788 789 /* CEE or IEEE 802.1Qaz Application Priority data */ 790 struct ice_dcb_app_priority_table { 791 u16 prot_id; 792 u8 priority; 793 u8 selector; 794 }; 795 796 #define ICE_MAX_USER_PRIORITY 8 797 #define ICE_DCBX_MAX_APPS 64 798 #define ICE_DSCP_NUM_VAL 64 799 #define ICE_LLDPDU_SIZE 1500 800 #define ICE_TLV_STATUS_OPER 0x1 801 #define ICE_TLV_STATUS_SYNC 0x2 802 #define ICE_TLV_STATUS_ERR 0x4 803 #define ICE_APP_PROT_ID_FCOE 0x8906 804 #define ICE_APP_PROT_ID_ISCSI 0x0cbc 805 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 806 #define ICE_APP_PROT_ID_FIP 0x8914 807 #define ICE_APP_SEL_ETHTYPE 0x1 808 #define ICE_APP_SEL_TCPIP 0x2 809 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 810 #define ICE_CEE_APP_SEL_TCPIP 0x1 811 812 struct ice_dcbx_cfg { 813 u32 numapps; 814 u32 tlv_status; /* CEE mode TLV status */ 815 struct ice_dcb_ets_cfg etscfg; 816 struct ice_dcb_ets_cfg etsrec; 817 struct ice_dcb_pfc_cfg pfc; 818 #define ICE_QOS_MODE_VLAN 0x0 819 #define ICE_QOS_MODE_DSCP 0x1 820 u8 pfc_mode; 821 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 822 /* when DSCP mapping defined by user set its bit to 1 */ 823 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL); 824 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 825 u8 dscp_map[ICE_DSCP_NUM_VAL]; 826 u8 dcbx_mode; 827 #define ICE_DCBX_MODE_CEE 0x1 828 #define ICE_DCBX_MODE_IEEE 0x2 829 u8 app_mode; 830 #define ICE_DCBX_APPS_NON_WILLING 0x1 831 }; 832 833 struct ice_qos_cfg { 834 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 835 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 836 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 837 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 838 u8 is_sw_lldp : 1; 839 }; 840 841 struct ice_port_info { 842 struct ice_sched_node *root; /* Root Node per Port */ 843 struct ice_hw *hw; /* back pointer to HW instance */ 844 u32 last_node_teid; /* scheduler last node info */ 845 u16 sw_id; /* Initial switch ID belongs to port */ 846 u16 pf_vf_num; 847 u8 port_state; 848 #define ICE_SCHED_PORT_STATE_INIT 0x0 849 #define ICE_SCHED_PORT_STATE_READY 0x1 850 u8 lport; 851 #define ICE_LPORT_MASK 0xff 852 struct ice_fc_info fc; 853 struct ice_mac_info mac; 854 struct ice_phy_info phy; 855 struct ice_lock sched_lock; /* protect access to TXSched tree */ 856 struct ice_sched_node * 857 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 858 struct ice_bw_type_info root_node_bw_t_info; 859 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 860 struct ice_qos_cfg qos_cfg; 861 u8 is_vf:1; 862 }; 863 864 struct ice_switch_info { 865 struct LIST_HEAD_TYPE vsi_list_map_head; 866 struct ice_sw_recipe *recp_list; 867 u16 prof_res_bm_init; 868 u16 max_used_prof_index; 869 870 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 871 }; 872 873 /* Enum defining the different states of the mailbox snapshot in the 874 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 875 * states: 876 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 877 * within the mailbox buffer. 878 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 879 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 880 * mailbox and mark any VFs sending more messages than the threshold limit set. 881 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 882 */ 883 enum ice_mbx_snapshot_state { 884 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 885 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 886 ICE_MAL_VF_DETECT_STATE_DETECT, 887 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 888 }; 889 890 /* Structure to hold information of the static snapshot and the mailbox 891 * buffer data used to generate and track the snapshot. 892 * 1. state: the state of the mailbox snapshot in the malicious VF 893 * detection state handler ice_mbx_vf_state_handler() 894 * 2. head : head of the mailbox snapshot in a circular mailbox buffer 895 * 3. tail : tail of the mailbox snapshot in a circular mailbox buffer 896 * 4. num_iterations: number of messages traversed in circular mailbox buffer 897 * 5. num_msg_proc: number of messages processed in mailbox 898 * 6. num_pending_arq: number of pending asynchronous messages 899 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 900 * serviced work item or interrupt. 901 */ 902 struct ice_mbx_snap_buffer_data { 903 enum ice_mbx_snapshot_state state; 904 u32 head; 905 u32 tail; 906 u32 num_iterations; 907 u16 num_msg_proc; 908 u16 num_pending_arq; 909 u16 max_num_msgs_mbx; 910 }; 911 912 /* Structure to track messages sent by VFs on mailbox: 913 * 1. vf_cntr : a counter array of VFs to track the number of 914 * asynchronous messages sent by each VF 915 * 2. vfcntr_len : number of entries in VF counter array 916 */ 917 struct ice_mbx_vf_counter { 918 u32 *vf_cntr; 919 u32 vfcntr_len; 920 }; 921 922 /* Structure to hold data relevant to the captured static snapshot 923 * of the PF-VF mailbox. 924 */ 925 struct ice_mbx_snapshot { 926 struct ice_mbx_snap_buffer_data mbx_buf; 927 struct ice_mbx_vf_counter mbx_vf; 928 }; 929 930 /* Structure to hold data to be used for capturing or updating a 931 * static snapshot. 932 * 1. num_msg_proc: number of messages processed in mailbox 933 * 2. num_pending_arq: number of pending asynchronous messages 934 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 935 * serviced work item or interrupt. 936 * 4. async_watermark_val: An upper threshold set by caller to determine 937 * if the pending arq count is large enough to assume that there is 938 * the possibility of a mailicious VF. 939 */ 940 struct ice_mbx_data { 941 u16 num_msg_proc; 942 u16 num_pending_arq; 943 u16 max_num_msgs_mbx; 944 u16 async_watermark_val; 945 }; 946 947 /* PHY model */ 948 enum ice_phy_model { 949 ICE_PHY_UNSUP = -1, 950 ICE_PHY_E810 = 1, 951 ICE_PHY_E822, 952 }; 953 954 /* Port hardware description */ 955 struct ice_hw { 956 u8 *hw_addr; 957 void *back; 958 struct ice_aqc_layer_props *layer_info; 959 struct ice_port_info *port_info; 960 /* 2D Array for each Tx Sched RL Profile type */ 961 struct ice_sched_rl_profile **cir_profiles; 962 struct ice_sched_rl_profile **eir_profiles; 963 struct ice_sched_rl_profile **srl_profiles; 964 /* PSM clock frequency for calculating RL profile params */ 965 u32 psm_clk_freq; 966 u64 debug_mask; /* BITMAP for debug mask */ 967 enum ice_mac_type mac_type; 968 969 /* pci info */ 970 u16 device_id; 971 u16 vendor_id; 972 u16 subsystem_device_id; 973 u16 subsystem_vendor_id; 974 u8 revision_id; 975 976 u8 pf_id; /* device profile info */ 977 enum ice_phy_model phy_model; 978 979 u16 max_burst_size; /* driver sets this value */ 980 981 /* Tx Scheduler values */ 982 u8 num_tx_sched_layers; 983 u8 num_tx_sched_phys_layers; 984 u8 flattened_layers; 985 u8 max_cgds; 986 u8 sw_entry_point_layer; 987 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 988 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */ 989 /* List contain profile ID(s) and other params per layer */ 990 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 991 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 992 u8 evb_veb; /* true for VEB, false for VEPA */ 993 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 994 struct ice_bus_info bus; 995 struct ice_flash_info flash; 996 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 997 struct ice_hw_func_caps func_caps; /* function capabilities */ 998 999 struct ice_switch_info *switch_info; /* switch filter lists */ 1000 1001 /* Control Queue info */ 1002 struct ice_ctl_q_info adminq; 1003 struct ice_ctl_q_info mailboxq; 1004 u8 api_branch; /* API branch version */ 1005 u8 api_maj_ver; /* API major version */ 1006 u8 api_min_ver; /* API minor version */ 1007 u8 api_patch; /* API patch version */ 1008 u8 fw_branch; /* firmware branch version */ 1009 u8 fw_maj_ver; /* firmware major version */ 1010 u8 fw_min_ver; /* firmware minor version */ 1011 u8 fw_patch; /* firmware patch version */ 1012 u32 fw_build; /* firmware build number */ 1013 1014 struct ice_fwlog_cfg fwlog_cfg; 1015 bool fwlog_support_ena; /* does hardware support FW logging? */ 1016 1017 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 1018 * register. Used for determining the ITR/INTRL granularity during 1019 * initialization. 1020 */ 1021 #define ICE_MAX_AGG_BW_200G 0x0 1022 #define ICE_MAX_AGG_BW_100G 0X1 1023 #define ICE_MAX_AGG_BW_50G 0x2 1024 #define ICE_MAX_AGG_BW_25G 0x3 1025 /* ITR granularity for different speeds */ 1026 #define ICE_ITR_GRAN_ABOVE_25 2 1027 #define ICE_ITR_GRAN_MAX_25 4 1028 /* ITR granularity in 1 us */ 1029 u8 itr_gran; 1030 /* INTRL granularity for different speeds */ 1031 #define ICE_INTRL_GRAN_ABOVE_25 4 1032 #define ICE_INTRL_GRAN_MAX_25 8 1033 /* INTRL granularity in 1 us */ 1034 u8 intrl_gran; 1035 1036 /* true if VSIs can share unicast MAC addr */ 1037 u8 umac_shared; 1038 1039 #define ICE_PHY_PER_NAC_E822 1 1040 #define ICE_MAX_QUAD 2 1041 #define ICE_QUADS_PER_PHY_E822 2 1042 #define ICE_PORTS_PER_PHY_E822 8 1043 #define ICE_PORTS_PER_QUAD 4 1044 #define ICE_PORTS_PER_PHY_E810 4 1045 #define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD) 1046 1047 /* Active package version (currently active) */ 1048 struct ice_pkg_ver active_pkg_ver; 1049 u32 pkg_seg_id; 1050 u32 pkg_sign_type; 1051 u32 active_track_id; 1052 u8 pkg_has_signing_seg:1; 1053 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 1054 u8 active_pkg_in_nvm; 1055 1056 /* Driver's package ver - (from the Ice Metadata section) */ 1057 struct ice_pkg_ver pkg_ver; 1058 u8 pkg_name[ICE_PKG_NAME_SIZE]; 1059 1060 /* Driver's Ice segment format version and id (from the Ice seg) */ 1061 struct ice_pkg_ver ice_seg_fmt_ver; 1062 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 1063 1064 /* Pointer to the ice segment */ 1065 struct ice_seg *seg; 1066 1067 /* Pointer to allocated copy of pkg memory */ 1068 u8 *pkg_copy; 1069 u32 pkg_size; 1070 1071 /* tunneling info */ 1072 struct ice_lock tnl_lock; 1073 struct ice_tunnel_table tnl; 1074 1075 /* HW block tables */ 1076 struct ice_blk_info blk[ICE_BLK_COUNT]; 1077 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 1078 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT]; 1079 struct ice_lock rss_locks; /* protect RSS configuration */ 1080 struct LIST_HEAD_TYPE rss_list_head; 1081 struct ice_mbx_snapshot mbx_snapshot; 1082 u8 dvm_ena; 1083 }; 1084 1085 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1086 struct ice_eth_stats { 1087 u64 rx_bytes; /* gorc */ 1088 u64 rx_unicast; /* uprc */ 1089 u64 rx_multicast; /* mprc */ 1090 u64 rx_broadcast; /* bprc */ 1091 u64 rx_discards; /* rdpc */ 1092 u64 rx_unknown_protocol; /* rupp */ 1093 u64 tx_bytes; /* gotc */ 1094 u64 tx_unicast; /* uptc */ 1095 u64 tx_multicast; /* mptc */ 1096 u64 tx_broadcast; /* bptc */ 1097 u64 tx_discards; /* tdpc */ 1098 u64 tx_errors; /* tepc */ 1099 u64 rx_no_desc; /* repc */ 1100 u64 rx_errors; /* repc */ 1101 }; 1102 1103 #define ICE_MAX_UP 8 1104 1105 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */ 1106 struct ice_veb_up_stats { 1107 u64 up_rx_pkts[ICE_MAX_UP]; 1108 u64 up_rx_bytes[ICE_MAX_UP]; 1109 u64 up_tx_pkts[ICE_MAX_UP]; 1110 u64 up_tx_bytes[ICE_MAX_UP]; 1111 }; 1112 1113 /* Statistics collected by the MAC */ 1114 struct ice_hw_port_stats { 1115 /* eth stats collected by the port */ 1116 struct ice_eth_stats eth; 1117 /* additional port specific stats */ 1118 u64 tx_dropped_link_down; /* tdold */ 1119 u64 crc_errors; /* crcerrs */ 1120 u64 illegal_bytes; /* illerrc */ 1121 u64 error_bytes; /* errbc */ 1122 u64 mac_local_faults; /* mlfc */ 1123 u64 mac_remote_faults; /* mrfc */ 1124 u64 rx_len_errors; /* rlec */ 1125 u64 link_xon_rx; /* lxonrxc */ 1126 u64 link_xoff_rx; /* lxoffrxc */ 1127 u64 link_xon_tx; /* lxontxc */ 1128 u64 link_xoff_tx; /* lxofftxc */ 1129 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1130 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1131 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1132 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1133 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1134 u64 rx_size_64; /* prc64 */ 1135 u64 rx_size_127; /* prc127 */ 1136 u64 rx_size_255; /* prc255 */ 1137 u64 rx_size_511; /* prc511 */ 1138 u64 rx_size_1023; /* prc1023 */ 1139 u64 rx_size_1522; /* prc1522 */ 1140 u64 rx_size_big; /* prc9522 */ 1141 u64 rx_undersize; /* ruc */ 1142 u64 rx_fragments; /* rfc */ 1143 u64 rx_oversize; /* roc */ 1144 u64 rx_jabber; /* rjc */ 1145 u64 tx_size_64; /* ptc64 */ 1146 u64 tx_size_127; /* ptc127 */ 1147 u64 tx_size_255; /* ptc255 */ 1148 u64 tx_size_511; /* ptc511 */ 1149 u64 tx_size_1023; /* ptc1023 */ 1150 u64 tx_size_1522; /* ptc1522 */ 1151 u64 tx_size_big; /* ptc9522 */ 1152 u64 mac_short_pkt_dropped; /* mspdc */ 1153 /* EEE LPI */ 1154 u32 tx_lpi_status; 1155 u32 rx_lpi_status; 1156 u64 tx_lpi_count; /* etlpic */ 1157 u64 rx_lpi_count; /* erlpic */ 1158 }; 1159 1160 enum ice_sw_fwd_act_type { 1161 ICE_FWD_TO_VSI = 0, 1162 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 1163 ICE_FWD_TO_Q, 1164 ICE_FWD_TO_QGRP, 1165 ICE_DROP_PACKET, 1166 ICE_LG_ACTION, 1167 ICE_INVAL_ACT 1168 }; 1169 1170 struct ice_aq_get_set_rss_lut_params { 1171 u16 vsi_handle; /* software VSI handle */ 1172 u16 lut_size; /* size of the LUT buffer */ 1173 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1174 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1175 u8 global_lut_id; /* only valid when lut_type is global */ 1176 }; 1177 1178 /* Checksum and Shadow RAM pointers */ 1179 #define ICE_SR_NVM_CTRL_WORD 0x00 1180 #define ICE_SR_PHY_ANALOG_PTR 0x04 1181 #define ICE_SR_OPTION_ROM_PTR 0x05 1182 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1183 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1184 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1185 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09 1186 #define ICE_SR_EMP_IMAGE_PTR 0x0B 1187 #define ICE_SR_PE_IMAGE_PTR 0x0C 1188 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D 1189 #define ICE_SR_MNG_CFG_PTR 0x0E 1190 #define ICE_SR_EMP_MODULE_PTR 0x0F 1191 #define ICE_SR_PBA_BLOCK_PTR 0x16 1192 #define ICE_SR_BOOT_CFG_PTR 0x132 1193 #define ICE_SR_NVM_WOL_CFG 0x19 1194 #define ICE_NVM_OROM_VER_OFF 0x02 1195 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1196 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27 1197 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28 1198 #define ICE_SR_NVM_MAP_VER 0x29 1199 #define ICE_SR_NVM_IMAGE_VER 0x2A 1200 #define ICE_SR_NVM_STRUCTURE_VER 0x2B 1201 #define ICE_SR_NVM_EETRACK_LO 0x2D 1202 #define ICE_SR_NVM_EETRACK_HI 0x2E 1203 #define ICE_NVM_VER_LO_SHIFT 0 1204 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1205 #define ICE_NVM_VER_HI_SHIFT 12 1206 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1207 #define ICE_OEM_EETRACK_ID 0xffffffff 1208 #define ICE_OROM_VER_PATCH_SHIFT 0 1209 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1210 #define ICE_OROM_VER_BUILD_SHIFT 8 1211 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1212 #define ICE_OROM_VER_SHIFT 24 1213 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1214 #define ICE_SR_VPD_PTR 0x2F 1215 #define ICE_SR_PXE_SETUP_PTR 0x30 1216 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31 1217 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1218 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1219 #define ICE_SR_VLAN_CFG_PTR 0x37 1220 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1221 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1222 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1223 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1224 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D 1225 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1226 #define ICE_SR_SW_CHECKSUM_WORD 0x3F 1227 #define ICE_SR_PFA_PTR 0x40 1228 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41 1229 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1230 #define ICE_SR_NVM_BANK_SIZE 0x43 1231 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 1232 #define ICE_SR_OROM_BANK_SIZE 0x45 1233 #define ICE_SR_NETLIST_BANK_PTR 0x46 1234 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1235 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48 1236 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D 1237 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E 1238 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 1239 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118 1240 1241 /* CSS Header words */ 1242 #define ICE_NVM_CSS_HDR_LEN_L 0x02 1243 #define ICE_NVM_CSS_HDR_LEN_H 0x03 1244 #define ICE_NVM_CSS_SREV_L 0x14 1245 #define ICE_NVM_CSS_SREV_H 0x15 1246 1247 /* Length of Authentication header section in words */ 1248 #define ICE_NVM_AUTH_HEADER_LEN 0x08 1249 1250 /* The Link Topology Netlist section is stored as a series of words. It is 1251 * stored in the NVM as a TLV, with the first two words containing the type 1252 * and length. 1253 */ 1254 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1255 #define ICE_NETLIST_TYPE_OFFSET 0x0000 1256 #define ICE_NETLIST_LEN_OFFSET 0x0001 1257 1258 /* The Link Topology section follows the TLV header. When reading the netlist 1259 * using ice_read_netlist_module, we need to account for the 2-word TLV 1260 * header. 1261 */ 1262 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1263 1264 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1265 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1266 1267 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0) 1268 1269 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1270 #define ICE_NETLIST_ID_BLK_SIZE 0x30 1271 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1272 1273 /* netlist ID block field offsets (word offsets) */ 1274 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1275 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1276 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1277 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1278 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1279 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1280 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1281 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1282 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1283 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1284 1285 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1286 #define ICE_SR_VPD_SIZE_WORDS 512 1287 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512 1288 #define ICE_SR_CTRL_WORD_1_S 0x06 1289 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1290 #define ICE_SR_CTRL_WORD_VALID 0x1 1291 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1292 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1293 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1294 1295 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1296 1297 /* Shadow RAM related */ 1298 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1299 #define ICE_SR_BUF_ALIGNMENT 4096 1300 #define ICE_SR_WORDS_IN_1KB 512 1301 /* Checksum should be calculated such that after adding all the words, 1302 * including the checksum word itself, the sum should be 0xBABA. 1303 */ 1304 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA 1305 1306 /* Link override related */ 1307 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1308 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1309 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1310 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1311 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1312 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1313 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1314 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1315 1316 #define ICE_PBA_FLAG_DFLT 0xFAFA 1317 /* Hash redirection LUT for VSI - maximum array size */ 1318 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1319 1320 /* 1321 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register. 1322 * This is needed to determine the BAR0 space for the VFs 1323 */ 1324 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0 1325 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1 1326 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2 1327 1328 /* AQ API version for LLDP_FILTER_CONTROL */ 1329 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1330 #define ICE_FW_API_LLDP_FLTR_MIN 7 1331 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1332 1333 /* AQ API version for report default configuration */ 1334 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1335 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1336 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1337 1338 /* FW version for FEC disable in Auto FEC mode */ 1339 #define ICE_FW_FEC_DIS_AUTO_BRANCH 1 1340 #define ICE_FW_FEC_DIS_AUTO_MAJ 7 1341 #define ICE_FW_FEC_DIS_AUTO_MIN 0 1342 #define ICE_FW_FEC_DIS_AUTO_PATCH 5 1343 1344 /* AQ API version for FW health reports */ 1345 #define ICE_FW_API_HEALTH_REPORT_MAJ 1 1346 #define ICE_FW_API_HEALTH_REPORT_MIN 7 1347 #define ICE_FW_API_HEALTH_REPORT_PATCH 6 1348 1349 /* AQ API version for FW auto drop reports */ 1350 #define ICE_FW_API_AUTO_DROP_MAJ 1 1351 #define ICE_FW_API_AUTO_DROP_MIN 4 1352 #endif /* _ICE_TYPE_H_ */ 1353