1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_TYPE_H_ 33 #define _ICE_TYPE_H_ 34 35 #include "ice_defs.h" 36 #include "ice_status.h" 37 #include "ice_hw_autogen.h" 38 #include "ice_devids.h" 39 #include "ice_osdep.h" 40 #include "ice_bitops.h" /* Must come before ice_controlq.h */ 41 #include "ice_lan_tx_rx.h" 42 #include "ice_ddp_common.h" 43 #include "ice_controlq.h" 44 #include "ice_flex_type.h" 45 #include "ice_protocol_type.h" 46 #include "ice_vlan_mode.h" 47 #include "ice_fwlog.h" 48 49 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc) 50 { 51 return !!(bitmap & BIT(tc)); 52 } 53 54 /** 55 * DIV_S64 - Divide signed 64-bit value with signed 64-bit divisor 56 * @dividend: value to divide 57 * @divisor: value to divide by 58 * 59 * Use DIV_S64 for any 64-bit divide which operates on signed 64-bit dividends. 60 * Do not use this for unsigned 64-bit dividends as it will not produce 61 * correct results if the dividend is larger than S64_MAX. 62 */ 63 static inline s64 DIV_S64(s64 dividend, s64 divisor) 64 { 65 return dividend / divisor; 66 } 67 68 /** 69 * DIV_U64 - Divide unsigned 64-bit value by unsigned 64-bit divisor 70 * @dividend: value to divide 71 * @divisor: value to divide by 72 * 73 * Use DIV_U64 for any 64-bit divide which operates on unsigned 64-bit 74 * dividends. Do not use this for signed 64-bit dividends as it will not 75 * handle negative values correctly. 76 */ 77 static inline u64 DIV_U64(u64 dividend, u64 divisor) 78 { 79 return dividend / divisor; 80 } 81 82 static inline u64 round_up_64bit(u64 a, u32 b) 83 { 84 return DIV_U64(((a) + (b) / 2), (b)); 85 } 86 87 static inline u32 ice_round_to_num(u32 N, u32 R) 88 { 89 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 90 ((((N) + (R) - 1) / (R)) * (R))); 91 } 92 93 /* Driver always calls main vsi_handle first */ 94 #define ICE_MAIN_VSI_HANDLE 0 95 96 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 97 #define ICE_MS_TO_GTIME(time) ((time) * 1000) 98 99 /* Data type manipulation macros. */ 100 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 101 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 102 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 103 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF)) 104 #define ICE_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 105 #define ICE_LO_BYTE(x) ((u8)((x) & 0xFF)) 106 107 /* debug masks - set these bits in hw->debug_mask to control output */ 108 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */ 109 #define ICE_DBG_INIT BIT_ULL(1) 110 #define ICE_DBG_RELEASE BIT_ULL(2) 111 #define ICE_DBG_FW_LOG BIT_ULL(3) 112 #define ICE_DBG_LINK BIT_ULL(4) 113 #define ICE_DBG_PHY BIT_ULL(5) 114 #define ICE_DBG_QCTX BIT_ULL(6) 115 #define ICE_DBG_NVM BIT_ULL(7) 116 #define ICE_DBG_LAN BIT_ULL(8) 117 #define ICE_DBG_FLOW BIT_ULL(9) 118 #define ICE_DBG_DCB BIT_ULL(10) 119 #define ICE_DBG_DIAG BIT_ULL(11) 120 #define ICE_DBG_FD BIT_ULL(12) 121 #define ICE_DBG_SW BIT_ULL(13) 122 #define ICE_DBG_SCHED BIT_ULL(14) 123 124 #define ICE_DBG_RDMA BIT_ULL(15) 125 #define ICE_DBG_PKG BIT_ULL(16) 126 #define ICE_DBG_RES BIT_ULL(17) 127 #define ICE_DBG_AQ_MSG BIT_ULL(24) 128 #define ICE_DBG_AQ_DESC BIT_ULL(25) 129 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 130 #define ICE_DBG_AQ_CMD BIT_ULL(27) 131 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 132 ICE_DBG_AQ_DESC | \ 133 ICE_DBG_AQ_DESC_BUF | \ 134 ICE_DBG_AQ_CMD) 135 #define ICE_DBG_PARSER BIT_ULL(28) 136 137 #define ICE_DBG_USER BIT_ULL(31) 138 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL 139 140 #define IS_UNICAST_ETHER_ADDR(addr) \ 141 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0)) 142 143 #define IS_MULTICAST_ETHER_ADDR(addr) \ 144 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1)) 145 146 /* Check whether an address is broadcast. */ 147 #define IS_BROADCAST_ETHER_ADDR(addr) \ 148 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff)))) 149 150 #define IS_ZERO_ETHER_ADDR(addr) \ 151 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \ 152 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \ 153 ((bool)((((u16 *)(addr))[2] == ((u16)0x0))))) 154 155 #ifndef IS_ETHER_ADDR_EQUAL 156 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \ 157 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \ 158 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \ 159 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2])))) 160 #endif 161 162 enum ice_aq_res_ids { 163 ICE_NVM_RES_ID = 1, 164 ICE_SPD_RES_ID, 165 ICE_CHANGE_LOCK_RES_ID, 166 ICE_GLOBAL_CFG_LOCK_RES_ID 167 }; 168 169 /* FW update timeout definitions are in milliseconds */ 170 #define ICE_NVM_TIMEOUT 180000 171 #define ICE_CHANGE_LOCK_TIMEOUT 1000 172 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 173 174 struct ice_driver_ver { 175 u8 major_ver; 176 u8 minor_ver; 177 u8 build_ver; 178 u8 subbuild_ver; 179 u8 driver_string[32]; 180 }; 181 182 enum ice_fc_mode { 183 ICE_FC_NONE = 0, 184 ICE_FC_RX_PAUSE, 185 ICE_FC_TX_PAUSE, 186 ICE_FC_FULL, 187 ICE_FC_AUTO, 188 ICE_FC_PFC, 189 ICE_FC_DFLT 190 }; 191 192 enum ice_phy_cache_mode { 193 ICE_FC_MODE = 0, 194 ICE_SPEED_MODE, 195 ICE_FEC_MODE 196 }; 197 198 enum ice_fec_mode { 199 ICE_FEC_NONE = 0, 200 ICE_FEC_RS, 201 ICE_FEC_BASER, 202 ICE_FEC_AUTO, 203 ICE_FEC_DIS_AUTO 204 }; 205 206 struct ice_phy_cache_mode_data { 207 union { 208 enum ice_fec_mode curr_user_fec_req; 209 enum ice_fc_mode curr_user_fc_req; 210 u16 curr_user_speed_req; 211 } data; 212 }; 213 214 enum ice_set_fc_aq_failures { 215 ICE_SET_FC_AQ_FAIL_NONE = 0, 216 ICE_SET_FC_AQ_FAIL_GET, 217 ICE_SET_FC_AQ_FAIL_SET, 218 ICE_SET_FC_AQ_FAIL_UPDATE 219 }; 220 221 /* These are structs for managing the hardware information and the operations */ 222 /* MAC types */ 223 enum ice_mac_type { 224 ICE_MAC_UNKNOWN = 0, 225 ICE_MAC_VF, 226 ICE_MAC_E810, 227 ICE_MAC_GENERIC, 228 ICE_MAC_GENERIC_3K, 229 ICE_MAC_GENERIC_3K_E825, 230 }; 231 232 /* Media Types */ 233 enum ice_media_type { 234 ICE_MEDIA_NONE = 0, 235 ICE_MEDIA_UNKNOWN, 236 ICE_MEDIA_FIBER, 237 ICE_MEDIA_BASET, 238 ICE_MEDIA_BACKPLANE, 239 ICE_MEDIA_DA, 240 ICE_MEDIA_AUI, 241 }; 242 243 #define ICE_MEDIA_BASET_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_100BASE_TX | \ 244 ICE_PHY_TYPE_LOW_1000BASE_T | \ 245 ICE_PHY_TYPE_LOW_2500BASE_T | \ 246 ICE_PHY_TYPE_LOW_5GBASE_T | \ 247 ICE_PHY_TYPE_LOW_10GBASE_T | \ 248 ICE_PHY_TYPE_LOW_25GBASE_T) 249 250 #define ICE_MEDIA_C2M_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC | \ 251 ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC | \ 252 ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC | \ 253 ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC | \ 254 ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC | \ 255 ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC | \ 256 ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC | \ 257 ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) 258 259 #define ICE_MEDIA_C2M_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC | \ 260 ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) 261 262 #define ICE_MEDIA_OPT_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_1000BASE_SX | \ 263 ICE_PHY_TYPE_LOW_1000BASE_LX | \ 264 ICE_PHY_TYPE_LOW_10GBASE_SR | \ 265 ICE_PHY_TYPE_LOW_10GBASE_LR | \ 266 ICE_PHY_TYPE_LOW_25GBASE_SR | \ 267 ICE_PHY_TYPE_LOW_25GBASE_LR | \ 268 ICE_PHY_TYPE_LOW_40GBASE_SR4 | \ 269 ICE_PHY_TYPE_LOW_40GBASE_LR4 | \ 270 ICE_PHY_TYPE_LOW_50GBASE_SR2 | \ 271 ICE_PHY_TYPE_LOW_50GBASE_LR2 | \ 272 ICE_PHY_TYPE_LOW_50GBASE_SR | \ 273 ICE_PHY_TYPE_LOW_50GBASE_LR | \ 274 ICE_PHY_TYPE_LOW_100GBASE_SR4 | \ 275 ICE_PHY_TYPE_LOW_100GBASE_LR4 | \ 276 ICE_PHY_TYPE_LOW_100GBASE_SR2 | \ 277 ICE_PHY_TYPE_LOW_50GBASE_FR | \ 278 ICE_PHY_TYPE_LOW_100GBASE_DR) 279 280 #define ICE_MEDIA_BP_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_1000BASE_KX | \ 281 ICE_PHY_TYPE_LOW_2500BASE_KX | \ 282 ICE_PHY_TYPE_LOW_5GBASE_KR | \ 283 ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 | \ 284 ICE_PHY_TYPE_LOW_25GBASE_KR | \ 285 ICE_PHY_TYPE_LOW_25GBASE_KR_S | \ 286 ICE_PHY_TYPE_LOW_25GBASE_KR1 | \ 287 ICE_PHY_TYPE_LOW_40GBASE_KR4 | \ 288 ICE_PHY_TYPE_LOW_50GBASE_KR2 | \ 289 ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 | \ 290 ICE_PHY_TYPE_LOW_100GBASE_KR4 | \ 291 ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) 292 293 #define ICE_MEDIA_BP_PHY_TYPE_HIGH_M ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 294 295 #define ICE_MEDIA_DAC_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_10G_SFI_DA | \ 296 ICE_PHY_TYPE_LOW_25GBASE_CR | \ 297 ICE_PHY_TYPE_LOW_25GBASE_CR_S | \ 298 ICE_PHY_TYPE_LOW_25GBASE_CR1 | \ 299 ICE_PHY_TYPE_LOW_40GBASE_CR4 | \ 300 ICE_PHY_TYPE_LOW_50GBASE_CR2 | \ 301 ICE_PHY_TYPE_LOW_100GBASE_CR4 | \ 302 ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 | \ 303 ICE_PHY_TYPE_LOW_50GBASE_CP | \ 304 ICE_PHY_TYPE_LOW_100GBASE_CP2) 305 306 #define ICE_MEDIA_C2C_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_100M_SGMII | \ 307 ICE_PHY_TYPE_LOW_1G_SGMII | \ 308 ICE_PHY_TYPE_LOW_2500BASE_X | \ 309 ICE_PHY_TYPE_LOW_10G_SFI_C2C | \ 310 ICE_PHY_TYPE_LOW_25G_AUI_C2C | \ 311 ICE_PHY_TYPE_LOW_40G_XLAUI | \ 312 ICE_PHY_TYPE_LOW_50G_LAUI2 | \ 313 ICE_PHY_TYPE_LOW_50G_AUI2 | \ 314 ICE_PHY_TYPE_LOW_50G_AUI1 | \ 315 ICE_PHY_TYPE_LOW_100G_CAUI4 | \ 316 ICE_PHY_TYPE_LOW_100G_AUI4) 317 318 #define ICE_MEDIA_C2C_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2 | \ 319 ICE_PHY_TYPE_HIGH_100G_AUI2) 320 321 /* Software VSI types. */ 322 enum ice_vsi_type { 323 ICE_VSI_PF = 0, 324 ICE_VSI_VF = 1, 325 ICE_VSI_LB = 6, 326 }; 327 328 struct ice_link_status { 329 /* Refer to ice_aq_phy_type for bits definition */ 330 u64 phy_type_low; 331 u64 phy_type_high; 332 u8 topo_media_conflict; 333 u16 max_frame_size; 334 u16 link_speed; 335 u16 req_speeds; 336 u8 link_cfg_err; 337 u8 lse_ena; /* Link Status Event notification */ 338 u8 link_info; 339 u8 an_info; 340 u8 ext_info; 341 u8 fec_info; 342 u8 pacing; 343 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 344 * ice_aqc_get_phy_caps structure 345 */ 346 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 347 }; 348 349 /* Different data queue types: These are mainly for SW consumption. */ 350 enum ice_q { 351 ICE_DATA_Q_DOORBELL, 352 ICE_DATA_Q_CMPL, 353 ICE_DATA_Q_QUANTA, 354 ICE_DATA_Q_RX, 355 ICE_DATA_Q_TX, 356 }; 357 358 /* Different reset sources for which a disable queue AQ call has to be made in 359 * order to clean the Tx scheduler as a part of the reset 360 */ 361 enum ice_disq_rst_src { 362 ICE_NO_RESET = 0, 363 ICE_VM_RESET, 364 ICE_VF_RESET, 365 }; 366 367 /* PHY info such as phy_type, etc... */ 368 struct ice_phy_info { 369 struct ice_link_status link_info; 370 struct ice_link_status link_info_old; 371 u64 phy_type_low; 372 u64 phy_type_high; 373 enum ice_media_type media_type; 374 u8 get_link_info; 375 /* Please refer to struct ice_aqc_get_link_status_data to get 376 * detail of enable bit in curr_user_speed_req 377 */ 378 u16 curr_user_speed_req; 379 enum ice_fec_mode curr_user_fec_req; 380 enum ice_fc_mode curr_user_fc_req; 381 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 382 }; 383 384 #define ICE_MAX_NUM_MIRROR_RULES 64 385 386 #define ICE_L2TPV2_FLAGS_CTRL 0x8000 387 #define ICE_L2TPV2_FLAGS_LEN 0x4000 388 #define ICE_L2TPV2_FLAGS_SEQ 0x0800 389 #define ICE_L2TPV2_FLAGS_OFF 0x0200 390 #define ICE_L2TPV2_FLAGS_VER 0x0002 391 392 #define ICE_L2TPV2_PKT_LENGTH 6 393 #define ICE_PPP_PKT_LENGTH 4 394 395 /* Common HW capabilities for SW use */ 396 struct ice_hw_common_caps { 397 /* Write CSR protection */ 398 u64 wr_csr_prot; 399 u32 switching_mode; 400 /* switching mode supported - EVB switching (including cloud) */ 401 #define ICE_NVM_IMAGE_TYPE_EVB 0x0 402 403 /* Manageablity mode & supported protocols over MCTP */ 404 u32 mgmt_mode; 405 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF 406 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0 407 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00 408 409 u32 mgmt_protocols_mctp; 410 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0) 411 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1) 412 #define ICE_MGMT_MODE_PROTO_OEM BIT(2) 413 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3) 414 415 u32 os2bmc; 416 u32 valid_functions; 417 /* DCB capabilities */ 418 u32 active_tc_bitmap; 419 u32 maxtc; 420 421 /* RSS related capabilities */ 422 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 423 u32 rss_table_entry_width; /* RSS Entry width in bits */ 424 425 /* Tx/Rx queues */ 426 u32 num_rxq; /* Number/Total Rx queues */ 427 u32 rxq_first_id; /* First queue ID for Rx queues */ 428 u32 num_txq; /* Number/Total Tx queues */ 429 u32 txq_first_id; /* First queue ID for Tx queues */ 430 431 /* MSI-X vectors */ 432 u32 num_msix_vectors; 433 u32 msix_vector_first_id; 434 435 /* Max MTU for function or device */ 436 u32 max_mtu; 437 438 /* WOL related */ 439 u32 num_wol_proxy_fltr; 440 u32 wol_proxy_vsi_seid; 441 442 /* LED/SDP pin count */ 443 u32 led_pin_num; 444 u32 sdp_pin_num; 445 446 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 447 #define ICE_MAX_SUPPORTED_GPIO_LED 12 448 #define ICE_MAX_SUPPORTED_GPIO_SDP 8 449 u8 led[ICE_MAX_SUPPORTED_GPIO_LED]; 450 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP]; 451 452 /* SR-IOV virtualization */ 453 u8 sr_iov_1_1; /* SR-IOV enabled */ 454 455 /* EVB capabilities */ 456 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 457 u8 evb_802_1_qbh; /* Bridge Port Extension */ 458 459 u8 dcb; 460 u8 iscsi; 461 u8 mgmt_cem; 462 u8 iwarp; 463 u8 roce_lag; 464 465 /* WoL and APM support */ 466 #define ICE_WOL_SUPPORT_M BIT(0) 467 #define ICE_ACPI_PROG_MTHD_M BIT(1) 468 #define ICE_PROXY_SUPPORT_M BIT(2) 469 u8 apm_wol_support; 470 u8 acpi_prog_mthd; 471 u8 proxy_support; 472 bool sec_rev_disabled; 473 bool update_disabled; 474 bool nvm_unified_update; 475 bool netlist_auth; 476 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) 477 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) 478 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 479 #define ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5) 480 /* PCIe reset avoidance */ 481 bool pcie_reset_avoidance; /* false: not supported, true: supported */ 482 /* Post update reset restriction */ 483 bool reset_restrict_support; /* false: not supported, true: supported */ 484 485 /* External topology device images within the NVM */ 486 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4 487 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT]; 488 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT]; 489 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT]; 490 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8 491 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \ 492 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S) 493 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; 494 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0) 495 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; 496 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1) 497 bool ext_topo_dev_img_ver_schema[ICE_EXT_TOPO_DEV_IMG_COUNT]; 498 #define ICE_EXT_TOPO_DEV_IMG_VER_SCHEMA BIT(2) 499 bool tx_sched_topo_comp_mode_en; 500 bool dyn_flattening_en; 501 /* Support for OROM update in Recovery Mode */ 502 bool orom_recovery_update; 503 }; 504 505 #define ICE_NAC_TOPO_PRIMARY_M BIT(0) 506 #define ICE_NAC_TOPO_DUAL_M BIT(1) 507 #define ICE_NAC_TOPO_ID_M MAKEMASK(0xf, 0) 508 509 struct ice_nac_topology { 510 u32 mode; 511 u8 id; 512 }; 513 514 /* Function specific capabilities */ 515 struct ice_hw_func_caps { 516 struct ice_hw_common_caps common_cap; 517 u32 num_allocd_vfs; /* Number of allocated VFs */ 518 u32 vf_base_id; /* Logical ID of the first VF */ 519 u32 guar_num_vsi; 520 }; 521 522 /* Device wide capabilities */ 523 struct ice_hw_dev_caps { 524 struct ice_hw_common_caps common_cap; 525 u32 num_vfs_exposed; /* Total number of VFs exposed */ 526 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 527 u32 num_funcs; 528 struct ice_nac_topology nac_topo; 529 /* bitmap of supported sensors */ 530 u32 supported_sensors; 531 #define ICE_SENSOR_SUPPORT_E810_INT_TEMP BIT(0) 532 }; 533 534 /* Information about MAC such as address, etc... */ 535 struct ice_mac_info { 536 u8 lan_addr[ETH_ALEN]; 537 u8 perm_addr[ETH_ALEN]; 538 u8 port_addr[ETH_ALEN]; 539 u8 wol_addr[ETH_ALEN]; 540 }; 541 542 /* PCI bus types */ 543 enum ice_bus_type { 544 ice_bus_unknown = 0, 545 ice_bus_pci_express, 546 ice_bus_embedded, /* Is device Embedded versus card */ 547 ice_bus_reserved 548 }; 549 550 /* PCI bus speeds */ 551 enum ice_pcie_bus_speed { 552 ice_pcie_speed_unknown = 0xff, 553 ice_pcie_speed_2_5GT = 0x14, 554 ice_pcie_speed_5_0GT = 0x15, 555 ice_pcie_speed_8_0GT = 0x16, 556 ice_pcie_speed_16_0GT = 0x17 557 }; 558 559 /* PCI bus widths */ 560 enum ice_pcie_link_width { 561 ice_pcie_lnk_width_resrv = 0x00, 562 ice_pcie_lnk_x1 = 0x01, 563 ice_pcie_lnk_x2 = 0x02, 564 ice_pcie_lnk_x4 = 0x04, 565 ice_pcie_lnk_x8 = 0x08, 566 ice_pcie_lnk_x12 = 0x0C, 567 ice_pcie_lnk_x16 = 0x10, 568 ice_pcie_lnk_x32 = 0x20, 569 ice_pcie_lnk_width_unknown = 0xff, 570 }; 571 572 /* Reset types used to determine which kind of reset was requested. These 573 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 574 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 575 * because its reset source is different than the other types listed. 576 */ 577 enum ice_reset_req { 578 ICE_RESET_POR = 0, 579 ICE_RESET_INVAL = 0, 580 ICE_RESET_CORER = 1, 581 ICE_RESET_GLOBR = 2, 582 ICE_RESET_EMPR = 3, 583 ICE_RESET_PFR = 4, 584 }; 585 586 /* Bus parameters */ 587 struct ice_bus_info { 588 enum ice_pcie_bus_speed speed; 589 enum ice_pcie_link_width width; 590 enum ice_bus_type type; 591 u16 domain_num; 592 u16 device; 593 u8 func; 594 u8 bus_num; 595 }; 596 597 /* Flow control (FC) parameters */ 598 struct ice_fc_info { 599 enum ice_fc_mode current_mode; /* FC mode in effect */ 600 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 601 }; 602 603 /* Option ROM version information */ 604 struct ice_orom_info { 605 u8 major; /* Major version of OROM */ 606 u8 patch; /* Patch version of OROM */ 607 u16 build; /* Build version of OROM */ 608 u32 srev; /* Security revision */ 609 }; 610 611 /* NVM version information */ 612 struct ice_nvm_info { 613 u32 eetrack; 614 u32 srev; 615 u8 major; 616 u8 minor; 617 }; 618 619 /* Minimum Security Revision information */ 620 struct ice_minsrev_info { 621 u32 nvm; 622 u32 orom; 623 u8 nvm_valid : 1; 624 u8 orom_valid : 1; 625 }; 626 627 /* netlist version information */ 628 struct ice_netlist_info { 629 u32 major; /* major high/low */ 630 u32 minor; /* minor high/low */ 631 u32 type; /* type high/low */ 632 u32 rev; /* revision high/low */ 633 u32 hash; /* SHA-1 hash word */ 634 u16 cust_ver; /* customer version */ 635 }; 636 637 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 638 * of the flash image. 639 */ 640 enum ice_flash_bank { 641 ICE_INVALID_FLASH_BANK, 642 ICE_1ST_FLASH_BANK, 643 ICE_2ND_FLASH_BANK, 644 }; 645 646 /* Enumeration of which flash bank is desired to read from, either the active 647 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 648 * code which just wants to read the active or inactive flash bank. 649 */ 650 enum ice_bank_select { 651 ICE_ACTIVE_FLASH_BANK, 652 ICE_INACTIVE_FLASH_BANK, 653 }; 654 655 /* information for accessing NVM, OROM, and Netlist flash banks */ 656 struct ice_bank_info { 657 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 658 u32 nvm_size; /* Size of NVM bank */ 659 u32 orom_ptr; /* Pointer to 1st OROM bank */ 660 u32 orom_size; /* Size of OROM bank */ 661 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 662 u32 netlist_size; /* Size of Netlist bank */ 663 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 664 enum ice_flash_bank orom_bank; /* Active OROM bank */ 665 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 666 }; 667 668 /* Flash Chip Information */ 669 struct ice_flash_info { 670 struct ice_orom_info orom; /* Option ROM version info */ 671 struct ice_nvm_info nvm; /* NVM version information */ 672 struct ice_netlist_info netlist;/* Netlist version info */ 673 struct ice_bank_info banks; /* Flash Bank information */ 674 u16 sr_words; /* Shadow RAM size in words */ 675 u32 flash_size; /* Size of available flash in bytes */ 676 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 677 }; 678 679 struct ice_link_default_override_tlv { 680 u8 options; 681 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 682 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 683 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 684 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 685 #define ICE_LINK_OVERRIDE_EN BIT(3) 686 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 687 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 688 u8 phy_config; 689 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 690 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 691 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 692 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 693 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 694 u8 fec_options; 695 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 696 u8 rsvd1; 697 u64 phy_type_low; 698 u64 phy_type_high; 699 }; 700 701 #define ICE_NVM_VER_LEN 32 702 703 /* Max number of port to queue branches w.r.t topology */ 704 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 705 706 #define ice_for_each_traffic_class(_i) \ 707 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 708 709 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 710 * to driver defined policy for default aggregator 711 */ 712 #define ICE_INVAL_TEID 0xFFFFFFFF 713 #define ICE_DFLT_AGG_ID 0 714 715 struct ice_sched_node { 716 struct ice_sched_node *parent; 717 struct ice_sched_node *sibling; /* next sibling in the same layer */ 718 struct ice_sched_node **children; 719 struct ice_aqc_txsched_elem_data info; 720 u32 agg_id; /* aggregator group ID */ 721 u16 vsi_handle; 722 u8 in_use; /* suspended or in use */ 723 u8 tx_sched_layer; /* Logical Layer (1-9) */ 724 u8 num_children; 725 u8 tc_num; 726 u8 owner; 727 #define ICE_SCHED_NODE_OWNER_LAN 0 728 #define ICE_SCHED_NODE_OWNER_AE 1 729 #define ICE_SCHED_NODE_OWNER_RDMA 2 730 }; 731 732 /* Access Macros for Tx Sched Elements data */ 733 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid) 734 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid) 735 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \ 736 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx) 737 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \ 738 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx) 739 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id) 740 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \ 741 LE16_TO_CPU((x)->info.cir_bw.bw_alloc) 742 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \ 743 LE16_TO_CPU((x)->info.eir_bw.bw_alloc) 744 745 struct ice_sched_rl_profile { 746 u32 rate; /* In Kbps */ 747 struct ice_aqc_rl_profile_elem info; 748 }; 749 750 /* The aggregator type determines if identifier is for a VSI group, 751 * aggregator group, aggregator of queues, or queue group. 752 */ 753 enum ice_agg_type { 754 ICE_AGG_TYPE_UNKNOWN = 0, 755 ICE_AGG_TYPE_TC, 756 ICE_AGG_TYPE_AGG, /* aggregator */ 757 ICE_AGG_TYPE_VSI, 758 ICE_AGG_TYPE_QG, 759 ICE_AGG_TYPE_Q 760 }; 761 762 /* Rate limit types */ 763 enum ice_rl_type { 764 ICE_UNKNOWN_BW = 0, 765 ICE_MIN_BW, /* for CIR profile */ 766 ICE_MAX_BW, /* for EIR profile */ 767 ICE_SHARED_BW /* for shared profile */ 768 }; 769 770 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 771 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 772 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 773 #define ICE_SCHED_NO_PRIORITY 0 774 #define ICE_SCHED_NO_BW_WT 0 775 #define ICE_SCHED_DFLT_RL_PROF_ID 0 776 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 777 #define ICE_SCHED_DFLT_BW_WT 4 778 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 779 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 780 781 /* Access Macros for Tx Sched RL Profile data */ 782 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id) 783 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size) 784 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply) 785 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc) 786 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode) 787 788 #define ICE_MAX_PORT_PER_PCI_DEV 8 789 790 /* The following tree example shows the naming conventions followed under 791 * ice_port_info struct for default scheduler tree topology. 792 * 793 * A tree on a port 794 * * ---> root node 795 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8) 796 * * * * * * * * * | 797 * / | 798 * * | 799 * / |-> num_elements (range:1 - 9) 800 * * | implies num_of_layers 801 * / | 802 * (a)* | 803 * 804 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under 805 * (a) as child node where queues get added, add Tx/Rx queue admin commands; 806 * need TEID of (a) to add queues. 807 * 808 * This tree 809 * -> has 8 branches (one for each TC) 810 * -> First branch (TC0) has 4 elements 811 * -> has 4 layers 812 * -> (a) is the topmost layer node created by firmware on branch 0 813 * 814 * Note: Above asterisk tree covers only basic terminology and scenario. 815 * Refer to the documentation for more info. 816 */ 817 818 /* Data structure for saving BW information */ 819 enum ice_bw_type { 820 ICE_BW_TYPE_PRIO, 821 ICE_BW_TYPE_CIR, 822 ICE_BW_TYPE_CIR_WT, 823 ICE_BW_TYPE_EIR, 824 ICE_BW_TYPE_EIR_WT, 825 ICE_BW_TYPE_SHARED, 826 ICE_BW_TYPE_CNT /* This must be last */ 827 }; 828 829 struct ice_bw { 830 u32 bw; 831 u16 bw_alloc; 832 }; 833 834 struct ice_bw_type_info { 835 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT); 836 u8 generic; 837 struct ice_bw cir_bw; 838 struct ice_bw eir_bw; 839 u32 shared_bw; 840 }; 841 842 /* VSI queue context structure for given TC */ 843 struct ice_q_ctx { 844 u16 q_handle; 845 u32 q_teid; 846 /* bw_t_info saves queue BW information */ 847 struct ice_bw_type_info bw_t_info; 848 }; 849 850 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 851 struct ice_sched_vsi_info { 852 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 853 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 854 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 855 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 856 /* bw_t_info saves VSI BW information */ 857 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 858 }; 859 860 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 861 struct ice_dcb_ets_cfg { 862 u8 willing; 863 u8 cbs; 864 u8 maxtcs; 865 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 866 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 867 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 868 }; 869 870 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 871 struct ice_dcb_pfc_cfg { 872 u8 willing; 873 u8 mbc; 874 u8 pfccap; 875 u8 pfcena; 876 }; 877 878 /* CEE or IEEE 802.1Qaz Application Priority data */ 879 struct ice_dcb_app_priority_table { 880 u16 prot_id; 881 u8 priority; 882 u8 selector; 883 }; 884 885 #define ICE_MAX_USER_PRIORITY 8 886 #define ICE_DCBX_MAX_APPS 64 887 #define ICE_DSCP_NUM_VAL 64 888 #define ICE_LLDPDU_SIZE 1500 889 #define ICE_TLV_STATUS_OPER 0x1 890 #define ICE_TLV_STATUS_SYNC 0x2 891 #define ICE_TLV_STATUS_ERR 0x4 892 #define ICE_APP_PROT_ID_FCOE 0x8906 893 #define ICE_APP_PROT_ID_ISCSI 0x0cbc 894 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 895 #define ICE_APP_PROT_ID_FIP 0x8914 896 #define ICE_APP_SEL_ETHTYPE 0x1 897 #define ICE_APP_SEL_TCPIP 0x2 898 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 899 #define ICE_CEE_APP_SEL_TCPIP 0x1 900 901 struct ice_dcbx_cfg { 902 u32 numapps; 903 u32 tlv_status; /* CEE mode TLV status */ 904 struct ice_dcb_ets_cfg etscfg; 905 struct ice_dcb_ets_cfg etsrec; 906 struct ice_dcb_pfc_cfg pfc; 907 #define ICE_QOS_MODE_VLAN 0x0 908 #define ICE_QOS_MODE_DSCP 0x1 909 u8 pfc_mode; 910 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 911 /* when DSCP mapping defined by user set its bit to 1 */ 912 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL); 913 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 914 u8 dscp_map[ICE_DSCP_NUM_VAL]; 915 u8 dcbx_mode; 916 #define ICE_DCBX_MODE_CEE 0x1 917 #define ICE_DCBX_MODE_IEEE 0x2 918 u8 app_mode; 919 #define ICE_DCBX_APPS_NON_WILLING 0x1 920 }; 921 922 struct ice_qos_cfg { 923 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 924 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 925 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 926 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 927 u8 is_sw_lldp : 1; 928 }; 929 930 struct ice_port_info { 931 struct ice_sched_node *root; /* Root Node per Port */ 932 struct ice_hw *hw; /* back pointer to HW instance */ 933 u32 last_node_teid; /* scheduler last node info */ 934 u16 sw_id; /* Initial switch ID belongs to port */ 935 u16 pf_vf_num; 936 u8 port_state; 937 #define ICE_SCHED_PORT_STATE_INIT 0x0 938 #define ICE_SCHED_PORT_STATE_READY 0x1 939 u8 lport; 940 #define ICE_LPORT_MASK 0xff 941 struct ice_fc_info fc; 942 struct ice_mac_info mac; 943 struct ice_phy_info phy; 944 struct ice_lock sched_lock; /* protect access to TXSched tree */ 945 struct ice_sched_node * 946 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 947 struct ice_bw_type_info root_node_bw_t_info; 948 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 949 struct ice_qos_cfg qos_cfg; 950 u8 is_vf:1; 951 u8 is_custom_tx_enabled:1; 952 }; 953 954 struct ice_switch_info { 955 struct LIST_HEAD_TYPE vsi_list_map_head; 956 struct ice_sw_recipe *recp_list; 957 u16 prof_res_bm_init; 958 u16 max_used_prof_index; 959 960 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 961 }; 962 963 /* Enum defining the different states of the mailbox snapshot in the 964 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 965 * states: 966 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 967 * within the mailbox buffer. 968 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 969 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 970 * mailbox and mark any VFs sending more messages than the threshold limit set. 971 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 972 */ 973 enum ice_mbx_snapshot_state { 974 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 975 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 976 ICE_MAL_VF_DETECT_STATE_DETECT, 977 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 978 }; 979 980 /* Structure to hold information of the static snapshot and the mailbox 981 * buffer data used to generate and track the snapshot. 982 * 1. state: the state of the mailbox snapshot in the malicious VF 983 * detection state handler ice_mbx_vf_state_handler() 984 * 2. head : head of the mailbox snapshot in a circular mailbox buffer 985 * 3. tail : tail of the mailbox snapshot in a circular mailbox buffer 986 * 4. num_iterations: number of messages traversed in circular mailbox buffer 987 * 5. num_msg_proc: number of messages processed in mailbox 988 * 6. num_pending_arq: number of pending asynchronous messages 989 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 990 * serviced work item or interrupt. 991 */ 992 struct ice_mbx_snap_buffer_data { 993 enum ice_mbx_snapshot_state state; 994 u32 head; 995 u32 tail; 996 u32 num_iterations; 997 u16 num_msg_proc; 998 u16 num_pending_arq; 999 u16 max_num_msgs_mbx; 1000 }; 1001 1002 /* Structure used to track a single VF's messages on the mailbox: 1003 * 1. list_entry: linked list entry node 1004 * 2. msg_count: the number of asynchronous messages sent by this VF 1005 * 3. malicious: whether this VF has been detected as malicious before 1006 */ 1007 struct ice_mbx_vf_info { 1008 struct LIST_ENTRY_TYPE list_entry; 1009 u32 msg_count; 1010 u8 malicious : 1; 1011 }; 1012 1013 /* Structure to hold data relevant to the captured static snapshot 1014 * of the PF-VF mailbox. 1015 */ 1016 struct ice_mbx_snapshot { 1017 struct ice_mbx_snap_buffer_data mbx_buf; 1018 struct LIST_HEAD_TYPE mbx_vf; 1019 }; 1020 1021 /* Structure to hold data to be used for capturing or updating a 1022 * static snapshot. 1023 * 1. num_msg_proc: number of messages processed in mailbox 1024 * 2. num_pending_arq: number of pending asynchronous messages 1025 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 1026 * serviced work item or interrupt. 1027 * 4. async_watermark_val: An upper threshold set by caller to determine 1028 * if the pending arq count is large enough to assume that there is 1029 * the possibility of a mailicious VF. 1030 */ 1031 struct ice_mbx_data { 1032 u16 num_msg_proc; 1033 u16 num_pending_arq; 1034 u16 max_num_msgs_mbx; 1035 u16 async_watermark_val; 1036 }; 1037 1038 /* PHY model */ 1039 enum ice_phy_model { 1040 ICE_PHY_UNSUP = -1, 1041 ICE_PHY_E810 = 1, 1042 ICE_PHY_E822, 1043 }; 1044 1045 /* Port hardware description */ 1046 struct ice_hw { 1047 u8 *hw_addr; 1048 void *back; 1049 struct ice_aqc_layer_props *layer_info; 1050 struct ice_port_info *port_info; 1051 /* 2D Array for each Tx Sched RL Profile type */ 1052 struct ice_sched_rl_profile **cir_profiles; 1053 struct ice_sched_rl_profile **eir_profiles; 1054 struct ice_sched_rl_profile **srl_profiles; 1055 /* PSM clock frequency for calculating RL profile params */ 1056 u32 psm_clk_freq; 1057 u64 debug_mask; /* BITMAP for debug mask */ 1058 enum ice_mac_type mac_type; 1059 1060 /* pci info */ 1061 u16 device_id; 1062 u16 vendor_id; 1063 u16 subsystem_device_id; 1064 u16 subsystem_vendor_id; 1065 u8 revision_id; 1066 1067 u8 pf_id; /* device profile info */ 1068 enum ice_phy_model phy_model; 1069 u8 phy_ports; 1070 u8 max_phy_port; 1071 1072 u16 max_burst_size; /* driver sets this value */ 1073 1074 /* Tx Scheduler values */ 1075 u8 num_tx_sched_layers; 1076 u8 num_tx_sched_phys_layers; 1077 u8 flattened_layers; 1078 u8 max_cgds; 1079 u8 sw_entry_point_layer; 1080 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1081 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */ 1082 /* List contain profile ID(s) and other params per layer */ 1083 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1084 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 1085 u8 evb_veb; /* true for VEB, false for VEPA */ 1086 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 1087 struct ice_bus_info bus; 1088 struct ice_flash_info flash; 1089 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 1090 struct ice_hw_func_caps func_caps; /* function capabilities */ 1091 1092 struct ice_switch_info *switch_info; /* switch filter lists */ 1093 1094 /* Control Queue info */ 1095 struct ice_ctl_q_info adminq; 1096 struct ice_ctl_q_info mailboxq; 1097 u8 api_branch; /* API branch version */ 1098 u8 api_maj_ver; /* API major version */ 1099 u8 api_min_ver; /* API minor version */ 1100 u8 api_patch; /* API patch version */ 1101 u8 fw_branch; /* firmware branch version */ 1102 u8 fw_maj_ver; /* firmware major version */ 1103 u8 fw_min_ver; /* firmware minor version */ 1104 u8 fw_patch; /* firmware patch version */ 1105 u32 fw_build; /* firmware build number */ 1106 1107 struct ice_fwlog_cfg fwlog_cfg; 1108 bool fwlog_support_ena; /* does hardware support FW logging? */ 1109 1110 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 1111 * register. Used for determining the ITR/INTRL granularity during 1112 * initialization. 1113 */ 1114 #define ICE_MAX_AGG_BW_200G 0x0 1115 #define ICE_MAX_AGG_BW_100G 0X1 1116 #define ICE_MAX_AGG_BW_50G 0x2 1117 #define ICE_MAX_AGG_BW_25G 0x3 1118 /* ITR granularity for different speeds */ 1119 #define ICE_ITR_GRAN_ABOVE_25 2 1120 #define ICE_ITR_GRAN_MAX_25 4 1121 /* ITR granularity in 1 us */ 1122 u8 itr_gran; 1123 /* INTRL granularity for different speeds */ 1124 #define ICE_INTRL_GRAN_ABOVE_25 4 1125 #define ICE_INTRL_GRAN_MAX_25 8 1126 /* INTRL granularity in 1 us */ 1127 u8 intrl_gran; 1128 1129 /* true if VSIs can share unicast MAC addr */ 1130 u8 umac_shared; 1131 1132 #define ICE_PHY_PER_NAC_E822 1 1133 #define ICE_MAX_QUAD 2 1134 #define ICE_QUADS_PER_PHY_E822 2 1135 #define ICE_PORTS_PER_PHY_E822 8 1136 #define ICE_PORTS_PER_QUAD 4 1137 #define ICE_PORTS_PER_PHY_E810 4 1138 #define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD) 1139 1140 /* Active package version (currently active) */ 1141 struct ice_pkg_ver active_pkg_ver; 1142 u32 pkg_seg_id; 1143 u32 pkg_sign_type; 1144 u32 active_track_id; 1145 u8 pkg_has_signing_seg:1; 1146 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 1147 u8 active_pkg_in_nvm; 1148 1149 /* Driver's package ver - (from the Ice Metadata section) */ 1150 struct ice_pkg_ver pkg_ver; 1151 u8 pkg_name[ICE_PKG_NAME_SIZE]; 1152 1153 /* Driver's Ice segment format version and id (from the Ice seg) */ 1154 struct ice_pkg_ver ice_seg_fmt_ver; 1155 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 1156 1157 /* Pointer to the ice segment */ 1158 struct ice_seg *seg; 1159 1160 /* Pointer to allocated copy of pkg memory */ 1161 u8 *pkg_copy; 1162 u32 pkg_size; 1163 1164 /* tunneling info */ 1165 struct ice_lock tnl_lock; 1166 struct ice_tunnel_table tnl; 1167 1168 /* HW block tables */ 1169 struct ice_blk_info blk[ICE_BLK_COUNT]; 1170 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 1171 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT]; 1172 struct ice_lock rss_locks; /* protect RSS configuration */ 1173 struct LIST_HEAD_TYPE rss_list_head; 1174 struct ice_mbx_snapshot mbx_snapshot; 1175 u8 dvm_ena; 1176 }; 1177 1178 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1179 struct ice_eth_stats { 1180 u64 rx_bytes; /* gorc */ 1181 u64 rx_unicast; /* uprc */ 1182 u64 rx_multicast; /* mprc */ 1183 u64 rx_broadcast; /* bprc */ 1184 u64 rx_discards; /* rdpc */ 1185 u64 rx_unknown_protocol; /* rupp */ 1186 u64 tx_bytes; /* gotc */ 1187 u64 tx_unicast; /* uptc */ 1188 u64 tx_multicast; /* mptc */ 1189 u64 tx_broadcast; /* bptc */ 1190 u64 tx_discards; /* tdpc */ 1191 u64 tx_errors; /* tepc */ 1192 u64 rx_no_desc; /* repc */ 1193 u64 rx_errors; /* repc */ 1194 }; 1195 1196 #define ICE_MAX_UP 8 1197 1198 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */ 1199 struct ice_veb_up_stats { 1200 u64 up_rx_pkts[ICE_MAX_UP]; 1201 u64 up_rx_bytes[ICE_MAX_UP]; 1202 u64 up_tx_pkts[ICE_MAX_UP]; 1203 u64 up_tx_bytes[ICE_MAX_UP]; 1204 }; 1205 1206 /* Statistics collected by the MAC */ 1207 struct ice_hw_port_stats { 1208 /* eth stats collected by the port */ 1209 struct ice_eth_stats eth; 1210 /* additional port specific stats */ 1211 u64 tx_dropped_link_down; /* tdold */ 1212 u64 crc_errors; /* crcerrs */ 1213 u64 illegal_bytes; /* illerrc */ 1214 u64 error_bytes; /* errbc */ 1215 u64 mac_local_faults; /* mlfc */ 1216 u64 mac_remote_faults; /* mrfc */ 1217 u64 rx_len_errors; /* rlec */ 1218 u64 link_xon_rx; /* lxonrxc */ 1219 u64 link_xoff_rx; /* lxoffrxc */ 1220 u64 link_xon_tx; /* lxontxc */ 1221 u64 link_xoff_tx; /* lxofftxc */ 1222 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1223 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1224 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1225 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1226 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1227 u64 rx_size_64; /* prc64 */ 1228 u64 rx_size_127; /* prc127 */ 1229 u64 rx_size_255; /* prc255 */ 1230 u64 rx_size_511; /* prc511 */ 1231 u64 rx_size_1023; /* prc1023 */ 1232 u64 rx_size_1522; /* prc1522 */ 1233 u64 rx_size_big; /* prc9522 */ 1234 u64 rx_undersize; /* ruc */ 1235 u64 rx_fragments; /* rfc */ 1236 u64 rx_oversize; /* roc */ 1237 u64 rx_jabber; /* rjc */ 1238 u64 tx_size_64; /* ptc64 */ 1239 u64 tx_size_127; /* ptc127 */ 1240 u64 tx_size_255; /* ptc255 */ 1241 u64 tx_size_511; /* ptc511 */ 1242 u64 tx_size_1023; /* ptc1023 */ 1243 u64 tx_size_1522; /* ptc1522 */ 1244 u64 tx_size_big; /* ptc9522 */ 1245 u64 mac_short_pkt_dropped; /* mspdc */ 1246 /* EEE LPI */ 1247 u32 tx_lpi_status; 1248 u32 rx_lpi_status; 1249 u64 tx_lpi_count; /* etlpic */ 1250 u64 rx_lpi_count; /* erlpic */ 1251 }; 1252 1253 enum ice_sw_fwd_act_type { 1254 ICE_FWD_TO_VSI = 0, 1255 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 1256 ICE_FWD_TO_Q, 1257 ICE_FWD_TO_QGRP, 1258 ICE_DROP_PACKET, 1259 ICE_LG_ACTION, 1260 ICE_INVAL_ACT 1261 }; 1262 1263 struct ice_aq_get_set_rss_lut_params { 1264 u16 vsi_handle; /* software VSI handle */ 1265 u16 lut_size; /* size of the LUT buffer */ 1266 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1267 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1268 u8 global_lut_id; /* only valid when lut_type is global */ 1269 }; 1270 1271 /* Checksum and Shadow RAM pointers */ 1272 #define ICE_SR_NVM_CTRL_WORD 0x00 1273 #define ICE_SR_PHY_ANALOG_PTR 0x04 1274 #define ICE_SR_OPTION_ROM_PTR 0x05 1275 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1276 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1277 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1278 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09 1279 #define ICE_SR_EMP_IMAGE_PTR 0x0B 1280 #define ICE_SR_PE_IMAGE_PTR 0x0C 1281 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D 1282 #define ICE_SR_MNG_CFG_PTR 0x0E 1283 #define ICE_SR_EMP_MODULE_PTR 0x0F 1284 #define ICE_SR_PBA_BLOCK_PTR 0x16 1285 #define ICE_SR_BOOT_CFG_PTR 0x132 1286 #define ICE_SR_NVM_WOL_CFG 0x19 1287 #define ICE_NVM_OROM_VER_OFF 0x02 1288 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1289 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27 1290 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28 1291 #define ICE_SR_NVM_MAP_VER 0x29 1292 #define ICE_SR_NVM_IMAGE_VER 0x2A 1293 #define ICE_SR_NVM_STRUCTURE_VER 0x2B 1294 #define ICE_SR_NVM_EETRACK_LO 0x2D 1295 #define ICE_SR_NVM_EETRACK_HI 0x2E 1296 #define ICE_NVM_VER_LO_SHIFT 0 1297 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1298 #define ICE_NVM_VER_HI_SHIFT 12 1299 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1300 #define ICE_OEM_EETRACK_ID 0xffffffff 1301 #define ICE_OROM_VER_PATCH_SHIFT 0 1302 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1303 #define ICE_OROM_VER_BUILD_SHIFT 8 1304 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1305 #define ICE_OROM_VER_SHIFT 24 1306 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1307 #define ICE_SR_VPD_PTR 0x2F 1308 #define ICE_SR_PXE_SETUP_PTR 0x30 1309 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31 1310 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1311 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1312 #define ICE_SR_VLAN_CFG_PTR 0x37 1313 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1314 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1315 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1316 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1317 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D 1318 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1319 #define ICE_SR_SW_CHECKSUM_WORD 0x3F 1320 #define ICE_SR_PFA_PTR 0x40 1321 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41 1322 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1323 #define ICE_SR_NVM_BANK_SIZE 0x43 1324 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 1325 #define ICE_SR_OROM_BANK_SIZE 0x45 1326 #define ICE_SR_NETLIST_BANK_PTR 0x46 1327 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1328 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48 1329 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D 1330 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E 1331 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 1332 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118 1333 1334 /* CSS Header words */ 1335 #define ICE_NVM_CSS_HDR_LEN_L 0x02 1336 #define ICE_NVM_CSS_HDR_LEN_H 0x03 1337 #define ICE_NVM_CSS_SREV_L 0x14 1338 #define ICE_NVM_CSS_SREV_H 0x15 1339 1340 /* Length of Authentication header section in words */ 1341 #define ICE_NVM_AUTH_HEADER_LEN 0x08 1342 1343 /* The Link Topology Netlist section is stored as a series of words. It is 1344 * stored in the NVM as a TLV, with the first two words containing the type 1345 * and length. 1346 */ 1347 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1348 #define ICE_NETLIST_TYPE_OFFSET 0x0000 1349 #define ICE_NETLIST_LEN_OFFSET 0x0001 1350 1351 /* The Link Topology section follows the TLV header. When reading the netlist 1352 * using ice_read_netlist_module, we need to account for the 2-word TLV 1353 * header. 1354 */ 1355 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1356 1357 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1358 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1359 1360 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0) 1361 1362 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1363 #define ICE_NETLIST_ID_BLK_SIZE 0x30 1364 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1365 1366 /* netlist ID block field offsets (word offsets) */ 1367 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1368 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1369 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1370 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1371 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1372 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1373 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1374 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1375 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1376 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1377 1378 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1379 #define ICE_SR_VPD_SIZE_WORDS 512 1380 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512 1381 #define ICE_SR_CTRL_WORD_1_S 0x06 1382 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1383 #define ICE_SR_CTRL_WORD_VALID 0x1 1384 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1385 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1386 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1387 1388 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1389 1390 /* Shadow RAM related */ 1391 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1392 #define ICE_SR_BUF_ALIGNMENT 4096 1393 #define ICE_SR_WORDS_IN_1KB 512 1394 /* Checksum should be calculated such that after adding all the words, 1395 * including the checksum word itself, the sum should be 0xBABA. 1396 */ 1397 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA 1398 1399 /* Link override related */ 1400 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1401 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1402 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1403 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1404 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1405 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1406 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1407 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1408 1409 #define ICE_PBA_FLAG_DFLT 0xFAFA 1410 /* Hash redirection LUT for VSI - maximum array size */ 1411 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1412 1413 /* 1414 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register. 1415 * This is needed to determine the BAR0 space for the VFs 1416 */ 1417 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0 1418 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1 1419 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2 1420 1421 /* AQ API version for LLDP_FILTER_CONTROL */ 1422 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1423 #define ICE_FW_API_LLDP_FLTR_MIN 7 1424 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1425 1426 /* AQ API version for report default configuration */ 1427 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1428 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1429 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1430 1431 /* FW version for FEC disable in Auto FEC mode */ 1432 #define ICE_FW_FEC_DIS_AUTO_BRANCH 1 1433 #define ICE_FW_FEC_DIS_AUTO_MAJ 7 1434 #define ICE_FW_FEC_DIS_AUTO_MIN 0 1435 #define ICE_FW_FEC_DIS_AUTO_PATCH 5 1436 1437 /* AQ API version for FW health reports */ 1438 #define ICE_FW_API_HEALTH_REPORT_MAJ 1 1439 #define ICE_FW_API_HEALTH_REPORT_MIN 7 1440 #define ICE_FW_API_HEALTH_REPORT_PATCH 6 1441 1442 /* AQ API version for FW auto drop reports */ 1443 #define ICE_FW_API_AUTO_DROP_MAJ 1 1444 #define ICE_FW_API_AUTO_DROP_MIN 4 1445 1446 #endif /* _ICE_TYPE_H_ */ 1447