1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2020, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_TYPE_H_ 34 #define _ICE_TYPE_H_ 35 36 #define ETH_ALEN 6 37 38 #define ETH_HEADER_LEN 14 39 40 #define BIT(a) (1UL << (a)) 41 #ifndef BIT_ULL 42 #define BIT_ULL(a) (1ULL << (a)) 43 #endif /* BIT_ULL */ 44 45 #define BITS_PER_BYTE 8 46 47 #define _FORCE_ 48 49 #define ICE_BYTES_PER_WORD 2 50 #define ICE_BYTES_PER_DWORD 4 51 #define ICE_MAX_TRAFFIC_CLASS 8 52 53 #ifndef MIN_T 54 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b)) 55 #endif 56 57 #define IS_ASCII(_ch) ((_ch) < 0x80) 58 59 #define ice_struct_size(ptr, field, num) \ 60 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num)) 61 62 #include "ice_status.h" 63 #include "ice_hw_autogen.h" 64 #include "ice_devids.h" 65 #include "ice_osdep.h" 66 #include "ice_bitops.h" /* Must come before ice_controlq.h */ 67 #include "ice_controlq.h" 68 #include "ice_lan_tx_rx.h" 69 #include "ice_flex_type.h" 70 #include "ice_protocol_type.h" 71 72 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc) 73 { 74 return !!(bitmap & BIT(tc)); 75 } 76 77 #define DIV_64BIT(n, d) ((n) / (d)) 78 79 static inline u64 round_up_64bit(u64 a, u32 b) 80 { 81 return DIV_64BIT(((a) + (b) / 2), (b)); 82 } 83 84 static inline u32 ice_round_to_num(u32 N, u32 R) 85 { 86 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 87 ((((N) + (R) - 1) / (R)) * (R))); 88 } 89 90 /* Driver always calls main vsi_handle first */ 91 #define ICE_MAIN_VSI_HANDLE 0 92 93 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 94 #define ICE_MS_TO_GTIME(time) ((time) * 1000) 95 96 /* Data type manipulation macros. */ 97 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 98 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 99 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 100 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF)) 101 102 /* debug masks - set these bits in hw->debug_mask to control output */ 103 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */ 104 #define ICE_DBG_INIT BIT_ULL(1) 105 #define ICE_DBG_RELEASE BIT_ULL(2) 106 #define ICE_DBG_FW_LOG BIT_ULL(3) 107 #define ICE_DBG_LINK BIT_ULL(4) 108 #define ICE_DBG_PHY BIT_ULL(5) 109 #define ICE_DBG_QCTX BIT_ULL(6) 110 #define ICE_DBG_NVM BIT_ULL(7) 111 #define ICE_DBG_LAN BIT_ULL(8) 112 #define ICE_DBG_FLOW BIT_ULL(9) 113 #define ICE_DBG_DCB BIT_ULL(10) 114 #define ICE_DBG_DIAG BIT_ULL(11) 115 #define ICE_DBG_FD BIT_ULL(12) 116 #define ICE_DBG_SW BIT_ULL(13) 117 #define ICE_DBG_SCHED BIT_ULL(14) 118 119 #define ICE_DBG_PKG BIT_ULL(16) 120 #define ICE_DBG_RES BIT_ULL(17) 121 #define ICE_DBG_AQ_MSG BIT_ULL(24) 122 #define ICE_DBG_AQ_DESC BIT_ULL(25) 123 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 124 #define ICE_DBG_AQ_CMD BIT_ULL(27) 125 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 126 ICE_DBG_AQ_DESC | \ 127 ICE_DBG_AQ_DESC_BUF | \ 128 ICE_DBG_AQ_CMD) 129 130 #define ICE_DBG_USER BIT_ULL(31) 131 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL 132 133 #define IS_UNICAST_ETHER_ADDR(addr) \ 134 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0)) 135 136 #define IS_MULTICAST_ETHER_ADDR(addr) \ 137 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1)) 138 139 /* Check whether an address is broadcast. */ 140 #define IS_BROADCAST_ETHER_ADDR(addr) \ 141 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff)))) 142 143 #define IS_ZERO_ETHER_ADDR(addr) \ 144 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \ 145 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \ 146 ((bool)((((u16 *)(addr))[2] == ((u16)0x0))))) 147 148 #ifndef IS_ETHER_ADDR_EQUAL 149 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \ 150 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \ 151 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \ 152 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2])))) 153 #endif 154 155 enum ice_aq_res_ids { 156 ICE_NVM_RES_ID = 1, 157 ICE_SPD_RES_ID, 158 ICE_CHANGE_LOCK_RES_ID, 159 ICE_GLOBAL_CFG_LOCK_RES_ID 160 }; 161 162 /* FW update timeout definitions are in milliseconds */ 163 #define ICE_NVM_TIMEOUT 180000 164 #define ICE_CHANGE_LOCK_TIMEOUT 1000 165 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 166 167 enum ice_aq_res_access_type { 168 ICE_RES_READ = 1, 169 ICE_RES_WRITE 170 }; 171 172 struct ice_driver_ver { 173 u8 major_ver; 174 u8 minor_ver; 175 u8 build_ver; 176 u8 subbuild_ver; 177 u8 driver_string[32]; 178 }; 179 180 enum ice_fc_mode { 181 ICE_FC_NONE = 0, 182 ICE_FC_RX_PAUSE, 183 ICE_FC_TX_PAUSE, 184 ICE_FC_FULL, 185 ICE_FC_AUTO, 186 ICE_FC_PFC, 187 ICE_FC_DFLT 188 }; 189 190 enum ice_phy_cache_mode { 191 ICE_FC_MODE = 0, 192 ICE_SPEED_MODE, 193 ICE_FEC_MODE 194 }; 195 196 enum ice_fec_mode { 197 ICE_FEC_NONE = 0, 198 ICE_FEC_RS, 199 ICE_FEC_BASER, 200 ICE_FEC_AUTO 201 }; 202 203 struct ice_phy_cache_mode_data { 204 union { 205 enum ice_fec_mode curr_user_fec_req; 206 enum ice_fc_mode curr_user_fc_req; 207 u16 curr_user_speed_req; 208 } data; 209 }; 210 211 enum ice_set_fc_aq_failures { 212 ICE_SET_FC_AQ_FAIL_NONE = 0, 213 ICE_SET_FC_AQ_FAIL_GET, 214 ICE_SET_FC_AQ_FAIL_SET, 215 ICE_SET_FC_AQ_FAIL_UPDATE 216 }; 217 218 /* These are structs for managing the hardware information and the operations */ 219 /* MAC types */ 220 enum ice_mac_type { 221 ICE_MAC_UNKNOWN = 0, 222 ICE_MAC_VF, 223 ICE_MAC_E810, 224 ICE_MAC_GENERIC, 225 }; 226 227 /* Media Types */ 228 enum ice_media_type { 229 ICE_MEDIA_UNKNOWN = 0, 230 ICE_MEDIA_FIBER, 231 ICE_MEDIA_BASET, 232 ICE_MEDIA_BACKPLANE, 233 ICE_MEDIA_DA, 234 }; 235 236 /* Software VSI types. */ 237 enum ice_vsi_type { 238 ICE_VSI_PF = 0, 239 ICE_VSI_VF = 1, 240 ICE_VSI_LB = 6, 241 }; 242 243 struct ice_link_status { 244 /* Refer to ice_aq_phy_type for bits definition */ 245 u64 phy_type_low; 246 u64 phy_type_high; 247 u8 topo_media_conflict; 248 u16 max_frame_size; 249 u16 link_speed; 250 u16 req_speeds; 251 u8 lse_ena; /* Link Status Event notification */ 252 u8 link_info; 253 u8 an_info; 254 u8 ext_info; 255 u8 fec_info; 256 u8 pacing; 257 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 258 * ice_aqc_get_phy_caps structure 259 */ 260 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 261 }; 262 263 /* Different data queue types: These are mainly for SW consumption. */ 264 enum ice_q { 265 ICE_DATA_Q_DOORBELL, 266 ICE_DATA_Q_CMPL, 267 ICE_DATA_Q_QUANTA, 268 ICE_DATA_Q_RX, 269 ICE_DATA_Q_TX, 270 }; 271 272 /* Different reset sources for which a disable queue AQ call has to be made in 273 * order to clean the Tx scheduler as a part of the reset 274 */ 275 enum ice_disq_rst_src { 276 ICE_NO_RESET = 0, 277 ICE_VM_RESET, 278 ICE_VF_RESET, 279 }; 280 281 /* PHY info such as phy_type, etc... */ 282 struct ice_phy_info { 283 struct ice_link_status link_info; 284 struct ice_link_status link_info_old; 285 u64 phy_type_low; 286 u64 phy_type_high; 287 enum ice_media_type media_type; 288 u8 get_link_info; 289 /* Please refer to struct ice_aqc_get_link_status_data to get 290 * detail of enable bit in curr_user_speed_req 291 */ 292 u16 curr_user_speed_req; 293 enum ice_fec_mode curr_user_fec_req; 294 enum ice_fc_mode curr_user_fc_req; 295 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 296 }; 297 298 #define ICE_MAX_NUM_MIRROR_RULES 64 299 300 /* Common HW capabilities for SW use */ 301 struct ice_hw_common_caps { 302 /* Write CSR protection */ 303 u64 wr_csr_prot; 304 u32 switching_mode; 305 /* switching mode supported - EVB switching (including cloud) */ 306 #define ICE_NVM_IMAGE_TYPE_EVB 0x0 307 308 /* Manageablity mode & supported protocols over MCTP */ 309 u32 mgmt_mode; 310 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF 311 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0 312 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00 313 314 u32 mgmt_protocols_mctp; 315 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0) 316 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1) 317 #define ICE_MGMT_MODE_PROTO_OEM BIT(2) 318 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3) 319 320 u32 os2bmc; 321 u32 valid_functions; 322 /* DCB capabilities */ 323 u32 active_tc_bitmap; 324 u32 maxtc; 325 326 /* RSS related capabilities */ 327 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 328 u32 rss_table_entry_width; /* RSS Entry width in bits */ 329 330 /* Tx/Rx queues */ 331 u32 num_rxq; /* Number/Total Rx queues */ 332 u32 rxq_first_id; /* First queue ID for Rx queues */ 333 u32 num_txq; /* Number/Total Tx queues */ 334 u32 txq_first_id; /* First queue ID for Tx queues */ 335 336 /* MSI-X vectors */ 337 u32 num_msix_vectors; 338 u32 msix_vector_first_id; 339 340 /* Max MTU for function or device */ 341 u32 max_mtu; 342 343 /* WOL related */ 344 u32 num_wol_proxy_fltr; 345 u32 wol_proxy_vsi_seid; 346 347 /* LED/SDP pin count */ 348 u32 led_pin_num; 349 u32 sdp_pin_num; 350 351 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 352 #define ICE_MAX_SUPPORTED_GPIO_LED 12 353 #define ICE_MAX_SUPPORTED_GPIO_SDP 8 354 u8 led[ICE_MAX_SUPPORTED_GPIO_LED]; 355 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP]; 356 357 /* SR-IOV virtualization */ 358 u8 sr_iov_1_1; /* SR-IOV enabled */ 359 360 /* EVB capabilities */ 361 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 362 u8 evb_802_1_qbh; /* Bridge Port Extension */ 363 364 u8 dcb; 365 u8 iscsi; 366 u8 mgmt_cem; 367 368 /* WoL and APM support */ 369 #define ICE_WOL_SUPPORT_M BIT(0) 370 #define ICE_ACPI_PROG_MTHD_M BIT(1) 371 #define ICE_PROXY_SUPPORT_M BIT(2) 372 u8 apm_wol_support; 373 u8 acpi_prog_mthd; 374 u8 proxy_support; 375 bool nvm_unified_update; 376 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 377 }; 378 379 /* Function specific capabilities */ 380 struct ice_hw_func_caps { 381 struct ice_hw_common_caps common_cap; 382 u32 num_allocd_vfs; /* Number of allocated VFs */ 383 u32 vf_base_id; /* Logical ID of the first VF */ 384 u32 guar_num_vsi; 385 }; 386 387 /* Device wide capabilities */ 388 struct ice_hw_dev_caps { 389 struct ice_hw_common_caps common_cap; 390 u32 num_vfs_exposed; /* Total number of VFs exposed */ 391 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 392 u32 num_funcs; 393 }; 394 395 /* Information about MAC such as address, etc... */ 396 struct ice_mac_info { 397 u8 lan_addr[ETH_ALEN]; 398 u8 perm_addr[ETH_ALEN]; 399 u8 port_addr[ETH_ALEN]; 400 u8 wol_addr[ETH_ALEN]; 401 }; 402 403 /* PCI bus types */ 404 enum ice_bus_type { 405 ice_bus_unknown = 0, 406 ice_bus_pci_express, 407 ice_bus_embedded, /* Is device Embedded versus card */ 408 ice_bus_reserved 409 }; 410 411 /* PCI bus speeds */ 412 enum ice_pcie_bus_speed { 413 ice_pcie_speed_unknown = 0xff, 414 ice_pcie_speed_2_5GT = 0x14, 415 ice_pcie_speed_5_0GT = 0x15, 416 ice_pcie_speed_8_0GT = 0x16, 417 ice_pcie_speed_16_0GT = 0x17 418 }; 419 420 /* PCI bus widths */ 421 enum ice_pcie_link_width { 422 ice_pcie_lnk_width_resrv = 0x00, 423 ice_pcie_lnk_x1 = 0x01, 424 ice_pcie_lnk_x2 = 0x02, 425 ice_pcie_lnk_x4 = 0x04, 426 ice_pcie_lnk_x8 = 0x08, 427 ice_pcie_lnk_x12 = 0x0C, 428 ice_pcie_lnk_x16 = 0x10, 429 ice_pcie_lnk_x32 = 0x20, 430 ice_pcie_lnk_width_unknown = 0xff, 431 }; 432 433 /* Reset types used to determine which kind of reset was requested. These 434 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 435 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 436 * because its reset source is different than the other types listed. 437 */ 438 enum ice_reset_req { 439 ICE_RESET_POR = 0, 440 ICE_RESET_INVAL = 0, 441 ICE_RESET_CORER = 1, 442 ICE_RESET_GLOBR = 2, 443 ICE_RESET_EMPR = 3, 444 ICE_RESET_PFR = 4, 445 }; 446 447 /* Bus parameters */ 448 struct ice_bus_info { 449 enum ice_pcie_bus_speed speed; 450 enum ice_pcie_link_width width; 451 enum ice_bus_type type; 452 u16 domain_num; 453 u16 device; 454 u8 func; 455 u8 bus_num; 456 }; 457 458 /* Flow control (FC) parameters */ 459 struct ice_fc_info { 460 enum ice_fc_mode current_mode; /* FC mode in effect */ 461 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 462 }; 463 464 /* Option ROM version information */ 465 struct ice_orom_info { 466 u8 major; /* Major version of OROM */ 467 u8 patch; /* Patch version of OROM */ 468 u16 build; /* Build version of OROM */ 469 }; 470 471 /* NVM Information */ 472 struct ice_nvm_info { 473 struct ice_orom_info orom; /* Option ROM version info */ 474 u32 eetrack; /* NVM data version */ 475 u16 sr_words; /* Shadow RAM size in words */ 476 u32 flash_size; /* Size of available flash in bytes */ 477 u8 major_ver; /* major version of dev starter */ 478 u8 minor_ver; /* minor version of dev starter */ 479 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/ 480 }; 481 482 struct ice_link_default_override_tlv { 483 u8 options; 484 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 485 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 486 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 487 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 488 #define ICE_LINK_OVERRIDE_EN BIT(3) 489 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 490 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 491 u8 phy_config; 492 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 493 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 494 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 495 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 496 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 497 u8 fec_options; 498 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 499 u8 rsvd1; 500 u64 phy_type_low; 501 u64 phy_type_high; 502 }; 503 504 #define ICE_NVM_VER_LEN 32 505 506 /* netlist version information */ 507 struct ice_netlist_ver_info { 508 u32 major; /* major high/low */ 509 u32 minor; /* minor high/low */ 510 u32 type; /* type high/low */ 511 u32 rev; /* revision high/low */ 512 u32 hash; /* SHA-1 hash word */ 513 u16 cust_ver; /* customer version */ 514 }; 515 516 /* Max number of port to queue branches w.r.t topology */ 517 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 518 519 #define ice_for_each_traffic_class(_i) \ 520 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 521 522 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 523 * to driver defined policy for default aggregator 524 */ 525 #define ICE_INVAL_TEID 0xFFFFFFFF 526 #define ICE_DFLT_AGG_ID 0 527 528 struct ice_sched_node { 529 struct ice_sched_node *parent; 530 struct ice_sched_node *sibling; /* next sibling in the same layer */ 531 struct ice_sched_node **children; 532 struct ice_aqc_txsched_elem_data info; 533 u32 agg_id; /* aggregator group ID */ 534 u16 vsi_handle; 535 u8 in_use; /* suspended or in use */ 536 u8 tx_sched_layer; /* Logical Layer (1-9) */ 537 u8 num_children; 538 u8 tc_num; 539 u8 owner; 540 #define ICE_SCHED_NODE_OWNER_LAN 0 541 #define ICE_SCHED_NODE_OWNER_AE 1 542 #define ICE_SCHED_NODE_OWNER_RDMA 2 543 }; 544 545 /* Access Macros for Tx Sched Elements data */ 546 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid) 547 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid) 548 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \ 549 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx) 550 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \ 551 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx) 552 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id) 553 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \ 554 LE16_TO_CPU((x)->info.cir_bw.bw_alloc) 555 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \ 556 LE16_TO_CPU((x)->info.eir_bw.bw_alloc) 557 558 struct ice_sched_rl_profile { 559 u32 rate; /* In Kbps */ 560 struct ice_aqc_rl_profile_elem info; 561 }; 562 563 /* The aggregator type determines if identifier is for a VSI group, 564 * aggregator group, aggregator of queues, or queue group. 565 */ 566 enum ice_agg_type { 567 ICE_AGG_TYPE_UNKNOWN = 0, 568 ICE_AGG_TYPE_TC, 569 ICE_AGG_TYPE_AGG, /* aggregator */ 570 ICE_AGG_TYPE_VSI, 571 ICE_AGG_TYPE_QG, 572 ICE_AGG_TYPE_Q 573 }; 574 575 /* Rate limit types */ 576 enum ice_rl_type { 577 ICE_UNKNOWN_BW = 0, 578 ICE_MIN_BW, /* for CIR profile */ 579 ICE_MAX_BW, /* for EIR profile */ 580 ICE_SHARED_BW /* for shared profile */ 581 }; 582 583 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 584 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 585 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 586 #define ICE_SCHED_NO_PRIORITY 0 587 #define ICE_SCHED_NO_BW_WT 0 588 #define ICE_SCHED_DFLT_RL_PROF_ID 0 589 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 590 #define ICE_SCHED_DFLT_BW_WT 1 591 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 592 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 593 594 /* Access Macros for Tx Sched RL Profile data */ 595 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id) 596 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size) 597 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply) 598 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc) 599 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode) 600 601 /* The following tree example shows the naming conventions followed under 602 * ice_port_info struct for default scheduler tree topology. 603 * 604 * A tree on a port 605 * * ---> root node 606 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8) 607 * * * * * * * * * | 608 * / | 609 * * | 610 * / |-> num_elements (range:1 - 9) 611 * * | implies num_of_layers 612 * / | 613 * (a)* | 614 * 615 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under 616 * (a) as child node where queues get added, add Tx/Rx queue admin commands; 617 * need TEID of (a) to add queues. 618 * 619 * This tree 620 * -> has 8 branches (one for each TC) 621 * -> First branch (TC0) has 4 elements 622 * -> has 4 layers 623 * -> (a) is the topmost layer node created by firmware on branch 0 624 * 625 * Note: Above asterisk tree covers only basic terminology and scenario. 626 * Refer to the documentation for more info. 627 */ 628 629 /* Data structure for saving BW information */ 630 enum ice_bw_type { 631 ICE_BW_TYPE_PRIO, 632 ICE_BW_TYPE_CIR, 633 ICE_BW_TYPE_CIR_WT, 634 ICE_BW_TYPE_EIR, 635 ICE_BW_TYPE_EIR_WT, 636 ICE_BW_TYPE_SHARED, 637 ICE_BW_TYPE_CNT /* This must be last */ 638 }; 639 640 struct ice_bw { 641 u32 bw; 642 u16 bw_alloc; 643 }; 644 645 struct ice_bw_type_info { 646 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT); 647 u8 generic; 648 struct ice_bw cir_bw; 649 struct ice_bw eir_bw; 650 u32 shared_bw; 651 }; 652 653 /* VSI queue context structure for given TC */ 654 struct ice_q_ctx { 655 u16 q_handle; 656 u32 q_teid; 657 /* bw_t_info saves queue BW information */ 658 struct ice_bw_type_info bw_t_info; 659 }; 660 661 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 662 struct ice_sched_vsi_info { 663 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 664 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 665 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 666 /* bw_t_info saves VSI BW information */ 667 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 668 }; 669 670 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 671 struct ice_dcb_ets_cfg { 672 u8 willing; 673 u8 cbs; 674 u8 maxtcs; 675 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 676 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 677 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 678 }; 679 680 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 681 struct ice_dcb_pfc_cfg { 682 u8 willing; 683 u8 mbc; 684 u8 pfccap; 685 u8 pfcena; 686 }; 687 688 /* CEE or IEEE 802.1Qaz Application Priority data */ 689 struct ice_dcb_app_priority_table { 690 u16 prot_id; 691 u8 priority; 692 u8 selector; 693 }; 694 695 #define ICE_MAX_USER_PRIORITY 8 696 #define ICE_DCBX_MAX_APPS 32 697 #define ICE_LLDPDU_SIZE 1500 698 #define ICE_TLV_STATUS_OPER 0x1 699 #define ICE_TLV_STATUS_SYNC 0x2 700 #define ICE_TLV_STATUS_ERR 0x4 701 #define ICE_APP_PROT_ID_FCOE 0x8906 702 #define ICE_APP_PROT_ID_ISCSI 0x0cbc 703 #define ICE_APP_PROT_ID_FIP 0x8914 704 #define ICE_APP_SEL_ETHTYPE 0x1 705 #define ICE_APP_SEL_TCPIP 0x2 706 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 707 #define ICE_CEE_APP_SEL_TCPIP 0x1 708 709 struct ice_dcbx_cfg { 710 u32 numapps; 711 u32 tlv_status; /* CEE mode TLV status */ 712 struct ice_dcb_ets_cfg etscfg; 713 struct ice_dcb_ets_cfg etsrec; 714 struct ice_dcb_pfc_cfg pfc; 715 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 716 u8 dcbx_mode; 717 #define ICE_DCBX_MODE_CEE 0x1 718 #define ICE_DCBX_MODE_IEEE 0x2 719 u8 app_mode; 720 #define ICE_DCBX_APPS_NON_WILLING 0x1 721 }; 722 723 struct ice_port_info { 724 struct ice_sched_node *root; /* Root Node per Port */ 725 struct ice_hw *hw; /* back pointer to HW instance */ 726 u32 last_node_teid; /* scheduler last node info */ 727 u16 sw_id; /* Initial switch ID belongs to port */ 728 u16 pf_vf_num; 729 u8 port_state; 730 #define ICE_SCHED_PORT_STATE_INIT 0x0 731 #define ICE_SCHED_PORT_STATE_READY 0x1 732 u8 lport; 733 #define ICE_LPORT_MASK 0xff 734 u16 dflt_tx_vsi_rule_id; 735 u16 dflt_tx_vsi_num; 736 u16 dflt_rx_vsi_rule_id; 737 u16 dflt_rx_vsi_num; 738 struct ice_fc_info fc; 739 struct ice_mac_info mac; 740 struct ice_phy_info phy; 741 struct ice_lock sched_lock; /* protect access to TXSched tree */ 742 struct ice_sched_node * 743 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 744 /* List contain profile ID(s) and other params per layer */ 745 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 746 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 747 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 748 /* DCBX info */ 749 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 750 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 751 /* LLDP/DCBX Status */ 752 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */ 753 u8 is_sw_lldp:1; 754 u8 is_vf:1; 755 }; 756 757 struct ice_switch_info { 758 struct LIST_HEAD_TYPE vsi_list_map_head; 759 struct ice_sw_recipe *recp_list; 760 u16 prof_res_bm_init; 761 762 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 763 }; 764 765 /* Port hardware description */ 766 struct ice_hw { 767 u8 *hw_addr; 768 void *back; 769 struct ice_aqc_layer_props *layer_info; 770 struct ice_port_info *port_info; 771 /* 2D Array for each Tx Sched RL Profile type */ 772 struct ice_sched_rl_profile **cir_profiles; 773 struct ice_sched_rl_profile **eir_profiles; 774 struct ice_sched_rl_profile **srl_profiles; 775 /* PSM clock frequency for calculating RL profile params */ 776 u32 psm_clk_freq; 777 u64 debug_mask; /* BITMAP for debug mask */ 778 enum ice_mac_type mac_type; 779 780 /* pci info */ 781 u16 device_id; 782 u16 vendor_id; 783 u16 subsystem_device_id; 784 u16 subsystem_vendor_id; 785 u8 revision_id; 786 787 u8 pf_id; /* device profile info */ 788 789 u16 max_burst_size; /* driver sets this value */ 790 791 /* Tx Scheduler values */ 792 u8 num_tx_sched_layers; 793 u8 num_tx_sched_phys_layers; 794 u8 flattened_layers; 795 u8 max_cgds; 796 u8 sw_entry_point_layer; 797 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 798 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */ 799 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 800 u8 evb_veb; /* true for VEB, false for VEPA */ 801 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 802 struct ice_bus_info bus; 803 struct ice_nvm_info nvm; 804 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 805 struct ice_hw_func_caps func_caps; /* function capabilities */ 806 struct ice_netlist_ver_info netlist_ver; /* netlist version info */ 807 808 struct ice_switch_info *switch_info; /* switch filter lists */ 809 810 /* Control Queue info */ 811 struct ice_ctl_q_info adminq; 812 struct ice_ctl_q_info mailboxq; 813 814 u8 api_branch; /* API branch version */ 815 u8 api_maj_ver; /* API major version */ 816 u8 api_min_ver; /* API minor version */ 817 u8 api_patch; /* API patch version */ 818 u8 fw_branch; /* firmware branch version */ 819 u8 fw_maj_ver; /* firmware major version */ 820 u8 fw_min_ver; /* firmware minor version */ 821 u8 fw_patch; /* firmware patch version */ 822 u32 fw_build; /* firmware build number */ 823 824 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 825 * register. Used for determining the ITR/INTRL granularity during 826 * initialization. 827 */ 828 #define ICE_MAX_AGG_BW_200G 0x0 829 #define ICE_MAX_AGG_BW_100G 0X1 830 #define ICE_MAX_AGG_BW_50G 0x2 831 #define ICE_MAX_AGG_BW_25G 0x3 832 /* ITR granularity for different speeds */ 833 #define ICE_ITR_GRAN_ABOVE_25 2 834 #define ICE_ITR_GRAN_MAX_25 4 835 /* ITR granularity in 1 us */ 836 u8 itr_gran; 837 /* INTRL granularity for different speeds */ 838 #define ICE_INTRL_GRAN_ABOVE_25 4 839 #define ICE_INTRL_GRAN_MAX_25 8 840 /* INTRL granularity in 1 us */ 841 u8 intrl_gran; 842 843 u8 ucast_shared; /* true if VSIs can share unicast addr */ 844 845 #define ICE_PHY_PER_NAC 1 846 #define ICE_MAX_QUAD 2 847 #define ICE_NUM_QUAD_TYPE 2 848 #define ICE_PORTS_PER_QUAD 4 849 #define ICE_PHY_0_LAST_QUAD 1 850 #define ICE_PORTS_PER_PHY 8 851 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY 852 853 /* Active package version (currently active) */ 854 struct ice_pkg_ver active_pkg_ver; 855 u32 active_track_id; 856 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 857 u8 active_pkg_in_nvm; 858 859 enum ice_aq_err pkg_dwnld_status; 860 861 /* Driver's package ver - (from the Metadata seg) */ 862 struct ice_pkg_ver pkg_ver; 863 u8 pkg_name[ICE_PKG_NAME_SIZE]; 864 865 /* Driver's Ice package version (from the Ice seg) */ 866 struct ice_pkg_ver ice_pkg_ver; 867 u8 ice_pkg_name[ICE_PKG_NAME_SIZE]; 868 869 /* Pointer to the ice segment */ 870 struct ice_seg *seg; 871 872 /* Pointer to allocated copy of pkg memory */ 873 u8 *pkg_copy; 874 u32 pkg_size; 875 876 /* tunneling info */ 877 struct ice_lock tnl_lock; 878 struct ice_tunnel_table tnl; 879 880 /* HW block tables */ 881 struct ice_blk_info blk[ICE_BLK_COUNT]; 882 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 883 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT]; 884 struct ice_lock rss_locks; /* protect RSS configuration */ 885 struct LIST_HEAD_TYPE rss_list_head; 886 }; 887 888 /* Statistics collected by each port, VSI, VEB, and S-channel */ 889 struct ice_eth_stats { 890 u64 rx_bytes; /* gorc */ 891 u64 rx_unicast; /* uprc */ 892 u64 rx_multicast; /* mprc */ 893 u64 rx_broadcast; /* bprc */ 894 u64 rx_discards; /* rdpc */ 895 u64 rx_unknown_protocol; /* rupp */ 896 u64 tx_bytes; /* gotc */ 897 u64 tx_unicast; /* uptc */ 898 u64 tx_multicast; /* mptc */ 899 u64 tx_broadcast; /* bptc */ 900 u64 tx_discards; /* tdpc */ 901 u64 tx_errors; /* tepc */ 902 u64 rx_no_desc; /* repc */ 903 u64 rx_errors; /* repc */ 904 }; 905 906 #define ICE_MAX_UP 8 907 908 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */ 909 struct ice_veb_up_stats { 910 u64 up_rx_pkts[ICE_MAX_UP]; 911 u64 up_rx_bytes[ICE_MAX_UP]; 912 u64 up_tx_pkts[ICE_MAX_UP]; 913 u64 up_tx_bytes[ICE_MAX_UP]; 914 }; 915 916 /* Statistics collected by the MAC */ 917 struct ice_hw_port_stats { 918 /* eth stats collected by the port */ 919 struct ice_eth_stats eth; 920 /* additional port specific stats */ 921 u64 tx_dropped_link_down; /* tdold */ 922 u64 crc_errors; /* crcerrs */ 923 u64 illegal_bytes; /* illerrc */ 924 u64 error_bytes; /* errbc */ 925 u64 mac_local_faults; /* mlfc */ 926 u64 mac_remote_faults; /* mrfc */ 927 u64 rx_len_errors; /* rlec */ 928 u64 link_xon_rx; /* lxonrxc */ 929 u64 link_xoff_rx; /* lxoffrxc */ 930 u64 link_xon_tx; /* lxontxc */ 931 u64 link_xoff_tx; /* lxofftxc */ 932 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 933 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 934 u64 priority_xon_tx[8]; /* pxontxc[8] */ 935 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 936 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 937 u64 rx_size_64; /* prc64 */ 938 u64 rx_size_127; /* prc127 */ 939 u64 rx_size_255; /* prc255 */ 940 u64 rx_size_511; /* prc511 */ 941 u64 rx_size_1023; /* prc1023 */ 942 u64 rx_size_1522; /* prc1522 */ 943 u64 rx_size_big; /* prc9522 */ 944 u64 rx_undersize; /* ruc */ 945 u64 rx_fragments; /* rfc */ 946 u64 rx_oversize; /* roc */ 947 u64 rx_jabber; /* rjc */ 948 u64 tx_size_64; /* ptc64 */ 949 u64 tx_size_127; /* ptc127 */ 950 u64 tx_size_255; /* ptc255 */ 951 u64 tx_size_511; /* ptc511 */ 952 u64 tx_size_1023; /* ptc1023 */ 953 u64 tx_size_1522; /* ptc1522 */ 954 u64 tx_size_big; /* ptc9522 */ 955 u64 mac_short_pkt_dropped; /* mspdc */ 956 /* EEE LPI */ 957 u32 tx_lpi_status; 958 u32 rx_lpi_status; 959 u64 tx_lpi_count; /* etlpic */ 960 u64 rx_lpi_count; /* erlpic */ 961 }; 962 963 enum ice_sw_fwd_act_type { 964 ICE_FWD_TO_VSI = 0, 965 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 966 ICE_FWD_TO_Q, 967 ICE_FWD_TO_QGRP, 968 ICE_DROP_PACKET, 969 ICE_INVAL_ACT 970 }; 971 972 /* Checksum and Shadow RAM pointers */ 973 #define ICE_SR_NVM_CTRL_WORD 0x00 974 #define ICE_SR_PHY_ANALOG_PTR 0x04 975 #define ICE_SR_OPTION_ROM_PTR 0x05 976 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 977 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07 978 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 979 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09 980 #define ICE_SR_EMP_IMAGE_PTR 0x0B 981 #define ICE_SR_PE_IMAGE_PTR 0x0C 982 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D 983 #define ICE_SR_MNG_CFG_PTR 0x0E 984 #define ICE_SR_EMP_MODULE_PTR 0x0F 985 #define ICE_SR_PBA_BLOCK_PTR 0x16 986 #define ICE_SR_BOOT_CFG_PTR 0x132 987 #define ICE_SR_NVM_WOL_CFG 0x19 988 #define ICE_NVM_OROM_VER_OFF 0x02 989 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 990 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27 991 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28 992 #define ICE_SR_NVM_MAP_VER 0x29 993 #define ICE_SR_NVM_IMAGE_VER 0x2A 994 #define ICE_SR_NVM_STRUCTURE_VER 0x2B 995 #define ICE_SR_NVM_EETRACK_LO 0x2D 996 #define ICE_SR_NVM_EETRACK_HI 0x2E 997 #define ICE_NVM_VER_LO_SHIFT 0 998 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 999 #define ICE_NVM_VER_HI_SHIFT 12 1000 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1001 #define ICE_OEM_EETRACK_ID 0xffffffff 1002 #define ICE_OROM_VER_PATCH_SHIFT 0 1003 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1004 #define ICE_OROM_VER_BUILD_SHIFT 8 1005 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1006 #define ICE_OROM_VER_SHIFT 24 1007 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1008 #define ICE_SR_VPD_PTR 0x2F 1009 #define ICE_SR_PXE_SETUP_PTR 0x30 1010 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31 1011 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1012 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1013 #define ICE_SR_VLAN_CFG_PTR 0x37 1014 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1015 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1016 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1017 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1018 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D 1019 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1020 #define ICE_SR_SW_CHECKSUM_WORD 0x3F 1021 #define ICE_SR_PFA_PTR 0x40 1022 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41 1023 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1024 #define ICE_SR_NVM_BANK_SIZE 0x43 1025 #define ICE_SR_1ND_OROM_BANK_PTR 0x44 1026 #define ICE_SR_OROM_BANK_SIZE 0x45 1027 #define ICE_SR_NETLIST_BANK_PTR 0x46 1028 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1029 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48 1030 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D 1031 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E 1032 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 1033 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118 1034 1035 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1036 #define ICE_SR_VPD_SIZE_WORDS 512 1037 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512 1038 #define ICE_SR_CTRL_WORD_1_S 0x06 1039 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1040 1041 /* Shadow RAM related */ 1042 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1043 #define ICE_SR_BUF_ALIGNMENT 4096 1044 #define ICE_SR_WORDS_IN_1KB 512 1045 /* Checksum should be calculated such that after adding all the words, 1046 * including the checksum word itself, the sum should be 0xBABA. 1047 */ 1048 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA 1049 1050 /* Link override related */ 1051 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1052 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1053 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1054 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1055 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1056 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1057 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1058 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1059 1060 #define ICE_PBA_FLAG_DFLT 0xFAFA 1061 /* Hash redirection LUT for VSI - maximum array size */ 1062 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1063 1064 /* 1065 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register. 1066 * This is needed to determine the BAR0 space for the VFs 1067 */ 1068 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0 1069 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1 1070 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2 1071 1072 #endif /* _ICE_TYPE_H_ */ 1073