1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_TYPE_H_ 34 #define _ICE_TYPE_H_ 35 36 #define ETH_ALEN 6 37 38 #define ETH_HEADER_LEN 14 39 40 #define BIT(a) (1UL << (a)) 41 #ifndef BIT_ULL 42 #define BIT_ULL(a) (1ULL << (a)) 43 #endif /* BIT_ULL */ 44 45 #define BITS_PER_BYTE 8 46 47 #define _FORCE_ 48 49 #define ICE_BYTES_PER_WORD 2 50 #define ICE_BYTES_PER_DWORD 4 51 #define ICE_MAX_TRAFFIC_CLASS 8 52 53 #ifndef MIN_T 54 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b)) 55 #endif 56 57 #define IS_ASCII(_ch) ((_ch) < 0x80) 58 59 #define STRUCT_HACK_VAR_LEN 60 /** 61 * ice_struct_size - size of struct with C99 flexible array member 62 * @ptr: pointer to structure 63 * @field: flexible array member (last member of the structure) 64 * @num: number of elements of that flexible array member 65 */ 66 #define ice_struct_size(ptr, field, num) \ 67 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num)) 68 69 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0])) 70 71 #include "ice_status.h" 72 #include "ice_hw_autogen.h" 73 #include "ice_devids.h" 74 #include "ice_osdep.h" 75 #include "ice_bitops.h" /* Must come before ice_controlq.h */ 76 #include "ice_controlq.h" 77 #include "ice_lan_tx_rx.h" 78 #include "ice_flex_type.h" 79 #include "ice_protocol_type.h" 80 #include "ice_vlan_mode.h" 81 #include "ice_fwlog.h" 82 83 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc) 84 { 85 return !!(bitmap & BIT(tc)); 86 } 87 88 /** 89 * DIV_S64 - Divide signed 64-bit value with signed 64-bit divisor 90 * @dividend: value to divide 91 * @divisor: value to divide by 92 * 93 * Use DIV_S64 for any 64-bit divide which operates on signed 64-bit dividends. 94 * Do not use this for unsigned 64-bit dividends as it will not produce 95 * correct results if the dividend is larger than S64_MAX. 96 */ 97 static inline s64 DIV_S64(s64 dividend, s64 divisor) 98 { 99 return dividend / divisor; 100 } 101 102 /** 103 * DIV_U64 - Divide unsigned 64-bit value by unsigned 64-bit divisor 104 * @dividend: value to divide 105 * @divisor: value to divide by 106 * 107 * Use DIV_U64 for any 64-bit divide which operates on unsigned 64-bit 108 * dividends. Do not use this for signed 64-bit dividends as it will not 109 * handle negative values correctly. 110 */ 111 static inline u64 DIV_U64(u64 dividend, u64 divisor) 112 { 113 return dividend / divisor; 114 } 115 116 static inline u64 round_up_64bit(u64 a, u32 b) 117 { 118 return DIV_U64(((a) + (b) / 2), (b)); 119 } 120 121 static inline u32 ice_round_to_num(u32 N, u32 R) 122 { 123 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 124 ((((N) + (R) - 1) / (R)) * (R))); 125 } 126 127 /* Driver always calls main vsi_handle first */ 128 #define ICE_MAIN_VSI_HANDLE 0 129 130 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 131 #define ICE_MS_TO_GTIME(time) ((time) * 1000) 132 133 /* Data type manipulation macros. */ 134 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 135 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 136 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 137 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF)) 138 139 /* debug masks - set these bits in hw->debug_mask to control output */ 140 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */ 141 #define ICE_DBG_INIT BIT_ULL(1) 142 #define ICE_DBG_RELEASE BIT_ULL(2) 143 #define ICE_DBG_FW_LOG BIT_ULL(3) 144 #define ICE_DBG_LINK BIT_ULL(4) 145 #define ICE_DBG_PHY BIT_ULL(5) 146 #define ICE_DBG_QCTX BIT_ULL(6) 147 #define ICE_DBG_NVM BIT_ULL(7) 148 #define ICE_DBG_LAN BIT_ULL(8) 149 #define ICE_DBG_FLOW BIT_ULL(9) 150 #define ICE_DBG_DCB BIT_ULL(10) 151 #define ICE_DBG_DIAG BIT_ULL(11) 152 #define ICE_DBG_FD BIT_ULL(12) 153 #define ICE_DBG_SW BIT_ULL(13) 154 #define ICE_DBG_SCHED BIT_ULL(14) 155 156 #define ICE_DBG_RDMA BIT_ULL(15) 157 #define ICE_DBG_PKG BIT_ULL(16) 158 #define ICE_DBG_RES BIT_ULL(17) 159 #define ICE_DBG_AQ_MSG BIT_ULL(24) 160 #define ICE_DBG_AQ_DESC BIT_ULL(25) 161 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 162 #define ICE_DBG_AQ_CMD BIT_ULL(27) 163 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 164 ICE_DBG_AQ_DESC | \ 165 ICE_DBG_AQ_DESC_BUF | \ 166 ICE_DBG_AQ_CMD) 167 #define ICE_DBG_PARSER BIT_ULL(28) 168 169 #define ICE_DBG_USER BIT_ULL(31) 170 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL 171 172 #define IS_UNICAST_ETHER_ADDR(addr) \ 173 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0)) 174 175 #define IS_MULTICAST_ETHER_ADDR(addr) \ 176 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1)) 177 178 /* Check whether an address is broadcast. */ 179 #define IS_BROADCAST_ETHER_ADDR(addr) \ 180 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff)))) 181 182 #define IS_ZERO_ETHER_ADDR(addr) \ 183 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \ 184 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \ 185 ((bool)((((u16 *)(addr))[2] == ((u16)0x0))))) 186 187 #ifndef IS_ETHER_ADDR_EQUAL 188 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \ 189 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \ 190 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \ 191 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2])))) 192 #endif 193 194 enum ice_aq_res_ids { 195 ICE_NVM_RES_ID = 1, 196 ICE_SPD_RES_ID, 197 ICE_CHANGE_LOCK_RES_ID, 198 ICE_GLOBAL_CFG_LOCK_RES_ID 199 }; 200 201 /* FW update timeout definitions are in milliseconds */ 202 #define ICE_NVM_TIMEOUT 180000 203 #define ICE_CHANGE_LOCK_TIMEOUT 1000 204 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 205 206 enum ice_aq_res_access_type { 207 ICE_RES_READ = 1, 208 ICE_RES_WRITE 209 }; 210 211 struct ice_driver_ver { 212 u8 major_ver; 213 u8 minor_ver; 214 u8 build_ver; 215 u8 subbuild_ver; 216 u8 driver_string[32]; 217 }; 218 219 enum ice_fc_mode { 220 ICE_FC_NONE = 0, 221 ICE_FC_RX_PAUSE, 222 ICE_FC_TX_PAUSE, 223 ICE_FC_FULL, 224 ICE_FC_AUTO, 225 ICE_FC_PFC, 226 ICE_FC_DFLT 227 }; 228 229 enum ice_phy_cache_mode { 230 ICE_FC_MODE = 0, 231 ICE_SPEED_MODE, 232 ICE_FEC_MODE 233 }; 234 235 enum ice_fec_mode { 236 ICE_FEC_NONE = 0, 237 ICE_FEC_RS, 238 ICE_FEC_BASER, 239 ICE_FEC_AUTO 240 }; 241 242 struct ice_phy_cache_mode_data { 243 union { 244 enum ice_fec_mode curr_user_fec_req; 245 enum ice_fc_mode curr_user_fc_req; 246 u16 curr_user_speed_req; 247 } data; 248 }; 249 250 enum ice_set_fc_aq_failures { 251 ICE_SET_FC_AQ_FAIL_NONE = 0, 252 ICE_SET_FC_AQ_FAIL_GET, 253 ICE_SET_FC_AQ_FAIL_SET, 254 ICE_SET_FC_AQ_FAIL_UPDATE 255 }; 256 257 /* These are structs for managing the hardware information and the operations */ 258 /* MAC types */ 259 enum ice_mac_type { 260 ICE_MAC_UNKNOWN = 0, 261 ICE_MAC_VF, 262 ICE_MAC_E810, 263 ICE_MAC_GENERIC, 264 }; 265 266 /* Media Types */ 267 enum ice_media_type { 268 ICE_MEDIA_UNKNOWN = 0, 269 ICE_MEDIA_FIBER, 270 ICE_MEDIA_BASET, 271 ICE_MEDIA_BACKPLANE, 272 ICE_MEDIA_DA, 273 ICE_MEDIA_AUI, 274 }; 275 276 /* Software VSI types. */ 277 enum ice_vsi_type { 278 ICE_VSI_PF = 0, 279 ICE_VSI_VF = 1, 280 ICE_VSI_LB = 6, 281 }; 282 283 struct ice_link_status { 284 /* Refer to ice_aq_phy_type for bits definition */ 285 u64 phy_type_low; 286 u64 phy_type_high; 287 u8 topo_media_conflict; 288 u16 max_frame_size; 289 u16 link_speed; 290 u16 req_speeds; 291 u8 link_cfg_err; 292 u8 lse_ena; /* Link Status Event notification */ 293 u8 link_info; 294 u8 an_info; 295 u8 ext_info; 296 u8 fec_info; 297 u8 pacing; 298 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 299 * ice_aqc_get_phy_caps structure 300 */ 301 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 302 }; 303 304 /* Different data queue types: These are mainly for SW consumption. */ 305 enum ice_q { 306 ICE_DATA_Q_DOORBELL, 307 ICE_DATA_Q_CMPL, 308 ICE_DATA_Q_QUANTA, 309 ICE_DATA_Q_RX, 310 ICE_DATA_Q_TX, 311 }; 312 313 /* Different reset sources for which a disable queue AQ call has to be made in 314 * order to clean the Tx scheduler as a part of the reset 315 */ 316 enum ice_disq_rst_src { 317 ICE_NO_RESET = 0, 318 ICE_VM_RESET, 319 ICE_VF_RESET, 320 }; 321 322 /* PHY info such as phy_type, etc... */ 323 struct ice_phy_info { 324 struct ice_link_status link_info; 325 struct ice_link_status link_info_old; 326 u64 phy_type_low; 327 u64 phy_type_high; 328 enum ice_media_type media_type; 329 u8 get_link_info; 330 /* Please refer to struct ice_aqc_get_link_status_data to get 331 * detail of enable bit in curr_user_speed_req 332 */ 333 u16 curr_user_speed_req; 334 enum ice_fec_mode curr_user_fec_req; 335 enum ice_fc_mode curr_user_fc_req; 336 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 337 }; 338 339 #define ICE_MAX_NUM_MIRROR_RULES 64 340 341 /* Common HW capabilities for SW use */ 342 struct ice_hw_common_caps { 343 /* Write CSR protection */ 344 u64 wr_csr_prot; 345 u32 switching_mode; 346 /* switching mode supported - EVB switching (including cloud) */ 347 #define ICE_NVM_IMAGE_TYPE_EVB 0x0 348 349 /* Manageablity mode & supported protocols over MCTP */ 350 u32 mgmt_mode; 351 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF 352 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0 353 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00 354 355 u32 mgmt_protocols_mctp; 356 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0) 357 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1) 358 #define ICE_MGMT_MODE_PROTO_OEM BIT(2) 359 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3) 360 361 u32 os2bmc; 362 u32 valid_functions; 363 /* DCB capabilities */ 364 u32 active_tc_bitmap; 365 u32 maxtc; 366 367 /* RSS related capabilities */ 368 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 369 u32 rss_table_entry_width; /* RSS Entry width in bits */ 370 371 /* Tx/Rx queues */ 372 u32 num_rxq; /* Number/Total Rx queues */ 373 u32 rxq_first_id; /* First queue ID for Rx queues */ 374 u32 num_txq; /* Number/Total Tx queues */ 375 u32 txq_first_id; /* First queue ID for Tx queues */ 376 377 /* MSI-X vectors */ 378 u32 num_msix_vectors; 379 u32 msix_vector_first_id; 380 381 /* Max MTU for function or device */ 382 u32 max_mtu; 383 384 /* WOL related */ 385 u32 num_wol_proxy_fltr; 386 u32 wol_proxy_vsi_seid; 387 388 /* LED/SDP pin count */ 389 u32 led_pin_num; 390 u32 sdp_pin_num; 391 392 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 393 #define ICE_MAX_SUPPORTED_GPIO_LED 12 394 #define ICE_MAX_SUPPORTED_GPIO_SDP 8 395 u8 led[ICE_MAX_SUPPORTED_GPIO_LED]; 396 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP]; 397 398 /* SR-IOV virtualization */ 399 u8 sr_iov_1_1; /* SR-IOV enabled */ 400 401 /* EVB capabilities */ 402 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 403 u8 evb_802_1_qbh; /* Bridge Port Extension */ 404 405 u8 dcb; 406 u8 iscsi; 407 u8 mgmt_cem; 408 u8 iwarp; 409 410 /* WoL and APM support */ 411 #define ICE_WOL_SUPPORT_M BIT(0) 412 #define ICE_ACPI_PROG_MTHD_M BIT(1) 413 #define ICE_PROXY_SUPPORT_M BIT(2) 414 u8 apm_wol_support; 415 u8 acpi_prog_mthd; 416 u8 proxy_support; 417 bool sec_rev_disabled; 418 bool update_disabled; 419 bool nvm_unified_update; 420 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) 421 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) 422 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 423 /* PCIe reset avoidance */ 424 bool pcie_reset_avoidance; /* false: not supported, true: supported */ 425 /* Post update reset restriction */ 426 bool reset_restrict_support; /* false: not supported, true: supported */ 427 428 /* External topology device images within the NVM */ 429 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4 430 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT]; 431 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT]; 432 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT]; 433 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8 434 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \ 435 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S) 436 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; 437 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0) 438 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; 439 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1) 440 }; 441 442 /* Function specific capabilities */ 443 struct ice_hw_func_caps { 444 struct ice_hw_common_caps common_cap; 445 u32 num_allocd_vfs; /* Number of allocated VFs */ 446 u32 vf_base_id; /* Logical ID of the first VF */ 447 u32 guar_num_vsi; 448 }; 449 450 /* Device wide capabilities */ 451 struct ice_hw_dev_caps { 452 struct ice_hw_common_caps common_cap; 453 u32 num_vfs_exposed; /* Total number of VFs exposed */ 454 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 455 u32 num_funcs; 456 }; 457 458 /* Information about MAC such as address, etc... */ 459 struct ice_mac_info { 460 u8 lan_addr[ETH_ALEN]; 461 u8 perm_addr[ETH_ALEN]; 462 u8 port_addr[ETH_ALEN]; 463 u8 wol_addr[ETH_ALEN]; 464 }; 465 466 /* PCI bus types */ 467 enum ice_bus_type { 468 ice_bus_unknown = 0, 469 ice_bus_pci_express, 470 ice_bus_embedded, /* Is device Embedded versus card */ 471 ice_bus_reserved 472 }; 473 474 /* PCI bus speeds */ 475 enum ice_pcie_bus_speed { 476 ice_pcie_speed_unknown = 0xff, 477 ice_pcie_speed_2_5GT = 0x14, 478 ice_pcie_speed_5_0GT = 0x15, 479 ice_pcie_speed_8_0GT = 0x16, 480 ice_pcie_speed_16_0GT = 0x17 481 }; 482 483 /* PCI bus widths */ 484 enum ice_pcie_link_width { 485 ice_pcie_lnk_width_resrv = 0x00, 486 ice_pcie_lnk_x1 = 0x01, 487 ice_pcie_lnk_x2 = 0x02, 488 ice_pcie_lnk_x4 = 0x04, 489 ice_pcie_lnk_x8 = 0x08, 490 ice_pcie_lnk_x12 = 0x0C, 491 ice_pcie_lnk_x16 = 0x10, 492 ice_pcie_lnk_x32 = 0x20, 493 ice_pcie_lnk_width_unknown = 0xff, 494 }; 495 496 /* Reset types used to determine which kind of reset was requested. These 497 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 498 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 499 * because its reset source is different than the other types listed. 500 */ 501 enum ice_reset_req { 502 ICE_RESET_POR = 0, 503 ICE_RESET_INVAL = 0, 504 ICE_RESET_CORER = 1, 505 ICE_RESET_GLOBR = 2, 506 ICE_RESET_EMPR = 3, 507 ICE_RESET_PFR = 4, 508 }; 509 510 /* Bus parameters */ 511 struct ice_bus_info { 512 enum ice_pcie_bus_speed speed; 513 enum ice_pcie_link_width width; 514 enum ice_bus_type type; 515 u16 domain_num; 516 u16 device; 517 u8 func; 518 u8 bus_num; 519 }; 520 521 /* Flow control (FC) parameters */ 522 struct ice_fc_info { 523 enum ice_fc_mode current_mode; /* FC mode in effect */ 524 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 525 }; 526 527 /* Option ROM version information */ 528 struct ice_orom_info { 529 u8 major; /* Major version of OROM */ 530 u8 patch; /* Patch version of OROM */ 531 u16 build; /* Build version of OROM */ 532 u32 srev; /* Security revision */ 533 }; 534 535 /* NVM version information */ 536 struct ice_nvm_info { 537 u32 eetrack; 538 u32 srev; 539 u8 major; 540 u8 minor; 541 }; 542 543 /* Minimum Security Revision information */ 544 struct ice_minsrev_info { 545 u32 nvm; 546 u32 orom; 547 u8 nvm_valid : 1; 548 u8 orom_valid : 1; 549 }; 550 551 /* netlist version information */ 552 struct ice_netlist_info { 553 u32 major; /* major high/low */ 554 u32 minor; /* minor high/low */ 555 u32 type; /* type high/low */ 556 u32 rev; /* revision high/low */ 557 u32 hash; /* SHA-1 hash word */ 558 u16 cust_ver; /* customer version */ 559 }; 560 561 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 562 * of the flash image. 563 */ 564 enum ice_flash_bank { 565 ICE_INVALID_FLASH_BANK, 566 ICE_1ST_FLASH_BANK, 567 ICE_2ND_FLASH_BANK, 568 }; 569 570 /* Enumeration of which flash bank is desired to read from, either the active 571 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 572 * code which just wants to read the active or inactive flash bank. 573 */ 574 enum ice_bank_select { 575 ICE_ACTIVE_FLASH_BANK, 576 ICE_INACTIVE_FLASH_BANK, 577 }; 578 579 /* information for accessing NVM, OROM, and Netlist flash banks */ 580 struct ice_bank_info { 581 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 582 u32 nvm_size; /* Size of NVM bank */ 583 u32 orom_ptr; /* Pointer to 1st OROM bank */ 584 u32 orom_size; /* Size of OROM bank */ 585 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 586 u32 netlist_size; /* Size of Netlist bank */ 587 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 588 enum ice_flash_bank orom_bank; /* Active OROM bank */ 589 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 590 }; 591 592 /* Flash Chip Information */ 593 struct ice_flash_info { 594 struct ice_orom_info orom; /* Option ROM version info */ 595 struct ice_nvm_info nvm; /* NVM version information */ 596 struct ice_netlist_info netlist;/* Netlist version info */ 597 struct ice_bank_info banks; /* Flash Bank information */ 598 u16 sr_words; /* Shadow RAM size in words */ 599 u32 flash_size; /* Size of available flash in bytes */ 600 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 601 }; 602 603 struct ice_link_default_override_tlv { 604 u8 options; 605 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 606 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 607 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 608 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 609 #define ICE_LINK_OVERRIDE_EN BIT(3) 610 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 611 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 612 u8 phy_config; 613 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 614 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 615 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 616 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 617 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 618 u8 fec_options; 619 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 620 u8 rsvd1; 621 u64 phy_type_low; 622 u64 phy_type_high; 623 }; 624 625 #define ICE_NVM_VER_LEN 32 626 627 /* Max number of port to queue branches w.r.t topology */ 628 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 629 630 #define ice_for_each_traffic_class(_i) \ 631 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 632 633 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 634 * to driver defined policy for default aggregator 635 */ 636 #define ICE_INVAL_TEID 0xFFFFFFFF 637 #define ICE_DFLT_AGG_ID 0 638 639 struct ice_sched_node { 640 struct ice_sched_node *parent; 641 struct ice_sched_node *sibling; /* next sibling in the same layer */ 642 struct ice_sched_node **children; 643 struct ice_aqc_txsched_elem_data info; 644 u32 agg_id; /* aggregator group ID */ 645 u16 vsi_handle; 646 u8 in_use; /* suspended or in use */ 647 u8 tx_sched_layer; /* Logical Layer (1-9) */ 648 u8 num_children; 649 u8 tc_num; 650 u8 owner; 651 #define ICE_SCHED_NODE_OWNER_LAN 0 652 #define ICE_SCHED_NODE_OWNER_AE 1 653 #define ICE_SCHED_NODE_OWNER_RDMA 2 654 }; 655 656 /* Access Macros for Tx Sched Elements data */ 657 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid) 658 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid) 659 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \ 660 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx) 661 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \ 662 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx) 663 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id) 664 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \ 665 LE16_TO_CPU((x)->info.cir_bw.bw_alloc) 666 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \ 667 LE16_TO_CPU((x)->info.eir_bw.bw_alloc) 668 669 struct ice_sched_rl_profile { 670 u32 rate; /* In Kbps */ 671 struct ice_aqc_rl_profile_elem info; 672 }; 673 674 /* The aggregator type determines if identifier is for a VSI group, 675 * aggregator group, aggregator of queues, or queue group. 676 */ 677 enum ice_agg_type { 678 ICE_AGG_TYPE_UNKNOWN = 0, 679 ICE_AGG_TYPE_TC, 680 ICE_AGG_TYPE_AGG, /* aggregator */ 681 ICE_AGG_TYPE_VSI, 682 ICE_AGG_TYPE_QG, 683 ICE_AGG_TYPE_Q 684 }; 685 686 /* Rate limit types */ 687 enum ice_rl_type { 688 ICE_UNKNOWN_BW = 0, 689 ICE_MIN_BW, /* for CIR profile */ 690 ICE_MAX_BW, /* for EIR profile */ 691 ICE_SHARED_BW /* for shared profile */ 692 }; 693 694 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 695 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 696 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 697 #define ICE_SCHED_NO_PRIORITY 0 698 #define ICE_SCHED_NO_BW_WT 0 699 #define ICE_SCHED_DFLT_RL_PROF_ID 0 700 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 701 #define ICE_SCHED_DFLT_BW_WT 4 702 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 703 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 704 705 /* Access Macros for Tx Sched RL Profile data */ 706 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id) 707 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size) 708 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply) 709 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc) 710 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode) 711 712 #define ICE_MAX_PORT_PER_PCI_DEV 8 713 714 /* The following tree example shows the naming conventions followed under 715 * ice_port_info struct for default scheduler tree topology. 716 * 717 * A tree on a port 718 * * ---> root node 719 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8) 720 * * * * * * * * * | 721 * / | 722 * * | 723 * / |-> num_elements (range:1 - 9) 724 * * | implies num_of_layers 725 * / | 726 * (a)* | 727 * 728 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under 729 * (a) as child node where queues get added, add Tx/Rx queue admin commands; 730 * need TEID of (a) to add queues. 731 * 732 * This tree 733 * -> has 8 branches (one for each TC) 734 * -> First branch (TC0) has 4 elements 735 * -> has 4 layers 736 * -> (a) is the topmost layer node created by firmware on branch 0 737 * 738 * Note: Above asterisk tree covers only basic terminology and scenario. 739 * Refer to the documentation for more info. 740 */ 741 742 /* Data structure for saving BW information */ 743 enum ice_bw_type { 744 ICE_BW_TYPE_PRIO, 745 ICE_BW_TYPE_CIR, 746 ICE_BW_TYPE_CIR_WT, 747 ICE_BW_TYPE_EIR, 748 ICE_BW_TYPE_EIR_WT, 749 ICE_BW_TYPE_SHARED, 750 ICE_BW_TYPE_CNT /* This must be last */ 751 }; 752 753 struct ice_bw { 754 u32 bw; 755 u16 bw_alloc; 756 }; 757 758 struct ice_bw_type_info { 759 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT); 760 u8 generic; 761 struct ice_bw cir_bw; 762 struct ice_bw eir_bw; 763 u32 shared_bw; 764 }; 765 766 /* VSI queue context structure for given TC */ 767 struct ice_q_ctx { 768 u16 q_handle; 769 u32 q_teid; 770 /* bw_t_info saves queue BW information */ 771 struct ice_bw_type_info bw_t_info; 772 }; 773 774 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 775 struct ice_sched_vsi_info { 776 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 777 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 778 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 779 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 780 /* bw_t_info saves VSI BW information */ 781 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 782 }; 783 784 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 785 struct ice_dcb_ets_cfg { 786 u8 willing; 787 u8 cbs; 788 u8 maxtcs; 789 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 790 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 791 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 792 }; 793 794 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 795 struct ice_dcb_pfc_cfg { 796 u8 willing; 797 u8 mbc; 798 u8 pfccap; 799 u8 pfcena; 800 }; 801 802 /* CEE or IEEE 802.1Qaz Application Priority data */ 803 struct ice_dcb_app_priority_table { 804 u16 prot_id; 805 u8 priority; 806 u8 selector; 807 }; 808 809 #define ICE_MAX_USER_PRIORITY 8 810 #define ICE_DCBX_MAX_APPS 64 811 #define ICE_DSCP_NUM_VAL 64 812 #define ICE_LLDPDU_SIZE 1500 813 #define ICE_TLV_STATUS_OPER 0x1 814 #define ICE_TLV_STATUS_SYNC 0x2 815 #define ICE_TLV_STATUS_ERR 0x4 816 #define ICE_APP_PROT_ID_FCOE 0x8906 817 #define ICE_APP_PROT_ID_ISCSI 0x0cbc 818 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 819 #define ICE_APP_PROT_ID_FIP 0x8914 820 #define ICE_APP_SEL_ETHTYPE 0x1 821 #define ICE_APP_SEL_TCPIP 0x2 822 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 823 #define ICE_CEE_APP_SEL_TCPIP 0x1 824 825 struct ice_dcbx_cfg { 826 u32 numapps; 827 u32 tlv_status; /* CEE mode TLV status */ 828 struct ice_dcb_ets_cfg etscfg; 829 struct ice_dcb_ets_cfg etsrec; 830 struct ice_dcb_pfc_cfg pfc; 831 #define ICE_QOS_MODE_VLAN 0x0 832 #define ICE_QOS_MODE_DSCP 0x1 833 u8 pfc_mode; 834 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 835 /* when DSCP mapping defined by user set its bit to 1 */ 836 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL); 837 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 838 u8 dscp_map[ICE_DSCP_NUM_VAL]; 839 u8 dcbx_mode; 840 #define ICE_DCBX_MODE_CEE 0x1 841 #define ICE_DCBX_MODE_IEEE 0x2 842 u8 app_mode; 843 #define ICE_DCBX_APPS_NON_WILLING 0x1 844 }; 845 846 struct ice_qos_cfg { 847 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 848 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 849 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 850 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 851 u8 is_sw_lldp : 1; 852 }; 853 854 struct ice_port_info { 855 struct ice_sched_node *root; /* Root Node per Port */ 856 struct ice_hw *hw; /* back pointer to HW instance */ 857 u32 last_node_teid; /* scheduler last node info */ 858 u16 sw_id; /* Initial switch ID belongs to port */ 859 u16 pf_vf_num; 860 u8 port_state; 861 #define ICE_SCHED_PORT_STATE_INIT 0x0 862 #define ICE_SCHED_PORT_STATE_READY 0x1 863 u8 lport; 864 #define ICE_LPORT_MASK 0xff 865 u16 dflt_tx_vsi_rule_id; 866 u16 dflt_tx_vsi_num; 867 u16 dflt_rx_vsi_rule_id; 868 u16 dflt_rx_vsi_num; 869 struct ice_fc_info fc; 870 struct ice_mac_info mac; 871 struct ice_phy_info phy; 872 struct ice_lock sched_lock; /* protect access to TXSched tree */ 873 struct ice_sched_node * 874 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 875 struct ice_bw_type_info root_node_bw_t_info; 876 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 877 struct ice_qos_cfg qos_cfg; 878 u8 is_vf:1; 879 }; 880 881 struct ice_switch_info { 882 struct LIST_HEAD_TYPE vsi_list_map_head; 883 struct ice_sw_recipe *recp_list; 884 u16 prof_res_bm_init; 885 u16 max_used_prof_index; 886 887 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 888 }; 889 890 891 /* Enum defining the different states of the mailbox snapshot in the 892 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 893 * states: 894 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 895 * within the mailbox buffer. 896 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 897 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 898 * mailbox and mark any VFs sending more messages than the threshold limit set. 899 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 900 */ 901 enum ice_mbx_snapshot_state { 902 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 903 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 904 ICE_MAL_VF_DETECT_STATE_DETECT, 905 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 906 }; 907 908 /* Structure to hold information of the static snapshot and the mailbox 909 * buffer data used to generate and track the snapshot. 910 * 1. state: the state of the mailbox snapshot in the malicious VF 911 * detection state handler ice_mbx_vf_state_handler() 912 * 2. head : head of the mailbox snapshot in a circular mailbox buffer 913 * 3. tail : tail of the mailbox snapshot in a circular mailbox buffer 914 * 4. num_iterations: number of messages traversed in circular mailbox buffer 915 * 5. num_msg_proc: number of messages processed in mailbox 916 * 6. num_pending_arq: number of pending asynchronous messages 917 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 918 * serviced work item or interrupt. 919 */ 920 struct ice_mbx_snap_buffer_data { 921 enum ice_mbx_snapshot_state state; 922 u32 head; 923 u32 tail; 924 u32 num_iterations; 925 u16 num_msg_proc; 926 u16 num_pending_arq; 927 u16 max_num_msgs_mbx; 928 }; 929 930 /* Structure to track messages sent by VFs on mailbox: 931 * 1. vf_cntr : a counter array of VFs to track the number of 932 * asynchronous messages sent by each VF 933 * 2. vfcntr_len : number of entries in VF counter array 934 */ 935 struct ice_mbx_vf_counter { 936 u32 *vf_cntr; 937 u32 vfcntr_len; 938 }; 939 940 /* Structure to hold data relevant to the captured static snapshot 941 * of the PF-VF mailbox. 942 */ 943 struct ice_mbx_snapshot { 944 struct ice_mbx_snap_buffer_data mbx_buf; 945 struct ice_mbx_vf_counter mbx_vf; 946 }; 947 948 /* Structure to hold data to be used for capturing or updating a 949 * static snapshot. 950 * 1. num_msg_proc: number of messages processed in mailbox 951 * 2. num_pending_arq: number of pending asynchronous messages 952 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 953 * serviced work item or interrupt. 954 * 4. async_watermark_val: An upper threshold set by caller to determine 955 * if the pending arq count is large enough to assume that there is 956 * the possibility of a mailicious VF. 957 */ 958 struct ice_mbx_data { 959 u16 num_msg_proc; 960 u16 num_pending_arq; 961 u16 max_num_msgs_mbx; 962 u16 async_watermark_val; 963 }; 964 965 /* Port hardware description */ 966 struct ice_hw { 967 u8 *hw_addr; 968 void *back; 969 struct ice_aqc_layer_props *layer_info; 970 struct ice_port_info *port_info; 971 /* 2D Array for each Tx Sched RL Profile type */ 972 struct ice_sched_rl_profile **cir_profiles; 973 struct ice_sched_rl_profile **eir_profiles; 974 struct ice_sched_rl_profile **srl_profiles; 975 /* PSM clock frequency for calculating RL profile params */ 976 u32 psm_clk_freq; 977 u64 debug_mask; /* BITMAP for debug mask */ 978 enum ice_mac_type mac_type; 979 980 /* pci info */ 981 u16 device_id; 982 u16 vendor_id; 983 u16 subsystem_device_id; 984 u16 subsystem_vendor_id; 985 u8 revision_id; 986 987 u8 pf_id; /* device profile info */ 988 989 u16 max_burst_size; /* driver sets this value */ 990 991 /* Tx Scheduler values */ 992 u8 num_tx_sched_layers; 993 u8 num_tx_sched_phys_layers; 994 u8 flattened_layers; 995 u8 max_cgds; 996 u8 sw_entry_point_layer; 997 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 998 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */ 999 /* List contain profile ID(s) and other params per layer */ 1000 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1001 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 1002 u8 evb_veb; /* true for VEB, false for VEPA */ 1003 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 1004 struct ice_bus_info bus; 1005 struct ice_flash_info flash; 1006 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 1007 struct ice_hw_func_caps func_caps; /* function capabilities */ 1008 1009 struct ice_switch_info *switch_info; /* switch filter lists */ 1010 1011 /* Control Queue info */ 1012 struct ice_ctl_q_info adminq; 1013 struct ice_ctl_q_info mailboxq; 1014 u8 api_branch; /* API branch version */ 1015 u8 api_maj_ver; /* API major version */ 1016 u8 api_min_ver; /* API minor version */ 1017 u8 api_patch; /* API patch version */ 1018 u8 fw_branch; /* firmware branch version */ 1019 u8 fw_maj_ver; /* firmware major version */ 1020 u8 fw_min_ver; /* firmware minor version */ 1021 u8 fw_patch; /* firmware patch version */ 1022 u32 fw_build; /* firmware build number */ 1023 1024 struct ice_fwlog_cfg fwlog_cfg; 1025 bool fwlog_support_ena; /* does hardware support FW logging? */ 1026 1027 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 1028 * register. Used for determining the ITR/INTRL granularity during 1029 * initialization. 1030 */ 1031 #define ICE_MAX_AGG_BW_200G 0x0 1032 #define ICE_MAX_AGG_BW_100G 0X1 1033 #define ICE_MAX_AGG_BW_50G 0x2 1034 #define ICE_MAX_AGG_BW_25G 0x3 1035 /* ITR granularity for different speeds */ 1036 #define ICE_ITR_GRAN_ABOVE_25 2 1037 #define ICE_ITR_GRAN_MAX_25 4 1038 /* ITR granularity in 1 us */ 1039 u8 itr_gran; 1040 /* INTRL granularity for different speeds */ 1041 #define ICE_INTRL_GRAN_ABOVE_25 4 1042 #define ICE_INTRL_GRAN_MAX_25 8 1043 /* INTRL granularity in 1 us */ 1044 u8 intrl_gran; 1045 1046 /* true if VSIs can share unicast MAC addr */ 1047 u8 umac_shared; 1048 1049 #define ICE_PHY_PER_NAC 1 1050 #define ICE_MAX_QUAD 2 1051 #define ICE_NUM_QUAD_TYPE 2 1052 #define ICE_PORTS_PER_QUAD 4 1053 #define ICE_PHY_0_LAST_QUAD 1 1054 #define ICE_PORTS_PER_PHY 8 1055 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY 1056 1057 /* Active package version (currently active) */ 1058 struct ice_pkg_ver active_pkg_ver; 1059 u32 pkg_seg_id; 1060 u32 active_track_id; 1061 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 1062 u8 active_pkg_in_nvm; 1063 1064 enum ice_aq_err pkg_dwnld_status; 1065 1066 /* Driver's package ver - (from the Ice Metadata section) */ 1067 struct ice_pkg_ver pkg_ver; 1068 u8 pkg_name[ICE_PKG_NAME_SIZE]; 1069 1070 /* Driver's Ice segment format version and id (from the Ice seg) */ 1071 struct ice_pkg_ver ice_seg_fmt_ver; 1072 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 1073 1074 /* Pointer to the ice segment */ 1075 struct ice_seg *seg; 1076 1077 /* Pointer to allocated copy of pkg memory */ 1078 u8 *pkg_copy; 1079 u32 pkg_size; 1080 1081 /* tunneling info */ 1082 struct ice_lock tnl_lock; 1083 struct ice_tunnel_table tnl; 1084 1085 /* HW block tables */ 1086 struct ice_blk_info blk[ICE_BLK_COUNT]; 1087 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 1088 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT]; 1089 struct ice_lock rss_locks; /* protect RSS configuration */ 1090 struct LIST_HEAD_TYPE rss_list_head; 1091 struct ice_mbx_snapshot mbx_snapshot; 1092 u8 dvm_ena; 1093 }; 1094 1095 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1096 struct ice_eth_stats { 1097 u64 rx_bytes; /* gorc */ 1098 u64 rx_unicast; /* uprc */ 1099 u64 rx_multicast; /* mprc */ 1100 u64 rx_broadcast; /* bprc */ 1101 u64 rx_discards; /* rdpc */ 1102 u64 rx_unknown_protocol; /* rupp */ 1103 u64 tx_bytes; /* gotc */ 1104 u64 tx_unicast; /* uptc */ 1105 u64 tx_multicast; /* mptc */ 1106 u64 tx_broadcast; /* bptc */ 1107 u64 tx_discards; /* tdpc */ 1108 u64 tx_errors; /* tepc */ 1109 u64 rx_no_desc; /* repc */ 1110 u64 rx_errors; /* repc */ 1111 }; 1112 1113 #define ICE_MAX_UP 8 1114 1115 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */ 1116 struct ice_veb_up_stats { 1117 u64 up_rx_pkts[ICE_MAX_UP]; 1118 u64 up_rx_bytes[ICE_MAX_UP]; 1119 u64 up_tx_pkts[ICE_MAX_UP]; 1120 u64 up_tx_bytes[ICE_MAX_UP]; 1121 }; 1122 1123 /* Statistics collected by the MAC */ 1124 struct ice_hw_port_stats { 1125 /* eth stats collected by the port */ 1126 struct ice_eth_stats eth; 1127 /* additional port specific stats */ 1128 u64 tx_dropped_link_down; /* tdold */ 1129 u64 crc_errors; /* crcerrs */ 1130 u64 illegal_bytes; /* illerrc */ 1131 u64 error_bytes; /* errbc */ 1132 u64 mac_local_faults; /* mlfc */ 1133 u64 mac_remote_faults; /* mrfc */ 1134 u64 rx_len_errors; /* rlec */ 1135 u64 link_xon_rx; /* lxonrxc */ 1136 u64 link_xoff_rx; /* lxoffrxc */ 1137 u64 link_xon_tx; /* lxontxc */ 1138 u64 link_xoff_tx; /* lxofftxc */ 1139 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1140 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1141 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1142 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1143 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1144 u64 rx_size_64; /* prc64 */ 1145 u64 rx_size_127; /* prc127 */ 1146 u64 rx_size_255; /* prc255 */ 1147 u64 rx_size_511; /* prc511 */ 1148 u64 rx_size_1023; /* prc1023 */ 1149 u64 rx_size_1522; /* prc1522 */ 1150 u64 rx_size_big; /* prc9522 */ 1151 u64 rx_undersize; /* ruc */ 1152 u64 rx_fragments; /* rfc */ 1153 u64 rx_oversize; /* roc */ 1154 u64 rx_jabber; /* rjc */ 1155 u64 tx_size_64; /* ptc64 */ 1156 u64 tx_size_127; /* ptc127 */ 1157 u64 tx_size_255; /* ptc255 */ 1158 u64 tx_size_511; /* ptc511 */ 1159 u64 tx_size_1023; /* ptc1023 */ 1160 u64 tx_size_1522; /* ptc1522 */ 1161 u64 tx_size_big; /* ptc9522 */ 1162 u64 mac_short_pkt_dropped; /* mspdc */ 1163 /* EEE LPI */ 1164 u32 tx_lpi_status; 1165 u32 rx_lpi_status; 1166 u64 tx_lpi_count; /* etlpic */ 1167 u64 rx_lpi_count; /* erlpic */ 1168 }; 1169 1170 enum ice_sw_fwd_act_type { 1171 ICE_FWD_TO_VSI = 0, 1172 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 1173 ICE_FWD_TO_Q, 1174 ICE_FWD_TO_QGRP, 1175 ICE_DROP_PACKET, 1176 ICE_INVAL_ACT 1177 }; 1178 1179 struct ice_aq_get_set_rss_lut_params { 1180 u16 vsi_handle; /* software VSI handle */ 1181 u16 lut_size; /* size of the LUT buffer */ 1182 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1183 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1184 u8 global_lut_id; /* only valid when lut_type is global */ 1185 }; 1186 1187 /* Checksum and Shadow RAM pointers */ 1188 #define ICE_SR_NVM_CTRL_WORD 0x00 1189 #define ICE_SR_PHY_ANALOG_PTR 0x04 1190 #define ICE_SR_OPTION_ROM_PTR 0x05 1191 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1192 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1193 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1194 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09 1195 #define ICE_SR_EMP_IMAGE_PTR 0x0B 1196 #define ICE_SR_PE_IMAGE_PTR 0x0C 1197 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D 1198 #define ICE_SR_MNG_CFG_PTR 0x0E 1199 #define ICE_SR_EMP_MODULE_PTR 0x0F 1200 #define ICE_SR_PBA_BLOCK_PTR 0x16 1201 #define ICE_SR_BOOT_CFG_PTR 0x132 1202 #define ICE_SR_NVM_WOL_CFG 0x19 1203 #define ICE_NVM_OROM_VER_OFF 0x02 1204 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1205 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27 1206 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28 1207 #define ICE_SR_NVM_MAP_VER 0x29 1208 #define ICE_SR_NVM_IMAGE_VER 0x2A 1209 #define ICE_SR_NVM_STRUCTURE_VER 0x2B 1210 #define ICE_SR_NVM_EETRACK_LO 0x2D 1211 #define ICE_SR_NVM_EETRACK_HI 0x2E 1212 #define ICE_NVM_VER_LO_SHIFT 0 1213 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1214 #define ICE_NVM_VER_HI_SHIFT 12 1215 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1216 #define ICE_OEM_EETRACK_ID 0xffffffff 1217 #define ICE_OROM_VER_PATCH_SHIFT 0 1218 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1219 #define ICE_OROM_VER_BUILD_SHIFT 8 1220 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1221 #define ICE_OROM_VER_SHIFT 24 1222 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1223 #define ICE_SR_VPD_PTR 0x2F 1224 #define ICE_SR_PXE_SETUP_PTR 0x30 1225 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31 1226 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1227 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1228 #define ICE_SR_VLAN_CFG_PTR 0x37 1229 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1230 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1231 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1232 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1233 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D 1234 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1235 #define ICE_SR_SW_CHECKSUM_WORD 0x3F 1236 #define ICE_SR_PFA_PTR 0x40 1237 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41 1238 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1239 #define ICE_SR_NVM_BANK_SIZE 0x43 1240 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 1241 #define ICE_SR_OROM_BANK_SIZE 0x45 1242 #define ICE_SR_NETLIST_BANK_PTR 0x46 1243 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1244 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48 1245 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D 1246 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E 1247 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 1248 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118 1249 1250 /* CSS Header words */ 1251 #define ICE_NVM_CSS_HDR_LEN_L 0x02 1252 #define ICE_NVM_CSS_HDR_LEN_H 0x03 1253 #define ICE_NVM_CSS_SREV_L 0x14 1254 #define ICE_NVM_CSS_SREV_H 0x15 1255 1256 /* Length of Authentication header section in words */ 1257 #define ICE_NVM_AUTH_HEADER_LEN 0x08 1258 1259 /* The Link Topology Netlist section is stored as a series of words. It is 1260 * stored in the NVM as a TLV, with the first two words containing the type 1261 * and length. 1262 */ 1263 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1264 #define ICE_NETLIST_TYPE_OFFSET 0x0000 1265 #define ICE_NETLIST_LEN_OFFSET 0x0001 1266 1267 /* The Link Topology section follows the TLV header. When reading the netlist 1268 * using ice_read_netlist_module, we need to account for the 2-word TLV 1269 * header. 1270 */ 1271 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1272 1273 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1274 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1275 1276 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0) 1277 1278 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1279 #define ICE_NETLIST_ID_BLK_SIZE 0x30 1280 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1281 1282 /* netlist ID block field offsets (word offsets) */ 1283 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1284 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1285 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1286 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1287 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1288 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1289 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1290 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1291 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1292 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1293 1294 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1295 #define ICE_SR_VPD_SIZE_WORDS 512 1296 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512 1297 #define ICE_SR_CTRL_WORD_1_S 0x06 1298 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1299 #define ICE_SR_CTRL_WORD_VALID 0x1 1300 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1301 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1302 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1303 1304 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1305 1306 /* Shadow RAM related */ 1307 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1308 #define ICE_SR_BUF_ALIGNMENT 4096 1309 #define ICE_SR_WORDS_IN_1KB 512 1310 /* Checksum should be calculated such that after adding all the words, 1311 * including the checksum word itself, the sum should be 0xBABA. 1312 */ 1313 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA 1314 1315 /* Link override related */ 1316 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1317 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1318 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1319 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1320 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1321 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1322 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1323 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1324 1325 #define ICE_PBA_FLAG_DFLT 0xFAFA 1326 /* Hash redirection LUT for VSI - maximum array size */ 1327 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1328 1329 /* 1330 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register. 1331 * This is needed to determine the BAR0 space for the VFs 1332 */ 1333 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0 1334 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1 1335 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2 1336 1337 /* AQ API version for LLDP_FILTER_CONTROL */ 1338 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1339 #define ICE_FW_API_LLDP_FLTR_MIN 7 1340 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1341 1342 /* AQ API version for report default configuration */ 1343 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1344 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1345 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1346 1347 /* AQ API version for FW health reports */ 1348 #define ICE_FW_API_HEALTH_REPORT_MAJ 1 1349 #define ICE_FW_API_HEALTH_REPORT_MIN 7 1350 #define ICE_FW_API_HEALTH_REPORT_PATCH 6 1351 1352 /* AQ API version for FW auto drop reports */ 1353 #define ICE_FW_API_AUTO_DROP_MAJ 1 1354 #define ICE_FW_API_AUTO_DROP_MIN 4 1355 #endif /* _ICE_TYPE_H_ */ 1356