171d51719SMichael Gmelin /* 271d51719SMichael Gmelin * Copyright (c) 2014 The DragonFly Project. All rights reserved. 371d51719SMichael Gmelin * 471d51719SMichael Gmelin * This code is derived from software contributed to The DragonFly Project 571d51719SMichael Gmelin * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 671d51719SMichael Gmelin * to FreeBSD by Michael Gmelin <freebsd@grem.de> 771d51719SMichael Gmelin * 871d51719SMichael Gmelin * Redistribution and use in source and binary forms, with or without 971d51719SMichael Gmelin * modification, are permitted provided that the following conditions 1071d51719SMichael Gmelin * are met: 1171d51719SMichael Gmelin * 1271d51719SMichael Gmelin * 1. Redistributions of source code must retain the above copyright 1371d51719SMichael Gmelin * notice, this list of conditions and the following disclaimer. 1471d51719SMichael Gmelin * 2. Redistributions in binary form must reproduce the above copyright 1571d51719SMichael Gmelin * notice, this list of conditions and the following disclaimer in 1671d51719SMichael Gmelin * the documentation and/or other materials provided with the 1771d51719SMichael Gmelin * distribution. 1871d51719SMichael Gmelin * 3. Neither the name of The DragonFly Project nor the names of its 1971d51719SMichael Gmelin * contributors may be used to endorse or promote products derived 2071d51719SMichael Gmelin * from this software without specific, prior written permission. 2171d51719SMichael Gmelin * 2271d51719SMichael Gmelin * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2371d51719SMichael Gmelin * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2471d51719SMichael Gmelin * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 2571d51719SMichael Gmelin * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 2671d51719SMichael Gmelin * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 2771d51719SMichael Gmelin * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 2871d51719SMichael Gmelin * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2971d51719SMichael Gmelin * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 3071d51719SMichael Gmelin * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 3171d51719SMichael Gmelin * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 3271d51719SMichael Gmelin * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3371d51719SMichael Gmelin * SUCH DAMAGE. 3471d51719SMichael Gmelin */ 3571d51719SMichael Gmelin 3671d51719SMichael Gmelin #include <sys/cdefs.h> 3771d51719SMichael Gmelin __FBSDID("$FreeBSD$"); 3871d51719SMichael Gmelin 3971d51719SMichael Gmelin /* 40eb6befbaSAndriy Gapon * Intel fourth generation mobile cpus integrated I2C device. 4171d51719SMichael Gmelin * 4271d51719SMichael Gmelin * See ig4_reg.h for datasheet reference and notes. 434cd6abddSMichael Gmelin * See ig4_var.h for locking semantics. 4471d51719SMichael Gmelin */ 4571d51719SMichael Gmelin 4688512838SVladimir Kondratyev #include "opt_acpi.h" 4788512838SVladimir Kondratyev 4871d51719SMichael Gmelin #include <sys/param.h> 4971d51719SMichael Gmelin #include <sys/systm.h> 5071d51719SMichael Gmelin #include <sys/kernel.h> 5171d51719SMichael Gmelin #include <sys/module.h> 5271d51719SMichael Gmelin #include <sys/errno.h> 53c59aca57SVladimir Kondratyev #include <sys/kdb.h> 5471d51719SMichael Gmelin #include <sys/lock.h> 5571d51719SMichael Gmelin #include <sys/mutex.h> 56c59aca57SVladimir Kondratyev #include <sys/proc.h> 574cd6abddSMichael Gmelin #include <sys/sx.h> 5871d51719SMichael Gmelin #include <sys/syslog.h> 5971d51719SMichael Gmelin #include <sys/bus.h> 6071d51719SMichael Gmelin #include <sys/sysctl.h> 6171d51719SMichael Gmelin 6271d51719SMichael Gmelin #include <machine/bus.h> 6371d51719SMichael Gmelin #include <sys/rman.h> 6471d51719SMichael Gmelin 6588512838SVladimir Kondratyev #ifdef DEV_ACPI 6688512838SVladimir Kondratyev #include <contrib/dev/acpica/include/acpi.h> 6788512838SVladimir Kondratyev #include <contrib/dev/acpica/include/accommon.h> 6888512838SVladimir Kondratyev #include <dev/acpica/acpivar.h> 6988512838SVladimir Kondratyev #endif 7088512838SVladimir Kondratyev 7171d51719SMichael Gmelin #include <dev/pci/pcivar.h> 7271d51719SMichael Gmelin #include <dev/pci/pcireg.h> 73448897d3SAndriy Gapon #include <dev/iicbus/iicbus.h> 74448897d3SAndriy Gapon #include <dev/iicbus/iiconf.h> 7571d51719SMichael Gmelin 7671d51719SMichael Gmelin #include <dev/ichiic/ig4_reg.h> 7771d51719SMichael Gmelin #include <dev/ichiic/ig4_var.h> 7871d51719SMichael Gmelin 7971d51719SMichael Gmelin #define TRANS_NORMAL 1 8071d51719SMichael Gmelin #define TRANS_PCALL 2 8171d51719SMichael Gmelin #define TRANS_BLOCK 3 8271d51719SMichael Gmelin 8341b24e09SVladimir Kondratyev #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll) 84c59aca57SVladimir Kondratyev 8588512838SVladimir Kondratyev /* 8688512838SVladimir Kondratyev * tLOW, tHIGH periods of the SCL clock and maximal falling time of both 8788512838SVladimir Kondratyev * lines are taken from I2C specifications. 8888512838SVladimir Kondratyev */ 8988512838SVladimir Kondratyev #define IG4_SPEED_STD_THIGH 4000 /* nsec */ 9088512838SVladimir Kondratyev #define IG4_SPEED_STD_TLOW 4700 /* nsec */ 9188512838SVladimir Kondratyev #define IG4_SPEED_STD_TF_MAX 300 /* nsec */ 9288512838SVladimir Kondratyev #define IG4_SPEED_FAST_THIGH 600 /* nsec */ 9388512838SVladimir Kondratyev #define IG4_SPEED_FAST_TLOW 1300 /* nsec */ 9488512838SVladimir Kondratyev #define IG4_SPEED_FAST_TF_MAX 300 /* nsec */ 9588512838SVladimir Kondratyev 9688512838SVladimir Kondratyev /* 9788512838SVladimir Kondratyev * Ig4 hardware parameters except Haswell are taken from intel_lpss driver 9888512838SVladimir Kondratyev */ 9988512838SVladimir Kondratyev static const struct ig4_hw ig4iic_hw[] = { 10088512838SVladimir Kondratyev [IG4_HASWELL] = { 10188512838SVladimir Kondratyev .ic_clock_rate = 100, /* MHz */ 10288512838SVladimir Kondratyev .sda_hold_time = 90, /* nsec */ 10383a66b9bSVladimir Kondratyev .txfifo_depth = 32, 10483a66b9bSVladimir Kondratyev .rxfifo_depth = 32, 10588512838SVladimir Kondratyev }, 10688512838SVladimir Kondratyev [IG4_ATOM] = { 10788512838SVladimir Kondratyev .ic_clock_rate = 100, 10888512838SVladimir Kondratyev .sda_fall_time = 280, 10988512838SVladimir Kondratyev .scl_fall_time = 240, 11088512838SVladimir Kondratyev .sda_hold_time = 60, 11183a66b9bSVladimir Kondratyev .txfifo_depth = 32, 11283a66b9bSVladimir Kondratyev .rxfifo_depth = 32, 11388512838SVladimir Kondratyev }, 11488512838SVladimir Kondratyev [IG4_SKYLAKE] = { 11588512838SVladimir Kondratyev .ic_clock_rate = 120, 11688512838SVladimir Kondratyev .sda_hold_time = 230, 11788512838SVladimir Kondratyev }, 11888512838SVladimir Kondratyev [IG4_APL] = { 11988512838SVladimir Kondratyev .ic_clock_rate = 133, 12088512838SVladimir Kondratyev .sda_fall_time = 171, 12188512838SVladimir Kondratyev .scl_fall_time = 208, 12288512838SVladimir Kondratyev .sda_hold_time = 207, 12388512838SVladimir Kondratyev }, 12488512838SVladimir Kondratyev }; 12588512838SVladimir Kondratyev 12671d51719SMichael Gmelin static void ig4iic_intr(void *cookie); 12771d51719SMichael Gmelin static void ig4iic_dump(ig4iic_softc_t *sc); 12871d51719SMichael Gmelin 12971d51719SMichael Gmelin static int ig4_dump; 13012e413beSMichael Gmelin SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW, 13112e413beSMichael Gmelin &ig4_dump, 0, "Dump controller registers"); 13271d51719SMichael Gmelin 13371d51719SMichael Gmelin /* 13488512838SVladimir Kondratyev * Clock registers initialization control 13588512838SVladimir Kondratyev * 0 - Try read clock registers from ACPI and fallback to p.1. 13688512838SVladimir Kondratyev * 1 - Calculate values based on controller type (IC clock rate). 13788512838SVladimir Kondratyev * 2 - Use values inherited from DragonflyBSD driver (old behavior). 13888512838SVladimir Kondratyev * 3 - Keep clock registers intact. 13988512838SVladimir Kondratyev */ 14088512838SVladimir Kondratyev static int ig4_timings; 14188512838SVladimir Kondratyev SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0, 14288512838SVladimir Kondratyev "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change"); 14388512838SVladimir Kondratyev 14488512838SVladimir Kondratyev /* 14571d51719SMichael Gmelin * Low-level inline support functions 14671d51719SMichael Gmelin */ 14771d51719SMichael Gmelin static __inline void 14871d51719SMichael Gmelin reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) 14971d51719SMichael Gmelin { 15071d51719SMichael Gmelin bus_write_4(sc->regs_res, reg, value); 15171d51719SMichael Gmelin bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE); 15271d51719SMichael Gmelin } 15371d51719SMichael Gmelin 15471d51719SMichael Gmelin static __inline uint32_t 15571d51719SMichael Gmelin reg_read(ig4iic_softc_t *sc, uint32_t reg) 15671d51719SMichael Gmelin { 15771d51719SMichael Gmelin uint32_t value; 15871d51719SMichael Gmelin 15971d51719SMichael Gmelin bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ); 16071d51719SMichael Gmelin value = bus_read_4(sc->regs_res, reg); 16171d51719SMichael Gmelin return (value); 16271d51719SMichael Gmelin } 16371d51719SMichael Gmelin 16421e459c6SVladimir Kondratyev static void 16521e459c6SVladimir Kondratyev set_intr_mask(ig4iic_softc_t *sc, uint32_t val) 16621e459c6SVladimir Kondratyev { 16721e459c6SVladimir Kondratyev if (sc->intr_mask != val) { 16821e459c6SVladimir Kondratyev reg_write(sc, IG4_REG_INTR_MASK, val); 16921e459c6SVladimir Kondratyev sc->intr_mask = val; 17021e459c6SVladimir Kondratyev } 17121e459c6SVladimir Kondratyev } 17221e459c6SVladimir Kondratyev 17371d51719SMichael Gmelin /* 17471d51719SMichael Gmelin * Enable or disable the controller and wait for the controller to acknowledge 17571d51719SMichael Gmelin * the state change. 17671d51719SMichael Gmelin */ 17771d51719SMichael Gmelin static int 17871d51719SMichael Gmelin set_controller(ig4iic_softc_t *sc, uint32_t ctl) 17971d51719SMichael Gmelin { 18071d51719SMichael Gmelin int retry; 18171d51719SMichael Gmelin int error; 18271d51719SMichael Gmelin uint32_t v; 18371d51719SMichael Gmelin 1840ba5622dSMichael Gmelin /* 1850ba5622dSMichael Gmelin * When the controller is enabled, interrupt on STOP detect 1860ba5622dSMichael Gmelin * or receive character ready and clear pending interrupts. 1870ba5622dSMichael Gmelin */ 18821e459c6SVladimir Kondratyev set_intr_mask(sc, 0); 18921e459c6SVladimir Kondratyev if (ctl & IG4_I2C_ENABLE) 1900ba5622dSMichael Gmelin reg_read(sc, IG4_REG_CLR_INTR); 1910ba5622dSMichael Gmelin 19271d51719SMichael Gmelin reg_write(sc, IG4_REG_I2C_EN, ctl); 193448897d3SAndriy Gapon error = IIC_ETIMEOUT; 19471d51719SMichael Gmelin 19571d51719SMichael Gmelin for (retry = 100; retry > 0; --retry) { 19671d51719SMichael Gmelin v = reg_read(sc, IG4_REG_ENABLE_STATUS); 19771d51719SMichael Gmelin if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { 19871d51719SMichael Gmelin error = 0; 19971d51719SMichael Gmelin break; 20071d51719SMichael Gmelin } 20185cd895fSVladimir Kondratyev pause("i2cslv", 1); 20271d51719SMichael Gmelin } 20371d51719SMichael Gmelin return (error); 20471d51719SMichael Gmelin } 20571d51719SMichael Gmelin 20671d51719SMichael Gmelin /* 20771d51719SMichael Gmelin * Wait up to 25ms for the requested status using a 25uS polling loop. 20871d51719SMichael Gmelin */ 20971d51719SMichael Gmelin static int 21071d51719SMichael Gmelin wait_status(ig4iic_softc_t *sc, uint32_t status) 21171d51719SMichael Gmelin { 21271d51719SMichael Gmelin uint32_t v; 21371d51719SMichael Gmelin int error; 21471d51719SMichael Gmelin int txlvl = -1; 21571d51719SMichael Gmelin u_int count_us = 0; 21671d51719SMichael Gmelin u_int limit_us = 25000; /* 25ms */ 21771d51719SMichael Gmelin 218448897d3SAndriy Gapon error = IIC_ETIMEOUT; 21971d51719SMichael Gmelin 22071d51719SMichael Gmelin for (;;) { 22171d51719SMichael Gmelin /* 22271d51719SMichael Gmelin * Check requested status 22371d51719SMichael Gmelin */ 22471d51719SMichael Gmelin v = reg_read(sc, IG4_REG_I2C_STA); 22571d51719SMichael Gmelin if (v & status) { 22671d51719SMichael Gmelin error = 0; 22771d51719SMichael Gmelin break; 22871d51719SMichael Gmelin } 22971d51719SMichael Gmelin 23071d51719SMichael Gmelin /* 23171d51719SMichael Gmelin * When waiting for the transmit FIFO to become empty, 23271d51719SMichael Gmelin * reset the timeout if we see a change in the transmit 23371d51719SMichael Gmelin * FIFO level as progress is being made. 23471d51719SMichael Gmelin */ 23571d51719SMichael Gmelin if (status & IG4_STATUS_TX_EMPTY) { 23671d51719SMichael Gmelin v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; 23771d51719SMichael Gmelin if (txlvl != v) { 23871d51719SMichael Gmelin txlvl = v; 23971d51719SMichael Gmelin count_us = 0; 24071d51719SMichael Gmelin } 24171d51719SMichael Gmelin } 24271d51719SMichael Gmelin 24371d51719SMichael Gmelin /* 24471d51719SMichael Gmelin * Stop if we've run out of time. 24571d51719SMichael Gmelin */ 24671d51719SMichael Gmelin if (count_us >= limit_us) 24771d51719SMichael Gmelin break; 24871d51719SMichael Gmelin 24971d51719SMichael Gmelin /* 25071d51719SMichael Gmelin * When waiting for receive data let the interrupt do its 25171d51719SMichael Gmelin * work, otherwise poll with the lock held. 25271d51719SMichael Gmelin */ 253c59aca57SVladimir Kondratyev if ((status & IG4_STATUS_RX_NOTEMPTY) && !DO_POLL(sc)) { 254733d657aSVladimir Kondratyev mtx_lock(&sc->io_lock); 25521e459c6SVladimir Kondratyev set_intr_mask(sc, IG4_INTR_STOP_DET | IG4_INTR_RX_FULL); 2564cd6abddSMichael Gmelin mtx_sleep(sc, &sc->io_lock, 0, "i2cwait", 25771d51719SMichael Gmelin (hz + 99) / 100); /* sleep up to 10ms */ 25821e459c6SVladimir Kondratyev set_intr_mask(sc, 0); 259733d657aSVladimir Kondratyev mtx_unlock(&sc->io_lock); 26071d51719SMichael Gmelin count_us += 10000; 26171d51719SMichael Gmelin } else { 26271d51719SMichael Gmelin DELAY(25); 26371d51719SMichael Gmelin count_us += 25; 26471d51719SMichael Gmelin } 26571d51719SMichael Gmelin } 26671d51719SMichael Gmelin 26771d51719SMichael Gmelin return (error); 26871d51719SMichael Gmelin } 26971d51719SMichael Gmelin 27071d51719SMichael Gmelin /* 27171d51719SMichael Gmelin * Set the slave address. The controller must be disabled when 27271d51719SMichael Gmelin * changing the address. 27371d51719SMichael Gmelin * 27471d51719SMichael Gmelin * This operation does not issue anything to the I2C bus but sets 27571d51719SMichael Gmelin * the target address for when the controller later issues a START. 27671d51719SMichael Gmelin */ 27771d51719SMichael Gmelin static void 278e3d25549SAndriy Gapon set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) 27971d51719SMichael Gmelin { 28071d51719SMichael Gmelin uint32_t tar; 28171d51719SMichael Gmelin uint32_t ctl; 28271d51719SMichael Gmelin int use_10bit; 28371d51719SMichael Gmelin 28471d51719SMichael Gmelin use_10bit = 0; 28571d51719SMichael Gmelin if (sc->slave_valid && sc->last_slave == slave && 28671d51719SMichael Gmelin sc->use_10bit == use_10bit) { 28771d51719SMichael Gmelin return; 28871d51719SMichael Gmelin } 28971d51719SMichael Gmelin sc->use_10bit = use_10bit; 29071d51719SMichael Gmelin 29171d51719SMichael Gmelin /* 29271d51719SMichael Gmelin * Wait for TXFIFO to drain before disabling the controller. 29371d51719SMichael Gmelin * 29471d51719SMichael Gmelin * If a write message has not been completed it's really a 29571d51719SMichael Gmelin * programming error, but for now in that case issue an extra 29671d51719SMichael Gmelin * byte + STOP. 29771d51719SMichael Gmelin * 29871d51719SMichael Gmelin * If a read message has not been completed it's also a programming 29971d51719SMichael Gmelin * error, for now just ignore it. 30071d51719SMichael Gmelin */ 30171d51719SMichael Gmelin wait_status(sc, IG4_STATUS_TX_NOTFULL); 30271d51719SMichael Gmelin if (sc->write_started) { 30371d51719SMichael Gmelin reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP); 30471d51719SMichael Gmelin sc->write_started = 0; 30571d51719SMichael Gmelin } 30671d51719SMichael Gmelin if (sc->read_started) 30771d51719SMichael Gmelin sc->read_started = 0; 30871d51719SMichael Gmelin wait_status(sc, IG4_STATUS_TX_EMPTY); 30971d51719SMichael Gmelin 31071d51719SMichael Gmelin set_controller(sc, 0); 31171d51719SMichael Gmelin ctl = reg_read(sc, IG4_REG_CTL); 31271d51719SMichael Gmelin ctl &= ~IG4_CTL_10BIT; 31371d51719SMichael Gmelin ctl |= IG4_CTL_RESTARTEN; 31471d51719SMichael Gmelin 31571d51719SMichael Gmelin tar = slave; 31671d51719SMichael Gmelin if (sc->use_10bit) { 31771d51719SMichael Gmelin tar |= IG4_TAR_10BIT; 31871d51719SMichael Gmelin ctl |= IG4_CTL_10BIT; 31971d51719SMichael Gmelin } 32071d51719SMichael Gmelin reg_write(sc, IG4_REG_CTL, ctl); 32171d51719SMichael Gmelin reg_write(sc, IG4_REG_TAR_ADD, tar); 32271d51719SMichael Gmelin set_controller(sc, IG4_I2C_ENABLE); 32371d51719SMichael Gmelin sc->slave_valid = 1; 32471d51719SMichael Gmelin sc->last_slave = slave; 32571d51719SMichael Gmelin } 32671d51719SMichael Gmelin 32771d51719SMichael Gmelin /* 328448897d3SAndriy Gapon * IICBUS API FUNCTIONS 329448897d3SAndriy Gapon */ 330448897d3SAndriy Gapon static int 331448897d3SAndriy Gapon ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave) 332448897d3SAndriy Gapon { 333e3d25549SAndriy Gapon set_slave_addr(sc, slave >> 1); 334448897d3SAndriy Gapon return (0); 335448897d3SAndriy Gapon } 336448897d3SAndriy Gapon 33783a66b9bSVladimir Kondratyev /* 33883a66b9bSVladimir Kondratyev * Amount of unread data before next burst to get better I2C bus utilization. 33983a66b9bSVladimir Kondratyev * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes. 34083a66b9bSVladimir Kondratyev * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs. 34183a66b9bSVladimir Kondratyev */ 34283a66b9bSVladimir Kondratyev #define IG4_FIFO_LOWAT 2 34383a66b9bSVladimir Kondratyev 344448897d3SAndriy Gapon static int 345448897d3SAndriy Gapon ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, 346448897d3SAndriy Gapon bool repeated_start, bool stop) 347448897d3SAndriy Gapon { 348448897d3SAndriy Gapon uint32_t cmd; 34983a66b9bSVladimir Kondratyev int requested = 0; 35083a66b9bSVladimir Kondratyev int received = 0; 35183a66b9bSVladimir Kondratyev int burst, target, lowat = 0; 352448897d3SAndriy Gapon int error; 353448897d3SAndriy Gapon 354448897d3SAndriy Gapon if (len == 0) 355448897d3SAndriy Gapon return (0); 356448897d3SAndriy Gapon 35783a66b9bSVladimir Kondratyev while (received < len) { 35883a66b9bSVladimir Kondratyev burst = sc->cfg.txfifo_depth - 35983a66b9bSVladimir Kondratyev (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); 36083a66b9bSVladimir Kondratyev /* Ensure we have enough free space in RXFIFO */ 36183a66b9bSVladimir Kondratyev burst = MIN(burst, sc->cfg.rxfifo_depth - lowat); 36283a66b9bSVladimir Kondratyev if (burst <= 0) { 36383a66b9bSVladimir Kondratyev error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 364448897d3SAndriy Gapon if (error) 365448897d3SAndriy Gapon break; 36683a66b9bSVladimir Kondratyev burst = 1; 367448897d3SAndriy Gapon } 36883a66b9bSVladimir Kondratyev target = MIN(requested + burst, (int)len); 36983a66b9bSVladimir Kondratyev while (requested < target) { 37083a66b9bSVladimir Kondratyev cmd = IG4_DATA_COMMAND_RD; 37183a66b9bSVladimir Kondratyev if (repeated_start && requested == 0) 37283a66b9bSVladimir Kondratyev cmd |= IG4_DATA_RESTART; 37383a66b9bSVladimir Kondratyev if (stop && requested == len - 1) 37483a66b9bSVladimir Kondratyev cmd |= IG4_DATA_STOP; 37583a66b9bSVladimir Kondratyev reg_write(sc, IG4_REG_DATA_CMD, cmd); 37683a66b9bSVladimir Kondratyev requested++; 37783a66b9bSVladimir Kondratyev } 37883a66b9bSVladimir Kondratyev /* Leave some data queued to maintain the hardware pipeline */ 37983a66b9bSVladimir Kondratyev lowat = 0; 38083a66b9bSVladimir Kondratyev if (requested != len && requested - received > IG4_FIFO_LOWAT) 38183a66b9bSVladimir Kondratyev lowat = IG4_FIFO_LOWAT; 38283a66b9bSVladimir Kondratyev /* After TXFLR fills up, clear it by reading available data */ 38383a66b9bSVladimir Kondratyev while (received < requested - lowat) { 38483a66b9bSVladimir Kondratyev burst = MIN((int)len - received, 38583a66b9bSVladimir Kondratyev reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK); 38683a66b9bSVladimir Kondratyev if (burst > 0) { 38783a66b9bSVladimir Kondratyev while (burst--) 38883a66b9bSVladimir Kondratyev buf[received++] = 0xFF & 38983a66b9bSVladimir Kondratyev reg_read(sc, IG4_REG_DATA_CMD); 39083a66b9bSVladimir Kondratyev } else { 39183a66b9bSVladimir Kondratyev error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY); 39283a66b9bSVladimir Kondratyev if (error) 39383a66b9bSVladimir Kondratyev goto out; 39483a66b9bSVladimir Kondratyev } 39583a66b9bSVladimir Kondratyev } 39683a66b9bSVladimir Kondratyev } 39783a66b9bSVladimir Kondratyev out: 398448897d3SAndriy Gapon (void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 399448897d3SAndriy Gapon return (error); 400448897d3SAndriy Gapon } 401448897d3SAndriy Gapon 402448897d3SAndriy Gapon static int 403448897d3SAndriy Gapon ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, 404448897d3SAndriy Gapon bool repeated_start, bool stop) 405448897d3SAndriy Gapon { 406448897d3SAndriy Gapon uint32_t cmd; 407448897d3SAndriy Gapon uint16_t i; 408448897d3SAndriy Gapon int error; 409448897d3SAndriy Gapon 410448897d3SAndriy Gapon if (len == 0) 411448897d3SAndriy Gapon return (0); 412448897d3SAndriy Gapon 413448897d3SAndriy Gapon cmd = repeated_start ? IG4_DATA_RESTART : 0; 414448897d3SAndriy Gapon for (i = 0; i < len; i++) { 415448897d3SAndriy Gapon error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 416448897d3SAndriy Gapon if (error) 417448897d3SAndriy Gapon break; 418448897d3SAndriy Gapon cmd |= buf[i]; 419448897d3SAndriy Gapon cmd |= stop && i == len - 1 ? IG4_DATA_STOP : 0; 420448897d3SAndriy Gapon reg_write(sc, IG4_REG_DATA_CMD, cmd); 421448897d3SAndriy Gapon cmd = 0; 422448897d3SAndriy Gapon } 423448897d3SAndriy Gapon 424448897d3SAndriy Gapon (void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 425448897d3SAndriy Gapon return (error); 426448897d3SAndriy Gapon } 427448897d3SAndriy Gapon 428448897d3SAndriy Gapon int 429448897d3SAndriy Gapon ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 430448897d3SAndriy Gapon { 431448897d3SAndriy Gapon ig4iic_softc_t *sc = device_get_softc(dev); 432448897d3SAndriy Gapon const char *reason = NULL; 433448897d3SAndriy Gapon uint32_t i; 434448897d3SAndriy Gapon int error; 435448897d3SAndriy Gapon int unit; 436448897d3SAndriy Gapon bool rpstart; 437448897d3SAndriy Gapon bool stop; 43841b24e09SVladimir Kondratyev bool allocated; 439448897d3SAndriy Gapon 440448897d3SAndriy Gapon /* 441448897d3SAndriy Gapon * The hardware interface imposes limits on allowed I2C messages. 442448897d3SAndriy Gapon * It is not possible to explicitly send a start or stop. 443448897d3SAndriy Gapon * They are automatically sent (or not sent, depending on the 444448897d3SAndriy Gapon * configuration) when a data byte is transferred. 445448897d3SAndriy Gapon * For this reason it's impossible to send a message with no data 446448897d3SAndriy Gapon * at all (like an SMBus quick message). 447448897d3SAndriy Gapon * The start condition is automatically generated after the stop 448448897d3SAndriy Gapon * condition, so it's impossible to not have a start after a stop. 449448897d3SAndriy Gapon * The repeated start condition is automatically sent if a change 450448897d3SAndriy Gapon * of the transfer direction happens, so it's impossible to have 451448897d3SAndriy Gapon * a change of direction without a (repeated) start. 452448897d3SAndriy Gapon * The repeated start can be forced even without the change of 453448897d3SAndriy Gapon * direction. 454448897d3SAndriy Gapon * Changing the target slave address requires resetting the hardware 455448897d3SAndriy Gapon * state, so it's impossible to do that without the stop followed 456448897d3SAndriy Gapon * by the start. 457448897d3SAndriy Gapon */ 458448897d3SAndriy Gapon for (i = 0; i < nmsgs; i++) { 459448897d3SAndriy Gapon #if 0 460448897d3SAndriy Gapon if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) { 461448897d3SAndriy Gapon reason = "first message without start"; 462448897d3SAndriy Gapon break; 463448897d3SAndriy Gapon } 464448897d3SAndriy Gapon if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) { 465448897d3SAndriy Gapon reason = "last message without stop"; 466448897d3SAndriy Gapon break; 467448897d3SAndriy Gapon } 468448897d3SAndriy Gapon #endif 469448897d3SAndriy Gapon if (msgs[i].len == 0) { 470448897d3SAndriy Gapon reason = "message with no data"; 471448897d3SAndriy Gapon break; 472448897d3SAndriy Gapon } 473448897d3SAndriy Gapon if (i > 0) { 474448897d3SAndriy Gapon if ((msgs[i].flags & IIC_M_NOSTART) != 0 && 475448897d3SAndriy Gapon (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) { 476448897d3SAndriy Gapon reason = "stop not followed by start"; 477448897d3SAndriy Gapon break; 478448897d3SAndriy Gapon } 479448897d3SAndriy Gapon if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 && 480448897d3SAndriy Gapon msgs[i].slave != msgs[i - 1].slave) { 481448897d3SAndriy Gapon reason = "change of slave without stop"; 482448897d3SAndriy Gapon break; 483448897d3SAndriy Gapon } 484448897d3SAndriy Gapon if ((msgs[i].flags & IIC_M_NOSTART) != 0 && 485448897d3SAndriy Gapon (msgs[i].flags & IIC_M_RD) != 486448897d3SAndriy Gapon (msgs[i - 1].flags & IIC_M_RD)) { 487448897d3SAndriy Gapon reason = "change of direction without repeated" 488448897d3SAndriy Gapon " start"; 489448897d3SAndriy Gapon break; 490448897d3SAndriy Gapon } 491448897d3SAndriy Gapon } 492448897d3SAndriy Gapon } 493448897d3SAndriy Gapon if (reason != NULL) { 494448897d3SAndriy Gapon if (bootverbose) 495448897d3SAndriy Gapon device_printf(dev, "%s\n", reason); 496448897d3SAndriy Gapon return (IIC_ENOTSUPP); 497448897d3SAndriy Gapon } 498448897d3SAndriy Gapon 49941b24e09SVladimir Kondratyev /* Check if device is already allocated with iicbus_request_bus() */ 50041b24e09SVladimir Kondratyev allocated = sx_xlocked(&sc->call_lock) != 0; 50141b24e09SVladimir Kondratyev if (!allocated) 502448897d3SAndriy Gapon sx_xlock(&sc->call_lock); 503448897d3SAndriy Gapon 504448897d3SAndriy Gapon /* Debugging - dump registers. */ 505448897d3SAndriy Gapon if (ig4_dump) { 506448897d3SAndriy Gapon unit = device_get_unit(dev); 507448897d3SAndriy Gapon if (ig4_dump & (1 << unit)) { 508448897d3SAndriy Gapon ig4_dump &= ~(1 << unit); 509448897d3SAndriy Gapon ig4iic_dump(sc); 510448897d3SAndriy Gapon } 511448897d3SAndriy Gapon } 512448897d3SAndriy Gapon 513448897d3SAndriy Gapon /* 514448897d3SAndriy Gapon * Clear any previous abort condition that may have been holding 515448897d3SAndriy Gapon * the txfifo in reset. 516448897d3SAndriy Gapon */ 517448897d3SAndriy Gapon reg_read(sc, IG4_REG_CLR_TX_ABORT); 518448897d3SAndriy Gapon 519448897d3SAndriy Gapon rpstart = false; 520448897d3SAndriy Gapon error = 0; 521448897d3SAndriy Gapon for (i = 0; i < nmsgs; i++) { 522448897d3SAndriy Gapon if ((msgs[i].flags & IIC_M_NOSTART) == 0) { 523448897d3SAndriy Gapon error = ig4iic_xfer_start(sc, msgs[i].slave); 524448897d3SAndriy Gapon } else { 525448897d3SAndriy Gapon if (!sc->slave_valid || 526448897d3SAndriy Gapon (msgs[i].slave >> 1) != sc->last_slave) { 527448897d3SAndriy Gapon device_printf(dev, "start condition suppressed" 528448897d3SAndriy Gapon "but slave address is not set up"); 529448897d3SAndriy Gapon error = EINVAL; 530448897d3SAndriy Gapon break; 531448897d3SAndriy Gapon } 532448897d3SAndriy Gapon rpstart = false; 533448897d3SAndriy Gapon } 534448897d3SAndriy Gapon if (error != 0) 535448897d3SAndriy Gapon break; 536448897d3SAndriy Gapon 537448897d3SAndriy Gapon stop = (msgs[i].flags & IIC_M_NOSTOP) == 0; 538448897d3SAndriy Gapon if (msgs[i].flags & IIC_M_RD) 539448897d3SAndriy Gapon error = ig4iic_read(sc, msgs[i].buf, msgs[i].len, 540448897d3SAndriy Gapon rpstart, stop); 541448897d3SAndriy Gapon else 542448897d3SAndriy Gapon error = ig4iic_write(sc, msgs[i].buf, msgs[i].len, 543448897d3SAndriy Gapon rpstart, stop); 544448897d3SAndriy Gapon if (error != 0) 545448897d3SAndriy Gapon break; 546448897d3SAndriy Gapon 547448897d3SAndriy Gapon rpstart = !stop; 548448897d3SAndriy Gapon } 549448897d3SAndriy Gapon 55041b24e09SVladimir Kondratyev if (!allocated) 551448897d3SAndriy Gapon sx_unlock(&sc->call_lock); 552448897d3SAndriy Gapon return (error); 553448897d3SAndriy Gapon } 554448897d3SAndriy Gapon 555448897d3SAndriy Gapon int 556448897d3SAndriy Gapon ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 557448897d3SAndriy Gapon { 558448897d3SAndriy Gapon ig4iic_softc_t *sc = device_get_softc(dev); 55941b24e09SVladimir Kondratyev bool allocated; 560448897d3SAndriy Gapon 56141b24e09SVladimir Kondratyev allocated = sx_xlocked(&sc->call_lock) != 0; 56241b24e09SVladimir Kondratyev if (!allocated) 563448897d3SAndriy Gapon sx_xlock(&sc->call_lock); 564448897d3SAndriy Gapon 565448897d3SAndriy Gapon /* TODO handle speed configuration? */ 566448897d3SAndriy Gapon if (oldaddr != NULL) 567448897d3SAndriy Gapon *oldaddr = sc->last_slave << 1; 568e3d25549SAndriy Gapon set_slave_addr(sc, addr >> 1); 569448897d3SAndriy Gapon if (addr == IIC_UNKNOWN) 570448897d3SAndriy Gapon sc->slave_valid = false; 571448897d3SAndriy Gapon 57241b24e09SVladimir Kondratyev if (!allocated) 573448897d3SAndriy Gapon sx_unlock(&sc->call_lock); 574448897d3SAndriy Gapon return (0); 575448897d3SAndriy Gapon } 576448897d3SAndriy Gapon 57741b24e09SVladimir Kondratyev int 57841b24e09SVladimir Kondratyev ig4iic_callback(device_t dev, int index, caddr_t data) 57941b24e09SVladimir Kondratyev { 58041b24e09SVladimir Kondratyev ig4iic_softc_t *sc = device_get_softc(dev); 58141b24e09SVladimir Kondratyev int error = 0; 58241b24e09SVladimir Kondratyev int how; 58341b24e09SVladimir Kondratyev 58441b24e09SVladimir Kondratyev switch (index) { 58541b24e09SVladimir Kondratyev case IIC_REQUEST_BUS: 58641b24e09SVladimir Kondratyev /* force polling if ig4iic is requested with IIC_DONTWAIT */ 58741b24e09SVladimir Kondratyev how = *(int *)data; 58841b24e09SVladimir Kondratyev if ((how & IIC_WAIT) == 0) { 58941b24e09SVladimir Kondratyev if (sx_try_xlock(&sc->call_lock) == 0) 59041b24e09SVladimir Kondratyev error = IIC_EBUSBSY; 59141b24e09SVladimir Kondratyev else 59241b24e09SVladimir Kondratyev sc->poll = true; 59341b24e09SVladimir Kondratyev } else 59441b24e09SVladimir Kondratyev sx_xlock(&sc->call_lock); 59541b24e09SVladimir Kondratyev break; 59641b24e09SVladimir Kondratyev 59741b24e09SVladimir Kondratyev case IIC_RELEASE_BUS: 59841b24e09SVladimir Kondratyev sc->poll = false; 59941b24e09SVladimir Kondratyev sx_unlock(&sc->call_lock); 60041b24e09SVladimir Kondratyev break; 60141b24e09SVladimir Kondratyev 60241b24e09SVladimir Kondratyev default: 60341b24e09SVladimir Kondratyev error = errno2iic(EINVAL); 60441b24e09SVladimir Kondratyev } 60541b24e09SVladimir Kondratyev 60641b24e09SVladimir Kondratyev return (error); 60741b24e09SVladimir Kondratyev } 60841b24e09SVladimir Kondratyev 609448897d3SAndriy Gapon /* 61088512838SVladimir Kondratyev * Clock register values can be calculated with following rough equations: 61188512838SVladimir Kondratyev * SCL_HCNT = ceil(IC clock rate * tHIGH) 61288512838SVladimir Kondratyev * SCL_LCNT = ceil(IC clock rate * tLOW) 61388512838SVladimir Kondratyev * SDA_HOLD = ceil(IC clock rate * SDA hold time) 61488512838SVladimir Kondratyev * Precise equations take signal's falling, rising and spike suppression 61588512838SVladimir Kondratyev * times in to account. They can be found in Synopsys or Intel documentation. 61688512838SVladimir Kondratyev * 61788512838SVladimir Kondratyev * Here we snarf formulas and defaults from Linux driver to be able to use 61888512838SVladimir Kondratyev * timing values provided by Intel LPSS driver "as is". 61988512838SVladimir Kondratyev */ 62088512838SVladimir Kondratyev static int 62188512838SVladimir Kondratyev ig4iic_clk_params(const struct ig4_hw *hw, int speed, 62288512838SVladimir Kondratyev uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) 62388512838SVladimir Kondratyev { 62488512838SVladimir Kondratyev uint32_t thigh, tlow, tf_max; /* nsec */ 62588512838SVladimir Kondratyev uint32_t sda_fall_time; /* nsec */ 62688512838SVladimir Kondratyev uint32_t scl_fall_time; /* nsec */ 62788512838SVladimir Kondratyev 62888512838SVladimir Kondratyev switch (speed) { 62988512838SVladimir Kondratyev case IG4_CTL_SPEED_STD: 63088512838SVladimir Kondratyev thigh = IG4_SPEED_STD_THIGH; 63188512838SVladimir Kondratyev tlow = IG4_SPEED_STD_TLOW; 63288512838SVladimir Kondratyev tf_max = IG4_SPEED_STD_TF_MAX; 63388512838SVladimir Kondratyev break; 63488512838SVladimir Kondratyev 63588512838SVladimir Kondratyev case IG4_CTL_SPEED_FAST: 63688512838SVladimir Kondratyev thigh = IG4_SPEED_FAST_THIGH; 63788512838SVladimir Kondratyev tlow = IG4_SPEED_FAST_TLOW; 63888512838SVladimir Kondratyev tf_max = IG4_SPEED_FAST_TF_MAX; 63988512838SVladimir Kondratyev break; 64088512838SVladimir Kondratyev 64188512838SVladimir Kondratyev default: 64288512838SVladimir Kondratyev return (EINVAL); 64388512838SVladimir Kondratyev } 64488512838SVladimir Kondratyev 64588512838SVladimir Kondratyev /* Use slowest falling time defaults to be on the safe side */ 64688512838SVladimir Kondratyev sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time; 64788512838SVladimir Kondratyev *scl_hcnt = (uint16_t) 64888512838SVladimir Kondratyev ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3); 64988512838SVladimir Kondratyev 65088512838SVladimir Kondratyev scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time; 65188512838SVladimir Kondratyev *scl_lcnt = (uint16_t) 65288512838SVladimir Kondratyev ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1); 65388512838SVladimir Kondratyev 65488512838SVladimir Kondratyev /* 65588512838SVladimir Kondratyev * There is no "known good" default value for tHD;DAT so keep SDA_HOLD 65688512838SVladimir Kondratyev * intact if sda_hold_time value is not provided. 65788512838SVladimir Kondratyev */ 65888512838SVladimir Kondratyev if (hw->sda_hold_time != 0) 65988512838SVladimir Kondratyev *sda_hold = (uint16_t) 66088512838SVladimir Kondratyev ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000); 66188512838SVladimir Kondratyev 66288512838SVladimir Kondratyev return (0); 66388512838SVladimir Kondratyev } 66488512838SVladimir Kondratyev 66588512838SVladimir Kondratyev #ifdef DEV_ACPI 66688512838SVladimir Kondratyev static ACPI_STATUS 66788512838SVladimir Kondratyev ig4iic_acpi_params(ACPI_HANDLE handle, char *method, 66888512838SVladimir Kondratyev uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) 66988512838SVladimir Kondratyev { 67088512838SVladimir Kondratyev ACPI_BUFFER buf; 67188512838SVladimir Kondratyev ACPI_OBJECT *obj, *elems; 67288512838SVladimir Kondratyev ACPI_STATUS status; 67388512838SVladimir Kondratyev 67488512838SVladimir Kondratyev buf.Pointer = NULL; 67588512838SVladimir Kondratyev buf.Length = ACPI_ALLOCATE_BUFFER; 67688512838SVladimir Kondratyev 67788512838SVladimir Kondratyev status = AcpiEvaluateObject(handle, method, NULL, &buf); 67888512838SVladimir Kondratyev if (ACPI_FAILURE(status)) 67988512838SVladimir Kondratyev return (status); 68088512838SVladimir Kondratyev 68188512838SVladimir Kondratyev status = AE_TYPE; 68288512838SVladimir Kondratyev obj = (ACPI_OBJECT *)buf.Pointer; 68388512838SVladimir Kondratyev if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) { 68488512838SVladimir Kondratyev elems = obj->Package.Elements; 68588512838SVladimir Kondratyev *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK; 68688512838SVladimir Kondratyev *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK; 68788512838SVladimir Kondratyev *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK; 68888512838SVladimir Kondratyev status = AE_OK; 68988512838SVladimir Kondratyev } 69088512838SVladimir Kondratyev 69188512838SVladimir Kondratyev AcpiOsFree(obj); 69288512838SVladimir Kondratyev 69388512838SVladimir Kondratyev return (status); 69488512838SVladimir Kondratyev } 69588512838SVladimir Kondratyev #endif /* DEV_ACPI */ 69688512838SVladimir Kondratyev 69788512838SVladimir Kondratyev static void 69888512838SVladimir Kondratyev ig4iic_get_config(ig4iic_softc_t *sc) 69988512838SVladimir Kondratyev { 70088512838SVladimir Kondratyev const struct ig4_hw *hw; 70183a66b9bSVladimir Kondratyev uint32_t v; 70288512838SVladimir Kondratyev #ifdef DEV_ACPI 70388512838SVladimir Kondratyev ACPI_HANDLE handle; 70488512838SVladimir Kondratyev #endif 70588512838SVladimir Kondratyev /* Fetch default hardware config from controller */ 70688512838SVladimir Kondratyev sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER); 70788512838SVladimir Kondratyev sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK; 70888512838SVladimir Kondratyev sc->cfg.ss_scl_hcnt = 70988512838SVladimir Kondratyev reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; 71088512838SVladimir Kondratyev sc->cfg.ss_scl_lcnt = 71188512838SVladimir Kondratyev reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; 71288512838SVladimir Kondratyev sc->cfg.fs_scl_hcnt = 71388512838SVladimir Kondratyev reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; 71488512838SVladimir Kondratyev sc->cfg.fs_scl_lcnt = 71588512838SVladimir Kondratyev reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; 71688512838SVladimir Kondratyev sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 71788512838SVladimir Kondratyev reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK; 71888512838SVladimir Kondratyev 71988512838SVladimir Kondratyev if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD) 72088512838SVladimir Kondratyev sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; 72188512838SVladimir Kondratyev 72283a66b9bSVladimir Kondratyev /* REG_COMP_PARAM1 is not documented in latest Intel specs */ 72383a66b9bSVladimir Kondratyev if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 72483a66b9bSVladimir Kondratyev v = reg_read(sc, IG4_REG_COMP_PARAM1); 72583a66b9bSVladimir Kondratyev if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0) 72683a66b9bSVladimir Kondratyev sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v); 72783a66b9bSVladimir Kondratyev if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0) 72883a66b9bSVladimir Kondratyev sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v); 72983a66b9bSVladimir Kondratyev } else { 73083a66b9bSVladimir Kondratyev /* 73183a66b9bSVladimir Kondratyev * Hardware does not allow FIFO Threshold Levels value to be 73283a66b9bSVladimir Kondratyev * set larger than the depth of the buffer. If an attempt is 73383a66b9bSVladimir Kondratyev * made to do that, the actual value set will be the maximum 73483a66b9bSVladimir Kondratyev * depth of the buffer. 73583a66b9bSVladimir Kondratyev */ 73683a66b9bSVladimir Kondratyev v = reg_read(sc, IG4_REG_TX_TL); 73783a66b9bSVladimir Kondratyev reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK); 73883a66b9bSVladimir Kondratyev sc->cfg.txfifo_depth = 73983a66b9bSVladimir Kondratyev (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1; 74083a66b9bSVladimir Kondratyev reg_write(sc, IG4_REG_TX_TL, v); 74183a66b9bSVladimir Kondratyev v = reg_read(sc, IG4_REG_RX_TL); 74283a66b9bSVladimir Kondratyev reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK); 74383a66b9bSVladimir Kondratyev sc->cfg.rxfifo_depth = 74483a66b9bSVladimir Kondratyev (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1; 74583a66b9bSVladimir Kondratyev reg_write(sc, IG4_REG_RX_TL, v); 74683a66b9bSVladimir Kondratyev } 74783a66b9bSVladimir Kondratyev 74888512838SVladimir Kondratyev /* Override hardware config with IC_clock-based counter values */ 74988512838SVladimir Kondratyev if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) { 75088512838SVladimir Kondratyev hw = &ig4iic_hw[sc->version]; 75188512838SVladimir Kondratyev sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; 75288512838SVladimir Kondratyev ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt, 75388512838SVladimir Kondratyev &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); 75488512838SVladimir Kondratyev ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt, 75588512838SVladimir Kondratyev &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); 75683a66b9bSVladimir Kondratyev if (hw->txfifo_depth != 0) 75783a66b9bSVladimir Kondratyev sc->cfg.txfifo_depth = hw->txfifo_depth; 75883a66b9bSVladimir Kondratyev if (hw->rxfifo_depth != 0) 75983a66b9bSVladimir Kondratyev sc->cfg.rxfifo_depth = hw->rxfifo_depth; 76088512838SVladimir Kondratyev } else if (ig4_timings == 2) { 76188512838SVladimir Kondratyev /* 76288512838SVladimir Kondratyev * Timings of original ig4 driver: 76388512838SVladimir Kondratyev * Program based on a 25000 Hz clock. This is a bit of a 76488512838SVladimir Kondratyev * hack (obviously). The defaults are 400 and 470 for standard 76588512838SVladimir Kondratyev * and 60 and 130 for fast. The defaults for standard fail 76688512838SVladimir Kondratyev * utterly (presumably cause an abort) because the clock time 76788512838SVladimir Kondratyev * is ~18.8ms by default. This brings it down to ~4ms. 76888512838SVladimir Kondratyev */ 76988512838SVladimir Kondratyev sc->cfg.bus_speed = IG4_CTL_SPEED_STD; 77088512838SVladimir Kondratyev sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100; 77188512838SVladimir Kondratyev sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125; 77288512838SVladimir Kondratyev if (sc->version == IG4_SKYLAKE) 77388512838SVladimir Kondratyev sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28; 77488512838SVladimir Kondratyev } 77588512838SVladimir Kondratyev 77688512838SVladimir Kondratyev #ifdef DEV_ACPI 77788512838SVladimir Kondratyev /* Evaluate SSCN and FMCN ACPI methods to fetch timings */ 77888512838SVladimir Kondratyev if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) { 77988512838SVladimir Kondratyev ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt, 78088512838SVladimir Kondratyev &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); 78188512838SVladimir Kondratyev ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt, 78288512838SVladimir Kondratyev &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); 78388512838SVladimir Kondratyev } 78488512838SVladimir Kondratyev #endif 78588512838SVladimir Kondratyev 78688512838SVladimir Kondratyev if (bootverbose) { 78788512838SVladimir Kondratyev device_printf(sc->dev, "Controller parameters:\n"); 78888512838SVladimir Kondratyev printf(" Speed: %s\n", 78988512838SVladimir Kondratyev sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast"); 79088512838SVladimir Kondratyev printf(" Regs: HCNT :LCNT :SDAHLD\n"); 79188512838SVladimir Kondratyev printf(" Std: 0x%04hx:0x%04hx:0x%04hx\n", 79288512838SVladimir Kondratyev sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt, 79388512838SVladimir Kondratyev sc->cfg.ss_sda_hold); 79488512838SVladimir Kondratyev printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n", 79588512838SVladimir Kondratyev sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt, 79688512838SVladimir Kondratyev sc->cfg.fs_sda_hold); 79783a66b9bSVladimir Kondratyev printf(" FIFO: RX:0x%04x: TX:0x%04x\n", 79883a66b9bSVladimir Kondratyev sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth); 79988512838SVladimir Kondratyev } 80088512838SVladimir Kondratyev } 80188512838SVladimir Kondratyev 80288512838SVladimir Kondratyev /* 80371d51719SMichael Gmelin * Called from ig4iic_pci_attach/detach() 80471d51719SMichael Gmelin */ 80571d51719SMichael Gmelin int 80671d51719SMichael Gmelin ig4iic_attach(ig4iic_softc_t *sc) 80771d51719SMichael Gmelin { 80871d51719SMichael Gmelin int error; 80971d51719SMichael Gmelin uint32_t v; 81071d51719SMichael Gmelin 8115c5bcb1dSOleksandr Tymoshenko mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF); 8125c5bcb1dSOleksandr Tymoshenko sx_init(&sc->call_lock, "IG4 call lock"); 8135c5bcb1dSOleksandr Tymoshenko 81488512838SVladimir Kondratyev ig4iic_get_config(sc); 81588512838SVladimir Kondratyev 816b16d03adSOleksandr Tymoshenko v = reg_read(sc, IG4_REG_DEVIDLE_CTRL); 817b16d03adSOleksandr Tymoshenko if (sc->version == IG4_SKYLAKE && (v & IG4_RESTORE_REQUIRED) ) { 818b16d03adSOleksandr Tymoshenko reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED); 819b16d03adSOleksandr Tymoshenko reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0); 820b16d03adSOleksandr Tymoshenko 821b16d03adSOleksandr Tymoshenko reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 822b16d03adSOleksandr Tymoshenko reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); 823b16d03adSOleksandr Tymoshenko DELAY(1000); 824b16d03adSOleksandr Tymoshenko } 825b16d03adSOleksandr Tymoshenko 826b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_ATOM) 82771d51719SMichael Gmelin v = reg_read(sc, IG4_REG_COMP_TYPE); 828b3e8ee5dSOleksandr Tymoshenko 829b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 83071d51719SMichael Gmelin v = reg_read(sc, IG4_REG_COMP_PARAM1); 83171d51719SMichael Gmelin v = reg_read(sc, IG4_REG_GENERAL); 832b3e8ee5dSOleksandr Tymoshenko /* 833b3e8ee5dSOleksandr Tymoshenko * The content of IG4_REG_GENERAL is different for each 834b3e8ee5dSOleksandr Tymoshenko * controller version. 835b3e8ee5dSOleksandr Tymoshenko */ 836b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_HASWELL && 837b3e8ee5dSOleksandr Tymoshenko (v & IG4_GENERAL_SWMODE) == 0) { 83871d51719SMichael Gmelin v |= IG4_GENERAL_SWMODE; 83971d51719SMichael Gmelin reg_write(sc, IG4_REG_GENERAL, v); 84071d51719SMichael Gmelin v = reg_read(sc, IG4_REG_GENERAL); 84171d51719SMichael Gmelin } 842b3e8ee5dSOleksandr Tymoshenko } 84371d51719SMichael Gmelin 844b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_HASWELL) { 84571d51719SMichael Gmelin v = reg_read(sc, IG4_REG_SW_LTR_VALUE); 84671d51719SMichael Gmelin v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); 847b3e8ee5dSOleksandr Tymoshenko } else if (sc->version == IG4_SKYLAKE) { 848b3e8ee5dSOleksandr Tymoshenko v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); 849b3e8ee5dSOleksandr Tymoshenko v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); 850b3e8ee5dSOleksandr Tymoshenko } 85171d51719SMichael Gmelin 852b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 85371d51719SMichael Gmelin v = reg_read(sc, IG4_REG_COMP_VER); 8545747fe4fSOleksandr Tymoshenko if (v < IG4_COMP_MIN_VER) { 85571d51719SMichael Gmelin error = ENXIO; 85671d51719SMichael Gmelin goto done; 85771d51719SMichael Gmelin } 858b3e8ee5dSOleksandr Tymoshenko } 859d117e363SVladimir Kondratyev 860d117e363SVladimir Kondratyev if (set_controller(sc, 0)) { 861d117e363SVladimir Kondratyev device_printf(sc->dev, "controller error during attach-1\n"); 862d117e363SVladimir Kondratyev error = ENXIO; 863d117e363SVladimir Kondratyev goto done; 864d117e363SVladimir Kondratyev } 865d117e363SVladimir Kondratyev 86621e459c6SVladimir Kondratyev reg_read(sc, IG4_REG_CLR_INTR); 86721e459c6SVladimir Kondratyev reg_write(sc, IG4_REG_INTR_MASK, 0); 86821e459c6SVladimir Kondratyev sc->intr_mask = 0; 86921e459c6SVladimir Kondratyev 87088512838SVladimir Kondratyev reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt); 87188512838SVladimir Kondratyev reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt); 87288512838SVladimir Kondratyev reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt); 87388512838SVladimir Kondratyev reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt); 87488512838SVladimir Kondratyev reg_write(sc, IG4_REG_SDA_HOLD, 87588512838SVladimir Kondratyev (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ? 87688512838SVladimir Kondratyev sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold); 87771d51719SMichael Gmelin 87871d51719SMichael Gmelin /* 87971d51719SMichael Gmelin * Use a threshold of 1 so we get interrupted on each character, 88071d51719SMichael Gmelin * allowing us to use mtx_sleep() in our poll code. Not perfect 88171d51719SMichael Gmelin * but this is better than using DELAY() for receiving data. 8824cd6abddSMichael Gmelin * 8834cd6abddSMichael Gmelin * See ig4_var.h for details on interrupt handler synchronization. 88471d51719SMichael Gmelin */ 885811ff4ddSVladimir Kondratyev reg_write(sc, IG4_REG_RX_TL, 0); 88671d51719SMichael Gmelin 88771d51719SMichael Gmelin reg_write(sc, IG4_REG_CTL, 88871d51719SMichael Gmelin IG4_CTL_MASTER | 88971d51719SMichael Gmelin IG4_CTL_SLAVE_DISABLE | 89071d51719SMichael Gmelin IG4_CTL_RESTARTEN | 89188512838SVladimir Kondratyev (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK)); 89271d51719SMichael Gmelin 893448897d3SAndriy Gapon sc->iicbus = device_add_child(sc->dev, "iicbus", -1); 894448897d3SAndriy Gapon if (sc->iicbus == NULL) { 895448897d3SAndriy Gapon device_printf(sc->dev, "iicbus driver not found\n"); 89671d51719SMichael Gmelin error = ENXIO; 89771d51719SMichael Gmelin goto done; 89871d51719SMichael Gmelin } 89971d51719SMichael Gmelin 90071d51719SMichael Gmelin #if 0 90171d51719SMichael Gmelin /* 90271d51719SMichael Gmelin * Don't do this, it blows up the PCI config 90371d51719SMichael Gmelin */ 904b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 905b3e8ee5dSOleksandr Tymoshenko reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); 906b3e8ee5dSOleksandr Tymoshenko reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); 907b3e8ee5dSOleksandr Tymoshenko } else if (sc->version = IG4_SKYLAKE) { 908b3e8ee5dSOleksandr Tymoshenko reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 909b3e8ee5dSOleksandr Tymoshenko reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); 910b3e8ee5dSOleksandr Tymoshenko } 91171d51719SMichael Gmelin #endif 91271d51719SMichael Gmelin 913bf9c3c58SVladimir Kondratyev if (set_controller(sc, IG4_I2C_ENABLE)) { 91471d51719SMichael Gmelin device_printf(sc->dev, "controller error during attach-2\n"); 915bf9c3c58SVladimir Kondratyev error = ENXIO; 916bf9c3c58SVladimir Kondratyev goto done; 917bf9c3c58SVladimir Kondratyev } 918edcf6a9fSVladimir Kondratyev if (set_controller(sc, 0)) { 919edcf6a9fSVladimir Kondratyev device_printf(sc->dev, "controller error during attach-3\n"); 920edcf6a9fSVladimir Kondratyev error = ENXIO; 921edcf6a9fSVladimir Kondratyev goto done; 922edcf6a9fSVladimir Kondratyev } 92371d51719SMichael Gmelin error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE, 92471d51719SMichael Gmelin NULL, ig4iic_intr, sc, &sc->intr_handle); 92571d51719SMichael Gmelin if (error) { 92671d51719SMichael Gmelin device_printf(sc->dev, 92771d51719SMichael Gmelin "Unable to setup irq: error %d\n", error); 92871d51719SMichael Gmelin } 92971d51719SMichael Gmelin 93071d51719SMichael Gmelin error = bus_generic_attach(sc->dev); 93171d51719SMichael Gmelin if (error) { 93271d51719SMichael Gmelin device_printf(sc->dev, 93371d51719SMichael Gmelin "failed to attach child: error %d\n", error); 93471d51719SMichael Gmelin } 9356777ccd9SVladimir Kondratyev 9366777ccd9SVladimir Kondratyev done: 9376777ccd9SVladimir Kondratyev return (error); 93871d51719SMichael Gmelin } 93971d51719SMichael Gmelin 94071d51719SMichael Gmelin int 94171d51719SMichael Gmelin ig4iic_detach(ig4iic_softc_t *sc) 94271d51719SMichael Gmelin { 94371d51719SMichael Gmelin int error; 94471d51719SMichael Gmelin 94571d51719SMichael Gmelin if (device_is_attached(sc->dev)) { 94671d51719SMichael Gmelin error = bus_generic_detach(sc->dev); 94771d51719SMichael Gmelin if (error) 94871d51719SMichael Gmelin return (error); 94971d51719SMichael Gmelin } 950448897d3SAndriy Gapon if (sc->iicbus) 951448897d3SAndriy Gapon device_delete_child(sc->dev, sc->iicbus); 95271d51719SMichael Gmelin if (sc->intr_handle) 95371d51719SMichael Gmelin bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); 95471d51719SMichael Gmelin 9554cd6abddSMichael Gmelin sx_xlock(&sc->call_lock); 95671d51719SMichael Gmelin 957448897d3SAndriy Gapon sc->iicbus = NULL; 95871d51719SMichael Gmelin sc->intr_handle = NULL; 95971d51719SMichael Gmelin reg_write(sc, IG4_REG_INTR_MASK, 0); 96071d51719SMichael Gmelin set_controller(sc, 0); 96171d51719SMichael Gmelin 9624cd6abddSMichael Gmelin sx_xunlock(&sc->call_lock); 9635c5bcb1dSOleksandr Tymoshenko 9645c5bcb1dSOleksandr Tymoshenko mtx_destroy(&sc->io_lock); 9655c5bcb1dSOleksandr Tymoshenko sx_destroy(&sc->call_lock); 9665c5bcb1dSOleksandr Tymoshenko 96771d51719SMichael Gmelin return (0); 96871d51719SMichael Gmelin } 96971d51719SMichael Gmelin 97071d51719SMichael Gmelin /* 9714cd6abddSMichael Gmelin * Interrupt Operation, see ig4_var.h for locking semantics. 97271d51719SMichael Gmelin */ 97371d51719SMichael Gmelin static void 97471d51719SMichael Gmelin ig4iic_intr(void *cookie) 97571d51719SMichael Gmelin { 97671d51719SMichael Gmelin ig4iic_softc_t *sc = cookie; 97771d51719SMichael Gmelin 9784cd6abddSMichael Gmelin mtx_lock(&sc->io_lock); 9790a6b1b56SVladimir Kondratyev /* Ignore stray interrupts */ 9800a6b1b56SVladimir Kondratyev if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) { 98121e459c6SVladimir Kondratyev set_intr_mask(sc, 0); 9820ba5622dSMichael Gmelin reg_read(sc, IG4_REG_CLR_INTR); 98371d51719SMichael Gmelin wakeup(sc); 9840a6b1b56SVladimir Kondratyev } 9854cd6abddSMichael Gmelin mtx_unlock(&sc->io_lock); 98671d51719SMichael Gmelin } 98771d51719SMichael Gmelin 98871d51719SMichael Gmelin #define REGDUMP(sc, reg) \ 98971d51719SMichael Gmelin device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) 99071d51719SMichael Gmelin 99171d51719SMichael Gmelin static void 99271d51719SMichael Gmelin ig4iic_dump(ig4iic_softc_t *sc) 99371d51719SMichael Gmelin { 99471d51719SMichael Gmelin device_printf(sc->dev, "ig4iic register dump:\n"); 99571d51719SMichael Gmelin REGDUMP(sc, IG4_REG_CTL); 99671d51719SMichael Gmelin REGDUMP(sc, IG4_REG_TAR_ADD); 99771d51719SMichael Gmelin REGDUMP(sc, IG4_REG_SS_SCL_HCNT); 99871d51719SMichael Gmelin REGDUMP(sc, IG4_REG_SS_SCL_LCNT); 99971d51719SMichael Gmelin REGDUMP(sc, IG4_REG_FS_SCL_HCNT); 100071d51719SMichael Gmelin REGDUMP(sc, IG4_REG_FS_SCL_LCNT); 100171d51719SMichael Gmelin REGDUMP(sc, IG4_REG_INTR_STAT); 100271d51719SMichael Gmelin REGDUMP(sc, IG4_REG_INTR_MASK); 100371d51719SMichael Gmelin REGDUMP(sc, IG4_REG_RAW_INTR_STAT); 100471d51719SMichael Gmelin REGDUMP(sc, IG4_REG_RX_TL); 100571d51719SMichael Gmelin REGDUMP(sc, IG4_REG_TX_TL); 100671d51719SMichael Gmelin REGDUMP(sc, IG4_REG_I2C_EN); 100771d51719SMichael Gmelin REGDUMP(sc, IG4_REG_I2C_STA); 100871d51719SMichael Gmelin REGDUMP(sc, IG4_REG_TXFLR); 100971d51719SMichael Gmelin REGDUMP(sc, IG4_REG_RXFLR); 101071d51719SMichael Gmelin REGDUMP(sc, IG4_REG_SDA_HOLD); 101171d51719SMichael Gmelin REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); 101271d51719SMichael Gmelin REGDUMP(sc, IG4_REG_SLV_DATA_NACK); 101371d51719SMichael Gmelin REGDUMP(sc, IG4_REG_DMA_CTRL); 101471d51719SMichael Gmelin REGDUMP(sc, IG4_REG_DMA_TDLR); 101571d51719SMichael Gmelin REGDUMP(sc, IG4_REG_DMA_RDLR); 101671d51719SMichael Gmelin REGDUMP(sc, IG4_REG_SDA_SETUP); 101771d51719SMichael Gmelin REGDUMP(sc, IG4_REG_ENABLE_STATUS); 101871d51719SMichael Gmelin REGDUMP(sc, IG4_REG_COMP_PARAM1); 101971d51719SMichael Gmelin REGDUMP(sc, IG4_REG_COMP_VER); 1020b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_ATOM) { 102171d51719SMichael Gmelin REGDUMP(sc, IG4_REG_COMP_TYPE); 102271d51719SMichael Gmelin REGDUMP(sc, IG4_REG_CLK_PARMS); 1023b3e8ee5dSOleksandr Tymoshenko } 1024b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1025b3e8ee5dSOleksandr Tymoshenko REGDUMP(sc, IG4_REG_RESETS_HSW); 102671d51719SMichael Gmelin REGDUMP(sc, IG4_REG_GENERAL); 1027b3e8ee5dSOleksandr Tymoshenko } else if (sc->version == IG4_SKYLAKE) { 1028b3e8ee5dSOleksandr Tymoshenko REGDUMP(sc, IG4_REG_RESETS_SKL); 1029b3e8ee5dSOleksandr Tymoshenko } 1030b3e8ee5dSOleksandr Tymoshenko if (sc->version == IG4_HASWELL) { 103171d51719SMichael Gmelin REGDUMP(sc, IG4_REG_SW_LTR_VALUE); 103271d51719SMichael Gmelin REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); 1033b3e8ee5dSOleksandr Tymoshenko } else if (sc->version == IG4_SKYLAKE) { 1034b3e8ee5dSOleksandr Tymoshenko REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); 1035b3e8ee5dSOleksandr Tymoshenko REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); 1036b3e8ee5dSOleksandr Tymoshenko } 103771d51719SMichael Gmelin } 103871d51719SMichael Gmelin #undef REGDUMP 103971d51719SMichael Gmelin 1040984ed3e4SVladimir Kondratyev devclass_t ig4iic_devclass; 1041984ed3e4SVladimir Kondratyev 1042984ed3e4SVladimir Kondratyev DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, iicbus_devclass, NULL, NULL); 1043984ed3e4SVladimir Kondratyev MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 1044984ed3e4SVladimir Kondratyev MODULE_VERSION(ig4iic, 1); 1045