1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 /* 38 * Intel fourth generation mobile cpus integrated I2C device. 39 * 40 * See ig4_reg.h for datasheet reference and notes. 41 * See ig4_var.h for locking semantics. 42 */ 43 44 #include "opt_acpi.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/errno.h> 51 #include <sys/kdb.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/proc.h> 55 #include <sys/sx.h> 56 #include <sys/syslog.h> 57 #include <sys/bus.h> 58 #include <sys/sysctl.h> 59 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 63 #ifdef DEV_ACPI 64 #include <contrib/dev/acpica/include/acpi.h> 65 #include <contrib/dev/acpica/include/accommon.h> 66 #include <dev/acpica/acpivar.h> 67 #endif 68 69 #include <dev/iicbus/iicbus.h> 70 #include <dev/iicbus/iiconf.h> 71 72 #include <dev/ichiic/ig4_reg.h> 73 #include <dev/ichiic/ig4_var.h> 74 75 #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll) 76 77 /* 78 * tLOW, tHIGH periods of the SCL clock and maximal falling time of both 79 * lines are taken from I2C specifications. 80 */ 81 #define IG4_SPEED_STD_THIGH 4000 /* nsec */ 82 #define IG4_SPEED_STD_TLOW 4700 /* nsec */ 83 #define IG4_SPEED_STD_TF_MAX 300 /* nsec */ 84 #define IG4_SPEED_FAST_THIGH 600 /* nsec */ 85 #define IG4_SPEED_FAST_TLOW 1300 /* nsec */ 86 #define IG4_SPEED_FAST_TF_MAX 300 /* nsec */ 87 88 /* 89 * Ig4 hardware parameters except Haswell are taken from intel_lpss driver 90 */ 91 static const struct ig4_hw ig4iic_hw[] = { 92 [IG4_EMAG] = { 93 .ic_clock_rate = 100, /* MHz */ 94 }, 95 [IG4_HASWELL] = { 96 .ic_clock_rate = 100, /* MHz */ 97 .sda_hold_time = 90, /* nsec */ 98 .txfifo_depth = 32, 99 .rxfifo_depth = 32, 100 }, 101 [IG4_ATOM] = { 102 .ic_clock_rate = 100, 103 .sda_fall_time = 280, 104 .scl_fall_time = 240, 105 .sda_hold_time = 60, 106 .txfifo_depth = 32, 107 .rxfifo_depth = 32, 108 }, 109 [IG4_SKYLAKE] = { 110 .ic_clock_rate = 120, 111 .sda_hold_time = 230, 112 }, 113 [IG4_APL] = { 114 .ic_clock_rate = 133, 115 .sda_fall_time = 171, 116 .scl_fall_time = 208, 117 .sda_hold_time = 207, 118 }, 119 [IG4_CANNONLAKE] = { 120 .ic_clock_rate = 216, 121 .sda_hold_time = 230, 122 }, 123 [IG4_TIGERLAKE] = { 124 .ic_clock_rate = 133, 125 .sda_fall_time = 171, 126 .scl_fall_time = 208, 127 .sda_hold_time = 42, 128 }, 129 [IG4_GEMINILAKE] = { 130 .ic_clock_rate = 133, 131 .sda_fall_time = 171, 132 .scl_fall_time = 290, 133 .sda_hold_time = 313, 134 }, 135 }; 136 137 static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset); 138 static driver_filter_t ig4iic_intr; 139 static void ig4iic_dump(ig4iic_softc_t *sc); 140 141 static int ig4_dump; 142 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW, 143 &ig4_dump, 0, "Dump controller registers"); 144 145 /* 146 * Clock registers initialization control 147 * 0 - Try read clock registers from ACPI and fallback to p.1. 148 * 1 - Calculate values based on controller type (IC clock rate). 149 * 2 - Use values inherited from DragonflyBSD driver (old behavior). 150 * 3 - Keep clock registers intact. 151 */ 152 static int ig4_timings; 153 SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0, 154 "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change"); 155 156 /* 157 * Low-level inline support functions 158 */ 159 static __inline void 160 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) 161 { 162 bus_write_4(sc->regs_res, reg, value); 163 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE); 164 } 165 166 static __inline uint32_t 167 reg_read(ig4iic_softc_t *sc, uint32_t reg) 168 { 169 uint32_t value; 170 171 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ); 172 value = bus_read_4(sc->regs_res, reg); 173 return (value); 174 } 175 176 static void 177 ig4iic_set_intr_mask(ig4iic_softc_t *sc, uint32_t val) 178 { 179 if (sc->intr_mask != val) { 180 reg_write(sc, IG4_REG_INTR_MASK, val); 181 sc->intr_mask = val; 182 } 183 } 184 185 static int 186 intrstat2iic(ig4iic_softc_t *sc, uint32_t val) 187 { 188 uint32_t src; 189 190 if (val & IG4_INTR_RX_UNDER) 191 reg_read(sc, IG4_REG_CLR_RX_UNDER); 192 if (val & IG4_INTR_RX_OVER) 193 reg_read(sc, IG4_REG_CLR_RX_OVER); 194 if (val & IG4_INTR_TX_OVER) 195 reg_read(sc, IG4_REG_CLR_TX_OVER); 196 197 if (val & IG4_INTR_TX_ABRT) { 198 src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 199 reg_read(sc, IG4_REG_CLR_TX_ABORT); 200 /* User-requested abort. Not really a error */ 201 if (src & IG4_ABRTSRC_TRANSFER) 202 return (IIC_ESTATUS); 203 /* Master has lost arbitration */ 204 if (src & IG4_ABRTSRC_ARBLOST) 205 return (IIC_EBUSBSY); 206 /* Did not receive an acknowledge from the remote slave */ 207 if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 | 208 IG4_ABRTSRC_TXNOACK_ADDR10_1 | 209 IG4_ABRTSRC_TXNOACK_ADDR10_2 | 210 IG4_ABRTSRC_TXNOACK_DATA | 211 IG4_ABRTSRC_GENCALL_NOACK)) 212 return (IIC_ENOACK); 213 /* Programming errors */ 214 if (src & (IG4_ABRTSRC_GENCALL_READ | 215 IG4_ABRTSRC_NORESTART_START | 216 IG4_ABRTSRC_NORESTART_10)) 217 return (IIC_ENOTSUPP); 218 /* Other errors */ 219 if (src & IG4_ABRTSRC_ACKED_START) 220 return (IIC_EBUSERR); 221 } 222 /* 223 * TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth 224 * detection or driver's read/write pipelining errors. 225 */ 226 if (val & (IG4_INTR_TX_OVER | IG4_INTR_RX_OVER)) 227 return (IIC_EOVERFLOW); 228 if (val & IG4_INTR_RX_UNDER) 229 return (IIC_EUNDERFLOW); 230 231 return (IIC_NOERR); 232 } 233 234 /* 235 * Enable or disable the controller and wait for the controller to acknowledge 236 * the state change. 237 */ 238 static int 239 set_controller(ig4iic_softc_t *sc, uint32_t ctl) 240 { 241 int retry; 242 int error; 243 uint32_t v; 244 245 /* 246 * When the controller is enabled, interrupt on STOP detect 247 * or receive character ready and clear pending interrupts. 248 */ 249 ig4iic_set_intr_mask(sc, 0); 250 if (ctl & IG4_I2C_ENABLE) 251 reg_read(sc, IG4_REG_CLR_INTR); 252 253 reg_write(sc, IG4_REG_I2C_EN, ctl); 254 error = IIC_ETIMEOUT; 255 256 for (retry = 100; retry > 0; --retry) { 257 v = reg_read(sc, IG4_REG_ENABLE_STATUS); 258 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { 259 error = 0; 260 break; 261 } 262 pause("i2cslv", 1); 263 } 264 return (error); 265 } 266 267 /* 268 * Wait up to 25ms for the requested interrupt using a 25uS polling loop. 269 */ 270 static int 271 wait_intr(ig4iic_softc_t *sc, uint32_t intr) 272 { 273 uint32_t v; 274 int error; 275 int txlvl = -1; 276 u_int count_us = 0; 277 u_int limit_us = 1000000; /* 1sec */ 278 279 for (;;) { 280 /* 281 * Check requested status 282 */ 283 v = reg_read(sc, IG4_REG_RAW_INTR_STAT); 284 error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK); 285 if (error || (v & intr)) 286 break; 287 288 /* 289 * When waiting for the transmit FIFO to become empty, 290 * reset the timeout if we see a change in the transmit 291 * FIFO level as progress is being made. 292 */ 293 if (intr & (IG4_INTR_TX_EMPTY | IG4_INTR_STOP_DET)) { 294 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; 295 if (txlvl != v) { 296 txlvl = v; 297 count_us = 0; 298 } 299 } 300 301 /* 302 * Stop if we've run out of time. 303 */ 304 if (count_us >= limit_us) { 305 error = IIC_ETIMEOUT; 306 break; 307 } 308 309 /* 310 * When polling is not requested let the interrupt do its work. 311 */ 312 if (!DO_POLL(sc)) { 313 mtx_lock_spin(&sc->io_lock); 314 ig4iic_set_intr_mask(sc, intr | IG4_INTR_ERR_MASK); 315 msleep_spin(sc, &sc->io_lock, "i2cwait", 316 (hz + 99) / 100); /* sleep up to 10ms */ 317 ig4iic_set_intr_mask(sc, 0); 318 mtx_unlock_spin(&sc->io_lock); 319 count_us += 10000; 320 } else { 321 DELAY(25); 322 count_us += 25; 323 } 324 } 325 326 return (error); 327 } 328 329 /* 330 * Set the slave address. The controller must be disabled when 331 * changing the address. 332 * 333 * This operation does not issue anything to the I2C bus but sets 334 * the target address for when the controller later issues a START. 335 */ 336 static void 337 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) 338 { 339 uint32_t tar; 340 uint32_t ctl; 341 bool use_10bit; 342 343 use_10bit = false; 344 if (sc->slave_valid && sc->last_slave == slave && 345 sc->use_10bit == use_10bit) { 346 return; 347 } 348 sc->use_10bit = use_10bit; 349 350 /* 351 * Wait for TXFIFO to drain before disabling the controller. 352 */ 353 wait_intr(sc, IG4_INTR_TX_EMPTY); 354 355 set_controller(sc, 0); 356 ctl = reg_read(sc, IG4_REG_CTL); 357 ctl &= ~IG4_CTL_10BIT; 358 ctl |= IG4_CTL_RESTARTEN; 359 360 tar = slave; 361 if (sc->use_10bit) { 362 tar |= IG4_TAR_10BIT; 363 ctl |= IG4_CTL_10BIT; 364 } 365 reg_write(sc, IG4_REG_CTL, ctl); 366 reg_write(sc, IG4_REG_TAR_ADD, tar); 367 set_controller(sc, IG4_I2C_ENABLE); 368 sc->slave_valid = true; 369 sc->last_slave = slave; 370 } 371 372 /* 373 * IICBUS API FUNCTIONS 374 */ 375 static int 376 ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start) 377 { 378 set_slave_addr(sc, slave >> 1); 379 380 if (!repeated_start) { 381 /* 382 * Clear any previous TX/RX FIFOs overflow/underflow bits 383 * and I2C bus STOP condition. 384 */ 385 reg_read(sc, IG4_REG_CLR_INTR); 386 } 387 388 return (0); 389 } 390 391 static bool 392 ig4iic_xfer_is_started(ig4iic_softc_t *sc) 393 { 394 /* 395 * It requires that no IG4_REG_CLR_INTR or IG4_REG_CLR_START/STOP_DET 396 * register reads is issued after START condition. 397 */ 398 return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) & 399 (IG4_INTR_START_DET | IG4_INTR_STOP_DET)) == IG4_INTR_START_DET); 400 } 401 402 static int 403 ig4iic_xfer_abort(ig4iic_softc_t *sc) 404 { 405 int error; 406 407 /* Request send of STOP condition and flush of TX FIFO */ 408 set_controller(sc, IG4_I2C_ABORT | IG4_I2C_ENABLE); 409 /* 410 * Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER 411 * bit set in TX_ABRT_SOURCE register. 412 */ 413 error = wait_intr(sc, IG4_INTR_STOP_DET); 414 set_controller(sc, IG4_I2C_ENABLE); 415 416 return (error == IIC_ESTATUS ? 0 : error); 417 } 418 419 /* 420 * Amount of unread data before next burst to get better I2C bus utilization. 421 * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes. 422 * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs. 423 */ 424 #define IG4_FIFO_LOWAT 2 425 426 static int 427 ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, 428 bool repeated_start, bool stop) 429 { 430 uint32_t cmd; 431 int requested = 0; 432 int received = 0; 433 int burst, target, lowat = 0; 434 int error; 435 436 if (len == 0) 437 return (0); 438 439 while (received < len) { 440 burst = sc->cfg.txfifo_depth - 441 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); 442 if (burst <= 0) { 443 error = wait_intr(sc, IG4_INTR_TX_EMPTY); 444 if (error) 445 break; 446 burst = sc->cfg.txfifo_depth; 447 } 448 /* Ensure we have enough free space in RXFIFO */ 449 burst = MIN(burst, sc->cfg.rxfifo_depth - lowat); 450 target = MIN(requested + burst, (int)len); 451 while (requested < target) { 452 cmd = IG4_DATA_COMMAND_RD; 453 if (repeated_start && requested == 0) 454 cmd |= IG4_DATA_RESTART; 455 if (stop && requested == len - 1) 456 cmd |= IG4_DATA_STOP; 457 reg_write(sc, IG4_REG_DATA_CMD, cmd); 458 requested++; 459 } 460 /* Leave some data queued to maintain the hardware pipeline */ 461 lowat = 0; 462 if (requested != len && requested - received > IG4_FIFO_LOWAT) 463 lowat = IG4_FIFO_LOWAT; 464 /* After TXFLR fills up, clear it by reading available data */ 465 while (received < requested - lowat) { 466 burst = MIN((int)len - received, 467 reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK); 468 if (burst > 0) { 469 while (burst--) 470 buf[received++] = 0xFF & 471 reg_read(sc, IG4_REG_DATA_CMD); 472 } else { 473 error = wait_intr(sc, IG4_INTR_RX_FULL); 474 if (error) 475 goto out; 476 } 477 } 478 } 479 out: 480 return (error); 481 } 482 483 static int 484 ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, 485 bool repeated_start, bool stop) 486 { 487 uint32_t cmd; 488 int sent = 0; 489 int burst, target; 490 int error; 491 bool lowat_set = false; 492 493 if (len == 0) 494 return (0); 495 496 while (sent < len) { 497 burst = sc->cfg.txfifo_depth - 498 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); 499 target = MIN(sent + burst, (int)len); 500 /* Leave some data queued to maintain the hardware pipeline */ 501 if (!lowat_set && target != len) { 502 lowat_set = true; 503 reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT); 504 } 505 while(sent < target) { 506 cmd = buf[sent]; 507 if (repeated_start && sent == 0) 508 cmd |= IG4_DATA_RESTART; 509 if (stop && sent == len - 1) 510 cmd |= IG4_DATA_STOP; 511 reg_write(sc, IG4_REG_DATA_CMD, cmd); 512 sent++; 513 } 514 if (sent < len) { 515 error = wait_intr(sc, IG4_INTR_TX_EMPTY); 516 if (error) 517 break; 518 } 519 } 520 if (lowat_set) 521 reg_write(sc, IG4_REG_TX_TL, 0); 522 523 return (error); 524 } 525 526 int 527 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 528 { 529 ig4iic_softc_t *sc = device_get_softc(dev); 530 const char *reason = NULL; 531 uint32_t i; 532 int error; 533 int unit; 534 bool rpstart; 535 bool stop; 536 bool allocated; 537 538 /* 539 * The hardware interface imposes limits on allowed I2C messages. 540 * It is not possible to explicitly send a start or stop. 541 * They are automatically sent (or not sent, depending on the 542 * configuration) when a data byte is transferred. 543 * For this reason it's impossible to send a message with no data 544 * at all (like an SMBus quick message). 545 * The start condition is automatically generated after the stop 546 * condition, so it's impossible to not have a start after a stop. 547 * The repeated start condition is automatically sent if a change 548 * of the transfer direction happens, so it's impossible to have 549 * a change of direction without a (repeated) start. 550 * The repeated start can be forced even without the change of 551 * direction. 552 * Changing the target slave address requires resetting the hardware 553 * state, so it's impossible to do that without the stop followed 554 * by the start. 555 */ 556 for (i = 0; i < nmsgs; i++) { 557 #if 0 558 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) { 559 reason = "first message without start"; 560 break; 561 } 562 if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) { 563 reason = "last message without stop"; 564 break; 565 } 566 #endif 567 if (msgs[i].len == 0) { 568 reason = "message with no data"; 569 break; 570 } 571 if (i > 0) { 572 if ((msgs[i].flags & IIC_M_NOSTART) != 0 && 573 (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) { 574 reason = "stop not followed by start"; 575 break; 576 } 577 if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 && 578 msgs[i].slave != msgs[i - 1].slave) { 579 reason = "change of slave without stop"; 580 break; 581 } 582 if ((msgs[i].flags & IIC_M_NOSTART) != 0 && 583 (msgs[i].flags & IIC_M_RD) != 584 (msgs[i - 1].flags & IIC_M_RD)) { 585 reason = "change of direction without repeated" 586 " start"; 587 break; 588 } 589 } 590 } 591 if (reason != NULL) { 592 if (bootverbose) 593 device_printf(dev, "%s\n", reason); 594 return (IIC_ENOTSUPP); 595 } 596 597 /* Check if device is already allocated with iicbus_request_bus() */ 598 allocated = sx_xlocked(&sc->call_lock) != 0; 599 if (!allocated) 600 sx_xlock(&sc->call_lock); 601 602 /* Debugging - dump registers. */ 603 if (ig4_dump) { 604 unit = device_get_unit(dev); 605 if (ig4_dump & (1 << unit)) { 606 ig4_dump &= ~(1 << unit); 607 ig4iic_dump(sc); 608 } 609 } 610 611 /* 612 * Clear any previous abort condition that may have been holding 613 * the txfifo in reset. 614 */ 615 reg_read(sc, IG4_REG_CLR_TX_ABORT); 616 617 rpstart = false; 618 error = 0; 619 for (i = 0; i < nmsgs; i++) { 620 if ((msgs[i].flags & IIC_M_NOSTART) == 0) { 621 error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart); 622 } else { 623 if (!sc->slave_valid || 624 (msgs[i].slave >> 1) != sc->last_slave) { 625 device_printf(dev, "start condition suppressed" 626 "but slave address is not set up"); 627 error = EINVAL; 628 break; 629 } 630 rpstart = false; 631 } 632 if (error != 0) 633 break; 634 635 stop = (msgs[i].flags & IIC_M_NOSTOP) == 0; 636 if (msgs[i].flags & IIC_M_RD) 637 error = ig4iic_read(sc, msgs[i].buf, msgs[i].len, 638 rpstart, stop); 639 else 640 error = ig4iic_write(sc, msgs[i].buf, msgs[i].len, 641 rpstart, stop); 642 643 /* Wait for error or stop condition occurred on the I2C bus */ 644 if (stop && error == 0) { 645 error = wait_intr(sc, IG4_INTR_STOP_DET); 646 if (error == 0) 647 reg_read(sc, IG4_REG_CLR_INTR); 648 } 649 650 if (error != 0) { 651 /* 652 * Send STOP condition if it's not done yet and flush 653 * both FIFOs. Do a controller soft reset if transfer 654 * abort is failed. 655 */ 656 if (ig4iic_xfer_is_started(sc) && 657 ig4iic_xfer_abort(sc) != 0) { 658 device_printf(sc->dev, "Failed to abort " 659 "transfer. Do the controller reset.\n"); 660 ig4iic_set_config(sc, true); 661 } else { 662 while (reg_read(sc, IG4_REG_I2C_STA) & 663 IG4_STATUS_RX_NOTEMPTY) 664 reg_read(sc, IG4_REG_DATA_CMD); 665 reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 666 reg_read(sc, IG4_REG_CLR_INTR); 667 } 668 break; 669 } 670 671 rpstart = !stop; 672 } 673 674 if (!allocated) 675 sx_unlock(&sc->call_lock); 676 return (error); 677 } 678 679 int 680 ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 681 { 682 ig4iic_softc_t *sc = device_get_softc(dev); 683 bool allocated; 684 685 allocated = sx_xlocked(&sc->call_lock) != 0; 686 if (!allocated) 687 sx_xlock(&sc->call_lock); 688 689 /* TODO handle speed configuration? */ 690 if (oldaddr != NULL) 691 *oldaddr = sc->last_slave << 1; 692 set_slave_addr(sc, addr >> 1); 693 if (addr == IIC_UNKNOWN) 694 sc->slave_valid = false; 695 696 if (!allocated) 697 sx_unlock(&sc->call_lock); 698 return (0); 699 } 700 701 int 702 ig4iic_callback(device_t dev, int index, caddr_t data) 703 { 704 ig4iic_softc_t *sc = device_get_softc(dev); 705 int error = 0; 706 int how; 707 708 switch (index) { 709 case IIC_REQUEST_BUS: 710 /* force polling if ig4iic is requested with IIC_DONTWAIT */ 711 how = *(int *)data; 712 if ((how & IIC_WAIT) == 0) { 713 if (sx_try_xlock(&sc->call_lock) == 0) 714 error = IIC_EBUSBSY; 715 else 716 sc->poll = true; 717 } else 718 sx_xlock(&sc->call_lock); 719 break; 720 721 case IIC_RELEASE_BUS: 722 sc->poll = false; 723 sx_unlock(&sc->call_lock); 724 break; 725 726 default: 727 error = errno2iic(EINVAL); 728 } 729 730 return (error); 731 } 732 733 /* 734 * Clock register values can be calculated with following rough equations: 735 * SCL_HCNT = ceil(IC clock rate * tHIGH) 736 * SCL_LCNT = ceil(IC clock rate * tLOW) 737 * SDA_HOLD = ceil(IC clock rate * SDA hold time) 738 * Precise equations take signal's falling, rising and spike suppression 739 * times in to account. They can be found in Synopsys or Intel documentation. 740 * 741 * Here we snarf formulas and defaults from Linux driver to be able to use 742 * timing values provided by Intel LPSS driver "as is". 743 */ 744 static int 745 ig4iic_clk_params(const struct ig4_hw *hw, int speed, 746 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) 747 { 748 uint32_t thigh, tlow, tf_max; /* nsec */ 749 uint32_t sda_fall_time; /* nsec */ 750 uint32_t scl_fall_time; /* nsec */ 751 752 switch (speed) { 753 case IG4_CTL_SPEED_STD: 754 thigh = IG4_SPEED_STD_THIGH; 755 tlow = IG4_SPEED_STD_TLOW; 756 tf_max = IG4_SPEED_STD_TF_MAX; 757 break; 758 759 case IG4_CTL_SPEED_FAST: 760 thigh = IG4_SPEED_FAST_THIGH; 761 tlow = IG4_SPEED_FAST_TLOW; 762 tf_max = IG4_SPEED_FAST_TF_MAX; 763 break; 764 765 default: 766 return (EINVAL); 767 } 768 769 /* Use slowest falling time defaults to be on the safe side */ 770 sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time; 771 *scl_hcnt = (uint16_t) 772 ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3); 773 774 scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time; 775 *scl_lcnt = (uint16_t) 776 ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1); 777 778 /* 779 * There is no "known good" default value for tHD;DAT so keep SDA_HOLD 780 * intact if sda_hold_time value is not provided. 781 */ 782 if (hw->sda_hold_time != 0) 783 *sda_hold = (uint16_t) 784 ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000); 785 786 return (0); 787 } 788 789 #ifdef DEV_ACPI 790 static ACPI_STATUS 791 ig4iic_acpi_params(ACPI_HANDLE handle, char *method, 792 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) 793 { 794 ACPI_BUFFER buf; 795 ACPI_OBJECT *obj, *elems; 796 ACPI_STATUS status; 797 798 buf.Pointer = NULL; 799 buf.Length = ACPI_ALLOCATE_BUFFER; 800 801 status = AcpiEvaluateObject(handle, method, NULL, &buf); 802 if (ACPI_FAILURE(status)) 803 return (status); 804 805 status = AE_TYPE; 806 obj = (ACPI_OBJECT *)buf.Pointer; 807 if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) { 808 elems = obj->Package.Elements; 809 *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK; 810 *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK; 811 *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK; 812 status = AE_OK; 813 } 814 815 AcpiOsFree(obj); 816 817 return (status); 818 } 819 #endif /* DEV_ACPI */ 820 821 static void 822 ig4iic_get_config(ig4iic_softc_t *sc) 823 { 824 const struct ig4_hw *hw; 825 uint32_t v; 826 #ifdef DEV_ACPI 827 ACPI_HANDLE handle; 828 #endif 829 /* Fetch default hardware config from controller */ 830 sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER); 831 sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK; 832 sc->cfg.ss_scl_hcnt = 833 reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; 834 sc->cfg.ss_scl_lcnt = 835 reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; 836 sc->cfg.fs_scl_hcnt = 837 reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; 838 sc->cfg.fs_scl_lcnt = 839 reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; 840 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 841 reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK; 842 843 if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD) 844 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; 845 846 /* REG_COMP_PARAM1 is not documented in latest Intel specs */ 847 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 848 v = reg_read(sc, IG4_REG_COMP_PARAM1); 849 if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0) 850 sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v); 851 if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0) 852 sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v); 853 } else { 854 /* 855 * Hardware does not allow FIFO Threshold Levels value to be 856 * set larger than the depth of the buffer. If an attempt is 857 * made to do that, the actual value set will be the maximum 858 * depth of the buffer. 859 */ 860 v = reg_read(sc, IG4_REG_TX_TL); 861 reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK); 862 sc->cfg.txfifo_depth = 863 (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1; 864 reg_write(sc, IG4_REG_TX_TL, v); 865 v = reg_read(sc, IG4_REG_RX_TL); 866 reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK); 867 sc->cfg.rxfifo_depth = 868 (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1; 869 reg_write(sc, IG4_REG_RX_TL, v); 870 } 871 872 /* Override hardware config with IC_clock-based counter values */ 873 if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) { 874 hw = &ig4iic_hw[sc->version]; 875 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; 876 ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt, 877 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); 878 ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt, 879 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); 880 if (hw->txfifo_depth != 0) 881 sc->cfg.txfifo_depth = hw->txfifo_depth; 882 if (hw->rxfifo_depth != 0) 883 sc->cfg.rxfifo_depth = hw->rxfifo_depth; 884 } else if (ig4_timings == 2) { 885 /* 886 * Timings of original ig4 driver: 887 * Program based on a 25000 Hz clock. This is a bit of a 888 * hack (obviously). The defaults are 400 and 470 for standard 889 * and 60 and 130 for fast. The defaults for standard fail 890 * utterly (presumably cause an abort) because the clock time 891 * is ~18.8ms by default. This brings it down to ~4ms. 892 */ 893 sc->cfg.bus_speed = IG4_CTL_SPEED_STD; 894 sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100; 895 sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125; 896 if (sc->version == IG4_SKYLAKE) 897 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28; 898 } 899 900 #ifdef DEV_ACPI 901 /* Evaluate SSCN and FMCN ACPI methods to fetch timings */ 902 if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) { 903 ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt, 904 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); 905 ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt, 906 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); 907 } 908 #endif 909 910 if (bootverbose) { 911 device_printf(sc->dev, "Controller parameters:\n"); 912 printf(" Speed: %s\n", 913 sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast"); 914 printf(" Regs: HCNT :LCNT :SDAHLD\n"); 915 printf(" Std: 0x%04hx:0x%04hx:0x%04hx\n", 916 sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt, 917 sc->cfg.ss_sda_hold); 918 printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n", 919 sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt, 920 sc->cfg.fs_sda_hold); 921 printf(" FIFO: RX:0x%04x: TX:0x%04x\n", 922 sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth); 923 } 924 } 925 926 static int 927 ig4iic_set_config(ig4iic_softc_t *sc, bool reset) 928 { 929 uint32_t v; 930 931 v = reg_read(sc, IG4_REG_DEVIDLE_CTRL); 932 if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) { 933 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED); 934 reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0); 935 pause("i2crst", 1); 936 reset = true; 937 } 938 939 if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) { 940 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); 941 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); 942 } else if (IG4_HAS_ADDREGS(sc->version) && reset) { 943 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 944 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); 945 } 946 947 if (sc->version == IG4_ATOM) 948 v = reg_read(sc, IG4_REG_COMP_TYPE); 949 950 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 951 v = reg_read(sc, IG4_REG_COMP_PARAM1); 952 v = reg_read(sc, IG4_REG_GENERAL); 953 /* 954 * The content of IG4_REG_GENERAL is different for each 955 * controller version. 956 */ 957 if (sc->version == IG4_HASWELL && 958 (v & IG4_GENERAL_SWMODE) == 0) { 959 v |= IG4_GENERAL_SWMODE; 960 reg_write(sc, IG4_REG_GENERAL, v); 961 v = reg_read(sc, IG4_REG_GENERAL); 962 } 963 } 964 965 if (sc->version == IG4_HASWELL) { 966 v = reg_read(sc, IG4_REG_SW_LTR_VALUE); 967 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); 968 } else if (IG4_HAS_ADDREGS(sc->version)) { 969 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); 970 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); 971 } 972 973 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 974 v = reg_read(sc, IG4_REG_COMP_VER); 975 if (v < IG4_COMP_MIN_VER) 976 return(ENXIO); 977 } 978 979 if (set_controller(sc, 0)) { 980 device_printf(sc->dev, "controller error during attach-1\n"); 981 return (ENXIO); 982 } 983 984 reg_read(sc, IG4_REG_CLR_INTR); 985 reg_write(sc, IG4_REG_INTR_MASK, 0); 986 sc->intr_mask = 0; 987 988 reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt); 989 reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt); 990 reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt); 991 reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt); 992 reg_write(sc, IG4_REG_SDA_HOLD, 993 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ? 994 sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold); 995 996 /* 997 * Use a threshold of 1 so we get interrupted on each character, 998 * allowing us to use mtx_sleep() in our poll code. Not perfect 999 * but this is better than using DELAY() for receiving data. 1000 * 1001 * See ig4_var.h for details on interrupt handler synchronization. 1002 */ 1003 reg_write(sc, IG4_REG_RX_TL, 0); 1004 reg_write(sc, IG4_REG_TX_TL, 0); 1005 1006 reg_write(sc, IG4_REG_CTL, 1007 IG4_CTL_MASTER | 1008 IG4_CTL_SLAVE_DISABLE | 1009 IG4_CTL_RESTARTEN | 1010 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK)); 1011 1012 /* Force setting of the target address on the next transfer */ 1013 sc->slave_valid = false; 1014 1015 return (0); 1016 } 1017 1018 /* 1019 * Called from ig4iic_pci_attach/detach() 1020 */ 1021 int 1022 ig4iic_attach(ig4iic_softc_t *sc) 1023 { 1024 int error; 1025 1026 mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_SPIN); 1027 sx_init(&sc->call_lock, "IG4 call lock"); 1028 1029 ig4iic_get_config(sc); 1030 1031 error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)); 1032 if (error) 1033 goto done; 1034 1035 sc->iicbus = device_add_child(sc->dev, "iicbus", -1); 1036 if (sc->iicbus == NULL) { 1037 device_printf(sc->dev, "iicbus driver not found\n"); 1038 error = ENXIO; 1039 goto done; 1040 } 1041 1042 if (set_controller(sc, IG4_I2C_ENABLE)) { 1043 device_printf(sc->dev, "controller error during attach-2\n"); 1044 error = ENXIO; 1045 goto done; 1046 } 1047 if (set_controller(sc, 0)) { 1048 device_printf(sc->dev, "controller error during attach-3\n"); 1049 error = ENXIO; 1050 goto done; 1051 } 1052 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE, 1053 ig4iic_intr, NULL, sc, &sc->intr_handle); 1054 if (error) { 1055 device_printf(sc->dev, 1056 "Unable to setup irq: error %d\n", error); 1057 } 1058 1059 error = bus_generic_attach(sc->dev); 1060 if (error) { 1061 device_printf(sc->dev, 1062 "failed to attach child: error %d\n", error); 1063 } 1064 1065 done: 1066 return (error); 1067 } 1068 1069 int 1070 ig4iic_detach(ig4iic_softc_t *sc) 1071 { 1072 int error; 1073 1074 if (device_is_attached(sc->dev)) { 1075 error = bus_generic_detach(sc->dev); 1076 if (error) 1077 return (error); 1078 } 1079 if (sc->iicbus) 1080 device_delete_child(sc->dev, sc->iicbus); 1081 if (sc->intr_handle) 1082 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); 1083 1084 sx_xlock(&sc->call_lock); 1085 1086 sc->iicbus = NULL; 1087 sc->intr_handle = NULL; 1088 reg_write(sc, IG4_REG_INTR_MASK, 0); 1089 set_controller(sc, 0); 1090 1091 sx_xunlock(&sc->call_lock); 1092 1093 mtx_destroy(&sc->io_lock); 1094 sx_destroy(&sc->call_lock); 1095 1096 return (0); 1097 } 1098 1099 int 1100 ig4iic_suspend(ig4iic_softc_t *sc) 1101 { 1102 int error; 1103 1104 /* suspend all children */ 1105 error = bus_generic_suspend(sc->dev); 1106 1107 sx_xlock(&sc->call_lock); 1108 set_controller(sc, 0); 1109 if (IG4_HAS_ADDREGS(sc->version)) { 1110 /* 1111 * Place the device in the idle state, just to be safe 1112 */ 1113 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE); 1114 /* 1115 * Controller can become dysfunctional if I2C lines are pulled 1116 * down when suspend procedure turns off power to I2C device. 1117 * Place device in the reset state to avoid this. 1118 */ 1119 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 1120 } 1121 sx_xunlock(&sc->call_lock); 1122 1123 return (error); 1124 } 1125 1126 int ig4iic_resume(ig4iic_softc_t *sc) 1127 { 1128 int error; 1129 1130 sx_xlock(&sc->call_lock); 1131 if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version))) 1132 device_printf(sc->dev, "controller error during resume\n"); 1133 sx_xunlock(&sc->call_lock); 1134 1135 error = bus_generic_resume(sc->dev); 1136 1137 return (error); 1138 } 1139 1140 /* 1141 * Interrupt Operation, see ig4_var.h for locking semantics. 1142 */ 1143 static int 1144 ig4iic_intr(void *cookie) 1145 { 1146 ig4iic_softc_t *sc = cookie; 1147 int retval = FILTER_STRAY; 1148 1149 mtx_lock_spin(&sc->io_lock); 1150 /* Ignore stray interrupts */ 1151 if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) { 1152 /* Interrupt bits are cleared in wait_intr() loop */ 1153 ig4iic_set_intr_mask(sc, 0); 1154 wakeup(sc); 1155 retval = FILTER_HANDLED; 1156 } 1157 mtx_unlock_spin(&sc->io_lock); 1158 1159 return (retval); 1160 } 1161 1162 #define REGDUMP(sc, reg) \ 1163 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) 1164 1165 static void 1166 ig4iic_dump(ig4iic_softc_t *sc) 1167 { 1168 device_printf(sc->dev, "ig4iic register dump:\n"); 1169 REGDUMP(sc, IG4_REG_CTL); 1170 REGDUMP(sc, IG4_REG_TAR_ADD); 1171 REGDUMP(sc, IG4_REG_SS_SCL_HCNT); 1172 REGDUMP(sc, IG4_REG_SS_SCL_LCNT); 1173 REGDUMP(sc, IG4_REG_FS_SCL_HCNT); 1174 REGDUMP(sc, IG4_REG_FS_SCL_LCNT); 1175 REGDUMP(sc, IG4_REG_INTR_STAT); 1176 REGDUMP(sc, IG4_REG_INTR_MASK); 1177 REGDUMP(sc, IG4_REG_RAW_INTR_STAT); 1178 REGDUMP(sc, IG4_REG_RX_TL); 1179 REGDUMP(sc, IG4_REG_TX_TL); 1180 REGDUMP(sc, IG4_REG_I2C_EN); 1181 REGDUMP(sc, IG4_REG_I2C_STA); 1182 REGDUMP(sc, IG4_REG_TXFLR); 1183 REGDUMP(sc, IG4_REG_RXFLR); 1184 REGDUMP(sc, IG4_REG_SDA_HOLD); 1185 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); 1186 REGDUMP(sc, IG4_REG_SLV_DATA_NACK); 1187 REGDUMP(sc, IG4_REG_DMA_CTRL); 1188 REGDUMP(sc, IG4_REG_DMA_TDLR); 1189 REGDUMP(sc, IG4_REG_DMA_RDLR); 1190 REGDUMP(sc, IG4_REG_SDA_SETUP); 1191 REGDUMP(sc, IG4_REG_ENABLE_STATUS); 1192 REGDUMP(sc, IG4_REG_COMP_PARAM1); 1193 REGDUMP(sc, IG4_REG_COMP_VER); 1194 if (sc->version == IG4_ATOM) { 1195 REGDUMP(sc, IG4_REG_COMP_TYPE); 1196 REGDUMP(sc, IG4_REG_CLK_PARMS); 1197 } 1198 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1199 REGDUMP(sc, IG4_REG_RESETS_HSW); 1200 REGDUMP(sc, IG4_REG_GENERAL); 1201 } else if (sc->version == IG4_SKYLAKE) { 1202 REGDUMP(sc, IG4_REG_RESETS_SKL); 1203 } 1204 if (sc->version == IG4_HASWELL) { 1205 REGDUMP(sc, IG4_REG_SW_LTR_VALUE); 1206 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); 1207 } else if (IG4_HAS_ADDREGS(sc->version)) { 1208 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); 1209 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); 1210 } 1211 } 1212 #undef REGDUMP 1213 1214 DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, NULL, NULL); 1215 #ifdef DEV_ACPI 1216 DRIVER_MODULE(acpi_iicbus, ig4iic, acpi_iicbus_driver, NULL, NULL); 1217 #endif 1218 MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 1219 MODULE_VERSION(ig4iic, 1); 1220