1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Intel fourth generation mobile cpus integrated I2C device. 37 * 38 * Datasheet reference: Section 22. 39 * 40 * http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation 41 * 42 * This is a from-scratch driver under the BSD license using the Intel data 43 * sheet and the linux driver for reference. All code is freshly written 44 * without referencing the linux driver code. However, during testing 45 * I am also using the linux driver code as a reference to help resolve any 46 * issues that come. These will be specifically documented in the code. 47 * 48 * This controller is an I2C master only and cannot act as a slave. The IO 49 * voltage should be set by the BIOS. Standard (100Kb/s) and Fast (400Kb/s) 50 * and fast mode plus (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT 51 * supported. 52 */ 53 54 #ifndef _ICHIIC_IG4_REG_H_ 55 #define _ICHIIC_IG4_REG_H_ 56 57 /* 58 * 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through 59 * BAR1 when in ACPI mode. 60 * 61 * Register width is 32-bits 62 * 63 * 22.2 Default Values on device reset are 0 except as specified here: 64 * TAR_ADD 0x00000055 65 * SS_SCL_HCNT 0x00000264 66 * SS_SCL_LCNT 0x000002C2 67 * FS_SCL_HCNT 0x0000006E 68 * FS_SCL_LCNT 0x000000CF 69 * INTR_MASK 0x000008FF 70 * I2C_STA 0x00000006 71 * SDA_HOLD 0x00000001 72 * SDA_SETUP 0x00000064 73 * COMP_PARAM1 0x00FFFF6E 74 */ 75 76 #define IG4_REG_CTL 0x0000 /* RW Control Register */ 77 #define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */ 78 #define IG4_REG_HS_MADDR 0x000C /* RW High Speed Master Mode Code Address*/ 79 #define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */ 80 #define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */ 81 #define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */ 82 #define IG4_REG_FS_SCL_HCNT 0x001C /* RW Fast Speed clock High Count */ 83 #define IG4_REG_FS_SCL_LCNT 0x0020 /* RW Fast Speed clock Low Count */ 84 #define IG4_REG_INTR_STAT 0x002C /* RO Interrupt Status */ 85 #define IG4_REG_INTR_MASK 0x0030 /* RW Interrupt Mask */ 86 #define IG4_REG_RAW_INTR_STAT 0x0034 /* RO Raw Interrupt Status */ 87 #define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */ 88 #define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */ 89 #define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */ 90 #define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */ 91 #define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */ 92 #define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */ 93 #define IG4_REG_CLR_RD_REQ 0x0050 /* RO Clear RD_Req Interrupt */ 94 #define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */ 95 #define IG4_REG_CLR_RX_DONE 0x0058 /* RO Clear RX_Done Interrupt */ 96 #define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */ 97 #define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */ 98 #define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */ 99 #define IG4_REG_CLR_GEN_CALL 0x0068 /* RO Clear General Call Interrupt */ 100 #define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */ 101 #define IG4_REG_I2C_STA 0x0070 /* RO I2C Status */ 102 #define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */ 103 #define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */ 104 #define IG4_REG_SDA_HOLD 0x007C /* RW SDA Hold Time Length */ 105 #define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */ 106 #define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */ 107 #define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */ 108 #define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */ 109 #define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */ 110 #define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */ 111 #define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */ 112 #define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */ 113 /* Available at least on Atom SoCs, Haswell mobile and some Skylakes. */ 114 #define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */ 115 #define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */ 116 /* Available at least on Atom SoCs */ 117 #define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */ 118 /* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */ 119 #define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */ 120 #define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */ 121 #define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */ 122 #define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */ 123 #define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */ 124 #define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */ 125 /* Available at least on Atom SoCs */ 126 #define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */ 127 /* Available at least on Atom SoCs and Haswell mobile */ 128 #define IG4_REG_RESETS_HSW 0x0804 /* RW Reset Register */ 129 #define IG4_REG_GENERAL 0x0808 /* RW General Register */ 130 /* These LTR config registers are at least available on Haswell mobile. */ 131 #define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */ 132 #define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */ 133 134 /* 135 * CTL - Control Register 22.2.1 136 * Default Value: 0x0000007F. 137 * 138 * RESTARTEN - RW Restart Enable 139 * 10BIT - RW Controller operates in 10-bit mode, else 7-bit 140 * 141 * NOTE: When restart is disabled the controller is incapable of 142 * performing the following functions: 143 * 144 * Sending a START Byte 145 * Performing any high-speed mode op 146 * Performing direction changes in combined format mode 147 * Performing a read operation with a 10-bit address 148 * 149 * Attempting to perform the above operations will result in the 150 * TX_ABORT bit being set in RAW_INTR_STAT. 151 */ 152 #define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */ 153 #define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */ 154 #define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */ 155 #define IG4_CTL_SPEED_MASK 0x0006 /* speed at which the I2C operates */ 156 #define IG4_CTL_MASTER 0x0001 /* snarfed from linux */ 157 158 #define IG4_CTL_SPEED_HIGH 0x0006 /* snarfed from linux */ 159 #define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */ 160 #define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */ 161 162 /* 163 * TAR_ADD - Target Address Register 22.2.2 164 * Default Value: 0x00000055F 165 * 166 * 10BIT - RW controller starts its transfers in 10-bit 167 * address mode, else 7-bit. 168 * 169 * SPECIAL - RW Indicates whether software performs a General Call 170 * or START BYTE command. 171 * 172 * 0 Ignore GC_OR_START and use TAR address. 173 * 174 * 1 Perform special I2C Command based on GC_OR_START. 175 * 176 * GC_OR_START - RW (only if SPECIAL is set) 177 * 178 * 0 General Call Address. After issuing a General Call, 179 * only writes may be performed. Attempting to issue 180 * a read command results in IX_ABRT in RAW_INTR_STAT. 181 * The controller remains in General Call mode until 182 * bit 11 (SPECIAL) is cleared. 183 * 184 * 1 START BYTE. 185 * 186 * 187 * IC_TAR - RW when transmitting a general call, these bits are 188 * ignored. To generate a START BYTE, the address 189 * needs to be written into these bits once. 190 * 191 * This register should only be updated when the IIC is disabled (I2C_ENABLE=0) 192 */ 193 #define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */ 194 #define IG4_TAR_SPECIAL 0x0800 /* Perform special command */ 195 #define IG4_TAR_GC_OR_START 0x0400 /* General Call or Start */ 196 #define IG4_TAR_ADDR_MASK 0x03FF /* Target address */ 197 198 /* 199 * TAR_DATA_CMD - Data Buffer and Command Register 22.2.3 200 * 201 * RESTART - RW This bit controls whether a forced RESTART is 202 * issued before the byte is sent or received. 203 * 204 * 0 If not set a RESTART is only issued if the transfer 205 * direction is changing from the previous command. 206 * 207 * 1 A RESTART is issued before the byte is sent or 208 * received, regardless of whether or not the transfer 209 * direction is changing from the previous command. 210 * 211 * STOP - RW This bit controls whether a STOP is issued after 212 * the byte is sent or received. 213 * 214 * 0 STOP is not issued after this byte, regardless 215 * of whether or not the Tx FIFO is empty. 216 * 217 * 1 STOP is issued after this byte, regardless of 218 * whether or not the Tx FIFO is empty. If the 219 * Tx FIFO is not empty the master immediately tries 220 * to start a new transfer by issuing a START and 221 * arbitrating for the bus. 222 * 223 * i.e. the STOP is issued along with this byte, 224 * within the write stream. 225 * 226 * COMMAND - RW Control whether a read or write is performed. 227 * 228 * 0 WRITE 229 * 230 * 1 READ 231 * 232 * DATA (7:0) - RW Contains the data to be transmitted or received 233 * on the I2C bus. 234 * 235 * NOTE: Writing to this register causes a START + slave + RW to be 236 * issued if the direction has changed or the last data byte was 237 * sent with a STOP. 238 * 239 * NOTE: We control termination? so this register must be written 240 * for each byte we wish to receive. We can then drain the 241 * receive FIFO. 242 */ 243 244 #define IG4_DATA_RESTART 0x0400 /* Force RESTART */ 245 #define IG4_DATA_STOP 0x0200 /* Force STOP[+START] */ 246 #define IG4_DATA_COMMAND_RD 0x0100 /* bus direction 0=write 1=read */ 247 #define IG4_DATA_MASK 0x00FF 248 249 /* 250 * SS_SCL_HCNT - Standard Speed Clock High Count Register 22.2.4 251 * SS_SCL_LCNT - Standard Speed Clock Low Count Register 22.2.5 252 * FS_SCL_HCNT - Fast Speed Clock High Count Register 22.2.6 253 * FS_SCL_LCNT - Fast Speed Clock Low Count Register 22.2.7 254 * 255 * COUNT (15:0) - Set the period count to a value between 6 and 256 * 65525. 257 */ 258 #define IG4_SCL_CLOCK_MASK 0xFFFFU /* count bits in register */ 259 260 /* 261 * INTR_STAT - (RO) Interrupt Status Register 22.2.8 262 * INTR_MASK - (RW) Interrupt Mask Register 22.2.9 263 * RAW_INTR_STAT- (RO) Raw Interrupt Status Register 22.2.10 264 * 265 * GEN_CALL Set only when a general call (broadcast) address 266 * is received and acknowleged, stays set until 267 * cleared by reading CLR_GEN_CALL. 268 * 269 * START_DET Set when a START or RESTART condition has occurred 270 * on the interface. 271 * 272 * STOP_DET Set when a STOP condition has occurred on the 273 * interface. 274 * 275 * ACTIVITY Set by any activity on the interface. Cleared 276 * by reading CLR_ACTIVITY or CLR_INTR. 277 * 278 * TX_ABRT Indicates the controller as a transmitter is 279 * unable to complete the intended action. When set, 280 * the controller will hold the TX FIFO in a reset 281 * state (flushed) until CLR_TX_ABORT is read to 282 * clear the condition. Once cleared, the TX FIFO 283 * will be available again. 284 * 285 * TX_EMPTY Indicates that the transmitter is at or below 286 * the specified TX_TL threshold. Automatically 287 * cleared by HW when the buffer level goes above 288 * the threshold. 289 * 290 * TX_OVER Indicates that the processor attempted to write 291 * to the TX FIFO while the TX FIFO was full. Cleared 292 * by reading CLR_TX_OVER. 293 * 294 * RX_FULL Indicates that the receive FIFO has reached or 295 * exceeded the specified RX_TL threshold. Cleared 296 * by HW when the cpu drains the FIFO to below the 297 * threshold. 298 * 299 * RX_OVER Indicates that the receive FIFO was unable to 300 * accept new data and data was lost. Cleared by 301 * reading CLR_RX_OVER. 302 * 303 * RX_UNDER Indicates that the cpu attempted to read data 304 * from the receive buffer while the RX FIFO was 305 * empty. Cleared by reading CLR_RX_UNDER. 306 * 307 * NOTES ON RAW_INTR_STAT: 308 * 309 * This register can be used to monitor the GEN_CALL, START_DET, 310 * STOP_DET, ACTIVITY, TX_ABRT, TX_EMPTY, TX_OVER, RX_FULL, RX_OVER, 311 * and RX_UNDER bits. The documentation is a bit unclear but presumably 312 * this is the unlatched version. 313 * 314 * Code should test FIFO conditions using the I2C_STA (status) register, 315 * not the interrupt status registers. 316 */ 317 318 #define IG4_INTR_GEN_CALL 0x0800 319 #define IG4_INTR_START_DET 0x0400 320 #define IG4_INTR_STOP_DET 0x0200 321 #define IG4_INTR_ACTIVITY 0x0100 322 #define IG4_INTR_TX_ABRT 0x0040 323 #define IG4_INTR_TX_EMPTY 0x0010 324 #define IG4_INTR_TX_OVER 0x0008 325 #define IG4_INTR_RX_FULL 0x0004 326 #define IG4_INTR_RX_OVER 0x0002 327 #define IG4_INTR_RX_UNDER 0x0001 328 329 #define IG4_INTR_ERR_MASK (IG4_INTR_TX_ABRT | IG4_INTR_TX_OVER | \ 330 IG4_INTR_RX_OVER | IG4_INTR_RX_UNDER) 331 332 /* 333 * RX_TL - (RW) Receive FIFO Threshold Register 22.2.11 334 * TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12 335 * 336 * Specify the receive and transmit FIFO threshold register. The 337 * FIFOs have 16 elements. The valid range is 0-15. Setting a 338 * value greater than 15 causes the actual value to be the maximum 339 * depth of the FIFO. 340 * 341 * Generally speaking since everything is messaged, we can use a 342 * mid-level setting for both parameters and (e.g.) fully drain the 343 * receive FIFO on the STOP_DET condition to handle loose ends. 344 */ 345 #define IG4_FIFO_MASK 0x00FF 346 #define IG4_FIFO_LIMIT 16 347 348 /* 349 * CLR_INTR - (RO) Clear Interrupt Register 22.2.13 350 * CLR_RX_UNDER - (RO) Clear Interrupt Register (specific) 22.2.14 351 * CLR_RX_OVER - (RO) Clear Interrupt Register (specific) 22.2.15 352 * CLR_TX_OVER - (RO) Clear Interrupt Register (specific) 22.2.16 353 * CLR_TX_ABORT - (RO) Clear Interrupt Register (specific) 22.2.17 354 * CLR_ACTIVITY - (RO) Clear Interrupt Register (specific) 22.2.18 355 * CLR_STOP_DET - (RO) Clear Interrupt Register (specific) 22.2.19 356 * CLR_START_DET- (RO) Clear Interrupt Register (specific) 22.2.20 357 * CLR_GEN_CALL - (RO) Clear Interrupt Register (specific) 22.2.21 358 * 359 * CLR_* specific operations clear the appropriate bit in the 360 * RAW_INTR_STAT register. Intel does not really document whether 361 * these operations clear the normal interrupt status register. 362 * 363 * CLR_INTR clears bits in the normal interrupt status register and 364 * presumably also the raw(?) register? Intel is again unclear. 365 * 366 * NOTE: CLR_INTR only clears software-clearable interrupts. Hardware 367 * clearable interrupts are controlled entirely by the hardware. 368 * CLR_INTR also clears the TX_ABRT_SOURCE register. 369 * 370 * NOTE: CLR_TX_ABORT also clears the TX_ABRT_SOURCE register and releases 371 * the TX FIFO from its flushed/reset state, allowing more writes 372 * to the TX FIFO. 373 * 374 * NOTE: CLR_ACTIVITY has no effect if the I2C bus is still active. 375 * Intel documents that the bit is automatically cleared when 376 * there is no further activity on the bus. 377 */ 378 #define IG4_CLR_BIT 0x0001 /* Reflects source */ 379 380 /* 381 * I2C_EN - (RW) I2C Enable Register 22.2.22 382 * 383 * ABORT Software can abort an I2C transfer by setting this 384 * bit. In response, the controller issues the STOP 385 * condition over the I2C bus, followed by TX FIFO flush. 386 * Hardware will clear the bit once the STOP has 387 * been detected. This bit can only be set while the 388 * I2C interface is enabled. 389 * 390 * I2C_ENABLE Enable the controller, else disable it. 391 * (Use I2C_ENABLE_STATUS to poll enable status 392 * & wait for changes) 393 */ 394 #define IG4_I2C_ABORT 0x0002 395 #define IG4_I2C_ENABLE 0x0001 396 397 /* 398 * I2C_STA - (RO) I2C Status Register 22.2.23 399 */ 400 #define IG4_STATUS_ACTIVITY 0x0020 /* Controller is active */ 401 #define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */ 402 #define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */ 403 #define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */ 404 #define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */ 405 #define IG4_STATUS_I2C_ACTIVE 0x0001 /* I2C bus is active */ 406 407 /* 408 * TXFLR - (RO) Transmit FIFO Level Register 22.2.24 409 * RXFLR - (RO) Receive FIFO Level Register 22.2.25 410 * 411 * Read the number of entries currently in the Transmit or Receive 412 * FIFOs. Note that for some reason the mask is 9 bits instead of 413 * the 8 bits the fill level controls. 414 */ 415 #define IG4_FIFOLVL_MASK 0x01FF 416 417 /* 418 * SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26 419 * 420 * Set the SDA hold time length register in I2C clocks. 421 */ 422 #define IG4_SDA_TX_HOLD_MASK 0x0000FFFF 423 424 /* 425 * TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27 426 * 427 * Indicates the cause of a transmit abort. This can indicate a 428 * software programming error or a device expected address width 429 * mismatch or other issues. The NORESTART conditions and GENCALL_NOACK 430 * can only occur if a programming error was made in the driver software. 431 * 432 * In particular, it should be possible to detect whether any devices 433 * are on the bus by observing the GENCALL_READ status, and it might 434 * be possible to detect ADDR7 vs ADDR10 mismatches. 435 */ 436 #define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */ 437 #define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */ 438 #define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */ 439 #define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */ 440 #define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */ 441 #define IG4_ABRTSRC_GENCALL_READ 0x00000020 /* Improper GENCALL */ 442 #define IG4_ABRTSRC_GENCALL_NOACK 0x00000010 /* Nobody acked GENCALL */ 443 #define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */ 444 #define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */ 445 #define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */ 446 #define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */ 447 448 /* 449 * SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28 450 * 451 * When the controller is a receiver a NACK can be generated on 452 * receipt of data. 453 * 454 * NACK_GENERATE Set to 0 for normal NACK/ACK generation. 455 * Set to 1 to generate a NACK after next data 456 * byte received. 457 * 458 */ 459 #define IG4_NACK_GENERATE 0x0001 460 461 /* 462 * DMA_CTRL - (RW) DMA Control Register 22.2.29 463 * 464 * Enables DMA on the transmit and/or receive DMA channel. 465 */ 466 #define IG4_TX_DMA_ENABLE 0x0002 467 #define IG4_RX_DMA_ENABLE 0x0001 468 469 /* 470 * DMA_TDLR - (RW) DMA Transmit Data Level Register 22.2.30 471 * DMA_RDLR - (RW) DMA Receive Data Level Register 22.2.31 472 * 473 * Similar to RX_TL and TX_TL but controls when a DMA burst occurs 474 * to empty or fill the FIFOs. Use the same IG4_FIFO_MASK and 475 * IG4_FIFO_LIMIT defines for RX_RL and TX_TL. 476 */ 477 /* empty */ 478 479 /* 480 * SDA_SETUP - (RW) SDA Setup Time Length Register 22.2.32 481 * 482 * Set the SDA setup time length register in I2C clocks. 483 * The register must be programmed with a value >=2. 484 * (Defaults to 0x64). 485 */ 486 #define IG4_SDA_SETUP_MASK 0x00FF 487 488 /* 489 * ACK_GEN_CALL - (RW) ACK General Call Register 22.2.33 490 * 491 * Control whether the controller responds with a ACK or NACK when 492 * it receives an I2C General Call address. 493 * 494 * If set to 0 a NACK is generated and a General Call interrupt is 495 * NOT generated. Otherwise an ACK + interrupt is generated. 496 */ 497 #define IG4_ACKGC_ACK 0x0001 498 499 /* 500 * ENABLE_STATUS - (RO) Enable Status Registger 22.2.34 501 * 502 * DATA_LOST - Indicates that a slave receiver operation has 503 * been aborted with at least one data byte received 504 * from a transfer due to the I2C controller being 505 * disabled (IG4_I2C_ENABLE -> 0) 506 * 507 * ENABLED - Intel documentation is lacking but I assume this 508 * is a reflection of the IG4_I2C_ENABLE bit in the 509 * I2C_EN register. 510 * 511 */ 512 #define IG4_ENASTAT_DATA_LOST 0x0004 513 #define IG4_ENASTAT_ENABLED 0x0001 514 515 /* 516 * COMP_PARAM1 - (RO) Component Parameter Register 22.2.35 517 * Default Value 0x00FFFF6E 518 * 519 * VALID - Intel documentation is unclear but I believe this 520 * must be read as a 1 to indicate that the rest of 521 * the bits in the register are valid. 522 * 523 * HASDMA - Indicates that the chip is DMA-capable. Presumably 524 * in certain virtualization cases the chip might be 525 * set to not be DMA-capable. 526 * 527 * INTR_IO - Indicates that all interrupts are combined to 528 * generate one interrupt. If not set, interrupts 529 * are individual (more virtualization stuff?) 530 * 531 * HCCNT_RO - Indicates that the clock timing registers are 532 * RW. If not set, the registers are RO. 533 * (more virtualization stuff). 534 * 535 * MAXSPEED - Indicates the maximum speed supported. 536 * 537 * DATAW - Indicates the internal bus width in bits. 538 */ 539 #define IG4_PARAM1_TXFIFO_DEPTH(v) ((((v) >> 16) & 0xFF) + 1) 540 #define IG4_PARAM1_RXFIFO_DEPTH(v) ((((v) >> 8) & 0xFF) + 1) 541 #define IG4_PARAM1_CONFIG_VALID 0x00000080 542 #define IG4_PARAM1_CONFIG_HASDMA 0x00000040 543 #define IG4_PARAM1_CONFIG_INTR_IO 0x00000020 544 #define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010 545 #define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C 546 #define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003 547 548 #define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000 549 #define IG4_CONFIG_MAXSPEED_STANDARD 0x00000004 550 #define IG4_CONFIG_MAXSPEED_FAST 0x00000008 551 #define IG4_CONFIG_MAXSPEED_HIGH 0x0000000C 552 553 #define IG4_CONFIG_DATAW_8 0x00000000 554 #define IG4_CONFIG_DATAW_16 0x00000001 555 #define IG4_CONFIG_DATAW_32 0x00000002 556 #define IG4_CONFIG_DATAW_RESERVED11 0x00000003 557 558 /* 559 * COMP_VER - (RO) Component Version Register 22.2.36 560 * 561 * Contains the chip version number. All 32 bits. 562 */ 563 #define IG4_COMP_MIN_VER 0x3131352A 564 565 /* 566 * COMP_TYPE - (RO) (linux) Endian and bus width probe 567 * 568 * Read32 from this register and test against IG4_COMP_TYPE 569 * to determine the bus width. e.g. 01404457 = endian-reversed, 570 * and 00000140 or 00004457 means internal 16-bit bus (?). 571 * 572 * This register is not in the intel documentation, I pulled it 573 * from the linux driver i2c-designware-core.c. 574 */ 575 #define IG4_COMP_TYPE 0x44570140 576 577 /* 578 * RESETS - (RW) Resets Register 22.2.37 579 * 580 * Used to reset the I2C host controller by SW. There is no timing 581 * requirement, software can assert and de-assert in back-to-back 582 * transactions. 583 * 584 * 00 I2C host controller is NOT in reset. 585 * 01 (reserved) 586 * 10 (reserved) 587 * 11 I2C host controller is in reset. 588 */ 589 #define IG4_RESETS_ASSERT_HSW 0x0003 590 #define IG4_RESETS_DEASSERT_HSW 0x0000 591 592 /* Skylake-U/Y and Kaby Lake-U/Y have the reset bits inverted */ 593 #define IG4_RESETS_DEASSERT_SKL 0x0003 594 #define IG4_RESETS_ASSERT_SKL 0x0000 595 596 /* Newer versions of the I2C controller allow to check whether 597 * the above ASSERT/DEASSERT is necessary by querying the DEVIDLE_CONTROL 598 * register. 599 * 600 * the RESTORE_REQUIRED bit can be cleared by writing 1 601 * the DEVICE_IDLE status can be set to put the controller in an idle state 602 * 603 */ 604 #define IG4_RESTORE_REQUIRED 0x0008 605 #define IG4_DEVICE_IDLE 0x0004 606 607 /* 608 * GENERAL - (RW) General Reigster 22.2.38 609 * 610 * IOVOLT 0=1.8V 1=3.3V 611 * 612 * LTR 0=Auto 1=SW 613 * 614 * In Auto mode the BIOS will write to the host controller's 615 * AUTO LTR Value register (offset 0x0814) with the active 616 * state LTR value, and will write to the SW LTR Value register 617 * (offset 0x0810) with the idle state LTR value. 618 * 619 * In SW mode the SW will write to the host controller SW LTR 620 * value (offset 0x0810). It is the SW responsibility to update 621 * the LTR with the appropriate value. 622 */ 623 #define IG4_GENERAL_IOVOLT3_3 0x0008 624 #define IG4_GENERAL_SWMODE 0x0004 625 626 /* 627 * SW_LTR_VALUE - (RW) SW LTR Value Register 22.2.39 628 * AUTO_LTR_VALUE - (RW) SW LTR Value Register 22.2.40 629 * 630 * Default value is 0x00000800 which means the best possible 631 * service/response time. 632 * 633 * It isn't quite clear how the snooping works. There are two scale 634 * bits for both sets but two of the four codes are reserved. The 635 * *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it 636 * indicates that the device cannot tolerate any delay and needs the 637 * best possible service/response time. 638 * 639 * I think this is for snooping (testing) the I2C bus. The lowest 640 * delay (0) probably runs the controller polling at a high, power hungry 641 * rate. But I dunno. 642 */ 643 #define IG4_SWLTR_NSNOOP_REQ 0x80000000 /* (ro) */ 644 #define IG4_SWLTR_NSNOOP_SCALE_MASK 0x1C000000 /* (ro) */ 645 #define IG4_SWLTR_NSNOOP_SCALE_1US 0x08000000 /* (ro) */ 646 #define IG4_SWLTR_NSNOOP_SCALE_32US 0x0C000000 /* (ro) */ 647 #define IG4_SWLTR_NSNOOP_VALUE_DECODE(v) (((v) >> 16) & 0x3F) 648 #define IG4_SWLTR_NSNOOP_VALUE_ENCODE(v) (((v) & 0x3F) << 16) 649 650 #define IG4_SWLTR_SNOOP_REQ 0x00008000 /* (rw) */ 651 #define IG4_SWLTR_SNOOP_SCALE_MASK 0x00001C00 /* (rw) */ 652 #define IG4_SWLTR_SNOOP_SCALE_1US 0x00000800 /* (rw) */ 653 #define IG4_SWLTR_SNOOP_SCALE_32US 0x00000C00 /* (rw) */ 654 #define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F) 655 #define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F) 656 657 #endif /* _ICHIIC_IG4_REG_H_ */ 658