1 /*- 2 * ichsmb_pci.c 3 * 4 * Author: Archie Cobbs <archie@freebsd.org> 5 * Copyright (c) 2000 Whistle Communications, Inc. 6 * All rights reserved. 7 * Author: Archie Cobbs <archie@freebsd.org> 8 * 9 * Subject to the following obligations and disclaimer of warranty, use and 10 * redistribution of this software, in source or object code forms, with or 11 * without modifications are expressly permitted by Whistle Communications; 12 * provided, however, that: 13 * 1. Any and all reproductions of the source or object code must include the 14 * copyright notice above and the following disclaimer of warranties; and 15 * 2. No rights are granted, in any manner or form, to use Whistle 16 * Communications, Inc. trademarks, including the mark "WHISTLE 17 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 18 * such appears in the above copyright notice or in the software. 19 * 20 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 21 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 22 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 23 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 25 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 26 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 27 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 28 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 29 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 30 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 31 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 36 * OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 /* 41 * Support for the SMBus controller logical device which is part of the 42 * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips. 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/errno.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/syslog.h> 53 #include <sys/bus.h> 54 55 #include <machine/bus.h> 56 #include <sys/rman.h> 57 #include <machine/resource.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 62 #include <dev/smbus/smbconf.h> 63 64 #include <dev/ichsmb/ichsmb_var.h> 65 #include <dev/ichsmb/ichsmb_reg.h> 66 67 /* PCI unique identifiers */ 68 #define PCI_VENDOR_INTEL 0x8086 69 #define ID_82801AA 0x2413 70 #define ID_82801AB 0x2423 71 #define ID_82801BA 0x2443 72 #define ID_82801CA 0x2483 73 #define ID_82801DC 0x24C3 74 #define ID_82801EB 0x24D3 75 #define ID_82801FB 0x266A 76 #define ID_82801GB 0x27da 77 #define ID_82801H 0x283e 78 #define ID_82801I 0x2930 79 #define ID_EP80579 0x5032 80 #define ID_82801JI 0x3a30 81 #define ID_82801JD 0x3a60 82 #define ID_PCH 0x3b30 83 #define ID_6300ESB 0x25a4 84 #define ID_631xESB 0x269b 85 #define ID_DH89XXCC 0x2330 86 #define ID_PATSBURG 0x1d22 87 #define ID_CPT 0x1c22 88 #define ID_PPT 0x1e22 89 #define ID_AVOTON 0x1f3c 90 #define ID_COLETOCRK 0x23B0 91 #define ID_LPT 0x8c22 92 #define ID_LPTLP 0x9c22 93 #define ID_WCPT 0x8ca2 94 #define ID_WCPTLP 0x9ca2 95 #define ID_BAYTRAIL 0x0f12 96 #define ID_BRASWELL 0x2292 97 #define ID_WELLSBURG 0x8d22 98 #define ID_SRPT 0xa123 99 #define ID_SRPTLP 0x9d23 100 #define ID_DENVERTON 0x19df 101 #define ID_BROXTON 0x5ad4 102 #define ID_LEWISBURG 0xa1a3 103 #define ID_LEWISBURG2 0xa223 104 #define ID_KABYLAKE 0xa2a3 105 #define ID_CANNONLAKE 0xa323 106 #define ID_COMETLAKE 0x02a3 107 #define ID_COMETLAKE2 0x06a3 108 #define ID_TIGERLAKE 0xa0a3 109 #define ID_TIGERLAKE2 0x43a3 110 #define ID_GEMINILAKE 0x31d4 111 #define ID_ICELAKE 0x34a3 112 #define ID_ALDERLAKE 0x7aa3 113 #define ID_ALDERLAKE2 0x51a3 114 #define ID_ALDERLAKE3 0x54a3 115 116 static const struct pci_device_table ichsmb_devices[] = { 117 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AA), 118 PCI_DESCR("Intel 82801AA (ICH) SMBus controller") }, 119 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AB), 120 PCI_DESCR("Intel 82801AB (ICH0) SMBus controller") }, 121 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801BA), 122 PCI_DESCR("Intel 82801BA (ICH2) SMBus controller") }, 123 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801CA), 124 PCI_DESCR("Intel 82801CA (ICH3) SMBus controller") }, 125 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801DC), 126 PCI_DESCR("Intel 82801DC (ICH4) SMBus controller") }, 127 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801EB), 128 PCI_DESCR("Intel 82801EB (ICH5) SMBus controller") }, 129 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801FB), 130 PCI_DESCR("Intel 82801FB (ICH6) SMBus controller") }, 131 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB), 132 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") }, 133 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H), 134 PCI_DESCR("Intel 82801H (ICH8) SMBus controller") }, 135 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I), 136 PCI_DESCR("Intel 82801I (ICH9) SMBus controller") }, 137 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB), 138 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") }, 139 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H), 140 PCI_DESCR("Intel 82801H (ICH8) SMBus controller") }, 141 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I), 142 PCI_DESCR("Intel 82801I (ICH9) SMBus controller") }, 143 { PCI_DEV(PCI_VENDOR_INTEL, ID_EP80579), 144 PCI_DESCR("Intel EP80579 SMBus controller") }, 145 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JI), 146 PCI_DESCR("Intel 82801JI (ICH10) SMBus controller") }, 147 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JD), 148 PCI_DESCR("Intel 82801JD (ICH10) SMBus controller") }, 149 { PCI_DEV(PCI_VENDOR_INTEL, ID_PCH), 150 PCI_DESCR("Intel PCH SMBus controller") }, 151 { PCI_DEV(PCI_VENDOR_INTEL, ID_6300ESB), 152 PCI_DESCR("Intel 6300ESB (ICH) SMBus controller") }, 153 { PCI_DEV(PCI_VENDOR_INTEL, ID_631xESB), 154 PCI_DESCR("Intel 631xESB/6321ESB (ESB2) SMBus controller") }, 155 { PCI_DEV(PCI_VENDOR_INTEL, ID_DH89XXCC), 156 PCI_DESCR("Intel DH89xxCC SMBus controller") }, 157 { PCI_DEV(PCI_VENDOR_INTEL, ID_PATSBURG), 158 PCI_DESCR("Intel Patsburg SMBus controller") }, 159 { PCI_DEV(PCI_VENDOR_INTEL, ID_CPT), 160 PCI_DESCR("Intel Cougar Point SMBus controller") }, 161 { PCI_DEV(PCI_VENDOR_INTEL, ID_PPT), 162 PCI_DESCR("Intel Panther Point SMBus controller") }, 163 { PCI_DEV(PCI_VENDOR_INTEL, ID_AVOTON), 164 PCI_DESCR("Intel Avoton SMBus controller") }, 165 { PCI_DEV(PCI_VENDOR_INTEL, ID_LPT), 166 PCI_DESCR("Intel Lynx Point SMBus controller") }, 167 { PCI_DEV(PCI_VENDOR_INTEL, ID_LPTLP), 168 PCI_DESCR("Intel Lynx Point-LP SMBus controller") }, 169 { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPT), 170 PCI_DESCR("Intel Wildcat Point SMBus controller") }, 171 { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPTLP), 172 PCI_DESCR("Intel Wildcat Point-LP SMBus controller") }, 173 { PCI_DEV(PCI_VENDOR_INTEL, ID_BAYTRAIL), 174 PCI_DESCR("Intel Baytrail SMBus controller") }, 175 { PCI_DEV(PCI_VENDOR_INTEL, ID_BRASWELL), 176 PCI_DESCR("Intel Braswell SMBus controller") }, 177 { PCI_DEV(PCI_VENDOR_INTEL, ID_COLETOCRK), 178 PCI_DESCR("Intel Coleto Creek SMBus controller") }, 179 { PCI_DEV(PCI_VENDOR_INTEL, ID_WELLSBURG), 180 PCI_DESCR("Intel Wellsburg SMBus controller") }, 181 { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPT), 182 PCI_DESCR("Intel Sunrise Point-H SMBus controller") }, 183 { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPTLP), 184 PCI_DESCR("Intel Sunrise Point-LP SMBus controller") }, 185 { PCI_DEV(PCI_VENDOR_INTEL, ID_DENVERTON), 186 PCI_DESCR("Intel Denverton SMBus controller") }, 187 { PCI_DEV(PCI_VENDOR_INTEL, ID_BROXTON), 188 PCI_DESCR("Intel Broxton SMBus controller") }, 189 { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG), 190 PCI_DESCR("Intel Lewisburg SMBus controller") }, 191 { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG2), 192 PCI_DESCR("Intel Lewisburg SMBus controller") }, 193 { PCI_DEV(PCI_VENDOR_INTEL, ID_KABYLAKE), 194 PCI_DESCR("Intel Kaby Lake SMBus controller") }, 195 { PCI_DEV(PCI_VENDOR_INTEL, ID_CANNONLAKE), 196 PCI_DESCR("Intel Cannon Lake SMBus controller") }, 197 { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE), 198 PCI_DESCR("Intel Comet Lake SMBus controller") }, 199 { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE2), 200 PCI_DESCR("Intel Comet Lake SMBus controller") }, 201 { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE), 202 PCI_DESCR("Intel Tiger Lake SMBus controller") }, 203 { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE2), 204 PCI_DESCR("Intel Tiger Lake SMBus controller") }, 205 { PCI_DEV(PCI_VENDOR_INTEL, ID_GEMINILAKE), 206 PCI_DESCR("Intel Gemini Lake SMBus controller") }, 207 { PCI_DEV(PCI_VENDOR_INTEL, ID_ICELAKE), 208 PCI_DESCR("Intel Ice Lake SMBus controller") }, 209 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE), 210 PCI_DESCR("Intel Alder Lake SMBus controller") }, 211 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE2), 212 PCI_DESCR("Intel Alder Lake SMBus controller") }, 213 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE3), 214 PCI_DESCR("Intel Alder Lake SMBus controller") }, 215 }; 216 217 /* Internal functions */ 218 static int ichsmb_pci_probe(device_t dev); 219 static int ichsmb_pci_attach(device_t dev); 220 /*Use generic one for now*/ 221 #if 0 222 static int ichsmb_pci_detach(device_t dev); 223 #endif 224 225 /* Device methods */ 226 static device_method_t ichsmb_pci_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, ichsmb_pci_probe), 229 DEVMETHOD(device_attach, ichsmb_pci_attach), 230 DEVMETHOD(device_detach, ichsmb_detach), 231 232 /* SMBus methods */ 233 DEVMETHOD(smbus_callback, ichsmb_callback), 234 DEVMETHOD(smbus_quick, ichsmb_quick), 235 DEVMETHOD(smbus_sendb, ichsmb_sendb), 236 DEVMETHOD(smbus_recvb, ichsmb_recvb), 237 DEVMETHOD(smbus_writeb, ichsmb_writeb), 238 DEVMETHOD(smbus_writew, ichsmb_writew), 239 DEVMETHOD(smbus_readb, ichsmb_readb), 240 DEVMETHOD(smbus_readw, ichsmb_readw), 241 DEVMETHOD(smbus_pcall, ichsmb_pcall), 242 DEVMETHOD(smbus_bwrite, ichsmb_bwrite), 243 DEVMETHOD(smbus_bread, ichsmb_bread), 244 245 DEVMETHOD_END 246 }; 247 248 static driver_t ichsmb_pci_driver = { 249 "ichsmb", 250 ichsmb_pci_methods, 251 sizeof(struct ichsmb_softc) 252 }; 253 254 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, 0, 0); 255 256 static int 257 ichsmb_pci_probe(device_t dev) 258 { 259 const struct pci_device_table *tbl; 260 261 tbl = PCI_MATCH(dev, ichsmb_devices); 262 if (tbl == NULL) 263 return (ENXIO); 264 265 device_set_desc(dev, tbl->descr); 266 return (ichsmb_probe(dev)); 267 } 268 269 static int 270 ichsmb_pci_attach(device_t dev) 271 { 272 const sc_p sc = device_get_softc(dev); 273 int error; 274 275 /* Initialize private state */ 276 bzero(sc, sizeof(*sc)); 277 sc->ich_cmd = -1; 278 sc->dev = dev; 279 280 /* Allocate an I/O range */ 281 sc->io_rid = ICH_SMB_BASE; 282 sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 283 &sc->io_rid, 16, RF_ACTIVE); 284 if (sc->io_res == NULL) 285 sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 286 &sc->io_rid, 32, RF_ACTIVE); 287 if (sc->io_res == NULL) { 288 device_printf(dev, "can't map I/O\n"); 289 error = ENXIO; 290 goto fail; 291 } 292 293 /* Allocate interrupt */ 294 sc->irq_rid = 0; 295 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 296 &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE); 297 if (sc->irq_res == NULL) { 298 device_printf(dev, "can't get IRQ\n"); 299 error = ENXIO; 300 goto fail; 301 } 302 303 /* Enable device */ 304 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); 305 306 /* Done */ 307 error = ichsmb_attach(dev); 308 if (error) 309 goto fail; 310 return (0); 311 312 fail: 313 /* Attach failed, release resources */ 314 ichsmb_release_resources(sc); 315 return (error); 316 } 317 318 319 MODULE_DEPEND(ichsmb, pci, 1, 1, 1); 320 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); 321 MODULE_VERSION(ichsmb, 1); 322 PCI_PNP_INFO(ichsmb_devices); 323