1 /*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 * SoC PMC support by Denir Li <denir.li@cas-well.com> 57 */ 58 59 #include <sys/cdefs.h> 60 __FBSDID("$FreeBSD$"); 61 62 #include <sys/param.h> 63 #include <sys/kernel.h> 64 #include <sys/module.h> 65 #include <sys/systm.h> 66 #include <sys/bus.h> 67 #include <machine/bus.h> 68 #include <sys/rman.h> 69 #include <machine/resource.h> 70 #include <sys/watchdog.h> 71 72 #include <isa/isavar.h> 73 #include <dev/pci/pcivar.h> 74 75 #include <dev/ichwd/ichwd.h> 76 77 static struct ichwd_device ichwd_devices[] = { 78 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, 79 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, 80 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 }, 81 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 }, 82 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 }, 83 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 }, 84 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 }, 85 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 }, 86 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 }, 87 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 }, 88 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 }, 89 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 }, 90 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 }, 91 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 }, 92 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 }, 93 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 }, 94 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 }, 95 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 }, 96 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 }, 97 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 }, 98 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 }, 99 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 }, 100 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 }, 101 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 }, 102 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 }, 103 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 }, 104 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 }, 105 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 }, 106 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 }, 107 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 }, 108 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 }, 109 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 }, 110 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 }, 111 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 }, 112 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 }, 113 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 }, 114 { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 }, 115 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 }, 116 { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 }, 117 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 }, 118 { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 }, 119 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 }, 120 { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 }, 121 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 }, 122 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 }, 123 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 }, 124 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 }, 125 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 }, 126 { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 }, 127 { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 }, 128 { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 }, 129 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 }, 130 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 }, 131 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 }, 132 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 }, 133 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 }, 134 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 }, 135 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 }, 136 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 }, 137 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 }, 138 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 }, 139 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 }, 140 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 }, 141 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 }, 142 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 }, 143 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 }, 144 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 }, 145 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 }, 146 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 }, 147 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 }, 148 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 }, 149 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 }, 150 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 }, 151 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 }, 152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 }, 153 { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 }, 154 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 }, 155 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 }, 156 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 }, 157 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 }, 158 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 }, 159 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 }, 160 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 }, 161 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 }, 162 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 }, 163 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 }, 164 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 }, 165 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 }, 166 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 }, 167 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 }, 168 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 }, 169 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 }, 170 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 }, 171 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 }, 172 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 }, 173 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 }, 174 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 }, 175 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 }, 176 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 }, 177 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 }, 178 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 }, 179 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 }, 180 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 }, 181 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 }, 182 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 }, 183 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 }, 184 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 }, 185 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 }, 186 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 }, 187 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 }, 188 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 }, 189 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 }, 190 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 }, 191 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 }, 192 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 }, 193 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 }, 194 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 }, 195 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 }, 196 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 }, 197 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 }, 198 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 }, 199 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 }, 200 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 }, 201 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 }, 202 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 }, 203 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 }, 204 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 }, 205 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 }, 206 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 }, 207 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 }, 208 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 }, 209 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 }, 210 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 }, 211 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 }, 212 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 }, 213 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 }, 214 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 }, 215 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 }, 216 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 }, 217 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 }, 218 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 }, 219 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 }, 220 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 }, 221 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 }, 222 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 }, 223 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 }, 224 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 }, 225 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 }, 226 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 }, 227 { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 }, 228 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 }, 229 { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 }, 230 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 }, 231 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 }, 232 { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 }, 233 { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 }, 234 { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 }, 235 { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 }, 236 { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 }, 237 { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 }, 238 { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 }, 239 { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 }, 240 { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 }, 241 { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 }, 242 { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 }, 243 { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 }, 244 { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 }, 245 { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 }, 246 { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 }, 247 { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 }, 248 { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 }, 249 { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 }, 250 { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 }, 251 { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 }, 252 { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 }, 253 { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 }, 254 { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 }, 255 { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 }, 256 { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 }, 257 { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 }, 258 { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 }, 259 { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 }, 260 { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 }, 261 { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 }, 262 { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 }, 263 { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 }, 264 { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 265 { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 266 { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 267 { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 268 { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 269 { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 270 { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 271 { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 272 { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 273 { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 274 { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 275 { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 276 { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 277 { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 278 { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 279 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 }, 280 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 }, 281 { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 282 { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 283 { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 284 { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 285 { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 }, 286 { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 }, 287 { 0, NULL, 0, 0 }, 288 }; 289 290 static devclass_t ichwd_devclass; 291 292 #define ichwd_read_tco_1(sc, off) \ 293 bus_read_1((sc)->tco_res, (off)) 294 #define ichwd_read_tco_2(sc, off) \ 295 bus_read_2((sc)->tco_res, (off)) 296 #define ichwd_read_tco_4(sc, off) \ 297 bus_read_4((sc)->tco_res, (off)) 298 #define ichwd_read_smi_4(sc, off) \ 299 bus_read_4((sc)->smi_res, (off)) 300 #define ichwd_read_gcs_4(sc, off) \ 301 bus_read_4((sc)->gcs_res, (off)) 302 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 303 #define ichwd_read_pmc_4(sc, off) \ 304 bus_read_4((sc)->gcs_res, (off)) 305 306 #define ichwd_write_tco_1(sc, off, val) \ 307 bus_write_1((sc)->tco_res, (off), (val)) 308 #define ichwd_write_tco_2(sc, off, val) \ 309 bus_write_2((sc)->tco_res, (off), (val)) 310 #define ichwd_write_tco_4(sc, off, val) \ 311 bus_write_4((sc)->tco_res, (off), (val)) 312 #define ichwd_write_smi_4(sc, off, val) \ 313 bus_write_4((sc)->smi_res, (off), (val)) 314 #define ichwd_write_gcs_4(sc, off, val) \ 315 bus_write_4((sc)->gcs_res, (off), (val)) 316 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 317 #define ichwd_write_pmc_4(sc, off, val) \ 318 bus_write_4((sc)->gcs_res, (off), (val)) 319 320 #define ichwd_verbose_printf(dev, ...) \ 321 do { \ 322 if (bootverbose) \ 323 device_printf(dev, __VA_ARGS__);\ 324 } while (0) 325 326 /* 327 * Disable the watchdog timeout SMI handler. 328 * 329 * Apparently, some BIOSes install handlers that reset or disable the 330 * watchdog timer instead of resetting the system, so we disable the SMI 331 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 332 * from happening. 333 */ 334 static __inline void 335 ichwd_smi_disable(struct ichwd_softc *sc) 336 { 337 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 338 } 339 340 /* 341 * Enable the watchdog timeout SMI handler. See above for details. 342 */ 343 static __inline void 344 ichwd_smi_enable(struct ichwd_softc *sc) 345 { 346 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 347 } 348 349 /* 350 * Check if the watchdog SMI triggering is enabled. 351 */ 352 static __inline int 353 ichwd_smi_is_enabled(struct ichwd_softc *sc) 354 { 355 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 356 } 357 358 /* 359 * Reset the watchdog status bits. 360 */ 361 static __inline void 362 ichwd_sts_reset(struct ichwd_softc *sc) 363 { 364 /* 365 * The watchdog status bits are set to 1 by the hardware to 366 * indicate various conditions. They can be cleared by software 367 * by writing a 1, not a 0. 368 */ 369 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 370 /* 371 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 372 * be done in two separate operations. 373 */ 374 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 375 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 376 } 377 378 /* 379 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 380 * TCO1_CNT register. This is complicated by the need to preserve bit 9 381 * of that same register, and the requirement that all other bits must be 382 * written back as zero. 383 */ 384 static __inline void 385 ichwd_tmr_enable(struct ichwd_softc *sc) 386 { 387 uint16_t cnt; 388 389 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 390 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 391 sc->active = 1; 392 ichwd_verbose_printf(sc->device, "timer enabled\n"); 393 } 394 395 /* 396 * Disable the watchdog timer. See above for details. 397 */ 398 static __inline void 399 ichwd_tmr_disable(struct ichwd_softc *sc) 400 { 401 uint16_t cnt; 402 403 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 404 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 405 sc->active = 0; 406 ichwd_verbose_printf(sc->device, "timer disabled\n"); 407 } 408 409 /* 410 * Reload the watchdog timer: writing anything to any of the lower five 411 * bits of the TCO_RLD register reloads the timer from the last value 412 * written to TCO_TMR. 413 */ 414 static __inline void 415 ichwd_tmr_reload(struct ichwd_softc *sc) 416 { 417 if (sc->tco_version == 1) 418 ichwd_write_tco_1(sc, TCO_RLD, 1); 419 else 420 ichwd_write_tco_2(sc, TCO_RLD, 1); 421 } 422 423 /* 424 * Set the initial timeout value. Note that this must always be followed 425 * by a reload. 426 */ 427 static __inline void 428 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 429 { 430 431 if (timeout < TCO_RLD_TMR_MIN) 432 timeout = TCO_RLD_TMR_MIN; 433 434 if (sc->tco_version == 1) { 435 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 436 437 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 438 if (timeout > TCO_RLD1_TMR_MAX) 439 timeout = TCO_RLD1_TMR_MAX; 440 tmr_val8 |= timeout; 441 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 442 } else { 443 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 444 445 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 446 if (timeout > TCO_RLD2_TMR_MAX) 447 timeout = TCO_RLD2_TMR_MAX; 448 tmr_val16 |= timeout; 449 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 450 } 451 452 sc->timeout = timeout; 453 454 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 455 } 456 457 static __inline int 458 ichwd_clear_noreboot(struct ichwd_softc *sc) 459 { 460 uint32_t status; 461 int rc = 0; 462 463 /* try to clear the NO_REBOOT bit */ 464 switch (sc->tco_version) { 465 case 1: 466 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 467 status &= ~ICH_GEN_STA_NO_REBOOT; 468 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 469 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 470 if (status & ICH_GEN_STA_NO_REBOOT) 471 rc = EIO; 472 break; 473 case 2: 474 status = ichwd_read_gcs_4(sc, 0); 475 status &= ~ICH_GCS_NO_REBOOT; 476 ichwd_write_gcs_4(sc, 0, status); 477 status = ichwd_read_gcs_4(sc, 0); 478 if (status & ICH_GCS_NO_REBOOT) 479 rc = EIO; 480 break; 481 case 3: 482 status = ichwd_read_pmc_4(sc, 0); 483 status &= ~ICH_PMC_NO_REBOOT; 484 ichwd_write_pmc_4(sc, 0, status); 485 status = ichwd_read_pmc_4(sc, 0); 486 if (status & ICH_PMC_NO_REBOOT) 487 rc = EIO; 488 break; 489 default: 490 ichwd_verbose_printf(sc->device, 491 "Unknown TCO Version: %d, can't set NO_REBOOT.\n", 492 sc->tco_version); 493 break; 494 } 495 496 if (rc) 497 device_printf(sc->device, 498 "ICH WDT present but disabled in BIOS or hardware\n"); 499 500 return (rc); 501 } 502 503 /* 504 * Watchdog event handler - called by the framework to enable or disable 505 * the watchdog or change the initial timeout value. 506 */ 507 static void 508 ichwd_event(void *arg, unsigned int cmd, int *error) 509 { 510 struct ichwd_softc *sc = arg; 511 unsigned int timeout; 512 513 /* convert from power-of-two-ns to WDT ticks */ 514 cmd &= WD_INTERVAL; 515 516 if (sc->tco_version == 3) { 517 timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK; 518 } else { 519 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 520 } 521 522 if (cmd) { 523 if (!sc->active) 524 ichwd_tmr_enable(sc); 525 if (timeout != sc->timeout) 526 ichwd_tmr_set(sc, timeout); 527 ichwd_tmr_reload(sc); 528 *error = 0; 529 } else { 530 if (sc->active) 531 ichwd_tmr_disable(sc); 532 } 533 } 534 535 static device_t 536 ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) 537 { 538 struct ichwd_device *id; 539 device_t isab, pci; 540 uint16_t devid; 541 542 /* Check whether parent ISA bridge looks familiar. */ 543 isab = device_get_parent(isa); 544 pci = device_get_parent(isab); 545 if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) 546 return (NULL); 547 if (pci_get_vendor(isab) != VENDORID_INTEL) 548 return (NULL); 549 devid = pci_get_device(isab); 550 for (id = ichwd_devices; id->desc != NULL; ++id) { 551 if (devid == id->device) { 552 if (id_p != NULL) 553 *id_p = id; 554 return (isab); 555 } 556 } 557 558 return (NULL); 559 } 560 561 /* 562 * Look for an ICH LPC interface bridge. If one is found, register an 563 * ichwd device. There can be only one. 564 */ 565 static void 566 ichwd_identify(driver_t *driver, device_t parent) 567 { 568 struct ichwd_device *id_p; 569 device_t ich = NULL; 570 device_t dev; 571 uint32_t base_address; 572 int rc; 573 574 ich = ichwd_find_ich_lpc_bridge(parent, &id_p); 575 if (ich == NULL) 576 return; 577 578 /* good, add child to bus */ 579 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 580 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 581 582 if (dev == NULL) 583 return; 584 585 switch (id_p->tco_version) { 586 case 1: 587 break; 588 case 2: 589 /* get RCBA (root complex base address) */ 590 base_address = pci_read_config(ich, ICH_RCBA, 4); 591 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 592 (base_address & 0xffffc000) + ICH_GCS_OFFSET, 593 ICH_GCS_SIZE); 594 if (rc) 595 ichwd_verbose_printf(dev, 596 "Can not set TCO v%d memory resource for RCBA\n", 597 id_p->tco_version); 598 break; 599 case 3: 600 /* get PBASE (Power Management Controller base address) */ 601 base_address = pci_read_config(ich, ICH_PBASE, 4); 602 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 603 (base_address & 0xfffffe00) + ICH_PMC_OFFSET, 604 ICH_PMC_SIZE); 605 if (rc) 606 ichwd_verbose_printf(dev, 607 "Can not set TCO v%d memory resource for PBASE\n", 608 id_p->tco_version); 609 break; 610 default: 611 ichwd_verbose_printf(dev, 612 "Can not set unknown TCO v%d memory resource for unknown base address\n", 613 id_p->tco_version); 614 break; 615 } 616 } 617 618 static int 619 ichwd_probe(device_t dev) 620 { 621 struct ichwd_device *id_p; 622 623 /* Do not claim some ISA PnP device by accident. */ 624 if (isa_get_logicalid(dev) != 0) 625 return (ENXIO); 626 627 if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL) 628 return (ENXIO); 629 630 device_set_desc_copy(dev, id_p->desc); 631 return (0); 632 } 633 634 static int 635 ichwd_attach(device_t dev) 636 { 637 struct ichwd_softc *sc; 638 struct ichwd_device *id_p; 639 device_t ich; 640 unsigned int pmbase = 0; 641 642 sc = device_get_softc(dev); 643 sc->device = dev; 644 645 ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p); 646 if (ich == NULL) { 647 device_printf(sc->device, "Can not find ICH device.\n"); 648 goto fail; 649 } 650 sc->ich = ich; 651 sc->ich_version = id_p->ich_version; 652 sc->tco_version = id_p->tco_version; 653 654 /* get ACPI base address */ 655 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 656 if (pmbase == 0) { 657 device_printf(dev, "ICH PMBASE register is empty\n"); 658 goto fail; 659 } 660 661 /* allocate I/O register space */ 662 sc->smi_rid = 0; 663 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 664 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 665 RF_ACTIVE | RF_SHAREABLE); 666 if (sc->smi_res == NULL) { 667 device_printf(dev, "unable to reserve SMI registers\n"); 668 goto fail; 669 } 670 671 sc->tco_rid = 1; 672 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 673 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 674 RF_ACTIVE | RF_SHAREABLE); 675 if (sc->tco_res == NULL) { 676 device_printf(dev, "unable to reserve TCO registers\n"); 677 goto fail; 678 } 679 680 sc->gcs_rid = 0; 681 if (sc->tco_version >= 2) { 682 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 683 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 684 if (sc->gcs_res == NULL) { 685 device_printf(dev, "unable to reserve GCS registers\n"); 686 goto fail; 687 } 688 } 689 690 if (ichwd_clear_noreboot(sc) != 0) 691 goto fail; 692 693 /* 694 * Determine if we are coming up after a watchdog-induced reset. Some 695 * BIOSes may clear this bit at bootup, preventing us from reporting 696 * this case on such systems. We clear this bit in ichwd_sts_reset(). 697 */ 698 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 699 device_printf(dev, 700 "resuming after hardware watchdog timeout\n"); 701 702 /* reset the watchdog status registers */ 703 ichwd_sts_reset(sc); 704 705 /* make sure the WDT starts out inactive */ 706 ichwd_tmr_disable(sc); 707 708 /* register the watchdog event handler */ 709 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 710 711 /* disable the SMI handler */ 712 sc->smi_enabled = ichwd_smi_is_enabled(sc); 713 ichwd_smi_disable(sc); 714 715 return (0); 716 fail: 717 sc = device_get_softc(dev); 718 if (sc->tco_res != NULL) 719 bus_release_resource(dev, SYS_RES_IOPORT, 720 sc->tco_rid, sc->tco_res); 721 if (sc->smi_res != NULL) 722 bus_release_resource(dev, SYS_RES_IOPORT, 723 sc->smi_rid, sc->smi_res); 724 if (sc->gcs_res != NULL) 725 bus_release_resource(ich, SYS_RES_MEMORY, 726 sc->gcs_rid, sc->gcs_res); 727 728 return (ENXIO); 729 } 730 731 static int 732 ichwd_detach(device_t dev) 733 { 734 struct ichwd_softc *sc; 735 736 sc = device_get_softc(dev); 737 738 /* halt the watchdog timer */ 739 if (sc->active) 740 ichwd_tmr_disable(sc); 741 742 /* enable the SMI handler */ 743 if (sc->smi_enabled != 0) 744 ichwd_smi_enable(sc); 745 746 /* deregister event handler */ 747 if (sc->ev_tag != NULL) 748 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 749 sc->ev_tag = NULL; 750 751 /* reset the watchdog status registers */ 752 ichwd_sts_reset(sc); 753 754 /* deallocate I/O register space */ 755 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 756 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 757 758 /* deallocate memory resource */ 759 if (sc->gcs_res) 760 bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, 761 sc->gcs_res); 762 763 return (0); 764 } 765 766 static device_method_t ichwd_methods[] = { 767 DEVMETHOD(device_identify, ichwd_identify), 768 DEVMETHOD(device_probe, ichwd_probe), 769 DEVMETHOD(device_attach, ichwd_attach), 770 DEVMETHOD(device_detach, ichwd_detach), 771 DEVMETHOD(device_shutdown, ichwd_detach), 772 {0,0} 773 }; 774 775 static driver_t ichwd_driver = { 776 "ichwd", 777 ichwd_methods, 778 sizeof(struct ichwd_softc), 779 }; 780 781 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 782