1 /*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58 #include <sys/cdefs.h> 59 __FBSDID("$FreeBSD$"); 60 61 #include <sys/param.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/systm.h> 65 #include <sys/bus.h> 66 #include <machine/bus.h> 67 #include <sys/rman.h> 68 #include <machine/resource.h> 69 #include <sys/watchdog.h> 70 71 #include <isa/isavar.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ichwd/ichwd.h> 75 76 static struct ichwd_device ichwd_devices[] = { 77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 }, 97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 113 { DEVICEID_PCH, "Intel PCH watchdog timer", 10 }, 114 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 }, 115 { DEVICEID_P55, "Intel P55 watchdog timer", 10 }, 116 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 }, 117 { DEVICEID_H55, "Intel H55 watchdog timer", 10 }, 118 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 }, 119 { DEVICEID_H57, "Intel H57 watchdog timer", 10 }, 120 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 }, 121 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 }, 122 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 }, 123 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 }, 124 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 }, 125 { DEVICEID_3400, "Intel 3400 watchdog timer", 10 }, 126 { DEVICEID_3420, "Intel 3420 watchdog timer", 10 }, 127 { DEVICEID_3450, "Intel 3450 watchdog timer", 10 }, 128 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 }, 129 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 }, 130 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 }, 131 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 }, 132 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 }, 133 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 }, 134 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 }, 135 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 }, 136 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 }, 137 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 }, 138 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 }, 139 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 }, 140 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 }, 141 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 }, 142 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 }, 143 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 }, 144 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 }, 145 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 }, 146 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 }, 147 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 }, 148 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 }, 149 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 }, 150 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 }, 151 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 153 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 }, 154 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 }, 155 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 }, 156 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 }, 157 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 }, 158 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 }, 159 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 }, 160 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 }, 161 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 }, 162 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 }, 163 { 0, NULL, 0 }, 164 }; 165 166 static devclass_t ichwd_devclass; 167 168 #define ichwd_read_tco_1(sc, off) \ 169 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 170 #define ichwd_read_tco_2(sc, off) \ 171 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 172 #define ichwd_read_tco_4(sc, off) \ 173 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 174 #define ichwd_read_smi_4(sc, off) \ 175 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 176 #define ichwd_read_gcs_4(sc, off) \ 177 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 178 179 #define ichwd_write_tco_1(sc, off, val) \ 180 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 181 #define ichwd_write_tco_2(sc, off, val) \ 182 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 183 #define ichwd_write_tco_4(sc, off, val) \ 184 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 185 #define ichwd_write_smi_4(sc, off, val) \ 186 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 187 #define ichwd_write_gcs_4(sc, off, val) \ 188 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 189 190 #define ichwd_verbose_printf(dev, ...) \ 191 do { \ 192 if (bootverbose) \ 193 device_printf(dev, __VA_ARGS__);\ 194 } while (0) 195 196 /* 197 * Disable the watchdog timeout SMI handler. 198 * 199 * Apparently, some BIOSes install handlers that reset or disable the 200 * watchdog timer instead of resetting the system, so we disable the SMI 201 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 202 * from happening. 203 */ 204 static __inline void 205 ichwd_smi_disable(struct ichwd_softc *sc) 206 { 207 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 208 } 209 210 /* 211 * Enable the watchdog timeout SMI handler. See above for details. 212 */ 213 static __inline void 214 ichwd_smi_enable(struct ichwd_softc *sc) 215 { 216 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 217 } 218 219 /* 220 * Reset the watchdog status bits. 221 */ 222 static __inline void 223 ichwd_sts_reset(struct ichwd_softc *sc) 224 { 225 /* 226 * The watchdog status bits are set to 1 by the hardware to 227 * indicate various conditions. They can be cleared by software 228 * by writing a 1, not a 0. 229 */ 230 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 231 /* 232 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 233 * be done in two separate operations. 234 */ 235 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 236 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 237 } 238 239 /* 240 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 241 * TCO1_CNT register. This is complicated by the need to preserve bit 9 242 * of that same register, and the requirement that all other bits must be 243 * written back as zero. 244 */ 245 static __inline void 246 ichwd_tmr_enable(struct ichwd_softc *sc) 247 { 248 uint16_t cnt; 249 250 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 251 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 252 sc->active = 1; 253 ichwd_verbose_printf(sc->device, "timer enabled\n"); 254 } 255 256 /* 257 * Disable the watchdog timer. See above for details. 258 */ 259 static __inline void 260 ichwd_tmr_disable(struct ichwd_softc *sc) 261 { 262 uint16_t cnt; 263 264 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 265 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 266 sc->active = 0; 267 ichwd_verbose_printf(sc->device, "timer disabled\n"); 268 } 269 270 /* 271 * Reload the watchdog timer: writing anything to any of the lower five 272 * bits of the TCO_RLD register reloads the timer from the last value 273 * written to TCO_TMR. 274 */ 275 static __inline void 276 ichwd_tmr_reload(struct ichwd_softc *sc) 277 { 278 if (sc->ich_version <= 5) 279 ichwd_write_tco_1(sc, TCO_RLD, 1); 280 else 281 ichwd_write_tco_2(sc, TCO_RLD, 1); 282 283 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 284 } 285 286 /* 287 * Set the initial timeout value. Note that this must always be followed 288 * by a reload. 289 */ 290 static __inline void 291 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 292 { 293 294 if (timeout < TCO_RLD_TMR_MIN) 295 timeout = TCO_RLD_TMR_MIN; 296 297 if (sc->ich_version <= 5) { 298 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 299 300 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 301 if (timeout > TCO_RLD1_TMR_MAX) 302 timeout = TCO_RLD1_TMR_MAX; 303 tmr_val8 |= timeout; 304 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 305 } else { 306 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 307 308 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 309 if (timeout > TCO_RLD2_TMR_MAX) 310 timeout = TCO_RLD2_TMR_MAX; 311 tmr_val16 |= timeout; 312 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 313 } 314 315 sc->timeout = timeout; 316 317 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 318 } 319 320 static __inline int 321 ichwd_clear_noreboot(struct ichwd_softc *sc) 322 { 323 uint32_t status; 324 int rc = 0; 325 326 /* try to clear the NO_REBOOT bit */ 327 if (sc->ich_version <= 5) { 328 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 329 status &= ~ICH_GEN_STA_NO_REBOOT; 330 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 331 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 332 if (status & ICH_GEN_STA_NO_REBOOT) 333 rc = EIO; 334 } else { 335 status = ichwd_read_gcs_4(sc, 0); 336 status &= ~ICH_GCS_NO_REBOOT; 337 ichwd_write_gcs_4(sc, 0, status); 338 status = ichwd_read_gcs_4(sc, 0); 339 if (status & ICH_GCS_NO_REBOOT) 340 rc = EIO; 341 } 342 343 if (rc) 344 device_printf(sc->device, 345 "ICH WDT present but disabled in BIOS or hardware\n"); 346 347 return (rc); 348 } 349 350 /* 351 * Watchdog event handler - called by the framework to enable or disable 352 * the watchdog or change the initial timeout value. 353 */ 354 static void 355 ichwd_event(void *arg, unsigned int cmd, int *error) 356 { 357 struct ichwd_softc *sc = arg; 358 unsigned int timeout; 359 360 /* convert from power-of-two-ns to WDT ticks */ 361 cmd &= WD_INTERVAL; 362 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 363 if (cmd) { 364 if (timeout != sc->timeout) { 365 if (!sc->active) 366 ichwd_tmr_enable(sc); 367 ichwd_tmr_set(sc, timeout); 368 } 369 ichwd_tmr_reload(sc); 370 *error = 0; 371 } else { 372 if (sc->active) 373 ichwd_tmr_disable(sc); 374 } 375 } 376 377 static device_t 378 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 379 { 380 struct ichwd_device *id; 381 device_t ich = NULL; 382 383 /* look for an ICH LPC interface bridge */ 384 for (id = ichwd_devices; id->desc != NULL; ++id) 385 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 386 break; 387 388 if (ich == NULL) 389 return (NULL); 390 391 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 392 id->version, id->desc); 393 394 if (id_p) 395 *id_p = id; 396 397 return (ich); 398 } 399 400 /* 401 * Look for an ICH LPC interface bridge. If one is found, register an 402 * ichwd device. There can be only one. 403 */ 404 static void 405 ichwd_identify(driver_t *driver, device_t parent) 406 { 407 struct ichwd_device *id_p; 408 device_t ich = NULL; 409 device_t dev; 410 uint32_t rcba; 411 int rc; 412 413 ich = ichwd_find_ich_lpc_bridge(&id_p); 414 if (ich == NULL) 415 return; 416 417 /* good, add child to bus */ 418 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 419 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 420 421 if (dev == NULL) 422 return; 423 424 device_set_desc_copy(dev, id_p->desc); 425 426 if (id_p->version >= 6) { 427 /* get RCBA (root complex base address) */ 428 rcba = pci_read_config(ich, ICH_RCBA, 4); 429 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 430 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 431 if (rc) 432 ichwd_verbose_printf(dev, 433 "Can not set memory resource for RCBA\n"); 434 } 435 } 436 437 static int 438 ichwd_probe(device_t dev) 439 { 440 441 /* Do not claim some ISA PnP device by accident. */ 442 if (isa_get_logicalid(dev) != 0) 443 return (ENXIO); 444 return (0); 445 } 446 447 static int 448 ichwd_attach(device_t dev) 449 { 450 struct ichwd_softc *sc; 451 struct ichwd_device *id_p; 452 device_t ich; 453 unsigned int pmbase = 0; 454 455 sc = device_get_softc(dev); 456 sc->device = dev; 457 458 ich = ichwd_find_ich_lpc_bridge(&id_p); 459 if (ich == NULL) { 460 device_printf(sc->device, "Can not find ICH device.\n"); 461 goto fail; 462 } 463 sc->ich = ich; 464 sc->ich_version = id_p->version; 465 466 /* get ACPI base address */ 467 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 468 if (pmbase == 0) { 469 device_printf(dev, "ICH PMBASE register is empty\n"); 470 goto fail; 471 } 472 473 /* allocate I/O register space */ 474 sc->smi_rid = 0; 475 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 476 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 477 RF_ACTIVE | RF_SHAREABLE); 478 if (sc->smi_res == NULL) { 479 device_printf(dev, "unable to reserve SMI registers\n"); 480 goto fail; 481 } 482 sc->smi_bst = rman_get_bustag(sc->smi_res); 483 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 484 485 sc->tco_rid = 1; 486 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 487 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 488 RF_ACTIVE | RF_SHAREABLE); 489 if (sc->tco_res == NULL) { 490 device_printf(dev, "unable to reserve TCO registers\n"); 491 goto fail; 492 } 493 sc->tco_bst = rman_get_bustag(sc->tco_res); 494 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 495 496 sc->gcs_rid = 0; 497 if (sc->ich_version >= 6) { 498 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 499 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 500 if (sc->gcs_res == NULL) { 501 device_printf(dev, "unable to reserve GCS registers\n"); 502 goto fail; 503 } 504 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 505 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 506 } else { 507 sc->gcs_res = 0; 508 sc->gcs_bst = 0; 509 sc->gcs_bsh = 0; 510 } 511 512 if (ichwd_clear_noreboot(sc) != 0) 513 goto fail; 514 515 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 516 device_get_desc(dev), sc->ich_version); 517 518 /* 519 * Determine if we are coming up after a watchdog-induced reset. Some 520 * BIOSes may clear this bit at bootup, preventing us from reporting 521 * this case on such systems. We clear this bit in ichwd_sts_reset(). 522 */ 523 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 524 device_printf(dev, 525 "resuming after hardware watchdog timeout\n"); 526 527 /* reset the watchdog status registers */ 528 ichwd_sts_reset(sc); 529 530 /* make sure the WDT starts out inactive */ 531 ichwd_tmr_disable(sc); 532 533 /* register the watchdog event handler */ 534 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 535 536 /* disable the SMI handler */ 537 ichwd_smi_disable(sc); 538 539 return (0); 540 fail: 541 sc = device_get_softc(dev); 542 if (sc->tco_res != NULL) 543 bus_release_resource(dev, SYS_RES_IOPORT, 544 sc->tco_rid, sc->tco_res); 545 if (sc->smi_res != NULL) 546 bus_release_resource(dev, SYS_RES_IOPORT, 547 sc->smi_rid, sc->smi_res); 548 if (sc->gcs_res != NULL) 549 bus_release_resource(ich, SYS_RES_MEMORY, 550 sc->gcs_rid, sc->gcs_res); 551 552 return (ENXIO); 553 } 554 555 static int 556 ichwd_detach(device_t dev) 557 { 558 struct ichwd_softc *sc; 559 device_t ich = NULL; 560 561 sc = device_get_softc(dev); 562 563 /* halt the watchdog timer */ 564 if (sc->active) 565 ichwd_tmr_disable(sc); 566 567 /* enable the SMI handler */ 568 ichwd_smi_enable(sc); 569 570 /* deregister event handler */ 571 if (sc->ev_tag != NULL) 572 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 573 sc->ev_tag = NULL; 574 575 /* reset the watchdog status registers */ 576 ichwd_sts_reset(sc); 577 578 /* deallocate I/O register space */ 579 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 580 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 581 582 /* deallocate memory resource */ 583 ich = ichwd_find_ich_lpc_bridge(NULL); 584 if (sc->gcs_res && ich) 585 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 586 587 return (0); 588 } 589 590 static device_method_t ichwd_methods[] = { 591 DEVMETHOD(device_identify, ichwd_identify), 592 DEVMETHOD(device_probe, ichwd_probe), 593 DEVMETHOD(device_attach, ichwd_attach), 594 DEVMETHOD(device_detach, ichwd_detach), 595 DEVMETHOD(device_shutdown, ichwd_detach), 596 {0,0} 597 }; 598 599 static driver_t ichwd_driver = { 600 "ichwd", 601 ichwd_methods, 602 sizeof(struct ichwd_softc), 603 }; 604 605 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 606