1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004 Texas A&M University 5 * All rights reserved. 6 * 7 * Developer: Wm. Daryl Hawkins 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Intel ICH Watchdog Timer (WDT) driver 33 * 34 * Originally developed by Wm. Daryl Hawkins of Texas A&M 35 * Heavily modified by <des@FreeBSD.org> 36 * 37 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 38 * device as it's actually an integrated function of the ICH LPC interface 39 * bridge. Detection is also awkward, because we can only infer the 40 * presence of the watchdog timer from the fact that the machine has an 41 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 42 * ACPI table (although this driver does not support the ACPI detection 43 * method). 44 * 45 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 46 * way of knowing if the WDT is permanently disabled (either by the BIOS 47 * or in hardware). 48 * 49 * The WDT is programmed through I/O registers in the ACPI I/O space. 50 * Intel swears it's always at offset 0x60, so we use that. 51 * 52 * For details about the ICH WDT, see Intel Application Note AP-725 53 * (document no. 292273-001). The WDT is also described in the individual 54 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 55 * (document no. 252516-001) sections 9.10 and 9.11. 56 * 57 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 58 * SoC PMC support by Denir Li <denir.li@cas-well.com> 59 */ 60 61 #include <sys/cdefs.h> 62 __FBSDID("$FreeBSD$"); 63 64 #include <sys/param.h> 65 #include <sys/kernel.h> 66 #include <sys/module.h> 67 #include <sys/systm.h> 68 #include <sys/bus.h> 69 #include <machine/bus.h> 70 #include <sys/rman.h> 71 #include <machine/resource.h> 72 #include <sys/watchdog.h> 73 74 #include <isa/isavar.h> 75 #include <dev/pci/pcivar.h> 76 77 #include <dev/ichwd/ichwd.h> 78 79 static struct ichwd_device ichwd_devices[] = { 80 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, 81 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, 82 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 }, 83 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 }, 84 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 }, 85 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 }, 86 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 }, 87 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 }, 88 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 }, 89 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 }, 90 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 }, 91 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 }, 92 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 }, 93 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 }, 94 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 }, 95 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 }, 96 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 }, 97 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 }, 98 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 }, 99 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 }, 100 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 }, 101 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 }, 102 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 }, 103 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 }, 104 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 }, 105 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 }, 106 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 }, 107 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 }, 108 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 }, 109 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 }, 110 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 }, 111 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 }, 112 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 }, 113 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 }, 114 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 }, 115 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 }, 116 { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 }, 117 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 }, 118 { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 }, 119 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 }, 120 { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 }, 121 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 }, 122 { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 }, 123 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 }, 124 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 }, 125 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 }, 126 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 }, 127 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 }, 128 { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 }, 129 { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 }, 130 { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 }, 131 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 }, 132 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 }, 133 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 }, 134 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 }, 135 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 }, 136 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 }, 137 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 }, 138 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 }, 139 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 }, 140 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 }, 141 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 }, 142 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 }, 143 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 }, 144 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 }, 145 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 }, 146 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 }, 147 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 }, 148 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 }, 149 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 }, 150 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 }, 151 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 }, 152 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 }, 153 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 }, 154 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 }, 155 { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 }, 156 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 }, 157 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 }, 158 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 }, 159 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 }, 160 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 }, 161 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 }, 162 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 }, 163 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 }, 164 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 }, 165 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 }, 166 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 }, 167 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 }, 168 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 }, 169 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 }, 170 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 }, 171 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 }, 172 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 }, 173 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 }, 174 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 }, 175 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 }, 176 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 }, 177 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 }, 178 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 }, 179 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 }, 180 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 }, 181 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 }, 182 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 }, 183 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 }, 184 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 }, 185 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 }, 186 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 }, 187 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 }, 188 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 }, 189 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 }, 190 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 }, 191 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 }, 192 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 }, 193 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 }, 194 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 }, 195 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 }, 196 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 }, 197 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 }, 198 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 }, 199 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 }, 200 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 }, 201 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 }, 202 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 }, 203 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 }, 204 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 }, 205 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 }, 206 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 }, 207 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 }, 208 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 }, 209 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 }, 210 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 }, 211 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 }, 212 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 }, 213 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 }, 214 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 }, 215 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 }, 216 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 }, 217 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 }, 218 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 }, 219 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 }, 220 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 }, 221 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 }, 222 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 }, 223 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 }, 224 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 }, 225 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 }, 226 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 }, 227 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 }, 228 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 }, 229 { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 }, 230 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 }, 231 { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 }, 232 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 }, 233 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 }, 234 { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 }, 235 { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 }, 236 { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 }, 237 { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 }, 238 { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 }, 239 { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 }, 240 { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 }, 241 { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 }, 242 { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 }, 243 { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 }, 244 { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 }, 245 { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 }, 246 { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 }, 247 { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 }, 248 { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 }, 249 { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 }, 250 { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 }, 251 { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 }, 252 { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 }, 253 { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 }, 254 { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 }, 255 { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 }, 256 { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 }, 257 { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 }, 258 { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 }, 259 { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 }, 260 { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 }, 261 { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 }, 262 { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 }, 263 { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 }, 264 { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 }, 265 { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 }, 266 { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 267 { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 268 { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 269 { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 270 { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 271 { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 272 { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 273 { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 274 { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 275 { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 276 { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 277 { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 278 { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 279 { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 280 { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 281 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 }, 282 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 }, 283 { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 284 { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 285 { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 286 { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 287 { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 }, 288 { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 }, 289 { 0, NULL, 0, 0 }, 290 }; 291 292 static struct ichwd_device ichwd_smb_devices[] = { 293 { DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 }, 294 { 0, NULL, 0, 0 }, 295 }; 296 297 static devclass_t ichwd_devclass; 298 299 #define ichwd_read_tco_1(sc, off) \ 300 bus_read_1((sc)->tco_res, (off)) 301 #define ichwd_read_tco_2(sc, off) \ 302 bus_read_2((sc)->tco_res, (off)) 303 #define ichwd_read_tco_4(sc, off) \ 304 bus_read_4((sc)->tco_res, (off)) 305 #define ichwd_read_smi_4(sc, off) \ 306 bus_read_4((sc)->smi_res, (off)) 307 #define ichwd_read_gcs_4(sc, off) \ 308 bus_read_4((sc)->gcs_res, (off)) 309 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 310 #define ichwd_read_pmc_4(sc, off) \ 311 bus_read_4((sc)->gcs_res, (off)) 312 313 #define ichwd_write_tco_1(sc, off, val) \ 314 bus_write_1((sc)->tco_res, (off), (val)) 315 #define ichwd_write_tco_2(sc, off, val) \ 316 bus_write_2((sc)->tco_res, (off), (val)) 317 #define ichwd_write_tco_4(sc, off, val) \ 318 bus_write_4((sc)->tco_res, (off), (val)) 319 #define ichwd_write_smi_4(sc, off, val) \ 320 bus_write_4((sc)->smi_res, (off), (val)) 321 #define ichwd_write_gcs_4(sc, off, val) \ 322 bus_write_4((sc)->gcs_res, (off), (val)) 323 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 324 #define ichwd_write_pmc_4(sc, off, val) \ 325 bus_write_4((sc)->gcs_res, (off), (val)) 326 327 #define ichwd_verbose_printf(dev, ...) \ 328 do { \ 329 if (bootverbose) \ 330 device_printf(dev, __VA_ARGS__);\ 331 } while (0) 332 333 /* 334 * Disable the watchdog timeout SMI handler. 335 * 336 * Apparently, some BIOSes install handlers that reset or disable the 337 * watchdog timer instead of resetting the system, so we disable the SMI 338 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 339 * from happening. 340 */ 341 static __inline void 342 ichwd_smi_disable(struct ichwd_softc *sc) 343 { 344 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 345 } 346 347 /* 348 * Enable the watchdog timeout SMI handler. See above for details. 349 */ 350 static __inline void 351 ichwd_smi_enable(struct ichwd_softc *sc) 352 { 353 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 354 } 355 356 /* 357 * Check if the watchdog SMI triggering is enabled. 358 */ 359 static __inline int 360 ichwd_smi_is_enabled(struct ichwd_softc *sc) 361 { 362 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 363 } 364 365 /* 366 * Reset the watchdog status bits. 367 */ 368 static __inline void 369 ichwd_sts_reset(struct ichwd_softc *sc) 370 { 371 /* 372 * The watchdog status bits are set to 1 by the hardware to 373 * indicate various conditions. They can be cleared by software 374 * by writing a 1, not a 0. 375 */ 376 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 377 /* 378 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 379 * be done in two separate operations. 380 */ 381 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 382 if (sc->tco_version < 4) 383 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 384 } 385 386 /* 387 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 388 * TCO1_CNT register. This is complicated by the need to preserve bit 9 389 * of that same register, and the requirement that all other bits must be 390 * written back as zero. 391 */ 392 static __inline void 393 ichwd_tmr_enable(struct ichwd_softc *sc) 394 { 395 uint16_t cnt; 396 397 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 398 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 399 sc->active = 1; 400 ichwd_verbose_printf(sc->device, "timer enabled\n"); 401 } 402 403 /* 404 * Disable the watchdog timer. See above for details. 405 */ 406 static __inline void 407 ichwd_tmr_disable(struct ichwd_softc *sc) 408 { 409 uint16_t cnt; 410 411 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 412 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 413 sc->active = 0; 414 ichwd_verbose_printf(sc->device, "timer disabled\n"); 415 } 416 417 /* 418 * Reload the watchdog timer: writing anything to any of the lower five 419 * bits of the TCO_RLD register reloads the timer from the last value 420 * written to TCO_TMR. 421 */ 422 static __inline void 423 ichwd_tmr_reload(struct ichwd_softc *sc) 424 { 425 if (sc->tco_version == 1) 426 ichwd_write_tco_1(sc, TCO_RLD, 1); 427 else 428 ichwd_write_tco_2(sc, TCO_RLD, 1); 429 } 430 431 /* 432 * Set the initial timeout value. Note that this must always be followed 433 * by a reload. 434 */ 435 static __inline void 436 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 437 { 438 439 if (timeout < TCO_RLD_TMR_MIN) 440 timeout = TCO_RLD_TMR_MIN; 441 442 if (sc->tco_version == 1) { 443 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 444 445 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 446 if (timeout > TCO_RLD1_TMR_MAX) 447 timeout = TCO_RLD1_TMR_MAX; 448 tmr_val8 |= timeout; 449 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 450 } else { 451 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 452 453 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 454 if (timeout > TCO_RLD2_TMR_MAX) 455 timeout = TCO_RLD2_TMR_MAX; 456 tmr_val16 |= timeout; 457 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 458 } 459 460 sc->timeout = timeout; 461 462 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 463 } 464 465 static __inline int 466 ichwd_clear_noreboot(struct ichwd_softc *sc) 467 { 468 uint32_t status; 469 int rc = 0; 470 471 /* try to clear the NO_REBOOT bit */ 472 switch (sc->tco_version) { 473 case 1: 474 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 475 status &= ~ICH_GEN_STA_NO_REBOOT; 476 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 477 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 478 if (status & ICH_GEN_STA_NO_REBOOT) 479 rc = EIO; 480 break; 481 case 2: 482 status = ichwd_read_gcs_4(sc, 0); 483 status &= ~ICH_GCS_NO_REBOOT; 484 ichwd_write_gcs_4(sc, 0, status); 485 status = ichwd_read_gcs_4(sc, 0); 486 if (status & ICH_GCS_NO_REBOOT) 487 rc = EIO; 488 break; 489 case 3: 490 status = ichwd_read_pmc_4(sc, 0); 491 status &= ~ICH_PMC_NO_REBOOT; 492 ichwd_write_pmc_4(sc, 0, status); 493 status = ichwd_read_pmc_4(sc, 0); 494 if (status & ICH_PMC_NO_REBOOT) 495 rc = EIO; 496 break; 497 case 4: 498 /* 499 * TODO. This needs access to a hidden PCI device at 31:1. 500 */ 501 break; 502 default: 503 ichwd_verbose_printf(sc->device, 504 "Unknown TCO Version: %d, can't set NO_REBOOT.\n", 505 sc->tco_version); 506 break; 507 } 508 509 if (rc) 510 device_printf(sc->device, 511 "ICH WDT present but disabled in BIOS or hardware\n"); 512 513 return (rc); 514 } 515 516 /* 517 * Watchdog event handler - called by the framework to enable or disable 518 * the watchdog or change the initial timeout value. 519 */ 520 static void 521 ichwd_event(void *arg, unsigned int cmd, int *error) 522 { 523 struct ichwd_softc *sc = arg; 524 unsigned int timeout; 525 526 /* convert from power-of-two-ns to WDT ticks */ 527 cmd &= WD_INTERVAL; 528 529 if (sc->tco_version == 3) { 530 timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK; 531 } else { 532 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 533 } 534 535 if (cmd) { 536 if (!sc->active) 537 ichwd_tmr_enable(sc); 538 if (timeout != sc->timeout) 539 ichwd_tmr_set(sc, timeout); 540 ichwd_tmr_reload(sc); 541 *error = 0; 542 } else { 543 if (sc->active) 544 ichwd_tmr_disable(sc); 545 } 546 } 547 548 static device_t 549 ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) 550 { 551 struct ichwd_device *id; 552 device_t isab, pci; 553 uint16_t devid; 554 555 /* Check whether parent ISA bridge looks familiar. */ 556 isab = device_get_parent(isa); 557 pci = device_get_parent(isab); 558 if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) 559 return (NULL); 560 if (pci_get_vendor(isab) != VENDORID_INTEL) 561 return (NULL); 562 devid = pci_get_device(isab); 563 for (id = ichwd_devices; id->desc != NULL; ++id) { 564 if (devid == id->device) { 565 if (id_p != NULL) 566 *id_p = id; 567 return (isab); 568 } 569 } 570 571 return (NULL); 572 } 573 574 static device_t 575 ichwd_find_smb_dev(device_t isa, struct ichwd_device **id_p) 576 { 577 struct ichwd_device *id; 578 device_t isab, smb; 579 uint16_t devid; 580 581 /* 582 * Check if SMBus controller provides TCO configuration. 583 * The controller's device and function are fixed and we expect 584 * it to be on the same bus as ISA bridge. 585 */ 586 isab = device_get_parent(isa); 587 smb = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 4); 588 if (smb == NULL) 589 return (NULL); 590 if (pci_get_vendor(smb) != VENDORID_INTEL) 591 return (NULL); 592 devid = pci_get_device(smb); 593 for (id = ichwd_smb_devices; id->desc != NULL; ++id) { 594 if (devid == id->device) { 595 if (id_p != NULL) 596 *id_p = id; 597 return (smb); 598 } 599 } 600 601 return (NULL); 602 } 603 604 /* 605 * Look for an ICH LPC interface bridge. If one is found, register an 606 * ichwd device. There can be only one. 607 */ 608 static void 609 ichwd_identify(driver_t *driver, device_t parent) 610 { 611 struct ichwd_device *id_p; 612 device_t ich, smb; 613 device_t dev; 614 uint32_t base_address; 615 uint32_t ctl; 616 int rc; 617 618 ich = ichwd_find_ich_lpc_bridge(parent, &id_p); 619 if (ich == NULL) { 620 smb = ichwd_find_smb_dev(parent, &id_p); 621 if (smb == NULL) 622 return; 623 } 624 625 /* good, add child to bus */ 626 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 627 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 628 629 if (dev == NULL) 630 return; 631 632 switch (id_p->tco_version) { 633 case 1: 634 break; 635 case 2: 636 /* get RCBA (root complex base address) */ 637 base_address = pci_read_config(ich, ICH_RCBA, 4); 638 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 639 (base_address & 0xffffc000) + ICH_GCS_OFFSET, 640 ICH_GCS_SIZE); 641 if (rc) 642 ichwd_verbose_printf(dev, 643 "Can not set TCO v%d memory resource for RCBA\n", 644 id_p->tco_version); 645 break; 646 case 3: 647 /* get PBASE (Power Management Controller base address) */ 648 base_address = pci_read_config(ich, ICH_PBASE, 4); 649 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 650 (base_address & 0xfffffe00) + ICH_PMC_OFFSET, 651 ICH_PMC_SIZE); 652 if (rc) 653 ichwd_verbose_printf(dev, 654 "Can not set TCO v%d memory resource for PBASE\n", 655 id_p->tco_version); 656 break; 657 case 4: 658 /* Get TCO base address. */ 659 ctl = pci_read_config(smb, ICH_TCOCTL, 4); 660 if ((ctl & ICH_TCOCTL_TCO_BASE_EN) == 0) { 661 ichwd_verbose_printf(dev, 662 "TCO v%d decoding is not enabled\n", 663 id_p->tco_version); 664 break; 665 } 666 base_address = pci_read_config(smb, ICH_TCOBASE, 4); 667 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, 668 base_address & ICH_TCOBASE_ADDRMASK, ICH_TCOBASE_SIZE); 669 if (rc != 0) { 670 ichwd_verbose_printf(dev, 671 "Can not set TCO v%d I/O resource (err = %d)\n", 672 id_p->tco_version, rc); 673 } 674 break; 675 default: 676 ichwd_verbose_printf(dev, 677 "Can not set unknown TCO v%d memory resource for unknown base address\n", 678 id_p->tco_version); 679 break; 680 } 681 } 682 683 static int 684 ichwd_probe(device_t dev) 685 { 686 struct ichwd_device *id_p; 687 688 /* Do not claim some ISA PnP device by accident. */ 689 if (isa_get_logicalid(dev) != 0) 690 return (ENXIO); 691 692 if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL && 693 ichwd_find_smb_dev(device_get_parent(dev), &id_p) == NULL) 694 return (ENXIO); 695 696 device_set_desc_copy(dev, id_p->desc); 697 return (0); 698 } 699 700 static int 701 ichwd_smb_attach(device_t dev) 702 { 703 struct ichwd_softc *sc; 704 struct ichwd_device *id_p; 705 device_t isab, pmdev; 706 device_t smb; 707 uint32_t acpi_base; 708 709 sc = device_get_softc(dev); 710 smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p); 711 if (smb == NULL) 712 return (ENXIO); 713 714 sc->ich_version = id_p->ich_version; 715 sc->tco_version = id_p->tco_version; 716 717 /* Allocate TCO control I/O register space. */ 718 sc->tco_rid = 0; 719 sc->tco_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->tco_rid, 720 RF_ACTIVE | RF_SHAREABLE); 721 if (sc->tco_res == NULL) { 722 device_printf(dev, "unable to reserve TCO registers\n"); 723 return (ENXIO); 724 } 725 726 /* Get ACPI base address. */ 727 isab = device_get_parent(device_get_parent(dev)); 728 pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2); 729 if (pmdev == NULL) { 730 device_printf(dev, "unable to find Power Management device\n"); 731 return (ENXIO); 732 } 733 acpi_base = pci_read_config(pmdev, ICH_PMBASE, 4) & 0xffffff00; 734 if (acpi_base == 0) { 735 device_printf(dev, "ACPI base address is not set\n"); 736 return (ENXIO); 737 } 738 739 /* Allocate SMI control I/O register space. */ 740 sc->smi_rid = 1; 741 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 742 acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN, 743 RF_ACTIVE | RF_SHAREABLE); 744 if (sc->smi_res == NULL) { 745 device_printf(dev, "unable to reserve SMI registers\n"); 746 return (ENXIO); 747 } 748 749 return (0); 750 } 751 752 static int 753 ichwd_lpc_attach(device_t dev) 754 { 755 struct ichwd_softc *sc; 756 struct ichwd_device *id_p; 757 device_t ich; 758 unsigned int pmbase = 0; 759 760 sc = device_get_softc(dev); 761 762 ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p); 763 if (ich == NULL) 764 return (ENXIO); 765 766 sc->ich = ich; 767 sc->ich_version = id_p->ich_version; 768 sc->tco_version = id_p->tco_version; 769 770 /* get ACPI base address */ 771 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 772 if (pmbase == 0) { 773 device_printf(dev, "ICH PMBASE register is empty\n"); 774 return (ENXIO); 775 } 776 777 /* allocate I/O register space */ 778 sc->smi_rid = 0; 779 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 780 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 781 RF_ACTIVE | RF_SHAREABLE); 782 if (sc->smi_res == NULL) { 783 device_printf(dev, "unable to reserve SMI registers\n"); 784 return (ENXIO); 785 } 786 787 sc->tco_rid = 1; 788 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 789 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 790 RF_ACTIVE | RF_SHAREABLE); 791 if (sc->tco_res == NULL) { 792 device_printf(dev, "unable to reserve TCO registers\n"); 793 return (ENXIO); 794 } 795 796 sc->gcs_rid = 0; 797 if (sc->tco_version >= 2) { 798 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 799 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 800 if (sc->gcs_res == NULL) { 801 device_printf(dev, "unable to reserve GCS registers\n"); 802 return (ENXIO); 803 } 804 } 805 806 return (0); 807 } 808 809 static int 810 ichwd_attach(device_t dev) 811 { 812 struct ichwd_softc *sc; 813 814 sc = device_get_softc(dev); 815 sc->device = dev; 816 817 if (ichwd_lpc_attach(dev) != 0 && ichwd_smb_attach(dev) != 0) 818 goto fail; 819 820 if (ichwd_clear_noreboot(sc) != 0) 821 goto fail; 822 823 /* 824 * Determine if we are coming up after a watchdog-induced reset. Some 825 * BIOSes may clear this bit at bootup, preventing us from reporting 826 * this case on such systems. We clear this bit in ichwd_sts_reset(). 827 */ 828 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 829 device_printf(dev, 830 "resuming after hardware watchdog timeout\n"); 831 832 /* reset the watchdog status registers */ 833 ichwd_sts_reset(sc); 834 835 /* make sure the WDT starts out inactive */ 836 ichwd_tmr_disable(sc); 837 838 /* register the watchdog event handler */ 839 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 840 841 /* disable the SMI handler */ 842 sc->smi_enabled = ichwd_smi_is_enabled(sc); 843 ichwd_smi_disable(sc); 844 845 return (0); 846 fail: 847 sc = device_get_softc(dev); 848 if (sc->tco_res != NULL) 849 bus_release_resource(dev, SYS_RES_IOPORT, 850 sc->tco_rid, sc->tco_res); 851 if (sc->smi_res != NULL) 852 bus_release_resource(dev, SYS_RES_IOPORT, 853 sc->smi_rid, sc->smi_res); 854 if (sc->gcs_res != NULL) 855 bus_release_resource(sc->ich, SYS_RES_MEMORY, 856 sc->gcs_rid, sc->gcs_res); 857 858 return (ENXIO); 859 } 860 861 static int 862 ichwd_detach(device_t dev) 863 { 864 struct ichwd_softc *sc; 865 866 sc = device_get_softc(dev); 867 868 /* halt the watchdog timer */ 869 if (sc->active) 870 ichwd_tmr_disable(sc); 871 872 /* enable the SMI handler */ 873 if (sc->smi_enabled != 0) 874 ichwd_smi_enable(sc); 875 876 /* deregister event handler */ 877 if (sc->ev_tag != NULL) 878 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 879 sc->ev_tag = NULL; 880 881 /* reset the watchdog status registers */ 882 ichwd_sts_reset(sc); 883 884 /* deallocate I/O register space */ 885 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 886 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 887 888 /* deallocate memory resource */ 889 if (sc->gcs_res) 890 bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, 891 sc->gcs_res); 892 893 return (0); 894 } 895 896 static device_method_t ichwd_methods[] = { 897 DEVMETHOD(device_identify, ichwd_identify), 898 DEVMETHOD(device_probe, ichwd_probe), 899 DEVMETHOD(device_attach, ichwd_attach), 900 DEVMETHOD(device_detach, ichwd_detach), 901 DEVMETHOD(device_shutdown, ichwd_detach), 902 {0,0} 903 }; 904 905 static driver_t ichwd_driver = { 906 "ichwd", 907 ichwd_methods, 908 sizeof(struct ichwd_softc), 909 }; 910 911 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 912