1 /*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58 #include <sys/cdefs.h> 59 __FBSDID("$FreeBSD$"); 60 61 #include <sys/param.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/systm.h> 65 #include <sys/bus.h> 66 #include <machine/bus.h> 67 #include <sys/rman.h> 68 #include <machine/resource.h> 69 #include <sys/watchdog.h> 70 71 #include <isa/isavar.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ichwd/ichwd.h> 75 76 static struct ichwd_device ichwd_devices[] = { 77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 }, 97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 113 { DEVICEID_PCH, "Intel PCH watchdog timer", 10 }, 114 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 }, 115 { DEVICEID_P55, "Intel P55 watchdog timer", 10 }, 116 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 }, 117 { DEVICEID_H55, "Intel H55 watchdog timer", 10 }, 118 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 }, 119 { DEVICEID_H57, "Intel H57 watchdog timer", 10 }, 120 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 }, 121 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 }, 122 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 }, 123 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 }, 124 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 }, 125 { DEVICEID_3400, "Intel 3400 watchdog timer", 10 }, 126 { DEVICEID_3420, "Intel 3420 watchdog timer", 10 }, 127 { DEVICEID_3450, "Intel 3450 watchdog timer", 10 }, 128 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 }, 129 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 }, 130 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 }, 131 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 }, 132 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 }, 133 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 }, 134 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 }, 135 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 }, 136 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 }, 137 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 }, 138 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 }, 139 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 }, 140 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 }, 141 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 }, 142 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 }, 143 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 }, 144 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 }, 145 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 }, 146 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 }, 147 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 }, 148 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 }, 149 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 }, 150 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 }, 151 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 153 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 }, 154 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 }, 155 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 }, 156 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 }, 157 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 }, 158 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 }, 159 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 }, 160 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 }, 161 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 }, 162 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 }, 163 { 0, NULL, 0 }, 164 }; 165 166 static devclass_t ichwd_devclass; 167 168 #define ichwd_read_tco_1(sc, off) \ 169 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 170 #define ichwd_read_tco_2(sc, off) \ 171 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 172 #define ichwd_read_tco_4(sc, off) \ 173 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 174 #define ichwd_read_smi_4(sc, off) \ 175 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 176 #define ichwd_read_gcs_4(sc, off) \ 177 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 178 179 #define ichwd_write_tco_1(sc, off, val) \ 180 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 181 #define ichwd_write_tco_2(sc, off, val) \ 182 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 183 #define ichwd_write_tco_4(sc, off, val) \ 184 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 185 #define ichwd_write_smi_4(sc, off, val) \ 186 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 187 #define ichwd_write_gcs_4(sc, off, val) \ 188 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 189 190 #define ichwd_verbose_printf(dev, ...) \ 191 do { \ 192 if (bootverbose) \ 193 device_printf(dev, __VA_ARGS__);\ 194 } while (0) 195 196 /* 197 * Disable the watchdog timeout SMI handler. 198 * 199 * Apparently, some BIOSes install handlers that reset or disable the 200 * watchdog timer instead of resetting the system, so we disable the SMI 201 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 202 * from happening. 203 */ 204 static __inline void 205 ichwd_smi_disable(struct ichwd_softc *sc) 206 { 207 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 208 } 209 210 /* 211 * Enable the watchdog timeout SMI handler. See above for details. 212 */ 213 static __inline void 214 ichwd_smi_enable(struct ichwd_softc *sc) 215 { 216 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 217 } 218 219 /* 220 * Check if the watchdog SMI triggering is enabled. 221 */ 222 static __inline int 223 ichwd_smi_is_enabled(struct ichwd_softc *sc) 224 { 225 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 226 } 227 228 /* 229 * Reset the watchdog status bits. 230 */ 231 static __inline void 232 ichwd_sts_reset(struct ichwd_softc *sc) 233 { 234 /* 235 * The watchdog status bits are set to 1 by the hardware to 236 * indicate various conditions. They can be cleared by software 237 * by writing a 1, not a 0. 238 */ 239 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 240 /* 241 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 242 * be done in two separate operations. 243 */ 244 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 245 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 246 } 247 248 /* 249 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 250 * TCO1_CNT register. This is complicated by the need to preserve bit 9 251 * of that same register, and the requirement that all other bits must be 252 * written back as zero. 253 */ 254 static __inline void 255 ichwd_tmr_enable(struct ichwd_softc *sc) 256 { 257 uint16_t cnt; 258 259 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 260 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 261 sc->active = 1; 262 ichwd_verbose_printf(sc->device, "timer enabled\n"); 263 } 264 265 /* 266 * Disable the watchdog timer. See above for details. 267 */ 268 static __inline void 269 ichwd_tmr_disable(struct ichwd_softc *sc) 270 { 271 uint16_t cnt; 272 273 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 274 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 275 sc->active = 0; 276 ichwd_verbose_printf(sc->device, "timer disabled\n"); 277 } 278 279 /* 280 * Reload the watchdog timer: writing anything to any of the lower five 281 * bits of the TCO_RLD register reloads the timer from the last value 282 * written to TCO_TMR. 283 */ 284 static __inline void 285 ichwd_tmr_reload(struct ichwd_softc *sc) 286 { 287 if (sc->ich_version <= 5) 288 ichwd_write_tco_1(sc, TCO_RLD, 1); 289 else 290 ichwd_write_tco_2(sc, TCO_RLD, 1); 291 292 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 293 } 294 295 /* 296 * Set the initial timeout value. Note that this must always be followed 297 * by a reload. 298 */ 299 static __inline void 300 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 301 { 302 303 if (timeout < TCO_RLD_TMR_MIN) 304 timeout = TCO_RLD_TMR_MIN; 305 306 if (sc->ich_version <= 5) { 307 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 308 309 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 310 if (timeout > TCO_RLD1_TMR_MAX) 311 timeout = TCO_RLD1_TMR_MAX; 312 tmr_val8 |= timeout; 313 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 314 } else { 315 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 316 317 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 318 if (timeout > TCO_RLD2_TMR_MAX) 319 timeout = TCO_RLD2_TMR_MAX; 320 tmr_val16 |= timeout; 321 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 322 } 323 324 sc->timeout = timeout; 325 326 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 327 } 328 329 static __inline int 330 ichwd_clear_noreboot(struct ichwd_softc *sc) 331 { 332 uint32_t status; 333 int rc = 0; 334 335 /* try to clear the NO_REBOOT bit */ 336 if (sc->ich_version <= 5) { 337 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 338 status &= ~ICH_GEN_STA_NO_REBOOT; 339 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 340 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 341 if (status & ICH_GEN_STA_NO_REBOOT) 342 rc = EIO; 343 } else { 344 status = ichwd_read_gcs_4(sc, 0); 345 status &= ~ICH_GCS_NO_REBOOT; 346 ichwd_write_gcs_4(sc, 0, status); 347 status = ichwd_read_gcs_4(sc, 0); 348 if (status & ICH_GCS_NO_REBOOT) 349 rc = EIO; 350 } 351 352 if (rc) 353 device_printf(sc->device, 354 "ICH WDT present but disabled in BIOS or hardware\n"); 355 356 return (rc); 357 } 358 359 /* 360 * Watchdog event handler - called by the framework to enable or disable 361 * the watchdog or change the initial timeout value. 362 */ 363 static void 364 ichwd_event(void *arg, unsigned int cmd, int *error) 365 { 366 struct ichwd_softc *sc = arg; 367 unsigned int timeout; 368 369 /* convert from power-of-two-ns to WDT ticks */ 370 cmd &= WD_INTERVAL; 371 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 372 if (cmd) { 373 if (timeout != sc->timeout) { 374 if (!sc->active) 375 ichwd_tmr_enable(sc); 376 ichwd_tmr_set(sc, timeout); 377 } 378 ichwd_tmr_reload(sc); 379 *error = 0; 380 } else { 381 if (sc->active) 382 ichwd_tmr_disable(sc); 383 } 384 } 385 386 static device_t 387 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 388 { 389 struct ichwd_device *id; 390 device_t ich = NULL; 391 392 /* look for an ICH LPC interface bridge */ 393 for (id = ichwd_devices; id->desc != NULL; ++id) 394 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 395 break; 396 397 if (ich == NULL) 398 return (NULL); 399 400 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 401 id->version, id->desc); 402 403 if (id_p) 404 *id_p = id; 405 406 return (ich); 407 } 408 409 /* 410 * Look for an ICH LPC interface bridge. If one is found, register an 411 * ichwd device. There can be only one. 412 */ 413 static void 414 ichwd_identify(driver_t *driver, device_t parent) 415 { 416 struct ichwd_device *id_p; 417 device_t ich = NULL; 418 device_t dev; 419 uint32_t rcba; 420 int rc; 421 422 ich = ichwd_find_ich_lpc_bridge(&id_p); 423 if (ich == NULL) 424 return; 425 426 /* good, add child to bus */ 427 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 428 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 429 430 if (dev == NULL) 431 return; 432 433 device_set_desc_copy(dev, id_p->desc); 434 435 if (id_p->version >= 6) { 436 /* get RCBA (root complex base address) */ 437 rcba = pci_read_config(ich, ICH_RCBA, 4); 438 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 439 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 440 if (rc) 441 ichwd_verbose_printf(dev, 442 "Can not set memory resource for RCBA\n"); 443 } 444 } 445 446 static int 447 ichwd_probe(device_t dev) 448 { 449 450 /* Do not claim some ISA PnP device by accident. */ 451 if (isa_get_logicalid(dev) != 0) 452 return (ENXIO); 453 return (0); 454 } 455 456 static int 457 ichwd_attach(device_t dev) 458 { 459 struct ichwd_softc *sc; 460 struct ichwd_device *id_p; 461 device_t ich; 462 unsigned int pmbase = 0; 463 464 sc = device_get_softc(dev); 465 sc->device = dev; 466 467 ich = ichwd_find_ich_lpc_bridge(&id_p); 468 if (ich == NULL) { 469 device_printf(sc->device, "Can not find ICH device.\n"); 470 goto fail; 471 } 472 sc->ich = ich; 473 sc->ich_version = id_p->version; 474 475 /* get ACPI base address */ 476 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 477 if (pmbase == 0) { 478 device_printf(dev, "ICH PMBASE register is empty\n"); 479 goto fail; 480 } 481 482 /* allocate I/O register space */ 483 sc->smi_rid = 0; 484 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 485 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 486 RF_ACTIVE | RF_SHAREABLE); 487 if (sc->smi_res == NULL) { 488 device_printf(dev, "unable to reserve SMI registers\n"); 489 goto fail; 490 } 491 sc->smi_bst = rman_get_bustag(sc->smi_res); 492 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 493 494 sc->tco_rid = 1; 495 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 496 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 497 RF_ACTIVE | RF_SHAREABLE); 498 if (sc->tco_res == NULL) { 499 device_printf(dev, "unable to reserve TCO registers\n"); 500 goto fail; 501 } 502 sc->tco_bst = rman_get_bustag(sc->tco_res); 503 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 504 505 sc->gcs_rid = 0; 506 if (sc->ich_version >= 6) { 507 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 508 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 509 if (sc->gcs_res == NULL) { 510 device_printf(dev, "unable to reserve GCS registers\n"); 511 goto fail; 512 } 513 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 514 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 515 } else { 516 sc->gcs_res = 0; 517 sc->gcs_bst = 0; 518 sc->gcs_bsh = 0; 519 } 520 521 if (ichwd_clear_noreboot(sc) != 0) 522 goto fail; 523 524 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 525 device_get_desc(dev), sc->ich_version); 526 527 /* 528 * Determine if we are coming up after a watchdog-induced reset. Some 529 * BIOSes may clear this bit at bootup, preventing us from reporting 530 * this case on such systems. We clear this bit in ichwd_sts_reset(). 531 */ 532 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 533 device_printf(dev, 534 "resuming after hardware watchdog timeout\n"); 535 536 /* reset the watchdog status registers */ 537 ichwd_sts_reset(sc); 538 539 /* make sure the WDT starts out inactive */ 540 ichwd_tmr_disable(sc); 541 542 /* register the watchdog event handler */ 543 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 544 545 /* disable the SMI handler */ 546 sc->smi_enabled = ichwd_smi_is_enabled(sc); 547 ichwd_smi_disable(sc); 548 549 return (0); 550 fail: 551 sc = device_get_softc(dev); 552 if (sc->tco_res != NULL) 553 bus_release_resource(dev, SYS_RES_IOPORT, 554 sc->tco_rid, sc->tco_res); 555 if (sc->smi_res != NULL) 556 bus_release_resource(dev, SYS_RES_IOPORT, 557 sc->smi_rid, sc->smi_res); 558 if (sc->gcs_res != NULL) 559 bus_release_resource(ich, SYS_RES_MEMORY, 560 sc->gcs_rid, sc->gcs_res); 561 562 return (ENXIO); 563 } 564 565 static int 566 ichwd_detach(device_t dev) 567 { 568 struct ichwd_softc *sc; 569 device_t ich = NULL; 570 571 sc = device_get_softc(dev); 572 573 /* halt the watchdog timer */ 574 if (sc->active) 575 ichwd_tmr_disable(sc); 576 577 /* enable the SMI handler */ 578 if (sc->smi_enabled != 0) 579 ichwd_smi_enable(sc); 580 581 /* deregister event handler */ 582 if (sc->ev_tag != NULL) 583 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 584 sc->ev_tag = NULL; 585 586 /* reset the watchdog status registers */ 587 ichwd_sts_reset(sc); 588 589 /* deallocate I/O register space */ 590 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 591 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 592 593 /* deallocate memory resource */ 594 ich = ichwd_find_ich_lpc_bridge(NULL); 595 if (sc->gcs_res && ich) 596 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 597 598 return (0); 599 } 600 601 static device_method_t ichwd_methods[] = { 602 DEVMETHOD(device_identify, ichwd_identify), 603 DEVMETHOD(device_probe, ichwd_probe), 604 DEVMETHOD(device_attach, ichwd_attach), 605 DEVMETHOD(device_detach, ichwd_detach), 606 DEVMETHOD(device_shutdown, ichwd_detach), 607 {0,0} 608 }; 609 610 static driver_t ichwd_driver = { 611 "ichwd", 612 ichwd_methods, 613 sizeof(struct ichwd_softc), 614 }; 615 616 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 617