1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <sys/cdefs.h> 8 __FBSDID("$FreeBSD$"); 9 10 #include "igc_api.h" 11 12 static s32 igc_init_nvm_params_i225(struct igc_hw *hw); 13 static s32 igc_init_mac_params_i225(struct igc_hw *hw); 14 static s32 igc_init_phy_params_i225(struct igc_hw *hw); 15 static s32 igc_reset_hw_i225(struct igc_hw *hw); 16 static s32 igc_acquire_nvm_i225(struct igc_hw *hw); 17 static void igc_release_nvm_i225(struct igc_hw *hw); 18 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw); 19 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words, 20 u16 *data); 21 static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw); 22 23 /** 24 * igc_init_nvm_params_i225 - Init NVM func ptrs. 25 * @hw: pointer to the HW structure 26 **/ 27 static s32 igc_init_nvm_params_i225(struct igc_hw *hw) 28 { 29 struct igc_nvm_info *nvm = &hw->nvm; 30 u32 eecd = IGC_READ_REG(hw, IGC_EECD); 31 u16 size; 32 33 DEBUGFUNC("igc_init_nvm_params_i225"); 34 35 size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >> 36 IGC_EECD_SIZE_EX_SHIFT); 37 /* 38 * Added to a constant, "size" becomes the left-shift value 39 * for setting word_size. 40 */ 41 size += NVM_WORD_SIZE_BASE_SHIFT; 42 43 /* Just in case size is out of range, cap it to the largest 44 * EEPROM size supported 45 */ 46 if (size > 15) 47 size = 15; 48 49 nvm->word_size = 1 << size; 50 nvm->opcode_bits = 8; 51 nvm->delay_usec = 1; 52 nvm->type = igc_nvm_eeprom_spi; 53 54 55 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 56 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 57 16 : 8; 58 59 if (nvm->word_size == (1 << 15)) 60 nvm->page_size = 128; 61 62 nvm->ops.acquire = igc_acquire_nvm_i225; 63 nvm->ops.release = igc_release_nvm_i225; 64 if (igc_get_flash_presence_i225(hw)) { 65 hw->nvm.type = igc_nvm_flash_hw; 66 nvm->ops.read = igc_read_nvm_srrd_i225; 67 nvm->ops.write = igc_write_nvm_srwr_i225; 68 nvm->ops.validate = igc_validate_nvm_checksum_i225; 69 nvm->ops.update = igc_update_nvm_checksum_i225; 70 } else { 71 hw->nvm.type = igc_nvm_invm; 72 nvm->ops.write = igc_null_write_nvm; 73 nvm->ops.validate = igc_null_ops_generic; 74 nvm->ops.update = igc_null_ops_generic; 75 } 76 77 return IGC_SUCCESS; 78 } 79 80 /** 81 * igc_init_mac_params_i225 - Init MAC func ptrs. 82 * @hw: pointer to the HW structure 83 **/ 84 static s32 igc_init_mac_params_i225(struct igc_hw *hw) 85 { 86 struct igc_mac_info *mac = &hw->mac; 87 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225; 88 89 DEBUGFUNC("igc_init_mac_params_i225"); 90 91 /* Initialize function pointer */ 92 igc_init_mac_ops_generic(hw); 93 94 /* Set media type */ 95 hw->phy.media_type = igc_media_type_copper; 96 /* Set mta register count */ 97 mac->mta_reg_count = 128; 98 /* Set rar entry count */ 99 mac->rar_entry_count = IGC_RAR_ENTRIES_BASE; 100 101 /* reset */ 102 mac->ops.reset_hw = igc_reset_hw_i225; 103 /* hw initialization */ 104 mac->ops.init_hw = igc_init_hw_i225; 105 /* link setup */ 106 mac->ops.setup_link = igc_setup_link_generic; 107 /* check for link */ 108 mac->ops.check_for_link = igc_check_for_link_i225; 109 /* link info */ 110 mac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic; 111 /* acquire SW_FW sync */ 112 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225; 113 /* release SW_FW sync */ 114 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225; 115 116 /* Allow a single clear of the SW semaphore on I225 */ 117 dev_spec->clear_semaphore_once = true; 118 mac->ops.setup_physical_interface = igc_setup_copper_link_i225; 119 120 /* Set if part includes ASF firmware */ 121 mac->asf_firmware_present = true; 122 123 /* multicast address update */ 124 mac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic; 125 126 mac->ops.write_vfta = igc_write_vfta_generic; 127 128 return IGC_SUCCESS; 129 } 130 131 /** 132 * igc_init_phy_params_i225 - Init PHY func ptrs. 133 * @hw: pointer to the HW structure 134 **/ 135 static s32 igc_init_phy_params_i225(struct igc_hw *hw) 136 { 137 struct igc_phy_info *phy = &hw->phy; 138 s32 ret_val = IGC_SUCCESS; 139 140 DEBUGFUNC("igc_init_phy_params_i225"); 141 142 143 if (hw->phy.media_type != igc_media_type_copper) { 144 phy->type = igc_phy_none; 145 goto out; 146 } 147 148 phy->ops.power_up = igc_power_up_phy_copper; 149 phy->ops.power_down = igc_power_down_phy_copper_base; 150 151 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; 152 153 phy->reset_delay_us = 100; 154 155 phy->ops.acquire = igc_acquire_phy_base; 156 phy->ops.check_reset_block = igc_check_reset_block_generic; 157 phy->ops.release = igc_release_phy_base; 158 phy->ops.reset = igc_phy_hw_reset_generic; 159 phy->ops.read_reg = igc_read_phy_reg_gpy; 160 phy->ops.write_reg = igc_write_phy_reg_gpy; 161 162 /* Make sure the PHY is in a good state. Several people have reported 163 * firmware leaving the PHY's page select register set to something 164 * other than the default of zero, which causes the PHY ID read to 165 * access something other than the intended register. 166 */ 167 ret_val = hw->phy.ops.reset(hw); 168 if (ret_val) 169 goto out; 170 171 ret_val = igc_get_phy_id(hw); 172 /* Verify phy id and set remaining function pointers */ 173 switch (phy->id) { 174 case I225_I_PHY_ID: 175 default: 176 phy->type = igc_phy_i225; 177 phy->ops.set_d0_lplu_state = igc_set_d0_lplu_state_i225; 178 phy->ops.set_d3_lplu_state = igc_set_d3_lplu_state_i225; 179 /* TODO - complete with GPY PHY information */ 180 break; 181 } 182 183 out: 184 return ret_val; 185 } 186 187 /** 188 * igc_reset_hw_i225 - Reset hardware 189 * @hw: pointer to the HW structure 190 * 191 * This resets the hardware into a known state. 192 **/ 193 static s32 igc_reset_hw_i225(struct igc_hw *hw) 194 { 195 u32 ctrl; 196 s32 ret_val; 197 198 DEBUGFUNC("igc_reset_hw_i225"); 199 200 /* 201 * Prevent the PCI-E bus from sticking if there is no TLP connection 202 * on the last TLP read/write transaction when MAC is reset. 203 */ 204 ret_val = igc_disable_pcie_master_generic(hw); 205 if (ret_val) 206 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 207 208 DEBUGOUT("Masking off all interrupts\n"); 209 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 210 211 IGC_WRITE_REG(hw, IGC_RCTL, 0); 212 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP); 213 IGC_WRITE_FLUSH(hw); 214 215 msec_delay(10); 216 217 ctrl = IGC_READ_REG(hw, IGC_CTRL); 218 219 DEBUGOUT("Issuing a global reset to MAC\n"); 220 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); 221 222 ret_val = igc_get_auto_rd_done_generic(hw); 223 if (ret_val) { 224 /* 225 * When auto config read does not complete, do not 226 * return with an error. This can happen in situations 227 * where there is no eeprom and prevents getting link. 228 */ 229 DEBUGOUT("Auto Read Done did not complete\n"); 230 } 231 232 /* Clear any pending interrupt events. */ 233 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 234 IGC_READ_REG(hw, IGC_ICR); 235 236 /* Install any alternate MAC address into RAR0 */ 237 ret_val = igc_check_alt_mac_addr_generic(hw); 238 239 return ret_val; 240 } 241 242 /* igc_acquire_nvm_i225 - Request for access to EEPROM 243 * @hw: pointer to the HW structure 244 * 245 * Acquire the necessary semaphores for exclusive access to the EEPROM. 246 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 247 * Return successful if access grant bit set, else clear the request for 248 * EEPROM access and return -IGC_ERR_NVM (-1). 249 */ 250 static s32 igc_acquire_nvm_i225(struct igc_hw *hw) 251 { 252 s32 ret_val; 253 254 DEBUGFUNC("igc_acquire_nvm_i225"); 255 256 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); 257 258 return ret_val; 259 } 260 261 /* igc_release_nvm_i225 - Release exclusive access to EEPROM 262 * @hw: pointer to the HW structure 263 * 264 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 265 * then release the semaphores acquired. 266 */ 267 static void igc_release_nvm_i225(struct igc_hw *hw) 268 { 269 DEBUGFUNC("igc_release_nvm_i225"); 270 271 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); 272 } 273 274 /* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore 275 * @hw: pointer to the HW structure 276 * @mask: specifies which semaphore to acquire 277 * 278 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 279 * will also specify which port we're acquiring the lock for. 280 */ 281 s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask) 282 { 283 u32 swfw_sync; 284 u32 swmask = mask; 285 u32 fwmask = mask << 16; 286 s32 ret_val = IGC_SUCCESS; 287 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 288 289 DEBUGFUNC("igc_acquire_swfw_sync_i225"); 290 291 while (i < timeout) { 292 if (igc_get_hw_semaphore_i225(hw)) { 293 ret_val = -IGC_ERR_SWFW_SYNC; 294 goto out; 295 } 296 297 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); 298 if (!(swfw_sync & (fwmask | swmask))) 299 break; 300 301 /* Firmware currently using resource (fwmask) 302 * or other software thread using resource (swmask) 303 */ 304 igc_put_hw_semaphore_generic(hw); 305 msec_delay_irq(5); 306 i++; 307 } 308 309 if (i == timeout) { 310 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 311 ret_val = -IGC_ERR_SWFW_SYNC; 312 goto out; 313 } 314 315 swfw_sync |= swmask; 316 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); 317 318 igc_put_hw_semaphore_generic(hw); 319 320 out: 321 return ret_val; 322 } 323 324 /* igc_release_swfw_sync_i225 - Release SW/FW semaphore 325 * @hw: pointer to the HW structure 326 * @mask: specifies which semaphore to acquire 327 * 328 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 329 * will also specify which port we're releasing the lock for. 330 */ 331 void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask) 332 { 333 u32 swfw_sync; 334 335 DEBUGFUNC("igc_release_swfw_sync_i225"); 336 337 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS) 338 ; /* Empty */ 339 340 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); 341 swfw_sync &= ~mask; 342 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); 343 344 igc_put_hw_semaphore_generic(hw); 345 } 346 347 /* 348 * igc_setup_copper_link_i225 - Configure copper link settings 349 * @hw: pointer to the HW structure 350 * 351 * Configures the link for auto-neg or forced speed and duplex. Then we check 352 * for link, once link is established calls to configure collision distance 353 * and flow control are called. 354 */ 355 s32 igc_setup_copper_link_i225(struct igc_hw *hw) 356 { 357 u32 phpm_reg; 358 s32 ret_val; 359 u32 ctrl; 360 361 DEBUGFUNC("igc_setup_copper_link_i225"); 362 363 ctrl = IGC_READ_REG(hw, IGC_CTRL); 364 ctrl |= IGC_CTRL_SLU; 365 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); 366 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 367 368 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM); 369 phpm_reg &= ~IGC_I225_PHPM_GO_LINKD; 370 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg); 371 372 ret_val = igc_setup_copper_link_generic(hw); 373 374 return ret_val; 375 } 376 377 /* igc_get_hw_semaphore_i225 - Acquire hardware semaphore 378 * @hw: pointer to the HW structure 379 * 380 * Acquire the HW semaphore to access the PHY or NVM 381 */ 382 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw) 383 { 384 u32 swsm; 385 s32 timeout = hw->nvm.word_size + 1; 386 s32 i = 0; 387 388 DEBUGFUNC("igc_get_hw_semaphore_i225"); 389 390 /* Get the SW semaphore */ 391 while (i < timeout) { 392 swsm = IGC_READ_REG(hw, IGC_SWSM); 393 if (!(swsm & IGC_SWSM_SMBI)) 394 break; 395 396 usec_delay(50); 397 i++; 398 } 399 400 if (i == timeout) { 401 /* In rare circumstances, the SW semaphore may already be held 402 * unintentionally. Clear the semaphore once before giving up. 403 */ 404 if (hw->dev_spec._i225.clear_semaphore_once) { 405 hw->dev_spec._i225.clear_semaphore_once = false; 406 igc_put_hw_semaphore_generic(hw); 407 for (i = 0; i < timeout; i++) { 408 swsm = IGC_READ_REG(hw, IGC_SWSM); 409 if (!(swsm & IGC_SWSM_SMBI)) 410 break; 411 412 usec_delay(50); 413 } 414 } 415 416 /* If we do not have the semaphore here, we have to give up. */ 417 if (i == timeout) { 418 DEBUGOUT("Driver can't access device -\n"); 419 DEBUGOUT("SMBI bit is set.\n"); 420 return -IGC_ERR_NVM; 421 } 422 } 423 424 /* Get the FW semaphore. */ 425 for (i = 0; i < timeout; i++) { 426 swsm = IGC_READ_REG(hw, IGC_SWSM); 427 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 428 429 /* Semaphore acquired if bit latched */ 430 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 431 break; 432 433 usec_delay(50); 434 } 435 436 if (i == timeout) { 437 /* Release semaphores */ 438 igc_put_hw_semaphore_generic(hw); 439 DEBUGOUT("Driver can't access the NVM\n"); 440 return -IGC_ERR_NVM; 441 } 442 443 return IGC_SUCCESS; 444 } 445 446 /* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register 447 * @hw: pointer to the HW structure 448 * @offset: offset of word in the Shadow Ram to read 449 * @words: number of words to read 450 * @data: word read from the Shadow Ram 451 * 452 * Reads a 16 bit word from the Shadow Ram using the EERD register. 453 * Uses necessary synchronization semaphores. 454 */ 455 s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words, 456 u16 *data) 457 { 458 s32 status = IGC_SUCCESS; 459 u16 i, count; 460 461 DEBUGFUNC("igc_read_nvm_srrd_i225"); 462 463 /* We cannot hold synchronization semaphores for too long, 464 * because of forceful takeover procedure. However it is more efficient 465 * to read in bursts than synchronizing access for each word. 466 */ 467 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { 468 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? 469 IGC_EERD_EEWR_MAX_COUNT : (words - i); 470 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 471 status = igc_read_nvm_eerd(hw, offset, count, 472 data + i); 473 hw->nvm.ops.release(hw); 474 } else { 475 status = IGC_ERR_SWFW_SYNC; 476 } 477 478 if (status != IGC_SUCCESS) 479 break; 480 } 481 482 return status; 483 } 484 485 /* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR 486 * @hw: pointer to the HW structure 487 * @offset: offset within the Shadow RAM to be written to 488 * @words: number of words to write 489 * @data: 16 bit word(s) to be written to the Shadow RAM 490 * 491 * Writes data to Shadow RAM at offset using EEWR register. 492 * 493 * If igc_update_nvm_checksum is not called after this function , the 494 * data will not be committed to FLASH and also Shadow RAM will most likely 495 * contain an invalid checksum. 496 * 497 * If error code is returned, data and Shadow RAM may be inconsistent - buffer 498 * partially written. 499 */ 500 s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words, 501 u16 *data) 502 { 503 s32 status = IGC_SUCCESS; 504 u16 i, count; 505 506 DEBUGFUNC("igc_write_nvm_srwr_i225"); 507 508 /* We cannot hold synchronization semaphores for too long, 509 * because of forceful takeover procedure. However it is more efficient 510 * to write in bursts than synchronizing access for each word. 511 */ 512 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { 513 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? 514 IGC_EERD_EEWR_MAX_COUNT : (words - i); 515 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 516 status = __igc_write_nvm_srwr(hw, offset, count, 517 data + i); 518 hw->nvm.ops.release(hw); 519 } else { 520 status = IGC_ERR_SWFW_SYNC; 521 } 522 523 if (status != IGC_SUCCESS) 524 break; 525 } 526 527 return status; 528 } 529 530 /* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR 531 * @hw: pointer to the HW structure 532 * @offset: offset within the Shadow Ram to be written to 533 * @words: number of words to write 534 * @data: 16 bit word(s) to be written to the Shadow Ram 535 * 536 * Writes data to Shadow Ram at offset using EEWR register. 537 * 538 * If igc_update_nvm_checksum is not called after this function , the 539 * Shadow Ram will most likely contain an invalid checksum. 540 */ 541 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words, 542 u16 *data) 543 { 544 struct igc_nvm_info *nvm = &hw->nvm; 545 u32 i, k, eewr = 0; 546 u32 attempts = 100000; 547 s32 ret_val = IGC_SUCCESS; 548 549 DEBUGFUNC("__igc_write_nvm_srwr"); 550 551 /* A check for invalid values: offset too large, too many words, 552 * too many words for the offset, and not enough words. 553 */ 554 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 555 (words == 0)) { 556 DEBUGOUT("nvm parameter(s) out of bounds\n"); 557 ret_val = -IGC_ERR_NVM; 558 goto out; 559 } 560 561 for (i = 0; i < words; i++) { 562 eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) | 563 (data[i] << IGC_NVM_RW_REG_DATA) | 564 IGC_NVM_RW_REG_START; 565 566 IGC_WRITE_REG(hw, IGC_SRWR, eewr); 567 568 for (k = 0; k < attempts; k++) { 569 if (IGC_NVM_RW_REG_DONE & 570 IGC_READ_REG(hw, IGC_SRWR)) { 571 ret_val = IGC_SUCCESS; 572 break; 573 } 574 usec_delay(5); 575 } 576 577 if (ret_val != IGC_SUCCESS) { 578 DEBUGOUT("Shadow RAM write EEWR timed out\n"); 579 break; 580 } 581 } 582 583 out: 584 return ret_val; 585 } 586 587 /* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum 588 * @hw: pointer to the HW structure 589 * 590 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 591 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 592 */ 593 s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw) 594 { 595 s32 status = IGC_SUCCESS; 596 s32 (*read_op_ptr)(struct igc_hw *, u16, u16, u16 *); 597 598 DEBUGFUNC("igc_validate_nvm_checksum_i225"); 599 600 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 601 /* Replace the read function with semaphore grabbing with 602 * the one that skips this for a while. 603 * We have semaphore taken already here. 604 */ 605 read_op_ptr = hw->nvm.ops.read; 606 hw->nvm.ops.read = igc_read_nvm_eerd; 607 608 status = igc_validate_nvm_checksum_generic(hw); 609 610 /* Revert original read operation. */ 611 hw->nvm.ops.read = read_op_ptr; 612 613 hw->nvm.ops.release(hw); 614 } else { 615 status = IGC_ERR_SWFW_SYNC; 616 } 617 618 return status; 619 } 620 621 /* igc_update_nvm_checksum_i225 - Update EEPROM checksum 622 * @hw: pointer to the HW structure 623 * 624 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 625 * up to the checksum. Then calculates the EEPROM checksum and writes the 626 * value to the EEPROM. Next commit EEPROM data onto the Flash. 627 */ 628 s32 igc_update_nvm_checksum_i225(struct igc_hw *hw) 629 { 630 s32 ret_val; 631 u16 checksum = 0; 632 u16 i, nvm_data; 633 634 DEBUGFUNC("igc_update_nvm_checksum_i225"); 635 636 /* Read the first word from the EEPROM. If this times out or fails, do 637 * not continue or we could be in for a very long wait while every 638 * EEPROM read fails 639 */ 640 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data); 641 if (ret_val != IGC_SUCCESS) { 642 DEBUGOUT("EEPROM read failed\n"); 643 goto out; 644 } 645 646 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 647 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read 648 * because we do not want to take the synchronization 649 * semaphores twice here. 650 */ 651 652 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 653 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data); 654 if (ret_val) { 655 hw->nvm.ops.release(hw); 656 DEBUGOUT("NVM Read Error while updating\n"); 657 DEBUGOUT("checksum.\n"); 658 goto out; 659 } 660 checksum += nvm_data; 661 } 662 checksum = (u16)NVM_SUM - checksum; 663 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, 664 &checksum); 665 if (ret_val != IGC_SUCCESS) { 666 hw->nvm.ops.release(hw); 667 DEBUGOUT("NVM Write Error while updating checksum.\n"); 668 goto out; 669 } 670 671 hw->nvm.ops.release(hw); 672 673 ret_val = igc_update_flash_i225(hw); 674 } else { 675 ret_val = IGC_ERR_SWFW_SYNC; 676 } 677 out: 678 return ret_val; 679 } 680 681 /* igc_get_flash_presence_i225 - Check if flash device is detected. 682 * @hw: pointer to the HW structure 683 */ 684 bool igc_get_flash_presence_i225(struct igc_hw *hw) 685 { 686 u32 eec = 0; 687 bool ret_val = false; 688 689 DEBUGFUNC("igc_get_flash_presence_i225"); 690 691 eec = IGC_READ_REG(hw, IGC_EECD); 692 693 if (eec & IGC_EECD_FLASH_DETECTED_I225) 694 ret_val = true; 695 696 return ret_val; 697 } 698 699 /* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst 700 * Counter in FLSWCNT register. 701 * 702 * @hw: pointer to the HW structure 703 * @burst_counter: size in bytes of the Flash burst to read or write 704 */ 705 s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, 706 u32 burst_counter) 707 { 708 s32 ret_val = IGC_SUCCESS; 709 710 DEBUGFUNC("igc_set_flsw_flash_burst_counter_i225"); 711 712 /* Validate input data */ 713 if (burst_counter < IGC_I225_SHADOW_RAM_SIZE) { 714 /* Write FLSWCNT - burst counter */ 715 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter); 716 } else { 717 ret_val = IGC_ERR_INVALID_ARGUMENT; 718 } 719 720 return ret_val; 721 } 722 723 /* igc_write_erase_flash_command_i225 - write/erase to a sector 724 * region on a given address. 725 * 726 * @hw: pointer to the HW structure 727 * @opcode: opcode to be used for the write command 728 * @address: the offset to write into the FLASH image 729 */ 730 s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode, 731 u32 address) 732 { 733 u32 flswctl = 0; 734 s32 timeout = IGC_NVM_GRANT_ATTEMPTS; 735 s32 ret_val = IGC_SUCCESS; 736 737 DEBUGFUNC("igc_write_erase_flash_command_i225"); 738 739 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 740 /* Polling done bit on FLSWCTL register */ 741 while (timeout) { 742 if (flswctl & IGC_FLSWCTL_DONE) 743 break; 744 usec_delay(5); 745 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 746 timeout--; 747 } 748 749 if (!timeout) { 750 DEBUGOUT("Flash transaction was not done\n"); 751 return -IGC_ERR_NVM; 752 } 753 754 /* Build and issue command on FLSWCTL register */ 755 flswctl = address | opcode; 756 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl); 757 758 /* Check if issued command is valid on FLSWCTL register */ 759 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 760 if (!(flswctl & IGC_FLSWCTL_CMDV)) { 761 DEBUGOUT("Write flash command failed\n"); 762 ret_val = IGC_ERR_INVALID_ARGUMENT; 763 } 764 765 return ret_val; 766 } 767 768 /* igc_update_flash_i225 - Commit EEPROM to the flash 769 * if fw_valid_bit is set, FW is active. setting FLUPD bit in EEC 770 * register makes the FW load the internal shadow RAM into the flash. 771 * Otherwise, fw_valid_bit is 0. if FL_SECU.block_prtotected_sw = 0 772 * then FW is not active so the SW is responsible shadow RAM dump. 773 * 774 * @hw: pointer to the HW structure 775 */ 776 s32 igc_update_flash_i225(struct igc_hw *hw) 777 { 778 u16 current_offset_data = 0; 779 u32 block_sw_protect = 1; 780 u16 base_address = 0x0; 781 u32 i, fw_valid_bit; 782 u16 current_offset; 783 s32 ret_val = 0; 784 u32 flup; 785 786 DEBUGFUNC("igc_update_flash_i225"); 787 788 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) & 789 IGC_FLSECU_BLK_SW_ACCESS_I225; 790 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) & 791 IGC_FWSM_FW_VALID_I225; 792 if (fw_valid_bit) { 793 ret_val = igc_pool_flash_update_done_i225(hw); 794 if (ret_val == -IGC_ERR_NVM) { 795 DEBUGOUT("Flash update time out\n"); 796 goto out; 797 } 798 799 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225; 800 IGC_WRITE_REG(hw, IGC_EECD, flup); 801 802 ret_val = igc_pool_flash_update_done_i225(hw); 803 if (ret_val == IGC_SUCCESS) 804 DEBUGOUT("Flash update complete\n"); 805 else 806 DEBUGOUT("Flash update time out\n"); 807 } else if (!block_sw_protect) { 808 /* FW is not active and security protection is disabled. 809 * therefore, SW is in charge of shadow RAM dump. 810 * Check which sector is valid. if sector 0 is valid, 811 * base address remains 0x0. otherwise, sector 1 is 812 * valid and it's base address is 0x1000 813 */ 814 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225) 815 base_address = 0x1000; 816 817 /* Valid sector erase */ 818 ret_val = igc_write_erase_flash_command_i225(hw, 819 IGC_I225_ERASE_CMD_OPCODE, 820 base_address); 821 if (!ret_val) { 822 DEBUGOUT("Sector erase failed\n"); 823 goto out; 824 } 825 826 current_offset = base_address; 827 828 /* Write */ 829 for (i = 0; i < IGC_I225_SHADOW_RAM_SIZE / 2; i++) { 830 /* Set burst write length */ 831 ret_val = igc_set_flsw_flash_burst_counter_i225(hw, 832 0x2); 833 if (ret_val != IGC_SUCCESS) 834 break; 835 836 /* Set address and opcode */ 837 ret_val = igc_write_erase_flash_command_i225(hw, 838 IGC_I225_WRITE_CMD_OPCODE, 839 2 * current_offset); 840 if (ret_val != IGC_SUCCESS) 841 break; 842 843 ret_val = igc_read_nvm_eerd(hw, current_offset, 844 1, ¤t_offset_data); 845 if (ret_val) { 846 DEBUGOUT("Failed to read from EEPROM\n"); 847 goto out; 848 } 849 850 /* Write CurrentOffseData to FLSWDATA register */ 851 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA, 852 current_offset_data); 853 current_offset++; 854 855 /* Wait till operation has finished */ 856 ret_val = igc_poll_eerd_eewr_done(hw, 857 IGC_NVM_POLL_READ); 858 if (ret_val) 859 break; 860 861 usec_delay(1000); 862 } 863 } 864 out: 865 return ret_val; 866 } 867 868 /* igc_pool_flash_update_done_i225 - Pool FLUDONE status. 869 * @hw: pointer to the HW structure 870 */ 871 s32 igc_pool_flash_update_done_i225(struct igc_hw *hw) 872 { 873 s32 ret_val = -IGC_ERR_NVM; 874 u32 i, reg; 875 876 DEBUGFUNC("igc_pool_flash_update_done_i225"); 877 878 for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) { 879 reg = IGC_READ_REG(hw, IGC_EECD); 880 if (reg & IGC_EECD_FLUDONE_I225) { 881 ret_val = IGC_SUCCESS; 882 break; 883 } 884 usec_delay(5); 885 } 886 887 return ret_val; 888 } 889 890 /* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds. 891 * @hw: pointer to the HW structure 892 * @link: bool indicating link status 893 * 894 * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC 895 * settings, otherwise specify that there is no LTR requirement. 896 */ 897 static s32 igc_set_ltr_i225(struct igc_hw *hw, bool link) 898 { 899 u16 speed, duplex; 900 u32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max; 901 s32 size; 902 903 DEBUGFUNC("igc_set_ltr_i225"); 904 905 /* If we do not have link, LTR thresholds are zero. */ 906 if (link) { 907 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 908 909 /* Check if using copper interface with EEE enabled or if the 910 * link speed is 10 Mbps. 911 */ 912 if ((hw->phy.media_type == igc_media_type_copper) && 913 !(hw->dev_spec._i225.eee_disable) && 914 (speed != SPEED_10)) { 915 /* EEE enabled, so send LTRMAX threshold. */ 916 ltrc = IGC_READ_REG(hw, IGC_LTRC) | 917 IGC_LTRC_EEEMS_EN; 918 IGC_WRITE_REG(hw, IGC_LTRC, ltrc); 919 920 /* Calculate tw_system (nsec). */ 921 if (speed == SPEED_100) { 922 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) & 923 IGC_TW_SYSTEM_100_MASK) >> 924 IGC_TW_SYSTEM_100_SHIFT) * 500; 925 } else { 926 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) & 927 IGC_TW_SYSTEM_1000_MASK) * 500; 928 } 929 } else { 930 tw_system = 0; 931 } 932 933 /* Get the Rx packet buffer size. */ 934 size = IGC_READ_REG(hw, IGC_RXPBS) & 935 IGC_RXPBS_SIZE_I225_MASK; 936 937 /* Calculations vary based on DMAC settings. */ 938 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) { 939 size -= (IGC_READ_REG(hw, IGC_DMACR) & 940 IGC_DMACR_DMACTHR_MASK) >> 941 IGC_DMACR_DMACTHR_SHIFT; 942 /* Convert size to bits. */ 943 size *= 1024 * 8; 944 } else { 945 /* Convert size to bytes, subtract the MTU, and then 946 * convert the size to bits. 947 */ 948 size *= 1024; 949 size -= hw->dev_spec._i225.mtu; 950 size *= 8; 951 } 952 953 if (size < 0) { 954 DEBUGOUT1("Invalid effective Rx buffer size %d\n", 955 size); 956 return -IGC_ERR_CONFIG; 957 } 958 959 /* Calculate the thresholds. Since speed is in Mbps, simplify 960 * the calculation by multiplying size/speed by 1000 for result 961 * to be in nsec before dividing by the scale in nsec. Set the 962 * scale such that the LTR threshold fits in the register. 963 */ 964 ltr_min = (1000 * size) / speed; 965 ltr_max = ltr_min + tw_system; 966 scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 : 967 IGC_LTRMINV_SCALE_32768; 968 scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 : 969 IGC_LTRMAXV_SCALE_32768; 970 ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768; 971 ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768; 972 973 /* Only write the LTR thresholds if they differ from before. */ 974 ltrv = IGC_READ_REG(hw, IGC_LTRMINV); 975 if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) { 976 ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min | 977 (scale_min << IGC_LTRMINV_SCALE_SHIFT); 978 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv); 979 } 980 981 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV); 982 if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) { 983 ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max | 984 (scale_min << IGC_LTRMAXV_SCALE_SHIFT); 985 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv); 986 } 987 } 988 989 return IGC_SUCCESS; 990 } 991 992 /* igc_check_for_link_i225 - Check for link 993 * @hw: pointer to the HW structure 994 * 995 * Checks to see of the link status of the hardware has changed. If a 996 * change in link status has been detected, then we read the PHY registers 997 * to get the current speed/duplex if link exists. 998 */ 999 s32 igc_check_for_link_i225(struct igc_hw *hw) 1000 { 1001 struct igc_mac_info *mac = &hw->mac; 1002 s32 ret_val; 1003 bool link = false; 1004 1005 DEBUGFUNC("igc_check_for_link_i225"); 1006 1007 /* We only want to go out to the PHY registers to see if 1008 * Auto-Neg has completed and/or if our link status has 1009 * changed. The get_link_status flag is set upon receiving 1010 * a Link Status Change or Rx Sequence Error interrupt. 1011 */ 1012 if (!mac->get_link_status) { 1013 ret_val = IGC_SUCCESS; 1014 goto out; 1015 } 1016 1017 /* First we want to see if the MII Status Register reports 1018 * link. If so, then we want to get the current speed/duplex 1019 * of the PHY. 1020 */ 1021 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 1022 if (ret_val) 1023 goto out; 1024 1025 if (!link) 1026 goto out; /* No link detected */ 1027 1028 /* First we want to see if the MII Status Register reports 1029 * link. If so, then we want to get the current speed/duplex 1030 * of the PHY. 1031 */ 1032 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 1033 if (ret_val) 1034 goto out; 1035 1036 if (!link) 1037 goto out; /* No link detected */ 1038 1039 mac->get_link_status = false; 1040 1041 /* Check if there was DownShift, must be checked 1042 * immediately after link-up 1043 */ 1044 igc_check_downshift_generic(hw); 1045 1046 /* If we are forcing speed/duplex, then we simply return since 1047 * we have already determined whether we have link or not. 1048 */ 1049 if (!mac->autoneg) 1050 goto out; 1051 1052 /* Auto-Neg is enabled. Auto Speed Detection takes care 1053 * of MAC speed/duplex configuration. So we only need to 1054 * configure Collision Distance in the MAC. 1055 */ 1056 mac->ops.config_collision_dist(hw); 1057 1058 /* Configure Flow Control now that Auto-Neg has completed. 1059 * First, we need to restore the desired flow control 1060 * settings because we may have had to re-autoneg with a 1061 * different link partner. 1062 */ 1063 ret_val = igc_config_fc_after_link_up_generic(hw); 1064 if (ret_val) 1065 DEBUGOUT("Error configuring flow control\n"); 1066 out: 1067 /* Now that we are aware of our link settings, we can set the LTR 1068 * thresholds. 1069 */ 1070 ret_val = igc_set_ltr_i225(hw, link); 1071 1072 return ret_val; 1073 } 1074 1075 /* igc_init_function_pointers_i225 - Init func ptrs. 1076 * @hw: pointer to the HW structure 1077 * 1078 * Called to initialize all function pointers and parameters. 1079 */ 1080 void igc_init_function_pointers_i225(struct igc_hw *hw) 1081 { 1082 igc_init_mac_ops_generic(hw); 1083 igc_init_phy_ops_generic(hw); 1084 igc_init_nvm_ops_generic(hw); 1085 hw->mac.ops.init_params = igc_init_mac_params_i225; 1086 hw->nvm.ops.init_params = igc_init_nvm_params_i225; 1087 hw->phy.ops.init_params = igc_init_phy_params_i225; 1088 } 1089 1090 /* igc_init_hw_i225 - Init hw for I225 1091 * @hw: pointer to the HW structure 1092 * 1093 * Called to initialize hw for i225 hw family. 1094 */ 1095 s32 igc_init_hw_i225(struct igc_hw *hw) 1096 { 1097 s32 ret_val; 1098 1099 DEBUGFUNC("igc_init_hw_i225"); 1100 1101 ret_val = igc_init_hw_base(hw); 1102 return ret_val; 1103 } 1104 1105 /* 1106 * igc_set_d0_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D0 state 1107 * @hw: pointer to the HW structure 1108 * @active: true to enable LPLU, false to disable 1109 * 1110 * Note: since I225 does not actually support LPLU, this function 1111 * simply enables/disables 1G and 2.5G speeds in D0. 1112 */ 1113 s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active) 1114 { 1115 u32 data; 1116 1117 DEBUGFUNC("igc_set_d0_lplu_state_i225"); 1118 1119 data = IGC_READ_REG(hw, IGC_I225_PHPM); 1120 1121 if (active) { 1122 data |= IGC_I225_PHPM_DIS_1000; 1123 data |= IGC_I225_PHPM_DIS_2500; 1124 } else { 1125 data &= ~IGC_I225_PHPM_DIS_1000; 1126 data &= ~IGC_I225_PHPM_DIS_2500; 1127 } 1128 1129 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); 1130 return IGC_SUCCESS; 1131 } 1132 1133 /* 1134 * igc_set_d3_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D3 state 1135 * @hw: pointer to the HW structure 1136 * @active: true to enable LPLU, false to disable 1137 * 1138 * Note: since I225 does not actually support LPLU, this function 1139 * simply enables/disables 100M, 1G and 2.5G speeds in D3. 1140 */ 1141 s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active) 1142 { 1143 u32 data; 1144 1145 DEBUGFUNC("igc_set_d3_lplu_state_i225"); 1146 1147 data = IGC_READ_REG(hw, IGC_I225_PHPM); 1148 1149 if (active) { 1150 data |= IGC_I225_PHPM_DIS_100_D3; 1151 data |= IGC_I225_PHPM_DIS_1000_D3; 1152 data |= IGC_I225_PHPM_DIS_2500_D3; 1153 } else { 1154 data &= ~IGC_I225_PHPM_DIS_100_D3; 1155 data &= ~IGC_I225_PHPM_DIS_1000_D3; 1156 data &= ~IGC_I225_PHPM_DIS_2500_D3; 1157 } 1158 1159 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); 1160 return IGC_SUCCESS; 1161 } 1162 1163 /** 1164 * igc_set_eee_i225 - Enable/disable EEE support 1165 * @hw: pointer to the HW structure 1166 * @adv2p5G: boolean flag enabling 2.5G EEE advertisement 1167 * @adv1G: boolean flag enabling 1G EEE advertisement 1168 * @adv100M: boolean flag enabling 100M EEE advertisement 1169 * 1170 * Enable/disable EEE based on setting in dev_spec structure. 1171 * 1172 **/ 1173 s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, 1174 bool adv100M) 1175 { 1176 u32 ipcnfg, eeer; 1177 1178 DEBUGFUNC("igc_set_eee_i225"); 1179 1180 if (hw->mac.type != igc_i225 || 1181 hw->phy.media_type != igc_media_type_copper) 1182 goto out; 1183 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG); 1184 eeer = IGC_READ_REG(hw, IGC_EEER); 1185 1186 /* enable or disable per user setting */ 1187 if (!(hw->dev_spec._i225.eee_disable)) { 1188 u32 eee_su = IGC_READ_REG(hw, IGC_EEE_SU); 1189 1190 if (adv100M) 1191 ipcnfg |= IGC_IPCNFG_EEE_100M_AN; 1192 else 1193 ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN; 1194 1195 if (adv1G) 1196 ipcnfg |= IGC_IPCNFG_EEE_1G_AN; 1197 else 1198 ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN; 1199 1200 if (adv2p5G) 1201 ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN; 1202 else 1203 ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN; 1204 1205 eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | 1206 IGC_EEER_LPI_FC); 1207 1208 /* This bit should not be set in normal operation. */ 1209 if (eee_su & IGC_EEE_SU_LPI_CLK_STP) 1210 DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 1211 } else { 1212 ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN | 1213 IGC_IPCNFG_EEE_100M_AN); 1214 eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | 1215 IGC_EEER_LPI_FC); 1216 } 1217 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg); 1218 IGC_WRITE_REG(hw, IGC_EEER, eeer); 1219 IGC_READ_REG(hw, IGC_IPCNFG); 1220 IGC_READ_REG(hw, IGC_EEER); 1221 out: 1222 1223 return IGC_SUCCESS; 1224 } 1225 1226