1517904deSPeter Grehan /*- 2517904deSPeter Grehan * Copyright 2021 Intel Corp 3517904deSPeter Grehan * Copyright 2021 Rubicon Communications, LLC (Netgate) 4517904deSPeter Grehan * SPDX-License-Identifier: BSD-3-Clause 5517904deSPeter Grehan */ 6517904deSPeter Grehan 7517904deSPeter Grehan #ifndef _IGC_I225_H_ 8517904deSPeter Grehan #define _IGC_I225_H_ 9517904deSPeter Grehan 10517904deSPeter Grehan bool igc_get_flash_presence_i225(struct igc_hw *hw); 11517904deSPeter Grehan s32 igc_update_flash_i225(struct igc_hw *hw); 12517904deSPeter Grehan s32 igc_update_nvm_checksum_i225(struct igc_hw *hw); 13517904deSPeter Grehan s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw); 14517904deSPeter Grehan s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, 15517904deSPeter Grehan u16 words, u16 *data); 16517904deSPeter Grehan s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, 17517904deSPeter Grehan u16 words, u16 *data); 18517904deSPeter Grehan s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, 19517904deSPeter Grehan u32 burst_counter); 20517904deSPeter Grehan s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode, 21517904deSPeter Grehan u32 address); 22517904deSPeter Grehan s32 igc_check_for_link_i225(struct igc_hw *hw); 23517904deSPeter Grehan s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask); 24517904deSPeter Grehan void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask); 25517904deSPeter Grehan s32 igc_init_hw_i225(struct igc_hw *hw); 26517904deSPeter Grehan s32 igc_setup_copper_link_i225(struct igc_hw *hw); 27517904deSPeter Grehan s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active); 28517904deSPeter Grehan s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active); 29517904deSPeter Grehan s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, 30517904deSPeter Grehan bool adv100M); 31517904deSPeter Grehan 32517904deSPeter Grehan #define ID_LED_DEFAULT_I225 ((ID_LED_OFF1_ON2 << 8) | \ 33517904deSPeter Grehan (ID_LED_DEF1_DEF2 << 4) | \ 34517904deSPeter Grehan (ID_LED_OFF1_OFF2)) 35517904deSPeter Grehan #define ID_LED_DEFAULT_I225_SERDES ((ID_LED_DEF1_DEF2 << 8) | \ 36517904deSPeter Grehan (ID_LED_DEF1_DEF2 << 4) | \ 37517904deSPeter Grehan (ID_LED_OFF1_ON2)) 38517904deSPeter Grehan 39517904deSPeter Grehan /* NVM offset defaults for I225 devices */ 40517904deSPeter Grehan #define NVM_INIT_CTRL_2_DEFAULT_I225 0X7243 41517904deSPeter Grehan #define NVM_INIT_CTRL_4_DEFAULT_I225 0x00C1 42517904deSPeter Grehan #define NVM_LED_1_CFG_DEFAULT_I225 0x0184 43517904deSPeter Grehan #define NVM_LED_0_2_CFG_DEFAULT_I225 0x200C 44517904deSPeter Grehan 45517904deSPeter Grehan #define IGC_MRQC_ENABLE_RSS_4Q 0x00000002 46517904deSPeter Grehan #define IGC_MRQC_ENABLE_VMDQ 0x00000003 47517904deSPeter Grehan #define IGC_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 48517904deSPeter Grehan #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 49517904deSPeter Grehan #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 50517904deSPeter Grehan #define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 51517904deSPeter Grehan #define IGC_I225_SHADOW_RAM_SIZE 4096 52517904deSPeter Grehan #define IGC_I225_ERASE_CMD_OPCODE 0x02000000 53517904deSPeter Grehan #define IGC_I225_WRITE_CMD_OPCODE 0x01000000 54517904deSPeter Grehan #define IGC_FLSWCTL_DONE 0x40000000 55517904deSPeter Grehan #define IGC_FLSWCTL_CMDV 0x10000000 56517904deSPeter Grehan 57517904deSPeter Grehan /* SRRCTL bit definitions */ 58517904deSPeter Grehan #define IGC_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 59517904deSPeter Grehan #define IGC_SRRCTL_DESCTYPE_LEGACY 0x00000000 60517904deSPeter Grehan #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 61517904deSPeter Grehan #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 62517904deSPeter Grehan #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 63517904deSPeter Grehan #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 64517904deSPeter Grehan #define IGC_SRRCTL_DESCTYPE_MASK 0x0E000000 65517904deSPeter Grehan #define IGC_SRRCTL_DROP_EN 0x80000000 66517904deSPeter Grehan #define IGC_SRRCTL_BSIZEPKT_MASK 0x0000007F 67517904deSPeter Grehan #define IGC_SRRCTL_BSIZEHDR_MASK 0x00003F00 68517904deSPeter Grehan 69517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_MASK 0x0000000F 70517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_SHIFT 12 71517904deSPeter Grehan #define IGC_RXDADV_HDRBUFLEN_MASK 0x7FE0 72517904deSPeter Grehan #define IGC_RXDADV_HDRBUFLEN_SHIFT 5 73517904deSPeter Grehan #define IGC_RXDADV_SPLITHEADER_EN 0x00001000 74517904deSPeter Grehan #define IGC_RXDADV_SPH 0x8000 75517904deSPeter Grehan #define IGC_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 76517904deSPeter Grehan #define IGC_RXDADV_ERR_HBO 0x00800000 77517904deSPeter Grehan 78517904deSPeter Grehan /* RSS Hash results */ 79517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_NONE 0x00000000 80517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 81517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV4 0x00000002 82517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 83517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV6_EX 0x00000004 84517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV6 0x00000005 85517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 86517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 87517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 88517904deSPeter Grehan #define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 89517904deSPeter Grehan 90517904deSPeter Grehan /* RSS Packet Types as indicated in the receive descriptor */ 91517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_ILMASK 0x000000F0 92517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_TLMASK 0x00000F00 93517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_NONE 0x00000000 94517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 95517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 96517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 97517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 98517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 99517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 100517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 101517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 102517904deSPeter Grehan 103517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 104517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 105517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 106517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 107517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 108517904deSPeter Grehan #define IGC_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 109517904deSPeter Grehan 110517904deSPeter Grehan #endif 111