1517904deSPeter Grehan /*-
2517904deSPeter Grehan * Copyright 2021 Intel Corp
3517904deSPeter Grehan * Copyright 2021 Rubicon Communications, LLC (Netgate)
4517904deSPeter Grehan * SPDX-License-Identifier: BSD-3-Clause
5517904deSPeter Grehan */
6517904deSPeter Grehan
7517904deSPeter Grehan #include <sys/cdefs.h>
8517904deSPeter Grehan #include "igc_api.h"
9517904deSPeter Grehan
10517904deSPeter Grehan static void igc_config_collision_dist_generic(struct igc_hw *hw);
11517904deSPeter Grehan
12517904deSPeter Grehan /**
13517904deSPeter Grehan * igc_init_mac_ops_generic - Initialize MAC function pointers
14517904deSPeter Grehan * @hw: pointer to the HW structure
15517904deSPeter Grehan *
16517904deSPeter Grehan * Setups up the function pointers to no-op functions
17517904deSPeter Grehan **/
igc_init_mac_ops_generic(struct igc_hw * hw)18517904deSPeter Grehan void igc_init_mac_ops_generic(struct igc_hw *hw)
19517904deSPeter Grehan {
20517904deSPeter Grehan struct igc_mac_info *mac = &hw->mac;
21517904deSPeter Grehan DEBUGFUNC("igc_init_mac_ops_generic");
22517904deSPeter Grehan
23517904deSPeter Grehan /* General Setup */
24517904deSPeter Grehan mac->ops.init_params = igc_null_ops_generic;
25517904deSPeter Grehan mac->ops.config_collision_dist = igc_config_collision_dist_generic;
26517904deSPeter Grehan mac->ops.rar_set = igc_rar_set_generic;
27517904deSPeter Grehan }
28517904deSPeter Grehan
29517904deSPeter Grehan /**
30517904deSPeter Grehan * igc_null_ops_generic - No-op function, returns 0
31517904deSPeter Grehan * @hw: pointer to the HW structure
32517904deSPeter Grehan **/
igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG * hw)33517904deSPeter Grehan s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw)
34517904deSPeter Grehan {
35517904deSPeter Grehan DEBUGFUNC("igc_null_ops_generic");
36517904deSPeter Grehan return IGC_SUCCESS;
37517904deSPeter Grehan }
38517904deSPeter Grehan
39517904deSPeter Grehan /**
40517904deSPeter Grehan * igc_null_mac_generic - No-op function, return void
41517904deSPeter Grehan * @hw: pointer to the HW structure
42517904deSPeter Grehan **/
igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG * hw)43517904deSPeter Grehan void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw)
44517904deSPeter Grehan {
45517904deSPeter Grehan DEBUGFUNC("igc_null_mac_generic");
46517904deSPeter Grehan return;
47517904deSPeter Grehan }
48517904deSPeter Grehan
49517904deSPeter Grehan /**
50517904deSPeter Grehan * igc_null_link_info - No-op function, return 0
51517904deSPeter Grehan * @hw: pointer to the HW structure
52517904deSPeter Grehan * @s: dummy variable
53517904deSPeter Grehan * @d: dummy variable
54517904deSPeter Grehan **/
igc_null_link_info(struct igc_hw IGC_UNUSEDARG * hw,u16 IGC_UNUSEDARG * s,u16 IGC_UNUSEDARG * d)55517904deSPeter Grehan s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw,
56517904deSPeter Grehan u16 IGC_UNUSEDARG *s, u16 IGC_UNUSEDARG *d)
57517904deSPeter Grehan {
58517904deSPeter Grehan DEBUGFUNC("igc_null_link_info");
59517904deSPeter Grehan return IGC_SUCCESS;
60517904deSPeter Grehan }
61517904deSPeter Grehan
62517904deSPeter Grehan /**
63517904deSPeter Grehan * igc_null_mng_mode - No-op function, return false
64517904deSPeter Grehan * @hw: pointer to the HW structure
65517904deSPeter Grehan **/
igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG * hw)66517904deSPeter Grehan bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw)
67517904deSPeter Grehan {
68517904deSPeter Grehan DEBUGFUNC("igc_null_mng_mode");
69517904deSPeter Grehan return false;
70517904deSPeter Grehan }
71517904deSPeter Grehan
72517904deSPeter Grehan /**
73517904deSPeter Grehan * igc_null_update_mc - No-op function, return void
74517904deSPeter Grehan * @hw: pointer to the HW structure
75517904deSPeter Grehan * @h: dummy variable
76517904deSPeter Grehan * @a: dummy variable
77517904deSPeter Grehan **/
igc_null_update_mc(struct igc_hw IGC_UNUSEDARG * hw,u8 IGC_UNUSEDARG * h,u32 IGC_UNUSEDARG a)78517904deSPeter Grehan void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw,
79517904deSPeter Grehan u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a)
80517904deSPeter Grehan {
81517904deSPeter Grehan DEBUGFUNC("igc_null_update_mc");
82517904deSPeter Grehan return;
83517904deSPeter Grehan }
84517904deSPeter Grehan
85517904deSPeter Grehan /**
86517904deSPeter Grehan * igc_null_write_vfta - No-op function, return void
87517904deSPeter Grehan * @hw: pointer to the HW structure
88517904deSPeter Grehan * @a: dummy variable
89517904deSPeter Grehan * @b: dummy variable
90517904deSPeter Grehan **/
igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG * hw,u32 IGC_UNUSEDARG a,u32 IGC_UNUSEDARG b)91517904deSPeter Grehan void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw,
92517904deSPeter Grehan u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b)
93517904deSPeter Grehan {
94517904deSPeter Grehan DEBUGFUNC("igc_null_write_vfta");
95517904deSPeter Grehan return;
96517904deSPeter Grehan }
97517904deSPeter Grehan
98517904deSPeter Grehan /**
99517904deSPeter Grehan * igc_null_rar_set - No-op function, return 0
100517904deSPeter Grehan * @hw: pointer to the HW structure
101517904deSPeter Grehan * @h: dummy variable
102517904deSPeter Grehan * @a: dummy variable
103517904deSPeter Grehan **/
igc_null_rar_set(struct igc_hw IGC_UNUSEDARG * hw,u8 IGC_UNUSEDARG * h,u32 IGC_UNUSEDARG a)104517904deSPeter Grehan int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw,
105517904deSPeter Grehan u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a)
106517904deSPeter Grehan {
107517904deSPeter Grehan DEBUGFUNC("igc_null_rar_set");
108517904deSPeter Grehan return IGC_SUCCESS;
109517904deSPeter Grehan }
110517904deSPeter Grehan
111517904deSPeter Grehan /**
112517904deSPeter Grehan * igc_set_lan_id_single_port - Set LAN id for a single port device
113517904deSPeter Grehan * @hw: pointer to the HW structure
114517904deSPeter Grehan *
115517904deSPeter Grehan * Sets the LAN function id to zero for a single port device.
116517904deSPeter Grehan **/
igc_set_lan_id_single_port(struct igc_hw * hw)117517904deSPeter Grehan void igc_set_lan_id_single_port(struct igc_hw *hw)
118517904deSPeter Grehan {
119517904deSPeter Grehan struct igc_bus_info *bus = &hw->bus;
120517904deSPeter Grehan
121517904deSPeter Grehan bus->func = 0;
122517904deSPeter Grehan }
123517904deSPeter Grehan
124517904deSPeter Grehan /**
125517904deSPeter Grehan * igc_clear_vfta_generic - Clear VLAN filter table
126517904deSPeter Grehan * @hw: pointer to the HW structure
127517904deSPeter Grehan *
128517904deSPeter Grehan * Clears the register array which contains the VLAN filter table by
129517904deSPeter Grehan * setting all the values to 0.
130517904deSPeter Grehan **/
igc_clear_vfta_generic(struct igc_hw * hw)131517904deSPeter Grehan void igc_clear_vfta_generic(struct igc_hw *hw)
132517904deSPeter Grehan {
133517904deSPeter Grehan u32 offset;
134517904deSPeter Grehan
135517904deSPeter Grehan DEBUGFUNC("igc_clear_vfta_generic");
136517904deSPeter Grehan
137517904deSPeter Grehan for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) {
138517904deSPeter Grehan IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0);
139517904deSPeter Grehan IGC_WRITE_FLUSH(hw);
140517904deSPeter Grehan }
141517904deSPeter Grehan }
142517904deSPeter Grehan
143517904deSPeter Grehan /**
144517904deSPeter Grehan * igc_write_vfta_generic - Write value to VLAN filter table
145517904deSPeter Grehan * @hw: pointer to the HW structure
146517904deSPeter Grehan * @offset: register offset in VLAN filter table
147517904deSPeter Grehan * @value: register value written to VLAN filter table
148517904deSPeter Grehan *
149517904deSPeter Grehan * Writes value at the given offset in the register array which stores
150517904deSPeter Grehan * the VLAN filter table.
151517904deSPeter Grehan **/
igc_write_vfta_generic(struct igc_hw * hw,u32 offset,u32 value)152517904deSPeter Grehan void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value)
153517904deSPeter Grehan {
154517904deSPeter Grehan DEBUGFUNC("igc_write_vfta_generic");
155517904deSPeter Grehan
156517904deSPeter Grehan IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);
157517904deSPeter Grehan IGC_WRITE_FLUSH(hw);
158517904deSPeter Grehan }
159517904deSPeter Grehan
160517904deSPeter Grehan /**
161517904deSPeter Grehan * igc_init_rx_addrs_generic - Initialize receive address's
162517904deSPeter Grehan * @hw: pointer to the HW structure
163517904deSPeter Grehan * @rar_count: receive address registers
164517904deSPeter Grehan *
165517904deSPeter Grehan * Setup the receive address registers by setting the base receive address
166517904deSPeter Grehan * register to the devices MAC address and clearing all the other receive
167517904deSPeter Grehan * address registers to 0.
168517904deSPeter Grehan **/
igc_init_rx_addrs_generic(struct igc_hw * hw,u16 rar_count)169517904deSPeter Grehan void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count)
170517904deSPeter Grehan {
171517904deSPeter Grehan u32 i;
172517904deSPeter Grehan u8 mac_addr[ETH_ADDR_LEN] = {0};
173517904deSPeter Grehan
174517904deSPeter Grehan DEBUGFUNC("igc_init_rx_addrs_generic");
175517904deSPeter Grehan
176517904deSPeter Grehan /* Setup the receive address */
177517904deSPeter Grehan DEBUGOUT("Programming MAC Address into RAR[0]\n");
178517904deSPeter Grehan
179517904deSPeter Grehan hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
180517904deSPeter Grehan
181517904deSPeter Grehan /* Zero out the other (rar_entry_count - 1) receive addresses */
182517904deSPeter Grehan DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
183517904deSPeter Grehan for (i = 1; i < rar_count; i++)
184517904deSPeter Grehan hw->mac.ops.rar_set(hw, mac_addr, i);
185517904deSPeter Grehan }
186517904deSPeter Grehan
187517904deSPeter Grehan /**
188517904deSPeter Grehan * igc_check_alt_mac_addr_generic - Check for alternate MAC addr
189517904deSPeter Grehan * @hw: pointer to the HW structure
190517904deSPeter Grehan *
191517904deSPeter Grehan * Checks the nvm for an alternate MAC address. An alternate MAC address
192517904deSPeter Grehan * can be setup by pre-boot software and must be treated like a permanent
193517904deSPeter Grehan * address and must override the actual permanent MAC address. If an
194517904deSPeter Grehan * alternate MAC address is found it is programmed into RAR0, replacing
195517904deSPeter Grehan * the permanent address that was installed into RAR0 by the Si on reset.
196517904deSPeter Grehan * This function will return SUCCESS unless it encounters an error while
197517904deSPeter Grehan * reading the EEPROM.
198517904deSPeter Grehan **/
igc_check_alt_mac_addr_generic(struct igc_hw * hw)199517904deSPeter Grehan s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw)
200517904deSPeter Grehan {
201517904deSPeter Grehan u32 i;
202517904deSPeter Grehan s32 ret_val;
203517904deSPeter Grehan u16 offset, nvm_alt_mac_addr_offset, nvm_data;
204517904deSPeter Grehan u8 alt_mac_addr[ETH_ADDR_LEN];
205517904deSPeter Grehan
206517904deSPeter Grehan DEBUGFUNC("igc_check_alt_mac_addr_generic");
207517904deSPeter Grehan
208517904deSPeter Grehan ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
209517904deSPeter Grehan if (ret_val)
210517904deSPeter Grehan return ret_val;
211517904deSPeter Grehan
212517904deSPeter Grehan
213517904deSPeter Grehan ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
214517904deSPeter Grehan &nvm_alt_mac_addr_offset);
215517904deSPeter Grehan if (ret_val) {
216517904deSPeter Grehan DEBUGOUT("NVM Read Error\n");
217517904deSPeter Grehan return ret_val;
218517904deSPeter Grehan }
219517904deSPeter Grehan
220517904deSPeter Grehan if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
221517904deSPeter Grehan (nvm_alt_mac_addr_offset == 0x0000))
222517904deSPeter Grehan /* There is no Alternate MAC Address */
223517904deSPeter Grehan return IGC_SUCCESS;
224517904deSPeter Grehan
225517904deSPeter Grehan if (hw->bus.func == IGC_FUNC_1)
226517904deSPeter Grehan nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1;
227517904deSPeter Grehan for (i = 0; i < ETH_ADDR_LEN; i += 2) {
228517904deSPeter Grehan offset = nvm_alt_mac_addr_offset + (i >> 1);
229517904deSPeter Grehan ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
230517904deSPeter Grehan if (ret_val) {
231517904deSPeter Grehan DEBUGOUT("NVM Read Error\n");
232517904deSPeter Grehan return ret_val;
233517904deSPeter Grehan }
234517904deSPeter Grehan
235517904deSPeter Grehan alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
236517904deSPeter Grehan alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
237517904deSPeter Grehan }
238517904deSPeter Grehan
239517904deSPeter Grehan /* if multicast bit is set, the alternate address will not be used */
240517904deSPeter Grehan if (alt_mac_addr[0] & 0x01) {
241517904deSPeter Grehan DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
242517904deSPeter Grehan return IGC_SUCCESS;
243517904deSPeter Grehan }
244517904deSPeter Grehan
245517904deSPeter Grehan /* We have a valid alternate MAC address, and we want to treat it the
246517904deSPeter Grehan * same as the normal permanent MAC address stored by the HW into the
247517904deSPeter Grehan * RAR. Do this by mapping this address into RAR0.
248517904deSPeter Grehan */
249517904deSPeter Grehan hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
250517904deSPeter Grehan
251517904deSPeter Grehan return IGC_SUCCESS;
252517904deSPeter Grehan }
253517904deSPeter Grehan
254517904deSPeter Grehan /**
255517904deSPeter Grehan * igc_rar_set_generic - Set receive address register
256517904deSPeter Grehan * @hw: pointer to the HW structure
257517904deSPeter Grehan * @addr: pointer to the receive address
258517904deSPeter Grehan * @index: receive address array register
259517904deSPeter Grehan *
260517904deSPeter Grehan * Sets the receive address array register at index to the address passed
261517904deSPeter Grehan * in by addr.
262517904deSPeter Grehan **/
igc_rar_set_generic(struct igc_hw * hw,u8 * addr,u32 index)263517904deSPeter Grehan int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index)
264517904deSPeter Grehan {
265517904deSPeter Grehan u32 rar_low, rar_high;
266517904deSPeter Grehan
267517904deSPeter Grehan DEBUGFUNC("igc_rar_set_generic");
268517904deSPeter Grehan
269517904deSPeter Grehan /* HW expects these in little endian so we reverse the byte order
270517904deSPeter Grehan * from network order (big endian) to little endian
271517904deSPeter Grehan */
272517904deSPeter Grehan rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
273517904deSPeter Grehan ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
274517904deSPeter Grehan
275517904deSPeter Grehan rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
276517904deSPeter Grehan
277517904deSPeter Grehan /* If MAC address zero, no need to set the AV bit */
278517904deSPeter Grehan if (rar_low || rar_high)
279517904deSPeter Grehan rar_high |= IGC_RAH_AV;
280517904deSPeter Grehan
281517904deSPeter Grehan /* Some bridges will combine consecutive 32-bit writes into
282517904deSPeter Grehan * a single burst write, which will malfunction on some parts.
283517904deSPeter Grehan * The flushes avoid this.
284517904deSPeter Grehan */
285517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
286517904deSPeter Grehan IGC_WRITE_FLUSH(hw);
287517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
288517904deSPeter Grehan IGC_WRITE_FLUSH(hw);
289517904deSPeter Grehan
290517904deSPeter Grehan return IGC_SUCCESS;
291517904deSPeter Grehan }
292517904deSPeter Grehan
293517904deSPeter Grehan /**
294517904deSPeter Grehan * igc_hash_mc_addr_generic - Generate a multicast hash value
295517904deSPeter Grehan * @hw: pointer to the HW structure
296517904deSPeter Grehan * @mc_addr: pointer to a multicast address
297517904deSPeter Grehan *
298517904deSPeter Grehan * Generates a multicast address hash value which is used to determine
299517904deSPeter Grehan * the multicast filter table array address and new table value.
300517904deSPeter Grehan **/
igc_hash_mc_addr_generic(struct igc_hw * hw,u8 * mc_addr)301517904deSPeter Grehan u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr)
302517904deSPeter Grehan {
303517904deSPeter Grehan u32 hash_value, hash_mask;
304517904deSPeter Grehan u8 bit_shift = 0;
305517904deSPeter Grehan
306517904deSPeter Grehan DEBUGFUNC("igc_hash_mc_addr_generic");
307517904deSPeter Grehan
308517904deSPeter Grehan /* Register count multiplied by bits per register */
309517904deSPeter Grehan hash_mask = (hw->mac.mta_reg_count * 32) - 1;
310517904deSPeter Grehan
311517904deSPeter Grehan /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
312517904deSPeter Grehan * where 0xFF would still fall within the hash mask.
313517904deSPeter Grehan */
314517904deSPeter Grehan while (hash_mask >> bit_shift != 0xFF)
315517904deSPeter Grehan bit_shift++;
316517904deSPeter Grehan
317517904deSPeter Grehan /* The portion of the address that is used for the hash table
318517904deSPeter Grehan * is determined by the mc_filter_type setting.
319517904deSPeter Grehan * The algorithm is such that there is a total of 8 bits of shifting.
320517904deSPeter Grehan * The bit_shift for a mc_filter_type of 0 represents the number of
321517904deSPeter Grehan * left-shifts where the MSB of mc_addr[5] would still fall within
322517904deSPeter Grehan * the hash_mask. Case 0 does this exactly. Since there are a total
323517904deSPeter Grehan * of 8 bits of shifting, then mc_addr[4] will shift right the
324517904deSPeter Grehan * remaining number of bits. Thus 8 - bit_shift. The rest of the
325517904deSPeter Grehan * cases are a variation of this algorithm...essentially raising the
326517904deSPeter Grehan * number of bits to shift mc_addr[5] left, while still keeping the
327517904deSPeter Grehan * 8-bit shifting total.
328517904deSPeter Grehan *
329517904deSPeter Grehan * For example, given the following Destination MAC Address and an
330517904deSPeter Grehan * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
331517904deSPeter Grehan * we can see that the bit_shift for case 0 is 4. These are the hash
332517904deSPeter Grehan * values resulting from each mc_filter_type...
333517904deSPeter Grehan * [0] [1] [2] [3] [4] [5]
334517904deSPeter Grehan * 01 AA 00 12 34 56
335517904deSPeter Grehan * LSB MSB
336517904deSPeter Grehan *
337517904deSPeter Grehan * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
338517904deSPeter Grehan * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
339517904deSPeter Grehan * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
340517904deSPeter Grehan * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
341517904deSPeter Grehan */
342517904deSPeter Grehan switch (hw->mac.mc_filter_type) {
343517904deSPeter Grehan default:
344517904deSPeter Grehan case 0:
345517904deSPeter Grehan break;
346517904deSPeter Grehan case 1:
347517904deSPeter Grehan bit_shift += 1;
348517904deSPeter Grehan break;
349517904deSPeter Grehan case 2:
350517904deSPeter Grehan bit_shift += 2;
351517904deSPeter Grehan break;
352517904deSPeter Grehan case 3:
353517904deSPeter Grehan bit_shift += 4;
354517904deSPeter Grehan break;
355517904deSPeter Grehan }
356517904deSPeter Grehan
357517904deSPeter Grehan hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
358517904deSPeter Grehan (((u16) mc_addr[5]) << bit_shift)));
359517904deSPeter Grehan
360517904deSPeter Grehan return hash_value;
361517904deSPeter Grehan }
362517904deSPeter Grehan
363517904deSPeter Grehan /**
364517904deSPeter Grehan * igc_update_mc_addr_list_generic - Update Multicast addresses
365517904deSPeter Grehan * @hw: pointer to the HW structure
366517904deSPeter Grehan * @mc_addr_list: array of multicast addresses to program
367517904deSPeter Grehan * @mc_addr_count: number of multicast addresses to program
368517904deSPeter Grehan *
369517904deSPeter Grehan * Updates entire Multicast Table Array.
370517904deSPeter Grehan * The caller must have a packed mc_addr_list of multicast addresses.
371517904deSPeter Grehan **/
igc_update_mc_addr_list_generic(struct igc_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)372517904deSPeter Grehan void igc_update_mc_addr_list_generic(struct igc_hw *hw,
373517904deSPeter Grehan u8 *mc_addr_list, u32 mc_addr_count)
374517904deSPeter Grehan {
375517904deSPeter Grehan u32 hash_value, hash_bit, hash_reg;
376517904deSPeter Grehan int i;
377517904deSPeter Grehan
378517904deSPeter Grehan DEBUGFUNC("igc_update_mc_addr_list_generic");
379517904deSPeter Grehan
380517904deSPeter Grehan /* clear mta_shadow */
381517904deSPeter Grehan memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
382517904deSPeter Grehan
383517904deSPeter Grehan /* update mta_shadow from mc_addr_list */
384517904deSPeter Grehan for (i = 0; (u32) i < mc_addr_count; i++) {
385517904deSPeter Grehan hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);
386517904deSPeter Grehan
387517904deSPeter Grehan hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
388517904deSPeter Grehan hash_bit = hash_value & 0x1F;
389517904deSPeter Grehan
390517904deSPeter Grehan hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
391517904deSPeter Grehan mc_addr_list += (ETH_ADDR_LEN);
392517904deSPeter Grehan }
393517904deSPeter Grehan
394517904deSPeter Grehan /* replace the entire MTA table */
395517904deSPeter Grehan for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
396517904deSPeter Grehan IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);
397517904deSPeter Grehan IGC_WRITE_FLUSH(hw);
398517904deSPeter Grehan }
399517904deSPeter Grehan
400517904deSPeter Grehan /**
401517904deSPeter Grehan * igc_clear_hw_cntrs_base_generic - Clear base hardware counters
402517904deSPeter Grehan * @hw: pointer to the HW structure
403517904deSPeter Grehan *
404517904deSPeter Grehan * Clears the base hardware counters by reading the counter registers.
405517904deSPeter Grehan **/
igc_clear_hw_cntrs_base_generic(struct igc_hw * hw)406517904deSPeter Grehan void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)
407517904deSPeter Grehan {
408517904deSPeter Grehan DEBUGFUNC("igc_clear_hw_cntrs_base_generic");
409517904deSPeter Grehan
410517904deSPeter Grehan IGC_READ_REG(hw, IGC_CRCERRS);
411517904deSPeter Grehan IGC_READ_REG(hw, IGC_MPC);
412517904deSPeter Grehan IGC_READ_REG(hw, IGC_SCC);
413517904deSPeter Grehan IGC_READ_REG(hw, IGC_ECOL);
414517904deSPeter Grehan IGC_READ_REG(hw, IGC_MCC);
415517904deSPeter Grehan IGC_READ_REG(hw, IGC_LATECOL);
416517904deSPeter Grehan IGC_READ_REG(hw, IGC_COLC);
417517904deSPeter Grehan IGC_READ_REG(hw, IGC_RERC);
418517904deSPeter Grehan IGC_READ_REG(hw, IGC_DC);
419517904deSPeter Grehan IGC_READ_REG(hw, IGC_RLEC);
420517904deSPeter Grehan IGC_READ_REG(hw, IGC_XONRXC);
421517904deSPeter Grehan IGC_READ_REG(hw, IGC_XONTXC);
422517904deSPeter Grehan IGC_READ_REG(hw, IGC_XOFFRXC);
423517904deSPeter Grehan IGC_READ_REG(hw, IGC_XOFFTXC);
424517904deSPeter Grehan IGC_READ_REG(hw, IGC_FCRUC);
425517904deSPeter Grehan IGC_READ_REG(hw, IGC_GPRC);
426517904deSPeter Grehan IGC_READ_REG(hw, IGC_BPRC);
427517904deSPeter Grehan IGC_READ_REG(hw, IGC_MPRC);
428517904deSPeter Grehan IGC_READ_REG(hw, IGC_GPTC);
429517904deSPeter Grehan IGC_READ_REG(hw, IGC_GORCL);
430517904deSPeter Grehan IGC_READ_REG(hw, IGC_GORCH);
431517904deSPeter Grehan IGC_READ_REG(hw, IGC_GOTCL);
432517904deSPeter Grehan IGC_READ_REG(hw, IGC_GOTCH);
433517904deSPeter Grehan IGC_READ_REG(hw, IGC_RNBC);
434517904deSPeter Grehan IGC_READ_REG(hw, IGC_RUC);
435517904deSPeter Grehan IGC_READ_REG(hw, IGC_RFC);
436517904deSPeter Grehan IGC_READ_REG(hw, IGC_ROC);
437517904deSPeter Grehan IGC_READ_REG(hw, IGC_RJC);
438517904deSPeter Grehan IGC_READ_REG(hw, IGC_TORL);
439517904deSPeter Grehan IGC_READ_REG(hw, IGC_TORH);
440517904deSPeter Grehan IGC_READ_REG(hw, IGC_TOTL);
441517904deSPeter Grehan IGC_READ_REG(hw, IGC_TOTH);
442517904deSPeter Grehan IGC_READ_REG(hw, IGC_TPR);
443517904deSPeter Grehan IGC_READ_REG(hw, IGC_TPT);
444517904deSPeter Grehan IGC_READ_REG(hw, IGC_MPTC);
445517904deSPeter Grehan IGC_READ_REG(hw, IGC_BPTC);
446517904deSPeter Grehan IGC_READ_REG(hw, IGC_TLPIC);
447517904deSPeter Grehan IGC_READ_REG(hw, IGC_RLPIC);
448517904deSPeter Grehan IGC_READ_REG(hw, IGC_RXDMTC);
449517904deSPeter Grehan }
450517904deSPeter Grehan
451517904deSPeter Grehan /**
452517904deSPeter Grehan * igc_check_for_copper_link_generic - Check for link (Copper)
453517904deSPeter Grehan * @hw: pointer to the HW structure
454517904deSPeter Grehan *
455517904deSPeter Grehan * Checks to see of the link status of the hardware has changed. If a
456517904deSPeter Grehan * change in link status has been detected, then we read the PHY registers
457517904deSPeter Grehan * to get the current speed/duplex if link exists.
458517904deSPeter Grehan **/
igc_check_for_copper_link_generic(struct igc_hw * hw)459517904deSPeter Grehan s32 igc_check_for_copper_link_generic(struct igc_hw *hw)
460517904deSPeter Grehan {
461517904deSPeter Grehan struct igc_mac_info *mac = &hw->mac;
462517904deSPeter Grehan s32 ret_val;
463517904deSPeter Grehan bool link = false;
464517904deSPeter Grehan
465517904deSPeter Grehan DEBUGFUNC("igc_check_for_copper_link");
466517904deSPeter Grehan
467517904deSPeter Grehan /* We only want to go out to the PHY registers to see if Auto-Neg
468517904deSPeter Grehan * has completed and/or if our link status has changed. The
469517904deSPeter Grehan * get_link_status flag is set upon receiving a Link Status
470517904deSPeter Grehan * Change or Rx Sequence Error interrupt.
471517904deSPeter Grehan */
472517904deSPeter Grehan if (!mac->get_link_status)
473517904deSPeter Grehan return IGC_SUCCESS;
474517904deSPeter Grehan
475517904deSPeter Grehan /* First we want to see if the MII Status Register reports
476517904deSPeter Grehan * link. If so, then we want to get the current speed/duplex
477517904deSPeter Grehan * of the PHY.
478517904deSPeter Grehan */
479517904deSPeter Grehan ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
480517904deSPeter Grehan if (ret_val)
481517904deSPeter Grehan return ret_val;
482517904deSPeter Grehan
483517904deSPeter Grehan if (!link)
484517904deSPeter Grehan return IGC_SUCCESS; /* No link detected */
485517904deSPeter Grehan
486517904deSPeter Grehan mac->get_link_status = false;
487517904deSPeter Grehan
488517904deSPeter Grehan /* Check if there was DownShift, must be checked
489517904deSPeter Grehan * immediately after link-up
490517904deSPeter Grehan */
491517904deSPeter Grehan igc_check_downshift_generic(hw);
492517904deSPeter Grehan
493517904deSPeter Grehan /* If we are forcing speed/duplex, then we simply return since
494517904deSPeter Grehan * we have already determined whether we have link or not.
495517904deSPeter Grehan */
496517904deSPeter Grehan if (!mac->autoneg)
497517904deSPeter Grehan return -IGC_ERR_CONFIG;
498517904deSPeter Grehan
499517904deSPeter Grehan /* Auto-Neg is enabled. Auto Speed Detection takes care
500517904deSPeter Grehan * of MAC speed/duplex configuration. So we only need to
501517904deSPeter Grehan * configure Collision Distance in the MAC.
502517904deSPeter Grehan */
503517904deSPeter Grehan mac->ops.config_collision_dist(hw);
504517904deSPeter Grehan
505517904deSPeter Grehan /* Configure Flow Control now that Auto-Neg has completed.
506517904deSPeter Grehan * First, we need to restore the desired flow control
507517904deSPeter Grehan * settings because we may have had to re-autoneg with a
508517904deSPeter Grehan * different link partner.
509517904deSPeter Grehan */
510517904deSPeter Grehan ret_val = igc_config_fc_after_link_up_generic(hw);
511517904deSPeter Grehan if (ret_val)
512517904deSPeter Grehan DEBUGOUT("Error configuring flow control\n");
513517904deSPeter Grehan
514517904deSPeter Grehan return ret_val;
515517904deSPeter Grehan }
516517904deSPeter Grehan
517517904deSPeter Grehan /**
518517904deSPeter Grehan * igc_setup_link_generic - Setup flow control and link settings
519517904deSPeter Grehan * @hw: pointer to the HW structure
520517904deSPeter Grehan *
521517904deSPeter Grehan * Determines which flow control settings to use, then configures flow
522517904deSPeter Grehan * control. Calls the appropriate media-specific link configuration
523517904deSPeter Grehan * function. Assuming the adapter has a valid link partner, a valid link
524517904deSPeter Grehan * should be established. Assumes the hardware has previously been reset
525517904deSPeter Grehan * and the transmitter and receiver are not enabled.
526517904deSPeter Grehan **/
igc_setup_link_generic(struct igc_hw * hw)527517904deSPeter Grehan s32 igc_setup_link_generic(struct igc_hw *hw)
528517904deSPeter Grehan {
529517904deSPeter Grehan s32 ret_val;
530517904deSPeter Grehan
531517904deSPeter Grehan DEBUGFUNC("igc_setup_link_generic");
532517904deSPeter Grehan
533517904deSPeter Grehan /* In the case of the phy reset being blocked, we already have a link.
534517904deSPeter Grehan * We do not need to set it up again.
535517904deSPeter Grehan */
536517904deSPeter Grehan if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
537517904deSPeter Grehan return IGC_SUCCESS;
538517904deSPeter Grehan
539517904deSPeter Grehan /* If requested flow control is set to default, set flow control
540517904deSPeter Grehan * for both 'rx' and 'tx' pause frames.
541517904deSPeter Grehan */
542517904deSPeter Grehan if (hw->fc.requested_mode == igc_fc_default) {
543517904deSPeter Grehan hw->fc.requested_mode = igc_fc_full;
544517904deSPeter Grehan }
545517904deSPeter Grehan
546517904deSPeter Grehan /* Save off the requested flow control mode for use later. Depending
547517904deSPeter Grehan * on the link partner's capabilities, we may or may not use this mode.
548517904deSPeter Grehan */
549517904deSPeter Grehan hw->fc.current_mode = hw->fc.requested_mode;
550517904deSPeter Grehan
551517904deSPeter Grehan DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
552517904deSPeter Grehan hw->fc.current_mode);
553517904deSPeter Grehan
554517904deSPeter Grehan /* Call the necessary media_type subroutine to configure the link. */
555517904deSPeter Grehan ret_val = hw->mac.ops.setup_physical_interface(hw);
556517904deSPeter Grehan if (ret_val)
557517904deSPeter Grehan return ret_val;
558517904deSPeter Grehan
559517904deSPeter Grehan /* Initialize the flow control address, type, and PAUSE timer
560517904deSPeter Grehan * registers to their default values. This is done even if flow
561517904deSPeter Grehan * control is disabled, because it does not hurt anything to
562517904deSPeter Grehan * initialize these registers.
563517904deSPeter Grehan */
564517904deSPeter Grehan DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
565517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);
566517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
567517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
568517904deSPeter Grehan
569517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);
570517904deSPeter Grehan
571517904deSPeter Grehan return igc_set_fc_watermarks_generic(hw);
572517904deSPeter Grehan }
573517904deSPeter Grehan
574517904deSPeter Grehan /**
575517904deSPeter Grehan * igc_config_collision_dist_generic - Configure collision distance
576517904deSPeter Grehan * @hw: pointer to the HW structure
577517904deSPeter Grehan *
578517904deSPeter Grehan * Configures the collision distance to the default value and is used
579517904deSPeter Grehan * during link setup.
580517904deSPeter Grehan **/
igc_config_collision_dist_generic(struct igc_hw * hw)581517904deSPeter Grehan static void igc_config_collision_dist_generic(struct igc_hw *hw)
582517904deSPeter Grehan {
583517904deSPeter Grehan u32 tctl;
584517904deSPeter Grehan
585517904deSPeter Grehan DEBUGFUNC("igc_config_collision_dist_generic");
586517904deSPeter Grehan
587517904deSPeter Grehan tctl = IGC_READ_REG(hw, IGC_TCTL);
588517904deSPeter Grehan
589517904deSPeter Grehan tctl &= ~IGC_TCTL_COLD;
590517904deSPeter Grehan tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
591517904deSPeter Grehan
592517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_TCTL, tctl);
593517904deSPeter Grehan IGC_WRITE_FLUSH(hw);
594517904deSPeter Grehan }
595517904deSPeter Grehan
596517904deSPeter Grehan /**
597517904deSPeter Grehan * igc_set_fc_watermarks_generic - Set flow control high/low watermarks
598517904deSPeter Grehan * @hw: pointer to the HW structure
599517904deSPeter Grehan *
600517904deSPeter Grehan * Sets the flow control high/low threshold (watermark) registers. If
601517904deSPeter Grehan * flow control XON frame transmission is enabled, then set XON frame
602517904deSPeter Grehan * transmission as well.
603517904deSPeter Grehan **/
igc_set_fc_watermarks_generic(struct igc_hw * hw)604517904deSPeter Grehan s32 igc_set_fc_watermarks_generic(struct igc_hw *hw)
605517904deSPeter Grehan {
606517904deSPeter Grehan u32 fcrtl = 0, fcrth = 0;
607517904deSPeter Grehan
608517904deSPeter Grehan DEBUGFUNC("igc_set_fc_watermarks_generic");
609517904deSPeter Grehan
610517904deSPeter Grehan /* Set the flow control receive threshold registers. Normally,
611517904deSPeter Grehan * these registers will be set to a default threshold that may be
612517904deSPeter Grehan * adjusted later by the driver's runtime code. However, if the
613517904deSPeter Grehan * ability to transmit pause frames is not enabled, then these
614517904deSPeter Grehan * registers will be set to 0.
615517904deSPeter Grehan */
616517904deSPeter Grehan if (hw->fc.current_mode & igc_fc_tx_pause) {
617517904deSPeter Grehan /* We need to set up the Receive Threshold high and low water
618517904deSPeter Grehan * marks as well as (optionally) enabling the transmission of
619517904deSPeter Grehan * XON frames.
620517904deSPeter Grehan */
621517904deSPeter Grehan fcrtl = hw->fc.low_water;
622517904deSPeter Grehan if (hw->fc.send_xon)
623517904deSPeter Grehan fcrtl |= IGC_FCRTL_XONE;
624517904deSPeter Grehan
625517904deSPeter Grehan fcrth = hw->fc.high_water;
626517904deSPeter Grehan }
627517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);
628517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_FCRTH, fcrth);
629517904deSPeter Grehan
630517904deSPeter Grehan return IGC_SUCCESS;
631517904deSPeter Grehan }
632517904deSPeter Grehan
633517904deSPeter Grehan /**
634517904deSPeter Grehan * igc_force_mac_fc_generic - Force the MAC's flow control settings
635517904deSPeter Grehan * @hw: pointer to the HW structure
636517904deSPeter Grehan *
637517904deSPeter Grehan * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
638517904deSPeter Grehan * device control register to reflect the adapter settings. TFCE and RFCE
639517904deSPeter Grehan * need to be explicitly set by software when a copper PHY is used because
640517904deSPeter Grehan * autonegotiation is managed by the PHY rather than the MAC. Software must
641517904deSPeter Grehan * also configure these bits when link is forced on a fiber connection.
642517904deSPeter Grehan **/
igc_force_mac_fc_generic(struct igc_hw * hw)643517904deSPeter Grehan s32 igc_force_mac_fc_generic(struct igc_hw *hw)
644517904deSPeter Grehan {
645517904deSPeter Grehan u32 ctrl;
646517904deSPeter Grehan
647517904deSPeter Grehan DEBUGFUNC("igc_force_mac_fc_generic");
648517904deSPeter Grehan
649517904deSPeter Grehan ctrl = IGC_READ_REG(hw, IGC_CTRL);
650517904deSPeter Grehan
651517904deSPeter Grehan /* Because we didn't get link via the internal auto-negotiation
652517904deSPeter Grehan * mechanism (we either forced link or we got link via PHY
653517904deSPeter Grehan * auto-neg), we have to manually enable/disable transmit an
654517904deSPeter Grehan * receive flow control.
655517904deSPeter Grehan *
656517904deSPeter Grehan * The "Case" statement below enables/disable flow control
657517904deSPeter Grehan * according to the "hw->fc.current_mode" parameter.
658517904deSPeter Grehan *
659517904deSPeter Grehan * The possible values of the "fc" parameter are:
660517904deSPeter Grehan * 0: Flow control is completely disabled
661517904deSPeter Grehan * 1: Rx flow control is enabled (we can receive pause
662517904deSPeter Grehan * frames but not send pause frames).
663517904deSPeter Grehan * 2: Tx flow control is enabled (we can send pause frames
664517904deSPeter Grehan * frames but we do not receive pause frames).
665517904deSPeter Grehan * 3: Both Rx and Tx flow control (symmetric) is enabled.
666517904deSPeter Grehan * other: No other values should be possible at this point.
667517904deSPeter Grehan */
668517904deSPeter Grehan DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
669517904deSPeter Grehan
670517904deSPeter Grehan switch (hw->fc.current_mode) {
671517904deSPeter Grehan case igc_fc_none:
672517904deSPeter Grehan ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
673517904deSPeter Grehan break;
674517904deSPeter Grehan case igc_fc_rx_pause:
675517904deSPeter Grehan ctrl &= (~IGC_CTRL_TFCE);
676517904deSPeter Grehan ctrl |= IGC_CTRL_RFCE;
677517904deSPeter Grehan break;
678517904deSPeter Grehan case igc_fc_tx_pause:
679517904deSPeter Grehan ctrl &= (~IGC_CTRL_RFCE);
680517904deSPeter Grehan ctrl |= IGC_CTRL_TFCE;
681517904deSPeter Grehan break;
682517904deSPeter Grehan case igc_fc_full:
683517904deSPeter Grehan ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
684517904deSPeter Grehan break;
685517904deSPeter Grehan default:
686517904deSPeter Grehan DEBUGOUT("Flow control param set incorrectly\n");
687517904deSPeter Grehan return -IGC_ERR_CONFIG;
688517904deSPeter Grehan }
689517904deSPeter Grehan
690517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
691517904deSPeter Grehan
692517904deSPeter Grehan return IGC_SUCCESS;
693517904deSPeter Grehan }
694517904deSPeter Grehan
695517904deSPeter Grehan /**
696517904deSPeter Grehan * igc_config_fc_after_link_up_generic - Configures flow control after link
697517904deSPeter Grehan * @hw: pointer to the HW structure
698517904deSPeter Grehan *
699517904deSPeter Grehan * Checks the status of auto-negotiation after link up to ensure that the
700517904deSPeter Grehan * speed and duplex were not forced. If the link needed to be forced, then
701517904deSPeter Grehan * flow control needs to be forced also. If auto-negotiation is enabled
702517904deSPeter Grehan * and did not fail, then we configure flow control based on our link
703517904deSPeter Grehan * partner.
704517904deSPeter Grehan **/
igc_config_fc_after_link_up_generic(struct igc_hw * hw)705517904deSPeter Grehan s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw)
706517904deSPeter Grehan {
707517904deSPeter Grehan struct igc_mac_info *mac = &hw->mac;
708517904deSPeter Grehan s32 ret_val = IGC_SUCCESS;
709517904deSPeter Grehan u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
710517904deSPeter Grehan u16 speed, duplex;
711517904deSPeter Grehan
712517904deSPeter Grehan DEBUGFUNC("igc_config_fc_after_link_up_generic");
713517904deSPeter Grehan
714517904deSPeter Grehan if (ret_val) {
715517904deSPeter Grehan DEBUGOUT("Error forcing flow control settings\n");
716517904deSPeter Grehan return ret_val;
717517904deSPeter Grehan }
718517904deSPeter Grehan
719517904deSPeter Grehan /* Check for the case where we have copper media and auto-neg is
720517904deSPeter Grehan * enabled. In this case, we need to check and see if Auto-Neg
721517904deSPeter Grehan * has completed, and if so, how the PHY and link partner has
722517904deSPeter Grehan * flow control configured.
723517904deSPeter Grehan */
724517904deSPeter Grehan if (mac->autoneg) {
725517904deSPeter Grehan /* Read the MII Status Register and check to see if AutoNeg
726517904deSPeter Grehan * has completed. We read this twice because this reg has
727517904deSPeter Grehan * some "sticky" (latched) bits.
728517904deSPeter Grehan */
729517904deSPeter Grehan ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
730517904deSPeter Grehan if (ret_val)
731517904deSPeter Grehan return ret_val;
732517904deSPeter Grehan ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
733517904deSPeter Grehan if (ret_val)
734517904deSPeter Grehan return ret_val;
735517904deSPeter Grehan
736517904deSPeter Grehan if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
737517904deSPeter Grehan DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
738517904deSPeter Grehan return ret_val;
739517904deSPeter Grehan }
740517904deSPeter Grehan
741517904deSPeter Grehan /* The AutoNeg process has completed, so we now need to
742517904deSPeter Grehan * read both the Auto Negotiation Advertisement
743517904deSPeter Grehan * Register (Address 4) and the Auto_Negotiation Base
744517904deSPeter Grehan * Page Ability Register (Address 5) to determine how
745517904deSPeter Grehan * flow control was negotiated.
746517904deSPeter Grehan */
747517904deSPeter Grehan ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
748517904deSPeter Grehan &mii_nway_adv_reg);
749517904deSPeter Grehan if (ret_val)
750517904deSPeter Grehan return ret_val;
751517904deSPeter Grehan ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
752517904deSPeter Grehan &mii_nway_lp_ability_reg);
753517904deSPeter Grehan if (ret_val)
754517904deSPeter Grehan return ret_val;
755517904deSPeter Grehan
756517904deSPeter Grehan /* Two bits in the Auto Negotiation Advertisement Register
757517904deSPeter Grehan * (Address 4) and two bits in the Auto Negotiation Base
758517904deSPeter Grehan * Page Ability Register (Address 5) determine flow control
759517904deSPeter Grehan * for both the PHY and the link partner. The following
760517904deSPeter Grehan * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
761517904deSPeter Grehan * 1999, describes these PAUSE resolution bits and how flow
762517904deSPeter Grehan * control is determined based upon these settings.
763517904deSPeter Grehan * NOTE: DC = Don't Care
764517904deSPeter Grehan *
765517904deSPeter Grehan * LOCAL DEVICE | LINK PARTNER
766517904deSPeter Grehan * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
767517904deSPeter Grehan *-------|---------|-------|---------|--------------------
768517904deSPeter Grehan * 0 | 0 | DC | DC | igc_fc_none
769517904deSPeter Grehan * 0 | 1 | 0 | DC | igc_fc_none
770517904deSPeter Grehan * 0 | 1 | 1 | 0 | igc_fc_none
771517904deSPeter Grehan * 0 | 1 | 1 | 1 | igc_fc_tx_pause
772517904deSPeter Grehan * 1 | 0 | 0 | DC | igc_fc_none
773517904deSPeter Grehan * 1 | DC | 1 | DC | igc_fc_full
774517904deSPeter Grehan * 1 | 1 | 0 | 0 | igc_fc_none
775517904deSPeter Grehan * 1 | 1 | 0 | 1 | igc_fc_rx_pause
776517904deSPeter Grehan *
777517904deSPeter Grehan * Are both PAUSE bits set to 1? If so, this implies
778517904deSPeter Grehan * Symmetric Flow Control is enabled at both ends. The
779517904deSPeter Grehan * ASM_DIR bits are irrelevant per the spec.
780517904deSPeter Grehan *
781517904deSPeter Grehan * For Symmetric Flow Control:
782517904deSPeter Grehan *
783517904deSPeter Grehan * LOCAL DEVICE | LINK PARTNER
784517904deSPeter Grehan * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
785517904deSPeter Grehan *-------|---------|-------|---------|--------------------
786517904deSPeter Grehan * 1 | DC | 1 | DC | IGC_fc_full
787517904deSPeter Grehan *
788517904deSPeter Grehan */
789517904deSPeter Grehan if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
790517904deSPeter Grehan (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
791517904deSPeter Grehan /* Now we need to check if the user selected Rx ONLY
792517904deSPeter Grehan * of pause frames. In this case, we had to advertise
793517904deSPeter Grehan * FULL flow control because we could not advertise Rx
794517904deSPeter Grehan * ONLY. Hence, we must now check to see if we need to
795517904deSPeter Grehan * turn OFF the TRANSMISSION of PAUSE frames.
796517904deSPeter Grehan */
797517904deSPeter Grehan if (hw->fc.requested_mode == igc_fc_full) {
798517904deSPeter Grehan hw->fc.current_mode = igc_fc_full;
799517904deSPeter Grehan DEBUGOUT("Flow Control = FULL.\n");
800517904deSPeter Grehan } else {
801517904deSPeter Grehan hw->fc.current_mode = igc_fc_rx_pause;
802517904deSPeter Grehan DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
803517904deSPeter Grehan }
804517904deSPeter Grehan }
805517904deSPeter Grehan /* For receiving PAUSE frames ONLY.
806517904deSPeter Grehan *
807517904deSPeter Grehan * LOCAL DEVICE | LINK PARTNER
808517904deSPeter Grehan * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
809517904deSPeter Grehan *-------|---------|-------|---------|--------------------
810517904deSPeter Grehan * 0 | 1 | 1 | 1 | igc_fc_tx_pause
811517904deSPeter Grehan */
812517904deSPeter Grehan else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
813517904deSPeter Grehan (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
814517904deSPeter Grehan (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
815517904deSPeter Grehan (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
816517904deSPeter Grehan hw->fc.current_mode = igc_fc_tx_pause;
817517904deSPeter Grehan DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
818517904deSPeter Grehan }
819517904deSPeter Grehan /* For transmitting PAUSE frames ONLY.
820517904deSPeter Grehan *
821517904deSPeter Grehan * LOCAL DEVICE | LINK PARTNER
822517904deSPeter Grehan * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
823517904deSPeter Grehan *-------|---------|-------|---------|--------------------
824517904deSPeter Grehan * 1 | 1 | 0 | 1 | igc_fc_rx_pause
825517904deSPeter Grehan */
826517904deSPeter Grehan else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
827517904deSPeter Grehan (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
828517904deSPeter Grehan !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
829517904deSPeter Grehan (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
830517904deSPeter Grehan hw->fc.current_mode = igc_fc_rx_pause;
831517904deSPeter Grehan DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
832517904deSPeter Grehan } else {
833517904deSPeter Grehan /* Per the IEEE spec, at this point flow control
834517904deSPeter Grehan * should be disabled.
835517904deSPeter Grehan */
836517904deSPeter Grehan hw->fc.current_mode = igc_fc_none;
837517904deSPeter Grehan DEBUGOUT("Flow Control = NONE.\n");
838517904deSPeter Grehan }
839517904deSPeter Grehan
840517904deSPeter Grehan /* Now we need to do one last check... If we auto-
841517904deSPeter Grehan * negotiated to HALF DUPLEX, flow control should not be
842517904deSPeter Grehan * enabled per IEEE 802.3 spec.
843517904deSPeter Grehan */
844517904deSPeter Grehan ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
845517904deSPeter Grehan if (ret_val) {
846517904deSPeter Grehan DEBUGOUT("Error getting link speed and duplex\n");
847517904deSPeter Grehan return ret_val;
848517904deSPeter Grehan }
849517904deSPeter Grehan
850517904deSPeter Grehan if (duplex == HALF_DUPLEX)
851517904deSPeter Grehan hw->fc.current_mode = igc_fc_none;
852517904deSPeter Grehan
853517904deSPeter Grehan /* Now we call a subroutine to actually force the MAC
854517904deSPeter Grehan * controller to use the correct flow control settings.
855517904deSPeter Grehan */
856517904deSPeter Grehan ret_val = igc_force_mac_fc_generic(hw);
857517904deSPeter Grehan if (ret_val) {
858517904deSPeter Grehan DEBUGOUT("Error forcing flow control settings\n");
859517904deSPeter Grehan return ret_val;
860517904deSPeter Grehan }
861517904deSPeter Grehan }
862517904deSPeter Grehan
863517904deSPeter Grehan return IGC_SUCCESS;
864517904deSPeter Grehan }
865517904deSPeter Grehan
866517904deSPeter Grehan /**
867517904deSPeter Grehan * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
868517904deSPeter Grehan * @hw: pointer to the HW structure
869517904deSPeter Grehan * @speed: stores the current speed
870517904deSPeter Grehan * @duplex: stores the current duplex
871517904deSPeter Grehan *
872517904deSPeter Grehan * Read the status register for the current speed/duplex and store the current
873517904deSPeter Grehan * speed and duplex for copper connections.
874517904deSPeter Grehan **/
igc_get_speed_and_duplex_copper_generic(struct igc_hw * hw,u16 * speed,u16 * duplex)875517904deSPeter Grehan s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,
876517904deSPeter Grehan u16 *duplex)
877517904deSPeter Grehan {
878517904deSPeter Grehan u32 status;
879517904deSPeter Grehan
880517904deSPeter Grehan DEBUGFUNC("igc_get_speed_and_duplex_copper_generic");
881517904deSPeter Grehan
882517904deSPeter Grehan status = IGC_READ_REG(hw, IGC_STATUS);
883517904deSPeter Grehan if (status & IGC_STATUS_SPEED_1000) {
884517904deSPeter Grehan /* For I225, STATUS will indicate 1G speed in both 1 Gbps
885517904deSPeter Grehan * and 2.5 Gbps link modes. An additional bit is used
886517904deSPeter Grehan * to differentiate between 1 Gbps and 2.5 Gbps.
887517904deSPeter Grehan */
888517904deSPeter Grehan if ((hw->mac.type == igc_i225) &&
889517904deSPeter Grehan (status & IGC_STATUS_SPEED_2500)) {
890517904deSPeter Grehan *speed = SPEED_2500;
891517904deSPeter Grehan DEBUGOUT("2500 Mbs, ");
892517904deSPeter Grehan } else {
893517904deSPeter Grehan *speed = SPEED_1000;
894517904deSPeter Grehan DEBUGOUT("1000 Mbs, ");
895517904deSPeter Grehan }
896517904deSPeter Grehan } else if (status & IGC_STATUS_SPEED_100) {
897517904deSPeter Grehan *speed = SPEED_100;
898517904deSPeter Grehan DEBUGOUT("100 Mbs, ");
899517904deSPeter Grehan } else {
900517904deSPeter Grehan *speed = SPEED_10;
901517904deSPeter Grehan DEBUGOUT("10 Mbs, ");
902517904deSPeter Grehan }
903517904deSPeter Grehan
904517904deSPeter Grehan if (status & IGC_STATUS_FD) {
905517904deSPeter Grehan *duplex = FULL_DUPLEX;
906517904deSPeter Grehan DEBUGOUT("Full Duplex\n");
907517904deSPeter Grehan } else {
908517904deSPeter Grehan *duplex = HALF_DUPLEX;
909517904deSPeter Grehan DEBUGOUT("Half Duplex\n");
910517904deSPeter Grehan }
911517904deSPeter Grehan
912517904deSPeter Grehan return IGC_SUCCESS;
913517904deSPeter Grehan }
914517904deSPeter Grehan
915517904deSPeter Grehan /**
916517904deSPeter Grehan * igc_get_hw_semaphore_generic - Acquire hardware semaphore
917517904deSPeter Grehan * @hw: pointer to the HW structure
918517904deSPeter Grehan *
919517904deSPeter Grehan * Acquire the HW semaphore to access the PHY or NVM
920517904deSPeter Grehan **/
igc_get_hw_semaphore_generic(struct igc_hw * hw)921517904deSPeter Grehan s32 igc_get_hw_semaphore_generic(struct igc_hw *hw)
922517904deSPeter Grehan {
923517904deSPeter Grehan u32 swsm;
924517904deSPeter Grehan s32 timeout = hw->nvm.word_size + 1;
925517904deSPeter Grehan s32 i = 0;
926517904deSPeter Grehan
927517904deSPeter Grehan DEBUGFUNC("igc_get_hw_semaphore_generic");
928517904deSPeter Grehan
929517904deSPeter Grehan /* Get the SW semaphore */
930517904deSPeter Grehan while (i < timeout) {
931517904deSPeter Grehan swsm = IGC_READ_REG(hw, IGC_SWSM);
932517904deSPeter Grehan if (!(swsm & IGC_SWSM_SMBI))
933517904deSPeter Grehan break;
934517904deSPeter Grehan
935517904deSPeter Grehan usec_delay(50);
936517904deSPeter Grehan i++;
937517904deSPeter Grehan }
938517904deSPeter Grehan
939517904deSPeter Grehan if (i == timeout) {
940517904deSPeter Grehan DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
941517904deSPeter Grehan return -IGC_ERR_NVM;
942517904deSPeter Grehan }
943517904deSPeter Grehan
944517904deSPeter Grehan /* Get the FW semaphore. */
945517904deSPeter Grehan for (i = 0; i < timeout; i++) {
946517904deSPeter Grehan swsm = IGC_READ_REG(hw, IGC_SWSM);
947517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
948517904deSPeter Grehan
949517904deSPeter Grehan /* Semaphore acquired if bit latched */
950517904deSPeter Grehan if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)
951517904deSPeter Grehan break;
952517904deSPeter Grehan
953517904deSPeter Grehan usec_delay(50);
954517904deSPeter Grehan }
955517904deSPeter Grehan
956517904deSPeter Grehan if (i == timeout) {
957517904deSPeter Grehan /* Release semaphores */
958517904deSPeter Grehan igc_put_hw_semaphore_generic(hw);
959517904deSPeter Grehan DEBUGOUT("Driver can't access the NVM\n");
960517904deSPeter Grehan return -IGC_ERR_NVM;
961517904deSPeter Grehan }
962517904deSPeter Grehan
963517904deSPeter Grehan return IGC_SUCCESS;
964517904deSPeter Grehan }
965517904deSPeter Grehan
966517904deSPeter Grehan /**
967517904deSPeter Grehan * igc_put_hw_semaphore_generic - Release hardware semaphore
968517904deSPeter Grehan * @hw: pointer to the HW structure
969517904deSPeter Grehan *
970517904deSPeter Grehan * Release hardware semaphore used to access the PHY or NVM
971517904deSPeter Grehan **/
igc_put_hw_semaphore_generic(struct igc_hw * hw)972517904deSPeter Grehan void igc_put_hw_semaphore_generic(struct igc_hw *hw)
973517904deSPeter Grehan {
974517904deSPeter Grehan u32 swsm;
975517904deSPeter Grehan
976517904deSPeter Grehan DEBUGFUNC("igc_put_hw_semaphore_generic");
977517904deSPeter Grehan
978517904deSPeter Grehan swsm = IGC_READ_REG(hw, IGC_SWSM);
979517904deSPeter Grehan
980517904deSPeter Grehan swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
981517904deSPeter Grehan
982517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_SWSM, swsm);
983517904deSPeter Grehan }
984517904deSPeter Grehan
985517904deSPeter Grehan /**
986517904deSPeter Grehan * igc_get_auto_rd_done_generic - Check for auto read completion
987517904deSPeter Grehan * @hw: pointer to the HW structure
988517904deSPeter Grehan *
989517904deSPeter Grehan * Check EEPROM for Auto Read done bit.
990517904deSPeter Grehan **/
igc_get_auto_rd_done_generic(struct igc_hw * hw)991517904deSPeter Grehan s32 igc_get_auto_rd_done_generic(struct igc_hw *hw)
992517904deSPeter Grehan {
993517904deSPeter Grehan s32 i = 0;
994517904deSPeter Grehan
995517904deSPeter Grehan DEBUGFUNC("igc_get_auto_rd_done_generic");
996517904deSPeter Grehan
997517904deSPeter Grehan while (i < AUTO_READ_DONE_TIMEOUT) {
998517904deSPeter Grehan if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)
999517904deSPeter Grehan break;
1000517904deSPeter Grehan msec_delay(1);
1001517904deSPeter Grehan i++;
1002517904deSPeter Grehan }
1003517904deSPeter Grehan
1004517904deSPeter Grehan if (i == AUTO_READ_DONE_TIMEOUT) {
1005517904deSPeter Grehan DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1006517904deSPeter Grehan return -IGC_ERR_RESET;
1007517904deSPeter Grehan }
1008517904deSPeter Grehan
1009517904deSPeter Grehan return IGC_SUCCESS;
1010517904deSPeter Grehan }
1011517904deSPeter Grehan
1012517904deSPeter Grehan /**
1013517904deSPeter Grehan * igc_disable_pcie_master_generic - Disables PCI-express master access
1014517904deSPeter Grehan * @hw: pointer to the HW structure
1015517904deSPeter Grehan *
1016517904deSPeter Grehan * Returns IGC_SUCCESS if successful, else returns -10
1017517904deSPeter Grehan * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1018517904deSPeter Grehan * the master requests to be disabled.
1019517904deSPeter Grehan *
1020517904deSPeter Grehan * Disables PCI-Express master access and verifies there are no pending
1021517904deSPeter Grehan * requests.
1022517904deSPeter Grehan **/
igc_disable_pcie_master_generic(struct igc_hw * hw)1023517904deSPeter Grehan s32 igc_disable_pcie_master_generic(struct igc_hw *hw)
1024517904deSPeter Grehan {
1025517904deSPeter Grehan u32 ctrl;
1026517904deSPeter Grehan s32 timeout = MASTER_DISABLE_TIMEOUT;
1027517904deSPeter Grehan
1028517904deSPeter Grehan DEBUGFUNC("igc_disable_pcie_master_generic");
1029517904deSPeter Grehan
1030517904deSPeter Grehan ctrl = IGC_READ_REG(hw, IGC_CTRL);
1031517904deSPeter Grehan ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
1032517904deSPeter Grehan IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
1033517904deSPeter Grehan
1034517904deSPeter Grehan while (timeout) {
1035517904deSPeter Grehan if (!(IGC_READ_REG(hw, IGC_STATUS) &
1036517904deSPeter Grehan IGC_STATUS_GIO_MASTER_ENABLE))
1037517904deSPeter Grehan break;
1038517904deSPeter Grehan usec_delay(100);
1039517904deSPeter Grehan timeout--;
1040517904deSPeter Grehan }
1041517904deSPeter Grehan
1042517904deSPeter Grehan if (!timeout) {
1043517904deSPeter Grehan DEBUGOUT("Master requests are pending.\n");
1044517904deSPeter Grehan return -IGC_ERR_MASTER_REQUESTS_PENDING;
1045517904deSPeter Grehan }
1046517904deSPeter Grehan
1047517904deSPeter Grehan return IGC_SUCCESS;
1048517904deSPeter Grehan }
1049