1 /*- 2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Development sponsored by Microsemi, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Helper code to recover a hung i2c bus by bit-banging a recovery sequence. 34 * 35 * An i2c bus can be hung by a slave driving the clock (rare) or data lines low. 36 * The most common cause is a partially-completed transaction such as rebooting 37 * while a slave is sending a byte of data. Because i2c allows the clock to 38 * freeze for any amount of time, the slave device will continue driving the 39 * data line until power is removed, or the clock cycles enough times to 40 * complete the current byte. After completing any partial byte, a START/STOP 41 * sequence resets the slave and the bus is recovered. 42 * 43 * Any i2c driver which is able to manually set the level of the clock and data 44 * lines can use this common code for bus recovery. On many SOCs that have 45 * embedded i2c controllers, the i2c pins can be temporarily reassigned as gpio 46 * pins to do the bus recovery, then can be assigned back to the i2c hardware. 47 */ 48 49 #include "opt_platform.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/bus.h> 54 55 #include <dev/iicbus/iic_recover_bus.h> 56 #include <dev/iicbus/iiconf.h> 57 58 int 59 iic_recover_bus(struct iicrb_pin_access *pins) 60 { 61 const u_int timeout_us = 40000; 62 const u_int delay_us = 500; 63 int i; 64 65 /* 66 * Start with clock and data high. 67 */ 68 pins->setsda(pins->ctx, 1); 69 pins->setscl(pins->ctx, 1); 70 71 /* 72 * At this point, SCL should be high. If it's not, some slave on the 73 * bus is doing clock-stretching and we should wait a while. If that 74 * slave is completely locked up there may be no way to recover at all. 75 * We wait up to 40 milliseconds, a seriously pessimistic time (even a 76 * cheap eeprom has a max post-write delay of only 10ms), and also long 77 * enough to allow SMB slaves to timeout normally after 35ms. 78 */ 79 for (i = 0; i < timeout_us; i += delay_us) { 80 if (pins->getscl(pins->ctx)) 81 break; 82 DELAY(delay_us); 83 } 84 if (i >= timeout_us) 85 return (IIC_EBUSERR); 86 87 /* 88 * At this point we should be able to control the clock line. Some 89 * slave may be part way through a byte transfer, and could be holding 90 * the data line low waiting for more clock pulses to finish the byte. 91 * Cycle the clock until we see the data line go high, but only up to 9 92 * times because if it's not free after 9 clocks we're never going to 93 * win this battle. We do 9 max because that's a byte plus an ack/nack 94 * bit, after which the slave must not be driving the data line anymore. 95 */ 96 for (i = 0; ; ++i) { 97 if (pins->getsda(pins->ctx)) 98 break; 99 if (i == 9) 100 return (IIC_EBUSERR); 101 pins->setscl(pins->ctx, 0); 102 DELAY(5); 103 pins->setscl(pins->ctx, 1); 104 DELAY(5); 105 } 106 107 /* 108 * At this point we should be in control of both the clock and data 109 * lines, and both lines should be high. To complete the reset of a 110 * slave that was part way through a transaction, we need to do a 111 * START/STOP sequence, which leaves both lines high at the end. 112 * - START: SDA transitions high->low while SCL remains high. 113 * - STOP: SDA transitions low->high while SCL remains high. 114 * Note that even though the clock line remains high, we transition the 115 * data line no faster than it would change state with a 100khz clock. 116 */ 117 pins->setsda(pins->ctx, 0); 118 DELAY(5); 119 pins->setsda(pins->ctx, 1); 120 DELAY(5); 121 122 return (0); 123 } 124 125