1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2017 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_H 37 #define IRDMA_H 38 39 #define RDMA_BIT2(type, a) ((u##type) 1UL << a) 40 #define RDMA_MASK3(type, mask, shift) ((u##type) mask << shift) 41 #define MAKEMASK(m, s) ((m) << (s)) 42 43 #define IRDMA_WQEALLOC_WQE_DESC_INDEX_S 20 44 #define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20) 45 46 #define IRDMA_CQPTAIL_WQTAIL_S 0 47 #define IRDMA_CQPTAIL_WQTAIL GENMASK(10, 0) 48 #define IRDMA_CQPTAIL_CQP_OP_ERR_S 31 49 #define IRDMA_CQPTAIL_CQP_OP_ERR BIT(31) 50 51 #define IRDMA_CQPERRCODES_CQP_MINOR_CODE_S 0 52 #define IRDMA_CQPERRCODES_CQP_MINOR_CODE GENMASK(15, 0) 53 #define IRDMA_CQPERRCODES_CQP_MAJOR_CODE_S 16 54 #define IRDMA_CQPERRCODES_CQP_MAJOR_CODE GENMASK(31, 16) 55 #define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE_S 4 56 #define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE GENMASK(5, 4) 57 #define IRDMA_GLINT_RATE_INTERVAL_S 0 58 #define IRDMA_GLINT_RATE_INTERVAL GENMASK(4, 0) 59 #define IRDMA_GLINT_RATE_INTRL_ENA_S 6 60 #define IRDMA_GLINT_RATE_INTRL_ENA_M BIT(6) 61 #define IRDMA_GLINT_RATE_INTRL_ENA BIT(6) 62 63 #define IRDMA_GLINT_DYN_CTL_INTENA_S 0 64 #define IRDMA_GLINT_DYN_CTL_INTENA BIT(0) 65 #define IRDMA_GLINT_DYN_CTL_CLEARPBA_S 1 66 #define IRDMA_GLINT_DYN_CTL_CLEARPBA BIT(1) 67 #define IRDMA_GLINT_DYN_CTL_ITR_INDX_S 3 68 #define IRDMA_GLINT_DYN_CTL_ITR_INDX GENMASK(4, 3) 69 #define IRDMA_GLINT_DYN_CTL_INTERVAL_S 5 70 #define IRDMA_GLINT_DYN_CTL_INTERVAL GENMASK(16, 5) 71 #define IRDMA_GLINT_CEQCTL_ITR_INDX_S 11 72 #define IRDMA_GLINT_CEQCTL_ITR_INDX GENMASK(12, 11) 73 #define IRDMA_GLINT_CEQCTL_CAUSE_ENA_S 30 74 #define IRDMA_GLINT_CEQCTL_CAUSE_ENA BIT(30) 75 #define IRDMA_GLINT_CEQCTL_MSIX_INDX_S 0 76 #define IRDMA_GLINT_CEQCTL_MSIX_INDX GENMASK(10, 0) 77 #define IRDMA_PFINT_AEQCTL_MSIX_INDX_S 0 78 #define IRDMA_PFINT_AEQCTL_MSIX_INDX GENMASK(10, 0) 79 #define IRDMA_PFINT_AEQCTL_ITR_INDX_S 11 80 #define IRDMA_PFINT_AEQCTL_ITR_INDX GENMASK(12, 11) 81 #define IRDMA_PFINT_AEQCTL_CAUSE_ENA_S 30 82 #define IRDMA_PFINT_AEQCTL_CAUSE_ENA BIT(30) 83 #define IRDMA_PFHMC_PDINV_PMSDIDX_S 0 84 #define IRDMA_PFHMC_PDINV_PMSDIDX GENMASK(11, 0) 85 #define IRDMA_PFHMC_PDINV_PMSDPARTSEL_S 15 86 #define IRDMA_PFHMC_PDINV_PMSDPARTSEL BIT(15) 87 #define IRDMA_PFHMC_PDINV_PMPDIDX_S 16 88 #define IRDMA_PFHMC_PDINV_PMPDIDX GENMASK(24, 16) 89 #define IRDMA_PFHMC_SDDATALOW_PMSDVALID_S 0 90 #define IRDMA_PFHMC_SDDATALOW_PMSDVALID BIT(0) 91 #define IRDMA_PFHMC_SDDATALOW_PMSDTYPE_S 1 92 #define IRDMA_PFHMC_SDDATALOW_PMSDTYPE BIT(1) 93 #define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT_S 2 94 #define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT GENMASK(11, 2) 95 #define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW_S 12 96 #define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW GENMASK(31, 12) 97 #define IRDMA_PFHMC_SDCMD_PMSDWR_S 31 98 #define IRDMA_PFHMC_SDCMD_PMSDWR BIT(31) 99 #define IRDMA_PFHMC_SDCMD_PMSDPARTSEL_S 15 100 #define IRDMA_PFHMC_SDCMD_PMSDPARTSEL BIT(15) 101 102 #define IRDMA_INVALID_CQ_IDX 0xffffffff 103 104 enum irdma_dyn_idx_t { 105 IRDMA_IDX_ITR0 = 0, 106 IRDMA_IDX_ITR1 = 1, 107 IRDMA_IDX_ITR2 = 2, 108 IRDMA_IDX_NOITR = 3, 109 }; 110 111 enum irdma_registers { 112 IRDMA_CQPTAIL, 113 IRDMA_CQPDB, 114 IRDMA_CCQPSTATUS, 115 IRDMA_CCQPHIGH, 116 IRDMA_CCQPLOW, 117 IRDMA_CQARM, 118 IRDMA_CQACK, 119 IRDMA_AEQALLOC, 120 IRDMA_CQPERRCODES, 121 IRDMA_WQEALLOC, 122 IRDMA_GLINT_DYN_CTL, 123 IRDMA_DB_ADDR_OFFSET, 124 IRDMA_GLPCI_LBARCTRL, 125 IRDMA_GLPE_CPUSTATUS0, 126 IRDMA_GLPE_CPUSTATUS1, 127 IRDMA_GLPE_CPUSTATUS2, 128 IRDMA_PFINT_AEQCTL, 129 IRDMA_GLINT_CEQCTL, 130 IRDMA_VSIQF_PE_CTL1, 131 IRDMA_PFHMC_PDINV, 132 IRDMA_GLHMC_VFPDINV, 133 IRDMA_GLPE_CRITERR, 134 IRDMA_GLINT_RATE, 135 IRDMA_MAX_REGS, /* Must be last entry */ 136 }; 137 138 enum irdma_shifts { 139 IRDMA_CCQPSTATUS_CCQP_DONE_S, 140 IRDMA_CCQPSTATUS_CCQP_ERR_S, 141 IRDMA_CQPSQ_STAG_PDID_S, 142 IRDMA_CQPSQ_CQ_CEQID_S, 143 IRDMA_CQPSQ_CQ_CQID_S, 144 IRDMA_COMMIT_FPM_CQCNT_S, 145 IRDMA_CQPSQ_UPESD_HMCFNID_S, 146 IRDMA_MAX_SHIFTS, 147 }; 148 149 enum irdma_masks { 150 IRDMA_CCQPSTATUS_CCQP_DONE_M, 151 IRDMA_CCQPSTATUS_CCQP_ERR_M, 152 IRDMA_CQPSQ_STAG_PDID_M, 153 IRDMA_CQPSQ_CQ_CEQID_M, 154 IRDMA_CQPSQ_CQ_CQID_M, 155 IRDMA_COMMIT_FPM_CQCNT_M, 156 IRDMA_CQPSQ_UPESD_HMCFNID_M, 157 IRDMA_MAX_MASKS, /* Must be last entry */ 158 }; 159 160 #define IRDMA_MAX_MGS_PER_CTX 8 161 162 struct irdma_mcast_grp_ctx_entry_info { 163 u32 qp_id; 164 bool valid_entry; 165 u16 dest_port; 166 u32 use_cnt; 167 }; 168 169 struct irdma_mcast_grp_info { 170 u8 dest_mac_addr[ETH_ALEN]; 171 u16 vlan_id; 172 u16 hmc_fcn_id; 173 bool ipv4_valid:1; 174 bool vlan_valid:1; 175 u16 mg_id; 176 u32 no_of_mgs; 177 u32 dest_ip_addr[4]; 178 u16 qs_handle; 179 struct irdma_dma_mem dma_mem_mc; 180 struct irdma_mcast_grp_ctx_entry_info mg_ctx_info[IRDMA_MAX_MGS_PER_CTX]; 181 }; 182 183 enum irdma_vers { 184 IRDMA_GEN_RSVD = 0, 185 IRDMA_GEN_1 = 1, 186 IRDMA_GEN_2 = 2, 187 IRDMA_GEN_MAX = 2, 188 }; 189 190 struct irdma_uk_attrs { 191 u64 feature_flags; 192 u32 max_hw_wq_frags; 193 u32 max_hw_read_sges; 194 u32 max_hw_inline; 195 u32 max_hw_rq_quanta; 196 u32 max_hw_wq_quanta; 197 u32 min_hw_cq_size; 198 u32 max_hw_cq_size; 199 u16 max_hw_sq_chunk; 200 u16 min_hw_wq_size; 201 u8 hw_rev; 202 }; 203 204 struct irdma_hw_attrs { 205 struct irdma_uk_attrs uk_attrs; 206 u64 max_hw_outbound_msg_size; 207 u64 max_hw_inbound_msg_size; 208 u64 max_mr_size; 209 u64 page_size_cap; 210 u32 min_hw_qp_id; 211 u32 min_hw_aeq_size; 212 u32 max_hw_aeq_size; 213 u32 min_hw_ceq_size; 214 u32 max_hw_ceq_size; 215 u32 max_hw_device_pages; 216 u32 max_hw_vf_fpm_id; 217 u32 first_hw_vf_fpm_id; 218 u32 max_hw_ird; 219 u32 max_hw_ord; 220 u32 max_hw_wqes; 221 u32 max_hw_pds; 222 u32 max_hw_ena_vf_count; 223 u32 max_qp_wr; 224 u32 max_pe_ready_count; 225 u32 max_done_count; 226 u32 max_sleep_count; 227 u32 max_cqp_compl_wait_time_ms; 228 u16 max_stat_inst; 229 u16 max_stat_idx; 230 }; 231 232 void icrdma_init_hw(struct irdma_sc_dev *dev); 233 void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp); 234 #endif /* IRDMA_H*/ 235