1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_TYPE_H 37 #define IRDMA_TYPE_H 38 39 #include "osdep.h" 40 41 #include "irdma.h" 42 #include "irdma_user.h" 43 #include "irdma_hmc.h" 44 #include "irdma_uda.h" 45 #include "irdma_ws.h" 46 enum irdma_debug_flag { 47 IRDMA_DEBUG_NONE = 0x00000000, 48 IRDMA_DEBUG_ERR = 0x00000001, 49 IRDMA_DEBUG_INIT = 0x00000002, 50 IRDMA_DEBUG_DEV = 0x00000004, 51 IRDMA_DEBUG_CM = 0x00000008, 52 IRDMA_DEBUG_VERBS = 0x00000010, 53 IRDMA_DEBUG_PUDA = 0x00000020, 54 IRDMA_DEBUG_ILQ = 0x00000040, 55 IRDMA_DEBUG_IEQ = 0x00000080, 56 IRDMA_DEBUG_QP = 0x00000100, 57 IRDMA_DEBUG_CQ = 0x00000200, 58 IRDMA_DEBUG_MR = 0x00000400, 59 IRDMA_DEBUG_PBLE = 0x00000800, 60 IRDMA_DEBUG_WQE = 0x00001000, 61 IRDMA_DEBUG_AEQ = 0x00002000, 62 IRDMA_DEBUG_CQP = 0x00004000, 63 IRDMA_DEBUG_HMC = 0x00008000, 64 IRDMA_DEBUG_USER = 0x00010000, 65 IRDMA_DEBUG_VIRT = 0x00020000, 66 IRDMA_DEBUG_DCB = 0x00040000, 67 IRDMA_DEBUG_CQE = 0x00800000, 68 IRDMA_DEBUG_CLNT = 0x01000000, 69 IRDMA_DEBUG_WS = 0x02000000, 70 IRDMA_DEBUG_STATS = 0x04000000, 71 IRDMA_DEBUG_ALL = 0xFFFFFFFF, 72 }; 73 74 enum irdma_page_size { 75 IRDMA_PAGE_SIZE_4K = 0, 76 IRDMA_PAGE_SIZE_2M, 77 IRDMA_PAGE_SIZE_1G, 78 }; 79 80 enum irdma_hdrct_flags { 81 DDP_LEN_FLAG = 0x80, 82 DDP_HDR_FLAG = 0x40, 83 RDMA_HDR_FLAG = 0x20, 84 }; 85 86 enum irdma_term_layers { 87 LAYER_RDMA = 0, 88 LAYER_DDP = 1, 89 LAYER_MPA = 2, 90 }; 91 92 enum irdma_term_error_types { 93 RDMAP_REMOTE_PROT = 1, 94 RDMAP_REMOTE_OP = 2, 95 DDP_CATASTROPHIC = 0, 96 DDP_TAGGED_BUF = 1, 97 DDP_UNTAGGED_BUF = 2, 98 DDP_LLP = 3, 99 }; 100 101 enum irdma_term_rdma_errors { 102 RDMAP_INV_STAG = 0x00, 103 RDMAP_INV_BOUNDS = 0x01, 104 RDMAP_ACCESS = 0x02, 105 RDMAP_UNASSOC_STAG = 0x03, 106 RDMAP_TO_WRAP = 0x04, 107 RDMAP_INV_RDMAP_VER = 0x05, 108 RDMAP_UNEXPECTED_OP = 0x06, 109 RDMAP_CATASTROPHIC_LOCAL = 0x07, 110 RDMAP_CATASTROPHIC_GLOBAL = 0x08, 111 RDMAP_CANT_INV_STAG = 0x09, 112 RDMAP_UNSPECIFIED = 0xff, 113 }; 114 115 enum irdma_term_ddp_errors { 116 DDP_CATASTROPHIC_LOCAL = 0x00, 117 DDP_TAGGED_INV_STAG = 0x00, 118 DDP_TAGGED_BOUNDS = 0x01, 119 DDP_TAGGED_UNASSOC_STAG = 0x02, 120 DDP_TAGGED_TO_WRAP = 0x03, 121 DDP_TAGGED_INV_DDP_VER = 0x04, 122 DDP_UNTAGGED_INV_QN = 0x01, 123 DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02, 124 DDP_UNTAGGED_INV_MSN_RANGE = 0x03, 125 DDP_UNTAGGED_INV_MO = 0x04, 126 DDP_UNTAGGED_INV_TOO_LONG = 0x05, 127 DDP_UNTAGGED_INV_DDP_VER = 0x06, 128 }; 129 130 enum irdma_term_mpa_errors { 131 MPA_CLOSED = 0x01, 132 MPA_CRC = 0x02, 133 MPA_MARKER = 0x03, 134 MPA_REQ_RSP = 0x04, 135 }; 136 137 enum irdma_hw_stats_index { 138 /* gen1 - 32-bit */ 139 IRDMA_HW_STAT_INDEX_IP4RXDISCARD = 0, 140 IRDMA_HW_STAT_INDEX_IP4RXTRUNC = 1, 141 IRDMA_HW_STAT_INDEX_IP4TXNOROUTE = 2, 142 IRDMA_HW_STAT_INDEX_IP6RXDISCARD = 3, 143 IRDMA_HW_STAT_INDEX_IP6RXTRUNC = 4, 144 IRDMA_HW_STAT_INDEX_IP6TXNOROUTE = 5, 145 IRDMA_HW_STAT_INDEX_TCPRTXSEG = 6, 146 IRDMA_HW_STAT_INDEX_TCPRXOPTERR = 7, 147 IRDMA_HW_STAT_INDEX_TCPRXPROTOERR = 8, 148 IRDMA_HW_STAT_INDEX_RXVLANERR = 9, 149 /* gen1 - 64-bit */ 150 IRDMA_HW_STAT_INDEX_IP4RXOCTS = 10, 151 IRDMA_HW_STAT_INDEX_IP4RXPKTS = 11, 152 IRDMA_HW_STAT_INDEX_IP4RXFRAGS = 12, 153 IRDMA_HW_STAT_INDEX_IP4RXMCPKTS = 13, 154 IRDMA_HW_STAT_INDEX_IP4TXOCTS = 14, 155 IRDMA_HW_STAT_INDEX_IP4TXPKTS = 15, 156 IRDMA_HW_STAT_INDEX_IP4TXFRAGS = 16, 157 IRDMA_HW_STAT_INDEX_IP4TXMCPKTS = 17, 158 IRDMA_HW_STAT_INDEX_IP6RXOCTS = 18, 159 IRDMA_HW_STAT_INDEX_IP6RXPKTS = 19, 160 IRDMA_HW_STAT_INDEX_IP6RXFRAGS = 20, 161 IRDMA_HW_STAT_INDEX_IP6RXMCPKTS = 21, 162 IRDMA_HW_STAT_INDEX_IP6TXOCTS = 22, 163 IRDMA_HW_STAT_INDEX_IP6TXPKTS = 23, 164 IRDMA_HW_STAT_INDEX_IP6TXFRAGS = 24, 165 IRDMA_HW_STAT_INDEX_IP6TXMCPKTS = 25, 166 IRDMA_HW_STAT_INDEX_TCPRXSEGS = 26, 167 IRDMA_HW_STAT_INDEX_TCPTXSEG = 27, 168 IRDMA_HW_STAT_INDEX_RDMARXRDS = 28, 169 IRDMA_HW_STAT_INDEX_RDMARXSNDS = 29, 170 IRDMA_HW_STAT_INDEX_RDMARXWRS = 30, 171 IRDMA_HW_STAT_INDEX_RDMATXRDS = 31, 172 IRDMA_HW_STAT_INDEX_RDMATXSNDS = 32, 173 IRDMA_HW_STAT_INDEX_RDMATXWRS = 33, 174 IRDMA_HW_STAT_INDEX_RDMAVBND = 34, 175 IRDMA_HW_STAT_INDEX_RDMAVINV = 35, 176 IRDMA_HW_STAT_INDEX_IP4RXMCOCTS = 36, 177 IRDMA_HW_STAT_INDEX_IP4TXMCOCTS = 37, 178 IRDMA_HW_STAT_INDEX_IP6RXMCOCTS = 38, 179 IRDMA_HW_STAT_INDEX_IP6TXMCOCTS = 39, 180 IRDMA_HW_STAT_INDEX_UDPRXPKTS = 40, 181 IRDMA_HW_STAT_INDEX_UDPTXPKTS = 41, 182 IRDMA_HW_STAT_INDEX_MAX_GEN_1 = 42, /* Must be same value as next entry */ 183 184 /* gen2 - 64-bit */ 185 IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS = 42, 186 187 /* gen2 - 32-bit */ 188 IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED = 43, 189 IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED = 44, 190 IRDMA_HW_STAT_INDEX_TXNPCNPSENT = 45, 191 IRDMA_HW_STAT_INDEX_MAX_GEN_2 = 46, 192 }; 193 194 #define IRDMA_MIN_FEATURES 2 195 196 enum irdma_feature_type { 197 IRDMA_FEATURE_FW_INFO = 0, 198 IRDMA_HW_VERSION_INFO = 1, 199 IRDMA_QSETS_MAX = 26, 200 IRDMA_MAX_FEATURES, /* Must be last entry */ 201 }; 202 203 enum irdma_sched_prio_type { 204 IRDMA_PRIO_WEIGHTED_RR = 1, 205 IRDMA_PRIO_STRICT = 2, 206 IRDMA_PRIO_WEIGHTED_STRICT = 3, 207 }; 208 209 enum irdma_vm_vf_type { 210 IRDMA_VF_TYPE = 0, 211 IRDMA_VM_TYPE, 212 IRDMA_PF_TYPE, 213 }; 214 215 enum irdma_cqp_hmc_profile { 216 IRDMA_HMC_PROFILE_DEFAULT = 1, 217 IRDMA_HMC_PROFILE_FAVOR_VF = 2, 218 IRDMA_HMC_PROFILE_EQUAL = 3, 219 }; 220 221 enum irdma_quad_entry_type { 222 IRDMA_QHASH_TYPE_TCP_ESTABLISHED = 1, 223 IRDMA_QHASH_TYPE_TCP_SYN, 224 IRDMA_QHASH_TYPE_UDP_UNICAST, 225 IRDMA_QHASH_TYPE_UDP_MCAST, 226 IRDMA_QHASH_TYPE_ROCE_MCAST, 227 IRDMA_QHASH_TYPE_ROCEV2_HW, 228 }; 229 230 enum irdma_quad_hash_manage_type { 231 IRDMA_QHASH_MANAGE_TYPE_DELETE = 0, 232 IRDMA_QHASH_MANAGE_TYPE_ADD, 233 IRDMA_QHASH_MANAGE_TYPE_MODIFY, 234 }; 235 236 enum irdma_syn_rst_handling { 237 IRDMA_SYN_RST_HANDLING_HW_TCP_SECURE = 0, 238 IRDMA_SYN_RST_HANDLING_HW_TCP, 239 IRDMA_SYN_RST_HANDLING_FW_TCP_SECURE, 240 IRDMA_SYN_RST_HANDLING_FW_TCP, 241 }; 242 243 enum irdma_queue_type { 244 IRDMA_QUEUE_TYPE_SQ_RQ = 0, 245 IRDMA_QUEUE_TYPE_CQP, 246 }; 247 248 struct irdma_sc_dev; 249 struct irdma_vsi_pestat; 250 251 struct irdma_dcqcn_cc_params { 252 u8 cc_cfg_valid; 253 u8 min_dec_factor; 254 u8 min_rate; 255 u8 dcqcn_f; 256 u16 rai_factor; 257 u16 hai_factor; 258 u16 dcqcn_t; 259 u32 dcqcn_b; 260 u32 rreduce_mperiod; 261 }; 262 263 struct irdma_cqp_init_info { 264 u64 cqp_compl_ctx; 265 u64 host_ctx_pa; 266 u64 sq_pa; 267 struct irdma_sc_dev *dev; 268 struct irdma_cqp_quanta *sq; 269 struct irdma_dcqcn_cc_params dcqcn_params; 270 __le64 *host_ctx; 271 u64 *scratch_array; 272 u32 sq_size; 273 u16 hw_maj_ver; 274 u16 hw_min_ver; 275 u8 struct_ver; 276 u8 hmc_profile; 277 u8 ena_vf_count; 278 u8 ceqs_per_vf; 279 bool en_datacenter_tcp:1; 280 bool disable_packed:1; 281 bool rocev2_rto_policy:1; 282 bool en_rem_endpoint_trk:1; 283 enum irdma_protocol_used protocol_used; 284 }; 285 286 struct irdma_terminate_hdr { 287 u8 layer_etype; 288 u8 error_code; 289 u8 hdrct; 290 u8 rsvd; 291 }; 292 293 struct irdma_cqp_sq_wqe { 294 __le64 buf[IRDMA_CQP_WQE_SIZE]; 295 }; 296 297 struct irdma_sc_aeqe { 298 __le64 buf[IRDMA_AEQE_SIZE]; 299 }; 300 301 struct irdma_ceqe { 302 __le64 buf[IRDMA_CEQE_SIZE]; 303 }; 304 305 struct irdma_cqp_ctx { 306 __le64 buf[IRDMA_CQP_CTX_SIZE]; 307 }; 308 309 struct irdma_cq_shadow_area { 310 __le64 buf[IRDMA_SHADOW_AREA_SIZE]; 311 }; 312 313 struct irdma_dev_hw_stats { 314 u64 stats_val[IRDMA_GATHER_STATS_BUF_SIZE / sizeof(u64)]; 315 }; 316 317 struct irdma_gather_stats { 318 u64 val[IRDMA_GATHER_STATS_BUF_SIZE / sizeof(u64)]; 319 }; 320 321 struct irdma_hw_stat_map { 322 u16 byteoff; 323 u8 bitoff; 324 u64 bitmask; 325 }; 326 327 struct irdma_stats_gather_info { 328 bool use_hmc_fcn_index:1; 329 bool use_stats_inst:1; 330 u16 hmc_fcn_index; 331 u16 stats_inst_index; 332 struct irdma_dma_mem stats_buff_mem; 333 void *gather_stats_va; 334 void *last_gather_stats_va; 335 }; 336 337 struct irdma_vsi_pestat { 338 struct irdma_hw *hw; 339 struct irdma_dev_hw_stats hw_stats; 340 struct irdma_stats_gather_info gather_info; 341 struct OS_TIMER stats_timer; 342 struct irdma_sc_vsi *vsi; 343 spinlock_t lock; /* rdma stats lock */ 344 }; 345 346 struct irdma_hw { 347 u8 IOMEM *hw_addr; 348 u8 IOMEM *priv_hw_addr; 349 void *dev_context; 350 struct irdma_hmc_info hmc; 351 }; 352 353 struct irdma_pfpdu { 354 struct list_head rxlist; 355 u32 rcv_nxt; 356 u32 fps; 357 u32 max_fpdu_data; 358 u32 nextseqnum; 359 u32 rcv_start_seq; 360 bool mode:1; 361 bool mpa_crc_err:1; 362 u8 marker_len; 363 u64 total_ieq_bufs; 364 u64 fpdu_processed; 365 u64 bad_seq_num; 366 u64 crc_err; 367 u64 no_tx_bufs; 368 u64 tx_err; 369 u64 out_of_order; 370 u64 pmode_count; 371 struct irdma_sc_ah *ah; 372 struct irdma_puda_buf *ah_buf; 373 spinlock_t lock; /* fpdu processing lock */ 374 struct irdma_puda_buf *lastrcv_buf; 375 }; 376 377 struct irdma_sc_pd { 378 struct irdma_sc_dev *dev; 379 u32 pd_id; 380 int abi_ver; 381 }; 382 383 struct irdma_cqp_quanta { 384 __le64 elem[IRDMA_CQP_WQE_SIZE]; 385 }; 386 387 struct irdma_sc_cqp { 388 u32 size; 389 u64 sq_pa; 390 u64 host_ctx_pa; 391 void *back_cqp; 392 struct irdma_sc_dev *dev; 393 int (*process_cqp_sds)(struct irdma_sc_dev *dev, 394 struct irdma_update_sds_info *info); 395 struct irdma_dma_mem sdbuf; 396 struct irdma_ring sq_ring; 397 struct irdma_cqp_quanta *sq_base; 398 struct irdma_dcqcn_cc_params dcqcn_params; 399 __le64 *host_ctx; 400 u64 *scratch_array; 401 u32 cqp_id; 402 u32 sq_size; 403 u32 hw_sq_size; 404 u16 hw_maj_ver; 405 u16 hw_min_ver; 406 u8 struct_ver; 407 u8 polarity; 408 u8 hmc_profile; 409 u8 ena_vf_count; 410 u8 timeout_count; 411 u8 ceqs_per_vf; 412 bool en_datacenter_tcp:1; 413 bool disable_packed:1; 414 bool rocev2_rto_policy:1; 415 bool en_rem_endpoint_trk:1; 416 enum irdma_protocol_used protocol_used; 417 }; 418 419 struct irdma_sc_aeq { 420 u32 size; 421 u64 aeq_elem_pa; 422 struct irdma_sc_dev *dev; 423 struct irdma_sc_aeqe *aeqe_base; 424 void *pbl_list; 425 u32 elem_cnt; 426 struct irdma_ring aeq_ring; 427 u8 pbl_chunk_size; 428 u32 first_pm_pbl_idx; 429 u32 msix_idx; 430 u8 polarity; 431 bool virtual_map:1; 432 }; 433 434 struct irdma_sc_ceq { 435 u32 size; 436 u64 ceq_elem_pa; 437 struct irdma_sc_dev *dev; 438 struct irdma_ceqe *ceqe_base; 439 void *pbl_list; 440 u32 ceq_id; 441 u32 elem_cnt; 442 struct irdma_ring ceq_ring; 443 u8 pbl_chunk_size; 444 u8 tph_val; 445 u32 first_pm_pbl_idx; 446 u8 polarity; 447 struct irdma_sc_vsi *vsi; 448 struct irdma_sc_cq **reg_cq; 449 u32 reg_cq_size; 450 spinlock_t req_cq_lock; /* protect access to reg_cq array */ 451 bool virtual_map:1; 452 bool tph_en:1; 453 bool itr_no_expire:1; 454 }; 455 456 struct irdma_sc_cq { 457 struct irdma_cq_uk cq_uk; 458 u64 cq_pa; 459 u64 shadow_area_pa; 460 struct irdma_sc_dev *dev; 461 struct irdma_sc_vsi *vsi; 462 void *pbl_list; 463 void *back_cq; 464 u32 ceq_id; 465 u32 shadow_read_threshold; 466 u8 pbl_chunk_size; 467 u8 cq_type; 468 u8 tph_val; 469 u32 first_pm_pbl_idx; 470 bool ceqe_mask:1; 471 bool virtual_map:1; 472 bool check_overflow:1; 473 bool ceq_id_valid:1; 474 bool tph_en; 475 }; 476 477 struct irdma_sc_qp { 478 struct irdma_qp_uk qp_uk; 479 u64 sq_pa; 480 u64 rq_pa; 481 u64 hw_host_ctx_pa; 482 u64 shadow_area_pa; 483 u64 q2_pa; 484 struct irdma_sc_dev *dev; 485 struct irdma_sc_vsi *vsi; 486 struct irdma_sc_pd *pd; 487 __le64 *hw_host_ctx; 488 void *llp_stream_handle; 489 struct irdma_pfpdu pfpdu; 490 u32 ieq_qp; 491 u8 *q2_buf; 492 u64 qp_compl_ctx; 493 u32 push_idx; 494 u16 qs_handle; 495 u16 push_offset; 496 u8 flush_wqes_count; 497 u8 sq_tph_val; 498 u8 rq_tph_val; 499 u8 qp_state; 500 u8 hw_sq_size; 501 u8 hw_rq_size; 502 u8 src_mac_addr_idx; 503 bool on_qoslist:1; 504 bool ieq_pass_thru:1; 505 bool sq_tph_en:1; 506 bool rq_tph_en:1; 507 bool rcv_tph_en:1; 508 bool xmit_tph_en:1; 509 bool virtual_map:1; 510 bool flush_sq:1; 511 bool flush_rq:1; 512 bool sq_flush_code:1; 513 bool rq_flush_code:1; 514 enum irdma_flush_opcode flush_code; 515 enum irdma_qp_event_type event_type; 516 u8 term_flags; 517 u8 user_pri; 518 struct list_head list; 519 }; 520 521 struct irdma_stats_inst_info { 522 bool use_hmc_fcn_index; 523 u16 hmc_fn_id; 524 u16 stats_idx; 525 }; 526 527 struct irdma_up_info { 528 u8 map[8]; 529 u8 cnp_up_override; 530 u16 hmc_fcn_idx; 531 bool use_vlan:1; 532 bool use_cnp_up_override:1; 533 }; 534 535 #define IRDMA_MAX_WS_NODES 0x3FF 536 #define IRDMA_WS_NODE_INVALID 0xFFFF 537 538 struct irdma_ws_node_info { 539 u16 id; 540 u16 vsi; 541 u16 parent_id; 542 u16 qs_handle; 543 bool type_leaf:1; 544 bool enable:1; 545 u8 prio_type; 546 u8 tc; 547 u8 weight; 548 }; 549 550 struct irdma_hmc_fpm_misc { 551 u32 max_ceqs; 552 u32 max_sds; 553 u32 xf_block_size; 554 u32 q1_block_size; 555 u32 ht_multiplier; 556 u32 timer_bucket; 557 u32 rrf_block_size; 558 u32 ooiscf_block_size; 559 }; 560 561 #define IRDMA_LEAF_DEFAULT_REL_BW 64 562 #define IRDMA_PARENT_DEFAULT_REL_BW 1 563 564 struct irdma_qos { 565 struct list_head qplist; 566 struct mutex qos_mutex; /* protect QoS attributes per QoS level */ 567 u64 lan_qos_handle; 568 u32 l2_sched_node_id; 569 u16 qs_handle; 570 u8 traffic_class; 571 u8 rel_bw; 572 u8 prio_type; 573 bool valid; 574 }; 575 576 struct irdma_config_check { 577 bool config_ok:1; 578 bool lfc_set:1; 579 bool pfc_set:1; 580 u8 traffic_class; 581 u16 qs_handle; 582 }; 583 584 #define IRDMA_INVALID_STATS_IDX 0xff 585 struct irdma_sc_vsi { 586 u16 vsi_idx; 587 struct irdma_sc_dev *dev; 588 void *back_vsi; 589 u32 ilq_count; 590 struct irdma_virt_mem ilq_mem; 591 struct irdma_puda_rsrc *ilq; 592 u32 ieq_count; 593 struct irdma_virt_mem ieq_mem; 594 struct irdma_puda_rsrc *ieq; 595 u32 exception_lan_q; 596 u16 mtu; 597 enum irdma_vm_vf_type vm_vf_type; 598 bool stats_inst_alloc:1; 599 bool tc_change_pending:1; 600 bool mtu_change_pending:1; 601 struct irdma_vsi_pestat *pestat; 602 ATOMIC qp_suspend_reqs; 603 int (*register_qset)(struct irdma_sc_vsi *vsi, 604 struct irdma_ws_node *tc_node); 605 void (*unregister_qset)(struct irdma_sc_vsi *vsi, 606 struct irdma_ws_node *tc_node); 607 struct irdma_config_check cfg_check[IRDMA_MAX_USER_PRIORITY]; 608 bool tc_print_warning[IRDMA_MAX_TRAFFIC_CLASS]; 609 u8 qos_rel_bw; 610 u8 qos_prio_type; 611 u16 stats_idx; 612 u8 dscp_map[IRDMA_DSCP_NUM_VAL]; 613 struct irdma_qos qos[IRDMA_MAX_USER_PRIORITY]; 614 bool dscp_mode:1; 615 }; 616 617 struct irdma_sc_dev { 618 struct list_head cqp_cmd_head; /* head of the CQP command list */ 619 spinlock_t cqp_lock; /* protect CQP list access */ 620 struct irdma_dma_mem vf_fpm_query_buf[IRDMA_MAX_PE_ENA_VF_COUNT]; 621 u64 fpm_query_buf_pa; 622 u64 fpm_commit_buf_pa; 623 __le64 *fpm_query_buf; 624 __le64 *fpm_commit_buf; 625 struct irdma_hw *hw; 626 u8 IOMEM *db_addr; 627 u32 IOMEM *wqe_alloc_db; 628 u32 IOMEM *cq_arm_db; 629 u32 IOMEM *aeq_alloc_db; 630 u32 IOMEM *cqp_db; 631 u32 IOMEM *cq_ack_db; 632 u32 IOMEM *ceq_itr_mask_db; 633 u32 IOMEM *aeq_itr_mask_db; 634 u32 IOMEM *hw_regs[IRDMA_MAX_REGS]; 635 u32 ceq_itr; /* Interrupt throttle, usecs between interrupts: 0 disabled. 2 - 8160 */ 636 u64 hw_masks[IRDMA_MAX_MASKS]; 637 u8 hw_shifts[IRDMA_MAX_SHIFTS]; 638 const struct irdma_hw_stat_map *hw_stats_map; 639 u64 feature_info[IRDMA_MAX_FEATURES]; 640 u64 cqp_cmd_stats[IRDMA_MAX_CQP_OPS]; 641 struct irdma_hw_attrs hw_attrs; 642 struct irdma_hmc_info *hmc_info; 643 struct irdma_sc_cqp *cqp; 644 struct irdma_sc_aeq *aeq; 645 struct irdma_sc_ceq *ceq[IRDMA_CEQ_MAX_COUNT]; 646 struct irdma_sc_cq *ccq; 647 const struct irdma_irq_ops *irq_ops; 648 struct irdma_hmc_fpm_misc hmc_fpm_misc; 649 struct irdma_ws_node *ws_tree_root; 650 struct mutex ws_mutex; /* ws tree mutex */ 651 u32 debug_mask; 652 u16 num_vfs; 653 u16 hmc_fn_id; 654 u8 vf_id; 655 bool vchnl_up:1; 656 bool ceq_valid:1; 657 u8 pci_rev; 658 int (*ws_add)(struct irdma_sc_vsi *vsi, u8 user_pri); 659 void (*ws_remove)(struct irdma_sc_vsi *vsi, u8 user_pri); 660 void (*ws_reset)(struct irdma_sc_vsi *vsi); 661 }; 662 663 struct irdma_modify_cq_info { 664 u64 cq_pa; 665 struct irdma_cqe *cq_base; 666 u32 cq_size; 667 u32 shadow_read_threshold; 668 u8 pbl_chunk_size; 669 u32 first_pm_pbl_idx; 670 bool virtual_map:1; 671 bool check_overflow; 672 bool cq_resize:1; 673 }; 674 675 struct irdma_create_qp_info { 676 bool ord_valid:1; 677 bool tcp_ctx_valid:1; 678 bool cq_num_valid:1; 679 bool arp_cache_idx_valid:1; 680 bool mac_valid:1; 681 bool force_lpb; 682 u8 next_iwarp_state; 683 }; 684 685 struct irdma_modify_qp_info { 686 u64 rx_win0; 687 u64 rx_win1; 688 u16 new_mss; 689 u8 next_iwarp_state; 690 u8 curr_iwarp_state; 691 u8 termlen; 692 bool ord_valid:1; 693 bool tcp_ctx_valid:1; 694 bool udp_ctx_valid:1; 695 bool cq_num_valid:1; 696 bool arp_cache_idx_valid:1; 697 bool reset_tcp_conn:1; 698 bool remove_hash_idx:1; 699 bool dont_send_term:1; 700 bool dont_send_fin:1; 701 bool cached_var_valid:1; 702 bool mss_change:1; 703 bool force_lpb:1; 704 bool mac_valid:1; 705 }; 706 707 struct irdma_ccq_cqe_info { 708 struct irdma_sc_cqp *cqp; 709 u64 scratch; 710 u32 op_ret_val; 711 u16 maj_err_code; 712 u16 min_err_code; 713 u8 op_code; 714 bool error; 715 }; 716 717 struct irdma_qos_tc_info { 718 u64 tc_ctx; 719 u8 rel_bw; 720 u8 prio_type; 721 u8 egress_virt_up; 722 u8 ingress_virt_up; 723 }; 724 725 struct irdma_l2params { 726 struct irdma_qos_tc_info tc_info[IRDMA_MAX_USER_PRIORITY]; 727 u32 num_apps; 728 u16 qs_handle_list[IRDMA_MAX_USER_PRIORITY]; 729 u16 mtu; 730 u8 up2tc[IRDMA_MAX_USER_PRIORITY]; 731 u8 dscp_map[IRDMA_DSCP_NUM_VAL]; 732 u8 num_tc; 733 u8 vsi_rel_bw; 734 u8 vsi_prio_type; 735 bool mtu_changed:1; 736 bool tc_changed:1; 737 bool dscp_mode:1; 738 }; 739 740 struct irdma_vsi_init_info { 741 struct irdma_sc_dev *dev; 742 void *back_vsi; 743 struct irdma_l2params *params; 744 u16 exception_lan_q; 745 u16 pf_data_vsi_num; 746 enum irdma_vm_vf_type vm_vf_type; 747 int (*register_qset)(struct irdma_sc_vsi *vsi, 748 struct irdma_ws_node *tc_node); 749 void (*unregister_qset)(struct irdma_sc_vsi *vsi, 750 struct irdma_ws_node *tc_node); 751 }; 752 753 struct irdma_vsi_stats_info { 754 struct irdma_vsi_pestat *pestat; 755 u8 fcn_id; 756 bool alloc_stats_inst; 757 }; 758 759 struct irdma_device_init_info { 760 u64 fpm_query_buf_pa; 761 u64 fpm_commit_buf_pa; 762 __le64 *fpm_query_buf; 763 __le64 *fpm_commit_buf; 764 struct irdma_hw *hw; 765 void IOMEM *bar0; 766 u16 max_vfs; 767 u16 hmc_fn_id; 768 u32 debug_mask; 769 }; 770 771 struct irdma_ceq_init_info { 772 u64 ceqe_pa; 773 struct irdma_sc_dev *dev; 774 u64 *ceqe_base; 775 void *pbl_list; 776 u32 elem_cnt; 777 u32 ceq_id; 778 bool virtual_map:1; 779 bool tph_en:1; 780 bool itr_no_expire:1; 781 u8 pbl_chunk_size; 782 u8 tph_val; 783 u32 first_pm_pbl_idx; 784 struct irdma_sc_vsi *vsi; 785 struct irdma_sc_cq **reg_cq; 786 u32 reg_cq_idx; 787 }; 788 789 struct irdma_aeq_init_info { 790 u64 aeq_elem_pa; 791 struct irdma_sc_dev *dev; 792 u32 *aeqe_base; 793 void *pbl_list; 794 u32 elem_cnt; 795 bool virtual_map; 796 u8 pbl_chunk_size; 797 u32 first_pm_pbl_idx; 798 u32 msix_idx; 799 }; 800 801 struct irdma_ccq_init_info { 802 u64 cq_pa; 803 u64 shadow_area_pa; 804 struct irdma_sc_dev *dev; 805 struct irdma_cqe *cq_base; 806 __le64 *shadow_area; 807 void *pbl_list; 808 u32 num_elem; 809 u32 ceq_id; 810 u32 shadow_read_threshold; 811 bool ceqe_mask:1; 812 bool ceq_id_valid:1; 813 bool avoid_mem_cflct:1; 814 bool virtual_map:1; 815 bool tph_en:1; 816 u8 tph_val; 817 u8 pbl_chunk_size; 818 u32 first_pm_pbl_idx; 819 struct irdma_sc_vsi *vsi; 820 }; 821 822 struct irdma_udp_offload_info { 823 bool ipv4:1; 824 bool insert_vlan_tag:1; 825 u8 ttl; 826 u8 tos; 827 u16 src_port; 828 u16 dst_port; 829 u32 dest_ip_addr[4]; 830 u32 snd_mss; 831 u16 vlan_tag; 832 u16 arp_idx; 833 u32 flow_label; 834 u8 udp_state; 835 u32 psn_nxt; 836 u32 lsn; 837 u32 epsn; 838 u32 psn_max; 839 u32 psn_una; 840 u32 local_ipaddr[4]; 841 u32 cwnd; 842 u8 rexmit_thresh; 843 u8 rnr_nak_thresh; 844 }; 845 846 struct irdma_roce_offload_info { 847 u16 p_key; 848 u32 err_rq_idx; 849 u32 qkey; 850 u32 dest_qp; 851 u8 roce_tver; 852 u8 ack_credits; 853 u8 err_rq_idx_valid; 854 u32 pd_id; 855 u16 ord_size; 856 u16 ird_size; 857 bool is_qp1:1; 858 bool udprivcq_en:1; 859 bool dcqcn_en:1; 860 bool rcv_no_icrc:1; 861 bool wr_rdresp_en:1; 862 bool bind_en:1; 863 bool fast_reg_en:1; 864 bool priv_mode_en:1; 865 bool rd_en:1; 866 bool timely_en:1; 867 bool dctcp_en:1; 868 bool fw_cc_enable:1; 869 bool use_stats_inst:1; 870 u16 t_high; 871 u16 t_low; 872 u8 last_byte_sent; 873 u8 mac_addr[ETH_ALEN]; 874 u8 rtomin; 875 }; 876 877 struct irdma_iwarp_offload_info { 878 u16 rcv_mark_offset; 879 u16 snd_mark_offset; 880 u8 ddp_ver; 881 u8 rdmap_ver; 882 u8 iwarp_mode; 883 u32 err_rq_idx; 884 u32 pd_id; 885 u16 ord_size; 886 u16 ird_size; 887 bool ib_rd_en:1; 888 bool align_hdrs:1; 889 bool rcv_no_mpa_crc:1; 890 bool err_rq_idx_valid:1; 891 bool snd_mark_en:1; 892 bool rcv_mark_en:1; 893 bool wr_rdresp_en:1; 894 bool bind_en:1; 895 bool fast_reg_en:1; 896 bool priv_mode_en:1; 897 bool rd_en:1; 898 bool timely_en:1; 899 bool use_stats_inst:1; 900 bool ecn_en:1; 901 bool dctcp_en:1; 902 u16 t_high; 903 u16 t_low; 904 u8 last_byte_sent; 905 u8 mac_addr[ETH_ALEN]; 906 u8 rtomin; 907 }; 908 909 struct irdma_tcp_offload_info { 910 bool ipv4:1; 911 bool no_nagle:1; 912 bool insert_vlan_tag:1; 913 bool time_stamp:1; 914 bool drop_ooo_seg:1; 915 bool avoid_stretch_ack:1; 916 bool wscale:1; 917 bool ignore_tcp_opt:1; 918 bool ignore_tcp_uns_opt:1; 919 u8 cwnd_inc_limit; 920 u8 dup_ack_thresh; 921 u8 ttl; 922 u8 src_mac_addr_idx; 923 u8 tos; 924 u16 src_port; 925 u16 dst_port; 926 u32 dest_ip_addr[4]; 927 //u32 dest_ip_addr0; 928 //u32 dest_ip_addr1; 929 //u32 dest_ip_addr2; 930 //u32 dest_ip_addr3; 931 u32 snd_mss; 932 u16 syn_rst_handling; 933 u16 vlan_tag; 934 u16 arp_idx; 935 u32 flow_label; 936 u8 tcp_state; 937 u8 snd_wscale; 938 u8 rcv_wscale; 939 u32 time_stamp_recent; 940 u32 time_stamp_age; 941 u32 snd_nxt; 942 u32 snd_wnd; 943 u32 rcv_nxt; 944 u32 rcv_wnd; 945 u32 snd_max; 946 u32 snd_una; 947 u32 srtt; 948 u32 rtt_var; 949 u32 ss_thresh; 950 u32 cwnd; 951 u32 snd_wl1; 952 u32 snd_wl2; 953 u32 max_snd_window; 954 u8 rexmit_thresh; 955 u32 local_ipaddr[4]; 956 }; 957 958 struct irdma_qp_host_ctx_info { 959 u64 qp_compl_ctx; 960 union { 961 struct irdma_tcp_offload_info *tcp_info; 962 struct irdma_udp_offload_info *udp_info; 963 }; 964 union { 965 struct irdma_iwarp_offload_info *iwarp_info; 966 struct irdma_roce_offload_info *roce_info; 967 }; 968 u32 send_cq_num; 969 u32 rcv_cq_num; 970 u32 rem_endpoint_idx; 971 u16 stats_idx; 972 bool srq_valid:1; 973 bool tcp_info_valid:1; 974 bool iwarp_info_valid:1; 975 bool stats_idx_valid:1; 976 u8 user_pri; 977 }; 978 979 struct irdma_aeqe_info { 980 u64 compl_ctx; 981 u32 qp_cq_id; 982 u32 wqe_idx; 983 u16 ae_id; 984 u8 tcp_state; 985 u8 iwarp_state; 986 bool qp:1; 987 bool cq:1; 988 bool sq:1; 989 bool rq:1; 990 bool in_rdrsp_wr:1; 991 bool out_rdrsp:1; 992 bool aeqe_overflow:1; 993 u8 q2_data_written; 994 u8 ae_src; 995 }; 996 997 struct irdma_allocate_stag_info { 998 u64 total_len; 999 u64 first_pm_pbl_idx; 1000 u32 chunk_size; 1001 u32 stag_idx; 1002 u32 page_size; 1003 u32 pd_id; 1004 u16 access_rights; 1005 bool remote_access:1; 1006 bool use_hmc_fcn_index:1; 1007 bool use_pf_rid:1; 1008 bool all_memory:1; 1009 u16 hmc_fcn_index; 1010 }; 1011 1012 struct irdma_mw_alloc_info { 1013 u32 mw_stag_index; 1014 u32 page_size; 1015 u32 pd_id; 1016 bool remote_access:1; 1017 bool mw_wide:1; 1018 bool mw1_bind_dont_vldt_key:1; 1019 }; 1020 1021 struct irdma_reg_ns_stag_info { 1022 u64 reg_addr_pa; 1023 u64 va; 1024 u64 total_len; 1025 u32 page_size; 1026 u32 chunk_size; 1027 u32 first_pm_pbl_index; 1028 enum irdma_addressing_type addr_type; 1029 irdma_stag_index stag_idx; 1030 u16 access_rights; 1031 u32 pd_id; 1032 irdma_stag_key stag_key; 1033 bool use_hmc_fcn_index:1; 1034 u16 hmc_fcn_index; 1035 bool use_pf_rid:1; 1036 bool all_memory:1; 1037 }; 1038 1039 struct irdma_fast_reg_stag_info { 1040 u64 wr_id; 1041 u64 reg_addr_pa; 1042 u64 fbo; 1043 void *va; 1044 u64 total_len; 1045 u32 page_size; 1046 u32 chunk_size; 1047 u32 first_pm_pbl_index; 1048 enum irdma_addressing_type addr_type; 1049 irdma_stag_index stag_idx; 1050 u16 access_rights; 1051 u32 pd_id; 1052 irdma_stag_key stag_key; 1053 bool local_fence:1; 1054 bool read_fence:1; 1055 bool signaled:1; 1056 bool push_wqe:1; 1057 bool use_hmc_fcn_index:1; 1058 u16 hmc_fcn_index; 1059 bool use_pf_rid:1; 1060 bool defer_flag:1; 1061 }; 1062 1063 struct irdma_dealloc_stag_info { 1064 u32 stag_idx; 1065 u32 pd_id; 1066 bool mr:1; 1067 bool dealloc_pbl:1; 1068 }; 1069 1070 struct irdma_register_shared_stag { 1071 u64 va; 1072 enum irdma_addressing_type addr_type; 1073 irdma_stag_index new_stag_idx; 1074 irdma_stag_index parent_stag_idx; 1075 u32 access_rights; 1076 u32 pd_id; 1077 u32 page_size; 1078 irdma_stag_key new_stag_key; 1079 }; 1080 1081 struct irdma_qp_init_info { 1082 struct irdma_qp_uk_init_info qp_uk_init_info; 1083 struct irdma_sc_pd *pd; 1084 struct irdma_sc_vsi *vsi; 1085 __le64 *host_ctx; 1086 u8 *q2; 1087 u64 sq_pa; 1088 u64 rq_pa; 1089 u64 host_ctx_pa; 1090 u64 q2_pa; 1091 u64 shadow_area_pa; 1092 u8 sq_tph_val; 1093 u8 rq_tph_val; 1094 bool sq_tph_en:1; 1095 bool rq_tph_en:1; 1096 bool rcv_tph_en:1; 1097 bool xmit_tph_en:1; 1098 bool virtual_map:1; 1099 }; 1100 1101 struct irdma_cq_init_info { 1102 struct irdma_sc_dev *dev; 1103 u64 cq_base_pa; 1104 u64 shadow_area_pa; 1105 u32 ceq_id; 1106 u32 shadow_read_threshold; 1107 u8 pbl_chunk_size; 1108 u32 first_pm_pbl_idx; 1109 bool virtual_map:1; 1110 bool ceqe_mask:1; 1111 bool ceq_id_valid:1; 1112 bool tph_en:1; 1113 u8 tph_val; 1114 u8 type; 1115 struct irdma_cq_uk_init_info cq_uk_init_info; 1116 struct irdma_sc_vsi *vsi; 1117 }; 1118 1119 struct irdma_upload_context_info { 1120 u64 buf_pa; 1121 u32 qp_id; 1122 u8 qp_type; 1123 bool freeze_qp:1; 1124 bool raw_format:1; 1125 }; 1126 1127 struct irdma_local_mac_entry_info { 1128 u8 mac_addr[6]; 1129 u16 entry_idx; 1130 }; 1131 1132 struct irdma_add_arp_cache_entry_info { 1133 u8 mac_addr[ETH_ALEN]; 1134 u32 reach_max; 1135 u16 arp_index; 1136 bool permanent; 1137 }; 1138 1139 struct irdma_apbvt_info { 1140 u16 port; 1141 bool add; 1142 }; 1143 1144 struct irdma_qhash_table_info { 1145 struct irdma_sc_vsi *vsi; 1146 enum irdma_quad_hash_manage_type manage; 1147 enum irdma_quad_entry_type entry_type; 1148 bool vlan_valid:1; 1149 bool ipv4_valid:1; 1150 u8 mac_addr[ETH_ALEN]; 1151 u16 vlan_id; 1152 u8 user_pri; 1153 u32 qp_num; 1154 u32 dest_ip[4]; 1155 u32 src_ip[4]; 1156 u16 dest_port; 1157 u16 src_port; 1158 }; 1159 1160 struct irdma_cqp_manage_push_page_info { 1161 u32 push_idx; 1162 u16 qs_handle; 1163 u8 free_page; 1164 u8 push_page_type; 1165 }; 1166 1167 struct irdma_qp_flush_info { 1168 u16 sq_minor_code; 1169 u16 sq_major_code; 1170 u16 rq_minor_code; 1171 u16 rq_major_code; 1172 u16 ae_code; 1173 u8 ae_src; 1174 bool sq:1; 1175 bool rq:1; 1176 bool userflushcode:1; 1177 bool generate_ae:1; 1178 }; 1179 1180 struct irdma_gen_ae_info { 1181 u16 ae_code; 1182 u8 ae_src; 1183 }; 1184 1185 struct irdma_cqp_timeout { 1186 u64 compl_cqp_cmds; 1187 u32 count; 1188 }; 1189 1190 struct irdma_irq_ops { 1191 void (*irdma_cfg_aeq)(struct irdma_sc_dev *dev, u32 idx, bool enable); 1192 void (*irdma_cfg_ceq)(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx, 1193 bool enable); 1194 void (*irdma_dis_irq)(struct irdma_sc_dev *dev, u32 idx); 1195 void (*irdma_en_irq)(struct irdma_sc_dev *dev, u32 idx); 1196 }; 1197 1198 void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq); 1199 int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch, 1200 bool check_overflow, bool post_sq); 1201 int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq); 1202 int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq, 1203 struct irdma_ccq_cqe_info *info); 1204 int irdma_sc_ccq_init(struct irdma_sc_cq *ccq, 1205 struct irdma_ccq_init_info *info); 1206 1207 int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch); 1208 int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq); 1209 1210 int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq); 1211 int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq, 1212 struct irdma_ceq_init_info *info); 1213 void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq); 1214 void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq); 1215 1216 int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, 1217 struct irdma_aeq_init_info *info); 1218 int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, 1219 struct irdma_aeqe_info *info); 1220 int irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count); 1221 1222 void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id, 1223 int abi_ver); 1224 void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable); 1225 void irdma_check_cqp_progress(struct irdma_cqp_timeout *cqp_timeout, 1226 struct irdma_sc_dev *dev); 1227 int irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err); 1228 int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp, bool free_hwcqp); 1229 int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp, 1230 struct irdma_cqp_init_info *info); 1231 void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp); 1232 int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 opcode, 1233 struct irdma_ccq_cqe_info *cmpl_info); 1234 int irdma_sc_qp_create(struct irdma_sc_qp *qp, 1235 struct irdma_create_qp_info *info, u64 scratch, 1236 bool post_sq); 1237 int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch, 1238 bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq); 1239 int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp, 1240 struct irdma_qp_flush_info *info, u64 scratch, 1241 bool post_sq); 1242 int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info); 1243 int irdma_sc_qp_modify(struct irdma_sc_qp *qp, 1244 struct irdma_modify_qp_info *info, u64 scratch, 1245 bool post_sq); 1246 void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size, 1247 irdma_stag stag); 1248 void irdma_sc_send_lsmm_nostag(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size); 1249 void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read); 1250 void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx, 1251 struct irdma_qp_host_ctx_info *info); 1252 void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, 1253 struct irdma_qp_host_ctx_info *info); 1254 int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq); 1255 int irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info); 1256 void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info); 1257 int irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch, bool post_sq); 1258 int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch, 1259 u16 hmc_fn_id, bool post_sq, 1260 bool poll_registers); 1261 1262 void sc_vsi_update_stats(struct irdma_sc_vsi *vsi); 1263 struct cqp_info { 1264 union { 1265 struct { 1266 struct irdma_sc_qp *qp; 1267 struct irdma_create_qp_info info; 1268 u64 scratch; 1269 } qp_create; 1270 1271 struct { 1272 struct irdma_sc_qp *qp; 1273 struct irdma_modify_qp_info info; 1274 u64 scratch; 1275 } qp_modify; 1276 1277 struct { 1278 struct irdma_sc_qp *qp; 1279 u64 scratch; 1280 bool remove_hash_idx; 1281 bool ignore_mw_bnd; 1282 } qp_destroy; 1283 1284 struct { 1285 struct irdma_sc_cq *cq; 1286 u64 scratch; 1287 bool check_overflow; 1288 } cq_create; 1289 1290 struct { 1291 struct irdma_sc_cq *cq; 1292 struct irdma_modify_cq_info info; 1293 u64 scratch; 1294 } cq_modify; 1295 1296 struct { 1297 struct irdma_sc_cq *cq; 1298 u64 scratch; 1299 } cq_destroy; 1300 1301 struct { 1302 struct irdma_sc_dev *dev; 1303 struct irdma_allocate_stag_info info; 1304 u64 scratch; 1305 } alloc_stag; 1306 1307 struct { 1308 struct irdma_sc_dev *dev; 1309 struct irdma_mw_alloc_info info; 1310 u64 scratch; 1311 } mw_alloc; 1312 1313 struct { 1314 struct irdma_sc_dev *dev; 1315 struct irdma_reg_ns_stag_info info; 1316 u64 scratch; 1317 } mr_reg_non_shared; 1318 1319 struct { 1320 struct irdma_sc_dev *dev; 1321 struct irdma_dealloc_stag_info info; 1322 u64 scratch; 1323 } dealloc_stag; 1324 1325 struct { 1326 struct irdma_sc_cqp *cqp; 1327 struct irdma_add_arp_cache_entry_info info; 1328 u64 scratch; 1329 } add_arp_cache_entry; 1330 1331 struct { 1332 struct irdma_sc_cqp *cqp; 1333 u64 scratch; 1334 u16 arp_index; 1335 } del_arp_cache_entry; 1336 1337 struct { 1338 struct irdma_sc_cqp *cqp; 1339 struct irdma_local_mac_entry_info info; 1340 u64 scratch; 1341 } add_local_mac_entry; 1342 1343 struct { 1344 struct irdma_sc_cqp *cqp; 1345 u64 scratch; 1346 u8 entry_idx; 1347 u8 ignore_ref_count; 1348 } del_local_mac_entry; 1349 1350 struct { 1351 struct irdma_sc_cqp *cqp; 1352 u64 scratch; 1353 } alloc_local_mac_entry; 1354 1355 struct { 1356 struct irdma_sc_cqp *cqp; 1357 struct irdma_cqp_manage_push_page_info info; 1358 u64 scratch; 1359 } manage_push_page; 1360 1361 struct { 1362 struct irdma_sc_dev *dev; 1363 struct irdma_upload_context_info info; 1364 u64 scratch; 1365 } qp_upload_context; 1366 1367 struct { 1368 struct irdma_sc_dev *dev; 1369 struct irdma_hmc_fcn_info info; 1370 u64 scratch; 1371 } manage_hmc_pm; 1372 1373 struct { 1374 struct irdma_sc_ceq *ceq; 1375 u64 scratch; 1376 } ceq_create; 1377 1378 struct { 1379 struct irdma_sc_ceq *ceq; 1380 u64 scratch; 1381 } ceq_destroy; 1382 1383 struct { 1384 struct irdma_sc_aeq *aeq; 1385 u64 scratch; 1386 } aeq_create; 1387 1388 struct { 1389 struct irdma_sc_aeq *aeq; 1390 u64 scratch; 1391 } aeq_destroy; 1392 1393 struct { 1394 struct irdma_sc_qp *qp; 1395 struct irdma_qp_flush_info info; 1396 u64 scratch; 1397 } qp_flush_wqes; 1398 1399 struct { 1400 struct irdma_sc_qp *qp; 1401 struct irdma_gen_ae_info info; 1402 u64 scratch; 1403 } gen_ae; 1404 1405 struct { 1406 struct irdma_sc_cqp *cqp; 1407 void *fpm_val_va; 1408 u64 fpm_val_pa; 1409 u16 hmc_fn_id; 1410 u64 scratch; 1411 } query_fpm_val; 1412 1413 struct { 1414 struct irdma_sc_cqp *cqp; 1415 void *fpm_val_va; 1416 u64 fpm_val_pa; 1417 u16 hmc_fn_id; 1418 u64 scratch; 1419 } commit_fpm_val; 1420 1421 struct { 1422 struct irdma_sc_cqp *cqp; 1423 struct irdma_apbvt_info info; 1424 u64 scratch; 1425 } manage_apbvt_entry; 1426 1427 struct { 1428 struct irdma_sc_cqp *cqp; 1429 struct irdma_qhash_table_info info; 1430 u64 scratch; 1431 } manage_qhash_table_entry; 1432 1433 struct { 1434 struct irdma_sc_dev *dev; 1435 struct irdma_update_sds_info info; 1436 u64 scratch; 1437 } update_pe_sds; 1438 1439 struct { 1440 struct irdma_sc_cqp *cqp; 1441 struct irdma_sc_qp *qp; 1442 u64 scratch; 1443 } suspend_resume; 1444 1445 struct { 1446 struct irdma_sc_cqp *cqp; 1447 struct irdma_ah_info info; 1448 u64 scratch; 1449 } ah_create; 1450 1451 struct { 1452 struct irdma_sc_cqp *cqp; 1453 struct irdma_ah_info info; 1454 u64 scratch; 1455 } ah_destroy; 1456 1457 struct { 1458 struct irdma_sc_cqp *cqp; 1459 struct irdma_mcast_grp_info info; 1460 u64 scratch; 1461 } mc_create; 1462 1463 struct { 1464 struct irdma_sc_cqp *cqp; 1465 struct irdma_mcast_grp_info info; 1466 u64 scratch; 1467 } mc_destroy; 1468 1469 struct { 1470 struct irdma_sc_cqp *cqp; 1471 struct irdma_mcast_grp_info info; 1472 u64 scratch; 1473 } mc_modify; 1474 1475 struct { 1476 struct irdma_sc_cqp *cqp; 1477 struct irdma_stats_inst_info info; 1478 u64 scratch; 1479 } stats_manage; 1480 1481 struct { 1482 struct irdma_sc_cqp *cqp; 1483 struct irdma_stats_gather_info info; 1484 u64 scratch; 1485 } stats_gather; 1486 1487 struct { 1488 struct irdma_sc_cqp *cqp; 1489 struct irdma_ws_node_info info; 1490 u64 scratch; 1491 } ws_node; 1492 1493 struct { 1494 struct irdma_sc_cqp *cqp; 1495 struct irdma_up_info info; 1496 u64 scratch; 1497 } up_map; 1498 1499 struct { 1500 struct irdma_sc_cqp *cqp; 1501 struct irdma_dma_mem query_buff_mem; 1502 u64 scratch; 1503 } query_rdma; 1504 } u; 1505 }; 1506 1507 struct cqp_cmds_info { 1508 struct list_head cqp_cmd_entry; 1509 u8 cqp_cmd; 1510 u8 post_sq; 1511 struct cqp_info in; 1512 }; 1513 1514 __le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch, 1515 u32 *wqe_idx); 1516 1517 /** 1518 * irdma_sc_cqp_get_next_send_wqe - get next wqe on cqp sq 1519 * @cqp: struct for cqp hw 1520 * @scratch: private data for CQP WQE 1521 */ 1522 static inline __le64 *irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp *cqp, u64 scratch) 1523 { 1524 u32 wqe_idx; 1525 1526 return irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); 1527 } 1528 #endif /* IRDMA_TYPE_H */ 1529