1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 23 * The full GNU General Public License is included in this distribution 24 * in the file called LICENSE.GPL. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 * $FreeBSD$ 55 */ 56 #ifndef _SCIC_SDS_CONTROLLER_H_ 57 #define _SCIC_SDS_CONTROLLER_H_ 58 59 /** 60 * @file 61 * 62 * @brief This file contains the structures, constants and prototypes used for 63 * the core controller object. 64 */ 65 66 #ifdef __cplusplus 67 extern "C" { 68 #endif // __cplusplus 69 70 #include <dev/isci/scil/sci_pool.h> 71 #include <dev/isci/scil/sci_controller_constants.h> 72 #include <dev/isci/scil/sci_memory_descriptor_list.h> 73 #include <dev/isci/scil/sci_base_controller.h> 74 #include <dev/isci/scil/scic_config_parameters.h> 75 #include <dev/isci/scil/scic_sds_port.h> 76 #include <dev/isci/scil/scic_sds_phy.h> 77 #include <dev/isci/scil/scic_sds_remote_node_table.h> 78 #include <dev/isci/scil/scu_registers.h> 79 #include <dev/isci/scil/scu_constants.h> 80 #include <dev/isci/scil/scu_remote_node_context.h> 81 #include <dev/isci/scil/scu_task_context.h> 82 #include <dev/isci/scil/scu_unsolicited_frame.h> 83 #include <dev/isci/scil/scic_sds_unsolicited_frame_control.h> 84 #include <dev/isci/scil/scic_sds_port_configuration_agent.h> 85 #include <dev/isci/scil/scic_sds_pci.h> 86 87 struct SCIC_SDS_REMOTE_DEVICE; 88 struct SCIC_SDS_REQUEST; 89 90 91 #define SCU_COMPLETION_RAM_ALIGNMENT (64) 92 93 /** 94 * @enum SCIC_SDS_CONTROLLER_MEMORY_DESCRIPTORS 95 * 96 * This enumeration depects the types of MDEs that are going to be created for 97 * the controller object. 98 */ 99 enum SCIC_SDS_CONTROLLER_MEMORY_DESCRIPTORS 100 { 101 /** 102 * Completion queue MDE entry 103 */ 104 SCU_MDE_COMPLETION_QUEUE, 105 106 /** 107 * Remote node context MDE entry 108 */ 109 SCU_MDE_REMOTE_NODE_CONTEXT, 110 111 /** 112 * Task context MDE entry 113 */ 114 SCU_MDE_TASK_CONTEXT, 115 116 /** 117 * Unsolicited frame buffer MDE entrys this is the start of the unsolicited 118 * frame buffer entries. 119 */ 120 SCU_MDE_UF_BUFFER, 121 122 SCU_MAX_MDES 123 }; 124 125 /** 126 * @struct SCIC_POWER_CONTROL 127 * 128 * This structure defines the fields for managing power control for direct 129 * attached disk devices. 130 */ 131 typedef struct SCIC_POWER_CONTROL 132 { 133 /** 134 * This field is set when the power control timer is running and cleared when 135 * it is not. 136 */ 137 BOOL timer_started; 138 139 /** 140 * This field is the handle to the driver timer object. This timer is used to 141 * control when the directed attached disks can consume power. 142 */ 143 void *timer; 144 145 /** 146 * This field is used to keep track of how many phys are put into the 147 * requesters field. 148 */ 149 U8 phys_waiting; 150 151 /** 152 * This field is used to keep track of how many remote devices have been granted to consume power 153 */ 154 U8 remote_devices_granted_power; 155 156 /** 157 * This field is an array of phys that we are waiting on. The phys are direct 158 * mapped into requesters via SCIC_SDS_PHY_T.phy_index 159 */ 160 SCIC_SDS_PHY_T *requesters[SCI_MAX_PHYS]; 161 162 } SCIC_POWER_CONTROL_T; 163 164 /** 165 * @struct SCIC_SDS_CONTROLLER 166 * 167 * This structure represents the SCU contoller object. 168 */ 169 typedef struct SCIC_SDS_CONTROLLER 170 { 171 /** 172 * The SCI_BASE_CONTROLLER is the parent object for the SCIC_SDS_CONTROLLER 173 * object. 174 */ 175 SCI_BASE_CONTROLLER_T parent; 176 177 /** 178 * This field is the driver timer object handler used to time the controller 179 * object start and stop requests. 180 */ 181 void *timeout_timer; 182 183 /** 184 * This field is the current set of state handlers assigned to this controller 185 * object. 186 */ 187 struct SCIC_SDS_CONTROLLER_STATE_HANDLER *state_handlers; 188 189 /** 190 * This field contains the user parameters to be utilized for this 191 * core controller object. 192 */ 193 SCIC_USER_PARAMETERS_T user_parameters; 194 195 /** 196 * This field contains the OEM parameters version defining the structure 197 * layout. It comes from the version in the OEM block header. 198 */ 199 U8 oem_parameters_version; 200 201 /** 202 * This field contains the OEM parameters to be utilized for this 203 * core controller object. 204 */ 205 SCIC_OEM_PARAMETERS_T oem_parameters; 206 207 /** 208 * This field contains the port configuration agent for this controller. 209 */ 210 SCIC_SDS_PORT_CONFIGURATION_AGENT_T port_agent; 211 212 /** 213 * This field is the array of port objects that are controlled by this 214 * controller object. There is one dummy port object also contained within 215 * this controller object. 216 */ 217 struct SCIC_SDS_PORT port_table[SCI_MAX_PORTS + 1]; 218 219 /** 220 * This field is the array of phy objects that are controlled by this 221 * controller object. 222 */ 223 struct SCIC_SDS_PHY phy_table[SCI_MAX_PHYS]; 224 225 /** 226 * This field is the array of device objects that are currently constructed 227 * for this controller object. This table is used as a fast lookup of device 228 * objects that need to handle device completion notifications from the 229 * hardware. The table is RNi based. 230 */ 231 struct SCIC_SDS_REMOTE_DEVICE *device_table[SCI_MAX_REMOTE_DEVICES]; 232 233 /** 234 * This field is the array of IO request objects that are currently active for 235 * this controller object. This table is used as a fast lookup of the io 236 * request object that need to handle completion queue notifications. The 237 * table is TCi based. 238 */ 239 struct SCIC_SDS_REQUEST *io_request_table[SCI_MAX_IO_REQUESTS]; 240 241 /** 242 * This field is the free RNi data structure 243 */ 244 SCIC_REMOTE_NODE_TABLE_T available_remote_nodes; 245 246 /** 247 * This field is the TCi pool used to manage the task context index. 248 */ 249 SCI_POOL_CREATE(tci_pool, U16, SCI_MAX_IO_REQUESTS); 250 251 /** 252 * This filed is the SCIC_POWER_CONTROL data used to control when direct 253 * attached devices can consume power. 254 */ 255 SCIC_POWER_CONTROL_T power_control; 256 257 /** 258 * This field is the array of sequence values for the IO Tag fields. Even 259 * though only 4 bits of the field is used for the sequence the sequence is 16 260 * bits in size so the sequence can be bitwise or'd with the TCi to build the 261 * IO Tag value. 262 */ 263 U16 io_request_sequence[SCI_MAX_IO_REQUESTS]; 264 265 /** 266 * This field in the array of sequence values for the RNi. These are used 267 * to control io request build to io request start operations. The sequence 268 * value is recorded into an io request when it is built and is checked on 269 * the io request start operation to make sure that there was not a device 270 * hot plug between the build and start operation. 271 */ 272 U8 remote_device_sequence[SCI_MAX_REMOTE_DEVICES]; 273 274 /** 275 * This field is a pointer to the memory allocated by the driver for the task 276 * context table. This data is shared between the hardware and software. 277 */ 278 SCU_TASK_CONTEXT_T *task_context_table; 279 280 /** 281 * This field is a pointer to the memory allocated by the driver for the 282 * remote node context table. This table is shared between the hardware and 283 * software. 284 */ 285 SCU_REMOTE_NODE_CONTEXT_T *remote_node_context_table; 286 287 /** 288 * This field is the array of physical memory requiremets for this controller 289 * object. 290 */ 291 SCI_PHYSICAL_MEMORY_DESCRIPTOR_T memory_descriptors[SCU_MAX_MDES]; 292 293 /** 294 * This field is a pointer to the completion queue. This memory is 295 * written to by the hardware and read by the software. 296 */ 297 U32 *completion_queue; 298 299 /** 300 * This field is the software copy of the completion queue get pointer. The 301 * controller object writes this value to the hardware after processing the 302 * completion entries. 303 */ 304 U32 completion_queue_get; 305 306 /** 307 * This field is the minimum of the number of hardware supported port entries 308 * and the software requested port entries. 309 */ 310 U32 logical_port_entries; 311 312 /** 313 * This field is the minimum number of hardware supported completion queue 314 * entries and the software requested completion queue entries. 315 */ 316 U32 completion_queue_entries; 317 318 /** 319 * This field is the minimum number of hardware supported event entries and 320 * the software requested event entries. 321 */ 322 U32 completion_event_entries; 323 324 /** 325 * This field is the minimum number of devices supported by the hardware and 326 * the number of devices requested by the software. 327 */ 328 U32 remote_node_entries; 329 330 /** 331 * This field is the minimum number of IO requests supported by the hardware 332 * and the number of IO requests requested by the software. 333 */ 334 U32 task_context_entries; 335 336 /** 337 * This object contains all of the unsolicited frame specific 338 * data utilized by the core controller. 339 */ 340 SCIC_SDS_UNSOLICITED_FRAME_CONTROL_T uf_control; 341 342 /** 343 * This field records the fact that the controller has encountered a fatal 344 * error and must be reset. 345 */ 346 BOOL encountered_fatal_error; 347 348 /** 349 * This field specifies that the controller should ignore 350 * completion processing for non-fastpath events. This will 351 * cause the completions to be thrown away. 352 */ 353 BOOL restrict_completions; 354 355 // Phy Startup Data 356 /** 357 * This field is the driver timer handle for controller phy request startup. 358 * On controller start the controller will start each PHY individually in 359 * order of phy index. 360 */ 361 void *phy_startup_timer; 362 363 /** 364 * This field is set when the phy_startup_timer is running and is cleared when 365 * the phy_startup_timer is stopped. 366 */ 367 BOOL phy_startup_timer_pending; 368 369 /** 370 * This field is the index of the next phy start. It is initialized to 0 and 371 * increments for each phy index that is started. 372 */ 373 U32 next_phy_to_start; 374 375 /** 376 * This field controls the invalid link up notifications to the SCI_USER. If 377 * an invalid_link_up notification is reported a bit for the PHY index is set 378 * so further notifications are not made. Once the PHY object reports link up 379 * and is made part of a port then this bit for the PHY index is cleared. 380 */ 381 U8 invalid_phy_mask; 382 383 /** 384 * This is the controller index for this controller object. 385 */ 386 U8 controller_index; 387 388 /** 389 * This field is the PCI revision code for the controller object. 390 */ 391 enum SCU_CONTROLLER_PCI_REVISION_CODE pci_revision; 392 393 /* 394 * This field saves the current interrupt coalescing number of the controller. 395 */ 396 U16 interrupt_coalesce_number; 397 398 /* 399 * This field saves the current interrupt coalescing timeout value in microseconds. 400 */ 401 U32 interrupt_coalesce_timeout; 402 403 // Hardware memory mapped register space 404 #ifdef ARLINGTON_BUILD 405 /** 406 * This field is a pointer to the memory mapped register space for the 407 * LEX_REGISTERS. 408 */ 409 LEX_REGISTERS_T *lex_registers; 410 #endif 411 412 /** 413 * This field is a pointer to the memory mapped register space for the 414 * SMU_REGISTERS. 415 */ 416 SMU_REGISTERS_T *smu_registers; 417 418 /** 419 * This field is a pointer to the memory mapped register space for the 420 * SCU_REGISTERS. 421 */ 422 SCU_REGISTERS_T *scu_registers; 423 424 } SCIC_SDS_CONTROLLER_T; 425 426 427 typedef void (*SCIC_SDS_CONTROLLER_PHY_HANDLER_T)( 428 struct SCIC_SDS_CONTROLLER *controller, 429 struct SCIC_SDS_PORT *port, 430 struct SCIC_SDS_PHY *phy 431 ); 432 433 typedef void (*SCIC_SDS_CONTROLLER_DEVICE_HANDLER_T)( 434 struct SCIC_SDS_CONTROLLER * controller, 435 struct SCIC_SDS_REMOTE_DEVICE * device 436 ); 437 /** 438 * @struct SCIC_SDS_CONTROLLER_STATE_HANDLER 439 * 440 * This structure contains the SDS core specific definition for the state 441 * handlers. 442 */ 443 typedef struct SCIC_SDS_CONTROLLER_STATE_HANDLER 444 { 445 SCI_BASE_CONTROLLER_STATE_HANDLER_T parent; 446 447 SCI_BASE_CONTROLLER_REQUEST_HANDLER_T terminate_request_handler; 448 SCIC_SDS_CONTROLLER_PHY_HANDLER_T link_up_handler; 449 SCIC_SDS_CONTROLLER_PHY_HANDLER_T link_down_handler; 450 SCIC_SDS_CONTROLLER_DEVICE_HANDLER_T remote_device_started_handler; 451 SCIC_SDS_CONTROLLER_DEVICE_HANDLER_T remote_device_stopped_handler; 452 453 } SCIC_SDS_CONTROLLER_STATE_HANDLER_T; 454 455 extern SCIC_SDS_CONTROLLER_STATE_HANDLER_T 456 scic_sds_controller_state_handler_table[]; 457 extern SCI_BASE_STATE_T scic_sds_controller_state_table[]; 458 459 /** 460 * This macro will increment the specified index to and if the index wraps 461 * to 0 it will toggel the cycle bit. 462 */ 463 #define INCREMENT_QUEUE_GET(index, cycle, entry_count, bit_toggle) \ 464 { \ 465 if ((index) + 1 == entry_count) \ 466 { \ 467 (index) = 0; \ 468 (cycle) = (cycle) ^ (bit_toggle); \ 469 } \ 470 else \ 471 { \ 472 index = index + 1; \ 473 } \ 474 } 475 476 /** 477 * This is a helper macro that sets the state handlers for the controller 478 * object 479 */ 480 #define scic_sds_controller_set_state_handlers(this_controller, handlers) \ 481 ((this_controller)->state_handlers = (handlers)) 482 483 /** 484 * This is a helper macro that gets the base state machine for the 485 * controller object 486 */ 487 #define scic_sds_controller_get_base_state_machine(this_contoroller) \ 488 (&(this_controller)->parent.state_machine) 489 490 /** 491 * This is a helper macro to get the port configuration agent from the 492 * controller object. 493 */ 494 #define scic_sds_controller_get_port_configuration_agent(controller) \ 495 (&(controller)->port_agent) 496 497 /** 498 * This is a helper macro that sets the base state machine state handlers 499 * based on the state id 500 */ 501 #define scic_sds_controller_set_base_state_handlers(this_controller, state_id) \ 502 scic_sds_controller_set_state_handlers( \ 503 this_controller, &scic_sds_controller_state_handler_table[(state_id)]) 504 505 /** 506 * This macro writes to the smu_register for this controller 507 */ 508 #define smu_register_write(controller, reg, value) \ 509 scic_sds_pci_write_smu_dword((controller), &(reg), (value)) 510 511 /** 512 * This macro reads the smu_register for this controller 513 */ 514 #define smu_register_read(controller, reg) \ 515 scic_sds_pci_read_smu_dword((controller), &(reg)) 516 517 /** 518 * This mcaro writes the scu_register for this controller 519 */ 520 #define scu_register_write(controller, reg, value) \ 521 scic_sds_pci_write_scu_dword((controller), &(reg), (value)) 522 523 /** 524 * This macro reads the scu_register for this controller 525 */ 526 #define scu_register_read(controller, reg) \ 527 scic_sds_pci_read_scu_dword((controller), &(reg)) 528 529 #ifdef ARLINGTON_BUILD 530 /** 531 * This macro writes to the lex_register for this controller. 532 */ 533 #define lex_register_write(controller, reg, value) \ 534 scic_cb_pci_write_dword((controller), (reg), (value)) 535 536 /** 537 * This macro reads from the lex_register for this controller. 538 */ 539 #define lex_register_read(controller, reg) \ 540 scic_cb_pci_read_dword((controller), (reg)) 541 #endif // ARLINGTON_BUILD 542 543 /** 544 * This macro returns the protocol engine group for this controller object. 545 * Presently we only support protocol engine group 0 so just return that 546 */ 547 #define scic_sds_controller_get_protocol_engine_group(controller) 0 548 549 /** 550 * This macro constructs an IO tag from the sequence and index values. 551 */ 552 #define scic_sds_io_tag_construct(sequence, task_index) \ 553 ((sequence) << 12 | (task_index)) 554 555 /** 556 * This macro returns the IO sequence from the IO tag value. 557 */ 558 #define scic_sds_io_tag_get_sequence(io_tag) \ 559 (((io_tag) & 0xF000) >> 12) 560 561 /** 562 * This macro returns the TCi from the io tag value 563 */ 564 #define scic_sds_io_tag_get_index(io_tag) \ 565 ((io_tag) & 0x0FFF) 566 567 /** 568 * This is a helper macro to increment the io sequence count. 569 * 570 * We may find in the future that it will be faster to store the sequence 571 * count in such a way as we dont perform the shift operation to build io 572 * tag values so therefore need a way to incrment them correctly 573 */ 574 #define scic_sds_io_sequence_increment(value) \ 575 ((value) = (((value) + 1) & 0x000F)) 576 577 #define scic_sds_remote_device_node_count(device) \ 578 ( \ 579 ( \ 580 (device)->target_protocols.u.bits.attached_stp_target \ 581 && ((device)->is_direct_attached != TRUE) \ 582 ) \ 583 ? SCU_STP_REMOTE_NODE_COUNT : SCU_SSP_REMOTE_NODE_COUNT \ 584 ) 585 586 /** 587 * This macro will set the bit in the invalid phy mask for this controller 588 * object. This is used to control messages reported for invalid link up 589 * notifications. 590 */ 591 #define scic_sds_controller_set_invalid_phy(controller, phy) \ 592 ((controller)->invalid_phy_mask |= (1 << (phy)->phy_index)) 593 594 /** 595 * This macro will clear the bit in the invalid phy mask for this controller 596 * object. This is used to control messages reported for invalid link up 597 * notifications. 598 */ 599 #define scic_sds_controller_clear_invalid_phy(controller, phy) \ 600 ((controller)->invalid_phy_mask &= ~(1 << (phy)->phy_index)) 601 602 // --------------------------------------------------------------------------- 603 604 U32 scic_sds_controller_get_object_size(void); 605 606 // --------------------------------------------------------------------------- 607 608 U32 scic_sds_controller_get_min_timer_count(void); 609 U32 scic_sds_controller_get_max_timer_count(void); 610 611 // --------------------------------------------------------------------------- 612 613 void scic_sds_controller_post_request( 614 SCIC_SDS_CONTROLLER_T *this_controller, 615 U32 request 616 ); 617 618 // --------------------------------------------------------------------------- 619 620 void scic_sds_controller_release_frame( 621 SCIC_SDS_CONTROLLER_T *this_controller, 622 U32 frame_index 623 ); 624 625 void scic_sds_controller_copy_sata_response( 626 void * response_buffer, 627 void * frame_header, 628 void * frame_buffer 629 ); 630 631 // --------------------------------------------------------------------------- 632 633 SCI_STATUS scic_sds_controller_allocate_remote_node_context( 634 SCIC_SDS_CONTROLLER_T *this_controller, 635 struct SCIC_SDS_REMOTE_DEVICE *the_device, 636 U16 *node_id 637 ); 638 639 void scic_sds_controller_free_remote_node_context( 640 SCIC_SDS_CONTROLLER_T *this_controller, 641 struct SCIC_SDS_REMOTE_DEVICE *the_device, 642 U16 node_id 643 ); 644 645 SCU_REMOTE_NODE_CONTEXT_T *scic_sds_controller_get_remote_node_context_buffer( 646 SCIC_SDS_CONTROLLER_T *this_controller, 647 U16 node_id 648 ); 649 650 // --------------------------------------------------------------------------- 651 652 struct SCIC_SDS_REQUEST *scic_sds_controller_get_io_request_from_tag( 653 SCIC_SDS_CONTROLLER_T *this_controller, 654 U16 io_tag 655 ); 656 657 U16 scic_sds_controller_get_io_sequence_from_tag( 658 SCIC_SDS_CONTROLLER_T *this_controller, 659 U16 io_tag 660 ); 661 662 SCU_TASK_CONTEXT_T *scic_sds_controller_get_task_context_buffer( 663 SCIC_SDS_CONTROLLER_T *this_controller, 664 U16 io_tag 665 ); 666 667 //----------------------------------------------------------------------------- 668 669 SCI_STATUS scic_sds_terminate_reqests( 670 SCIC_SDS_CONTROLLER_T *this_controller, 671 struct SCIC_SDS_REMOTE_DEVICE *this_remote_device, 672 struct SCIC_SDS_PORT *this_port 673 ); 674 675 //***************************************************************************** 676 //* CORE CONTROLLER POWER CONTROL METHODS 677 //***************************************************************************** 678 679 void scic_sds_controller_power_control_timer_handler( 680 void *controller 681 ); 682 683 void scic_sds_controller_power_control_queue_insert( 684 SCIC_SDS_CONTROLLER_T *this_controller, 685 struct SCIC_SDS_PHY *the_phy 686 ); 687 688 void scic_sds_controller_power_control_queue_remove( 689 SCIC_SDS_CONTROLLER_T *this_controller, 690 struct SCIC_SDS_PHY *the_phy 691 ); 692 693 //***************************************************************************** 694 //* CORE CONTROLLER PHY MESSAGE PROCESSING 695 //***************************************************************************** 696 697 void scic_sds_controller_link_up( 698 SCIC_SDS_CONTROLLER_T *this_controller, 699 struct SCIC_SDS_PORT *the_port, 700 struct SCIC_SDS_PHY *the_phy 701 ); 702 703 void scic_sds_controller_link_down( 704 SCIC_SDS_CONTROLLER_T *this_controller, 705 struct SCIC_SDS_PORT *the_port, 706 struct SCIC_SDS_PHY *the_phy 707 ); 708 709 //***************************************************************************** 710 //* CORE CONTROLLER PORT AGENT MESSAGE PROCESSING 711 //***************************************************************************** 712 void scic_sds_controller_port_agent_configured_ports( 713 SCIC_SDS_CONTROLLER_T * this_controller 714 ); 715 716 //***************************************************************************** 717 //* CORE CONTROLLER REMOTE DEVICE MESSAGE PROCESSING 718 //***************************************************************************** 719 720 BOOL scic_sds_controller_has_remote_devices_stopping( 721 SCIC_SDS_CONTROLLER_T * this_controller 722 ); 723 724 void scic_sds_controller_remote_device_started( 725 SCIC_SDS_CONTROLLER_T * this_controller, 726 struct SCIC_SDS_REMOTE_DEVICE * the_device 727 ); 728 729 void scic_sds_controller_remote_device_stopped( 730 SCIC_SDS_CONTROLLER_T * this_controller, 731 struct SCIC_SDS_REMOTE_DEVICE * the_device 732 ); 733 734 //***************************************************************************** 735 //* CORE CONTROLLER PRIVATE METHODS 736 //***************************************************************************** 737 738 #ifdef SCI_LOGGING 739 void scic_sds_controller_initialize_state_logging( 740 SCIC_SDS_CONTROLLER_T *this_controller 741 ); 742 743 void scic_sds_controller_deinitialize_state_logging( 744 SCIC_SDS_CONTROLLER_T *this_controller 745 ); 746 #else 747 #define scic_sds_controller_initialize_state_logging(x) 748 #define scic_sds_controller_deinitialize_state_logging(x) 749 #endif 750 751 SCI_STATUS scic_sds_controller_validate_memory_descriptor_table( 752 SCIC_SDS_CONTROLLER_T *this_controller 753 ); 754 755 void scic_sds_controller_ram_initialization( 756 SCIC_SDS_CONTROLLER_T *this_controller 757 ); 758 759 void scic_sds_controller_assign_task_entries( 760 SCIC_SDS_CONTROLLER_T *this_controller 761 ); 762 763 void scic_sds_controller_afe_initialization( 764 SCIC_SDS_CONTROLLER_T * this_controller 765 ); 766 767 void scic_sds_controller_enable_port_task_scheduler( 768 SCIC_SDS_CONTROLLER_T *this_controller 769 ); 770 771 void scic_sds_controller_initialize_completion_queue( 772 SCIC_SDS_CONTROLLER_T *this_controller 773 ); 774 775 void scic_sds_controller_initialize_unsolicited_frame_queue( 776 SCIC_SDS_CONTROLLER_T *this_controller 777 ); 778 779 void scic_sds_controller_phy_timer_stop( 780 SCIC_SDS_CONTROLLER_T *this_controller 781 ); 782 783 BOOL scic_sds_controller_is_start_complete( 784 SCIC_SDS_CONTROLLER_T *this_controller 785 ); 786 787 SCI_STATUS scic_sds_controller_start_next_phy( 788 SCIC_SDS_CONTROLLER_T *this_controller 789 ); 790 791 SCI_STATUS scic_sds_controller_stop_phys( 792 SCIC_SDS_CONTROLLER_T *this_controller 793 ); 794 795 SCI_STATUS scic_sds_controller_stop_ports( 796 SCIC_SDS_CONTROLLER_T *this_controller 797 ); 798 799 SCI_STATUS scic_sds_controller_stop_devices( 800 SCIC_SDS_CONTROLLER_T *this_controller 801 ); 802 803 void scic_sds_controller_copy_task_context( 804 SCIC_SDS_CONTROLLER_T *this_controller, 805 struct SCIC_SDS_REQUEST *this_request 806 ); 807 808 void scic_sds_controller_timeout_handler( 809 SCI_CONTROLLER_HANDLE_T controller 810 ); 811 812 void scic_sds_controller_initialize_power_control( 813 SCIC_SDS_CONTROLLER_T *this_controller 814 ); 815 816 void scic_sds_controller_register_setup( 817 SCIC_SDS_CONTROLLER_T *this_controller 818 ); 819 820 void scic_sds_controller_reset_hardware( 821 SCIC_SDS_CONTROLLER_T * this_controller 822 ); 823 824 #ifdef ARLINGTON_BUILD 825 void scic_sds_controller_lex_atux_initialization( 826 SCIC_SDS_CONTROLLER_T *this_controller 827 ); 828 829 void scic_sds_controller_enable_chipwatch( 830 SCIC_SDS_CONTROLLER_T *this_controller 831 ); 832 #endif // ARLINGTON_BUILD 833 834 void scic_sds_controller_build_memory_descriptor_table( 835 SCIC_SDS_CONTROLLER_T *this_controller 836 ); 837 838 #ifdef __cplusplus 839 } 840 #endif // __cplusplus 841 842 #endif // _SCIC_SDS_CONTROLLER_H_ 843