1f11c7f63SJim Harris /*- 2718cf2ccSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3718cf2ccSPedro F. Giffuni * 4f11c7f63SJim Harris * This file is provided under a dual BSD/GPLv2 license. When using or 5f11c7f63SJim Harris * redistributing this file, you may do so under either license. 6f11c7f63SJim Harris * 7f11c7f63SJim Harris * GPL LICENSE SUMMARY 8f11c7f63SJim Harris * 9f11c7f63SJim Harris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 10f11c7f63SJim Harris * 11f11c7f63SJim Harris * This program is free software; you can redistribute it and/or modify 12f11c7f63SJim Harris * it under the terms of version 2 of the GNU General Public License as 13f11c7f63SJim Harris * published by the Free Software Foundation. 14f11c7f63SJim Harris * 15f11c7f63SJim Harris * This program is distributed in the hope that it will be useful, but 16f11c7f63SJim Harris * WITHOUT ANY WARRANTY; without even the implied warranty of 17f11c7f63SJim Harris * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18f11c7f63SJim Harris * General Public License for more details. 19f11c7f63SJim Harris * 20f11c7f63SJim Harris * You should have received a copy of the GNU General Public License 21f11c7f63SJim Harris * along with this program; if not, write to the Free Software 22f11c7f63SJim Harris * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 23f11c7f63SJim Harris * The full GNU General Public License is included in this distribution 24f11c7f63SJim Harris * in the file called LICENSE.GPL. 25f11c7f63SJim Harris * 26f11c7f63SJim Harris * BSD LICENSE 27f11c7f63SJim Harris * 28f11c7f63SJim Harris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 29f11c7f63SJim Harris * All rights reserved. 30f11c7f63SJim Harris * 31f11c7f63SJim Harris * Redistribution and use in source and binary forms, with or without 32f11c7f63SJim Harris * modification, are permitted provided that the following conditions 33f11c7f63SJim Harris * are met: 34f11c7f63SJim Harris * 35f11c7f63SJim Harris * * Redistributions of source code must retain the above copyright 36f11c7f63SJim Harris * notice, this list of conditions and the following disclaimer. 37f11c7f63SJim Harris * * Redistributions in binary form must reproduce the above copyright 38f11c7f63SJim Harris * notice, this list of conditions and the following disclaimer in 39f11c7f63SJim Harris * the documentation and/or other materials provided with the 40f11c7f63SJim Harris * distribution. 41f11c7f63SJim Harris * 42f11c7f63SJim Harris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43f11c7f63SJim Harris * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44f11c7f63SJim Harris * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45f11c7f63SJim Harris * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46f11c7f63SJim Harris * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47f11c7f63SJim Harris * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48f11c7f63SJim Harris * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49f11c7f63SJim Harris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50f11c7f63SJim Harris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51f11c7f63SJim Harris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52f11c7f63SJim Harris * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53f11c7f63SJim Harris */ 54f11c7f63SJim Harris #ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_ 55f11c7f63SJim Harris #define _SCIC_SDS_CONTROLLER_REGISTERS_H_ 56f11c7f63SJim Harris 57f11c7f63SJim Harris /** 58f11c7f63SJim Harris * @file 59f11c7f63SJim Harris * 60f11c7f63SJim Harris * @brief This file contains macros used to perform the register reads/writes 61f11c7f63SJim Harris * to the SCU hardware. 62f11c7f63SJim Harris */ 63f11c7f63SJim Harris 64f11c7f63SJim Harris #ifdef __cplusplus 65f11c7f63SJim Harris extern "C" { 66f11c7f63SJim Harris #endif // __cplusplus 67f11c7f63SJim Harris 68f11c7f63SJim Harris #include <dev/isci/scil/scu_registers.h> 69f11c7f63SJim Harris #include <dev/isci/scil/scic_sds_controller.h> 70f11c7f63SJim Harris 71f11c7f63SJim Harris /** 72f11c7f63SJim Harris * @name SMU_REGISTER_ACCESS_MACROS 73f11c7f63SJim Harris */ 74f11c7f63SJim Harris /*@{*/ 75f11c7f63SJim Harris #define scic_sds_controller_smu_register_read(controller, reg) \ 76f11c7f63SJim Harris smu_register_read( \ 77f11c7f63SJim Harris (controller), \ 78f11c7f63SJim Harris (controller)->smu_registers->reg \ 79f11c7f63SJim Harris ) 80f11c7f63SJim Harris 81f11c7f63SJim Harris #define scic_sds_controller_smu_register_write(controller, reg, value) \ 82f11c7f63SJim Harris smu_register_write( \ 83f11c7f63SJim Harris (controller), \ 84f11c7f63SJim Harris (controller)->smu_registers->reg, \ 85f11c7f63SJim Harris (value) \ 86f11c7f63SJim Harris ) 87f11c7f63SJim Harris /*@}*/ 88f11c7f63SJim Harris 89f11c7f63SJim Harris /** 90f11c7f63SJim Harris * @name AFE_REGISTER_ACCESS_MACROS 91f11c7f63SJim Harris */ 92f11c7f63SJim Harris /*@{*/ 93f11c7f63SJim Harris #define scu_afe_register_write(controller, reg, value) \ 94f11c7f63SJim Harris scu_register_write( \ 95f11c7f63SJim Harris (controller), \ 96f11c7f63SJim Harris (controller)->scu_registers->afe.reg, \ 97f11c7f63SJim Harris (value) \ 98f11c7f63SJim Harris ) 99f11c7f63SJim Harris 100f11c7f63SJim Harris #define scu_afe_register_read(controller, reg) \ 101f11c7f63SJim Harris scu_register_read( \ 102f11c7f63SJim Harris (controller), \ 103f11c7f63SJim Harris (controller)->scu_registers->afe.reg \ 104f11c7f63SJim Harris ) 105f11c7f63SJim Harris /*@}*/ 106f11c7f63SJim Harris 107f11c7f63SJim Harris /** 108f11c7f63SJim Harris * @name SGPIO_PEG0_REGISTER_ACCESS_MACROS 109f11c7f63SJim Harris */ 110f11c7f63SJim Harris /*@{*/ 111f11c7f63SJim Harris #define scu_sgpio_peg0_register_read(controller, reg) \ 112f11c7f63SJim Harris scu_register_read( \ 113f11c7f63SJim Harris (controller), \ 114f11c7f63SJim Harris (controller)->scu_registers->peg0.sgpio.reg \ 115f11c7f63SJim Harris ) 116f11c7f63SJim Harris 117f11c7f63SJim Harris #define scu_sgpio_peg0_register_write(controller, reg, value) \ 118f11c7f63SJim Harris scu_register_write( \ 119f11c7f63SJim Harris (controller), \ 120f11c7f63SJim Harris (controller)->scu_registers->peg0.sgpio.reg, \ 121f11c7f63SJim Harris (value) \ 122f11c7f63SJim Harris ) 123f11c7f63SJim Harris /*@}*/ 124f11c7f63SJim Harris 125f11c7f63SJim Harris /** 126f11c7f63SJim Harris * @name VIIT_REGISTER_ACCESS_MACROS 127f11c7f63SJim Harris */ 128f11c7f63SJim Harris /*@{*/ 129f11c7f63SJim Harris #define scu_controller_viit_register_write(controller, index, reg, value) \ 130f11c7f63SJim Harris scu_register_write( \ 131f11c7f63SJim Harris (controller), \ 132f11c7f63SJim Harris (controller)->scu_registers->peg0.viit[index].reg, \ 133f11c7f63SJim Harris value \ 134f11c7f63SJim Harris ) 135f11c7f63SJim Harris /*@}*/ 136f11c7f63SJim Harris 137f11c7f63SJim Harris /** 138f11c7f63SJim Harris * @name SCRATCH_RAM_REGISTER_ACCESS_MACROS 139f11c7f63SJim Harris */ 140f11c7f63SJim Harris /*@{*/ 141f11c7f63SJim Harris // Scratch RAM access may be needed before the scu_registers pointer 142f11c7f63SJim Harris // has been initialized. So instead, explicitly cast BAR1 to a 143f11c7f63SJim Harris // SCU_REGISTERS_T data structure. 144f11c7f63SJim Harris 145f11c7f63SJim Harris // Scratch RAM is stored in the Zoning Permission Table for OROM use. 146f11c7f63SJim Harris #define scu_controller_scratch_ram_register_write(controller, index, value) \ 147f11c7f63SJim Harris scu_register_write( \ 148f11c7f63SJim Harris (controller), \ 149f11c7f63SJim Harris ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \ 150f11c7f63SJim Harris value \ 151f11c7f63SJim Harris ) 152f11c7f63SJim Harris 153f11c7f63SJim Harris #define scu_controller_scratch_ram_register_read(controller, index) \ 154f11c7f63SJim Harris scu_register_read( \ 155f11c7f63SJim Harris (controller), \ 156f11c7f63SJim Harris ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \ 157f11c7f63SJim Harris ) 158f11c7f63SJim Harris 159f11c7f63SJim Harris #define scu_controller_scratch_ram_register_write_ext(controller, index, value) \ 160f11c7f63SJim Harris scu_register_write( \ 161f11c7f63SJim Harris (controller), \ 162f11c7f63SJim Harris ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \ 163f11c7f63SJim Harris value \ 164f11c7f63SJim Harris ) 165f11c7f63SJim Harris 166f11c7f63SJim Harris #define scu_controller_scratch_ram_register_read_ext(controller, index) \ 167f11c7f63SJim Harris scu_register_read( \ 168f11c7f63SJim Harris (controller), \ 169f11c7f63SJim Harris ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \ 170f11c7f63SJim Harris ) 171f11c7f63SJim Harris /*@}*/ 172f11c7f63SJim Harris 173f11c7f63SJim Harris 174f11c7f63SJim Harris //***************************************************************************** 175f11c7f63SJim Harris //* SMU REGISTERS 176f11c7f63SJim Harris //***************************************************************************** 177f11c7f63SJim Harris 178f11c7f63SJim Harris /** 179f11c7f63SJim Harris * @name SMU_REGISTERS 180f11c7f63SJim Harris */ 181f11c7f63SJim Harris /*@{*/ 182f11c7f63SJim Harris #define SMU_PCP_WRITE(controller, value) \ 183f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 184f11c7f63SJim Harris controller, post_context_port, value \ 185f11c7f63SJim Harris ) 186f11c7f63SJim Harris 187f11c7f63SJim Harris #define SMU_TCR_READ(controller, value) \ 188f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 189f11c7f63SJim Harris controller, task_context_range \ 190f11c7f63SJim Harris ) 191f11c7f63SJim Harris 192f11c7f63SJim Harris #define SMU_TCR_WRITE(controller, value) \ 193f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 194f11c7f63SJim Harris controller, task_context_range, value \ 195f11c7f63SJim Harris ) 196f11c7f63SJim Harris 197f11c7f63SJim Harris #define SMU_HTTBAR_WRITE(controller, address) \ 198f11c7f63SJim Harris { \ 199f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 200f11c7f63SJim Harris controller, \ 201f11c7f63SJim Harris host_task_table_lower, \ 202f11c7f63SJim Harris sci_cb_physical_address_lower(address) \ 203f11c7f63SJim Harris );\ 204f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 205f11c7f63SJim Harris controller, \ 206f11c7f63SJim Harris host_task_table_upper, \ 207f11c7f63SJim Harris sci_cb_physical_address_upper(address) \ 208f11c7f63SJim Harris ); \ 209f11c7f63SJim Harris } 210f11c7f63SJim Harris 211f11c7f63SJim Harris #define SMU_CQBAR_WRITE(controller, address) \ 212f11c7f63SJim Harris { \ 213f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 214f11c7f63SJim Harris controller, \ 215f11c7f63SJim Harris completion_queue_lower, \ 216f11c7f63SJim Harris sci_cb_physical_address_lower(address) \ 217f11c7f63SJim Harris ); \ 218f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 219f11c7f63SJim Harris controller, \ 220f11c7f63SJim Harris completion_queue_upper, \ 221f11c7f63SJim Harris sci_cb_physical_address_upper(address) \ 222f11c7f63SJim Harris ); \ 223f11c7f63SJim Harris } 224f11c7f63SJim Harris 225f11c7f63SJim Harris #define SMU_CQGR_WRITE(controller, value) \ 226f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 227f11c7f63SJim Harris controller, completion_queue_get, value \ 228f11c7f63SJim Harris ) 229f11c7f63SJim Harris 230f11c7f63SJim Harris #define SMU_CQGR_READ(controller, value) \ 231f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 232f11c7f63SJim Harris controller, completion_queue_get \ 233f11c7f63SJim Harris ) 234f11c7f63SJim Harris 235f11c7f63SJim Harris #define SMU_CQPR_WRITE(controller, value) \ 236f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 237f11c7f63SJim Harris controller, completion_queue_put, value \ 238f11c7f63SJim Harris ) 239f11c7f63SJim Harris 240f11c7f63SJim Harris #define SMU_RNCBAR_WRITE(controller, address) \ 241f11c7f63SJim Harris { \ 242f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 243f11c7f63SJim Harris controller, \ 244f11c7f63SJim Harris remote_node_context_lower, \ 245f11c7f63SJim Harris sci_cb_physical_address_lower(address) \ 246f11c7f63SJim Harris ); \ 247f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 248f11c7f63SJim Harris controller, \ 249f11c7f63SJim Harris remote_node_context_upper, \ 250f11c7f63SJim Harris sci_cb_physical_address_upper(address) \ 251f11c7f63SJim Harris ); \ 252f11c7f63SJim Harris } 253f11c7f63SJim Harris 254f11c7f63SJim Harris #define SMU_AMR_READ(controller) \ 255f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 256f11c7f63SJim Harris controller, address_modifier \ 257f11c7f63SJim Harris ) 258f11c7f63SJim Harris 259f11c7f63SJim Harris #define SMU_IMR_READ(controller) \ 260f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 261f11c7f63SJim Harris controller, interrupt_mask \ 262f11c7f63SJim Harris ) 263f11c7f63SJim Harris 264f11c7f63SJim Harris #define SMU_IMR_WRITE(controller, mask) \ 265f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 266f11c7f63SJim Harris controller, interrupt_mask, mask \ 267f11c7f63SJim Harris ) 268f11c7f63SJim Harris 269f11c7f63SJim Harris #define SMU_ISR_READ(controller) \ 270f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 271f11c7f63SJim Harris controller, interrupt_status \ 272f11c7f63SJim Harris ) 273f11c7f63SJim Harris 274f11c7f63SJim Harris #define SMU_ISR_WRITE(controller, status) \ 275f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 276f11c7f63SJim Harris controller, interrupt_status, status \ 277f11c7f63SJim Harris ) 278f11c7f63SJim Harris 279f11c7f63SJim Harris #define SMU_ICC_READ(controller) \ 280f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 281f11c7f63SJim Harris controller, interrupt_coalesce_control \ 282f11c7f63SJim Harris ) 283f11c7f63SJim Harris 284f11c7f63SJim Harris #define SMU_ICC_WRITE(controller, value) \ 285f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 286f11c7f63SJim Harris controller, interrupt_coalesce_control, value \ 287f11c7f63SJim Harris ) 288f11c7f63SJim Harris 289f11c7f63SJim Harris #define SMU_CQC_WRITE(controller, value) \ 290f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 291f11c7f63SJim Harris controller, completion_queue_control, value \ 292f11c7f63SJim Harris ) 293f11c7f63SJim Harris 294f11c7f63SJim Harris #define SMU_SMUSRCR_WRITE(controller, value) \ 295f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 296f11c7f63SJim Harris controller, soft_reset_control, value \ 297f11c7f63SJim Harris ) 298f11c7f63SJim Harris 299f11c7f63SJim Harris #define SMU_TCA_WRITE(controller, index, value) \ 300f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 301f11c7f63SJim Harris controller, task_context_assignment[index], value \ 302f11c7f63SJim Harris ) 303f11c7f63SJim Harris 304f11c7f63SJim Harris #define SMU_TCA_READ(controller, index) \ 305f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 306f11c7f63SJim Harris controller, task_context_assignment[index] \ 307f11c7f63SJim Harris ) 308f11c7f63SJim Harris 309f11c7f63SJim Harris #define SMU_DCC_READ(controller) \ 310f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 311f11c7f63SJim Harris controller, device_context_capacity \ 312f11c7f63SJim Harris ) 313f11c7f63SJim Harris 314f11c7f63SJim Harris #define SMU_DFC_READ(controller) \ 315f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 316f11c7f63SJim Harris controller, device_function_capacity \ 317f11c7f63SJim Harris ) 318f11c7f63SJim Harris 319f11c7f63SJim Harris #define SMU_SMUCSR_READ(controller) \ 320f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 321f11c7f63SJim Harris controller, control_status \ 322f11c7f63SJim Harris ) 323f11c7f63SJim Harris 324f11c7f63SJim Harris #define SMU_CGUCR_READ(controller) \ 325f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 326f11c7f63SJim Harris controller, clock_gating_control \ 327f11c7f63SJim Harris ) 328f11c7f63SJim Harris 329f11c7f63SJim Harris #define SMU_CGUCR_WRITE(controller, value) \ 330f11c7f63SJim Harris scic_sds_controller_smu_register_write( \ 331f11c7f63SJim Harris controller, clock_gating_control, value \ 332f11c7f63SJim Harris ) 333f11c7f63SJim Harris 334f11c7f63SJim Harris #define SMU_CQPR_READ(controller) \ 335f11c7f63SJim Harris scic_sds_controller_smu_register_read( \ 336f11c7f63SJim Harris controller, completion_queue_put \ 337f11c7f63SJim Harris ) 338f11c7f63SJim Harris 339f11c7f63SJim Harris /*@}*/ 340f11c7f63SJim Harris 341f11c7f63SJim Harris /** 342f11c7f63SJim Harris * @name SCU_REGISTER_ACCESS_MACROS 343f11c7f63SJim Harris */ 344f11c7f63SJim Harris /*@{*/ 345f11c7f63SJim Harris #define scic_sds_controller_scu_register_read(controller, reg) \ 346f11c7f63SJim Harris scu_register_read( \ 347f11c7f63SJim Harris (controller), \ 348f11c7f63SJim Harris (controller)->scu_registers->reg \ 349f11c7f63SJim Harris ) 350f11c7f63SJim Harris 351f11c7f63SJim Harris #define scic_sds_controller_scu_register_write(controller, reg, value) \ 352f11c7f63SJim Harris scu_register_write( \ 353f11c7f63SJim Harris (controller), \ 354f11c7f63SJim Harris (controller)->scu_registers->reg, \ 355f11c7f63SJim Harris (value) \ 356f11c7f63SJim Harris ) 357f11c7f63SJim Harris /*@}*/ 358f11c7f63SJim Harris 359f11c7f63SJim Harris 360f11c7f63SJim Harris //**************************************************************************** 361f11c7f63SJim Harris //* SCU SDMA REGISTERS 362f11c7f63SJim Harris //**************************************************************************** 363f11c7f63SJim Harris 364f11c7f63SJim Harris /** 365f11c7f63SJim Harris * @name SCU_SDMA_REGISTER_ACCESS_MACROS 366f11c7f63SJim Harris */ 367f11c7f63SJim Harris /*@{*/ 368f11c7f63SJim Harris #define scu_sdma_register_read(controller, reg) \ 369f11c7f63SJim Harris scu_register_read( \ 370f11c7f63SJim Harris (controller), \ 371f11c7f63SJim Harris (controller)->scu_registers->sdma.reg \ 372f11c7f63SJim Harris ) 373f11c7f63SJim Harris 374f11c7f63SJim Harris #define scu_sdma_register_write(controller, reg, value) \ 375f11c7f63SJim Harris scu_register_write( \ 376f11c7f63SJim Harris (controller), \ 377f11c7f63SJim Harris (controller)->scu_registers->sdma.reg, \ 378f11c7f63SJim Harris (value) \ 379f11c7f63SJim Harris ) 380f11c7f63SJim Harris /*@}*/ 381f11c7f63SJim Harris 382f11c7f63SJim Harris /** 383f11c7f63SJim Harris * @name SCU_SDMA_REGISTERS 384f11c7f63SJim Harris */ 385f11c7f63SJim Harris /*@{*/ 386f11c7f63SJim Harris #define SCU_PUFATHAR_WRITE(controller, address) \ 387f11c7f63SJim Harris { \ 388f11c7f63SJim Harris scu_sdma_register_write( \ 389f11c7f63SJim Harris controller, \ 390f11c7f63SJim Harris uf_address_table_lower, \ 391f11c7f63SJim Harris sci_cb_physical_address_lower(address) \ 392f11c7f63SJim Harris ); \ 393f11c7f63SJim Harris scu_sdma_register_write( \ 394f11c7f63SJim Harris controller, \ 395f11c7f63SJim Harris uf_address_table_upper, \ 396f11c7f63SJim Harris sci_cb_physical_address_upper(address) \ 397f11c7f63SJim Harris ); \ 398f11c7f63SJim Harris } 399f11c7f63SJim Harris 400f11c7f63SJim Harris #define SCU_UFHBAR_WRITE(controller, address) \ 401f11c7f63SJim Harris { \ 402f11c7f63SJim Harris scu_sdma_register_write( \ 403f11c7f63SJim Harris controller, \ 404f11c7f63SJim Harris uf_header_base_address_lower, \ 405f11c7f63SJim Harris sci_cb_physical_address_lower(address) \ 406f11c7f63SJim Harris ); \ 407f11c7f63SJim Harris scu_sdma_register_write( \ 408f11c7f63SJim Harris controller, \ 409f11c7f63SJim Harris uf_header_base_address_upper, \ 410f11c7f63SJim Harris sci_cb_physical_address_upper(address) \ 411f11c7f63SJim Harris ); \ 412f11c7f63SJim Harris } 413f11c7f63SJim Harris 414f11c7f63SJim Harris #define SCU_UFQC_READ(controller) \ 415f11c7f63SJim Harris scu_sdma_register_read( \ 416f11c7f63SJim Harris controller, \ 417f11c7f63SJim Harris unsolicited_frame_queue_control \ 418f11c7f63SJim Harris ) 419f11c7f63SJim Harris 420f11c7f63SJim Harris #define SCU_UFQC_WRITE(controller, value) \ 421f11c7f63SJim Harris scu_sdma_register_write( \ 422f11c7f63SJim Harris controller, \ 423f11c7f63SJim Harris unsolicited_frame_queue_control, \ 424f11c7f63SJim Harris value \ 425f11c7f63SJim Harris ) 426f11c7f63SJim Harris 427f11c7f63SJim Harris #define SCU_UFQPP_READ(controller) \ 428f11c7f63SJim Harris scu_sdma_register_read( \ 429f11c7f63SJim Harris controller, \ 430f11c7f63SJim Harris unsolicited_frame_put_pointer \ 431f11c7f63SJim Harris ) 432f11c7f63SJim Harris 433f11c7f63SJim Harris #define SCU_UFQPP_WRITE(controller, value) \ 434f11c7f63SJim Harris scu_sdma_register_write( \ 435f11c7f63SJim Harris controller, \ 436f11c7f63SJim Harris unsolicited_frame_put_pointer, \ 437f11c7f63SJim Harris value \ 438f11c7f63SJim Harris ) 439f11c7f63SJim Harris 440f11c7f63SJim Harris #define SCU_UFQGP_WRITE(controller, value) \ 441f11c7f63SJim Harris scu_sdma_register_write( \ 442f11c7f63SJim Harris controller, \ 443f11c7f63SJim Harris unsolicited_frame_get_pointer, \ 444f11c7f63SJim Harris value \ 445f11c7f63SJim Harris ) 446f11c7f63SJim Harris 447f11c7f63SJim Harris #define SCU_PDMACR_READ(controller) \ 448f11c7f63SJim Harris scu_sdma_register_read( \ 449f11c7f63SJim Harris controller, \ 450f11c7f63SJim Harris pdma_configuration \ 451f11c7f63SJim Harris ) 452f11c7f63SJim Harris 453f11c7f63SJim Harris #define SCU_PDMACR_WRITE(controller, value) \ 454f11c7f63SJim Harris scu_sdma_register_write( \ 455f11c7f63SJim Harris controller, \ 456f11c7f63SJim Harris pdma_configuration, \ 457f11c7f63SJim Harris value \ 458f11c7f63SJim Harris ) 459f11c7f63SJim Harris 460f11c7f63SJim Harris #define SCU_CDMACR_READ(controller) \ 461f11c7f63SJim Harris scu_sdma_register_read( \ 462f11c7f63SJim Harris controller, \ 463f11c7f63SJim Harris cdma_configuration \ 464f11c7f63SJim Harris ) 465f11c7f63SJim Harris 466f11c7f63SJim Harris #define SCU_CDMACR_WRITE(controller, value) \ 467f11c7f63SJim Harris scu_sdma_register_write( \ 468f11c7f63SJim Harris controller, \ 469f11c7f63SJim Harris cdma_configuration, \ 470f11c7f63SJim Harris value \ 471f11c7f63SJim Harris ) 472f11c7f63SJim Harris /*@}*/ 473f11c7f63SJim Harris 474f11c7f63SJim Harris //***************************************************************************** 475f11c7f63SJim Harris //* SCU CRAM AND FBRAM Registers 476f11c7f63SJim Harris //***************************************************************************** 477f11c7f63SJim Harris /** 478f11c7f63SJim Harris * @name SCU_CRAM_REGISTER_ACCESS_MACROS 479f11c7f63SJim Harris */ 480f11c7f63SJim Harris /*@{*/ 481f11c7f63SJim Harris #define scu_cram_register_read(controller, reg) \ 482f11c7f63SJim Harris scu_register_read( \ 483f11c7f63SJim Harris (controller), \ 484f11c7f63SJim Harris (controller)->scu_registers->cram.reg \ 485f11c7f63SJim Harris ) 486f11c7f63SJim Harris 487f11c7f63SJim Harris #define scu_cram_register_write(controller, reg, value) \ 488f11c7f63SJim Harris scu_register_write( \ 489f11c7f63SJim Harris (controller), \ 490f11c7f63SJim Harris (controller)->scu_registers->cram.reg, \ 491f11c7f63SJim Harris (value) \ 492f11c7f63SJim Harris ) 493f11c7f63SJim Harris /*@}*/ 494f11c7f63SJim Harris 495f11c7f63SJim Harris /** 496f11c7f63SJim Harris * @name SCU_FBRAM_REGISTER_ACCESS_MACROS 497f11c7f63SJim Harris */ 498f11c7f63SJim Harris /*@{*/ 499f11c7f63SJim Harris #define scu_fbram_register_read(controller, reg) \ 500f11c7f63SJim Harris scu_register_read( \ 501f11c7f63SJim Harris (controller), \ 502f11c7f63SJim Harris (controller)->scu_registers->fbram.reg \ 503f11c7f63SJim Harris ) 504f11c7f63SJim Harris 505f11c7f63SJim Harris #define scu_fbram_register_write(controller, reg, value) \ 506f11c7f63SJim Harris scu_register_write( \ 507f11c7f63SJim Harris (controller), \ 508f11c7f63SJim Harris (controller)->scu_registers->fbram.reg, \ 509f11c7f63SJim Harris (value) \ 510f11c7f63SJim Harris ) 511f11c7f63SJim Harris /*@}*/ 512f11c7f63SJim Harris 513f11c7f63SJim Harris 514f11c7f63SJim Harris /** 515f11c7f63SJim Harris * @name SCU_CRAM_REGISTERS 516f11c7f63SJim Harris */ 517f11c7f63SJim Harris /*@{*/ 518f11c7f63SJim Harris 519f11c7f63SJim Harris // SRAM ECC CONTROL REGISTER BITS 520f11c7f63SJim Harris #define SIGNLE_BIT_ERROR_CORRECTION_ENABLE 0x00000001 521f11c7f63SJim Harris #define MULTI_BIT_ERROR_REPORTING_ENABLE 0x00000002 522f11c7f63SJim Harris #define SINGLE_BIT_ERROR_REPORTING_ENABLE 0x00000004 523f11c7f63SJim Harris 524f11c7f63SJim Harris //SRAM ECC control register (SECR0) 525f11c7f63SJim Harris #define SCU_SECR0_WRITE(controller, value) \ 526f11c7f63SJim Harris scu_cram_register_write( \ 527f11c7f63SJim Harris controller, \ 528f11c7f63SJim Harris sram_ecc_control_0, \ 529f11c7f63SJim Harris value \ 530f11c7f63SJim Harris ) 531f11c7f63SJim Harris /*@}*/ 532f11c7f63SJim Harris 533f11c7f63SJim Harris /** 534f11c7f63SJim Harris * @name SCU_FBRAM_REGISTERS 535f11c7f63SJim Harris */ 536f11c7f63SJim Harris /*@{*/ 537f11c7f63SJim Harris 538f11c7f63SJim Harris //SRAM ECC control register (SECR1) 539f11c7f63SJim Harris #define SCU_SECR1_WRITE(controller, value) \ 540f11c7f63SJim Harris scu_fbram_register_write( \ 541f11c7f63SJim Harris controller, \ 542f11c7f63SJim Harris sram_ecc_control_1, \ 543f11c7f63SJim Harris value \ 544f11c7f63SJim Harris ) 545f11c7f63SJim Harris /*@}*/ 546f11c7f63SJim Harris 547f11c7f63SJim Harris 548f11c7f63SJim Harris //***************************************************************************** 549f11c7f63SJim Harris //* SCU Port Task Scheduler Group Registers 550f11c7f63SJim Harris //***************************************************************************** 551f11c7f63SJim Harris 552f11c7f63SJim Harris /** 553f11c7f63SJim Harris * @name SCU_PTSG_REGISTER_ACCESS_MACROS 554f11c7f63SJim Harris */ 555f11c7f63SJim Harris /*@{*/ 556f11c7f63SJim Harris #define scu_ptsg_register_read(controller, reg) \ 557f11c7f63SJim Harris scu_register_read( \ 558f11c7f63SJim Harris (controller), \ 559f11c7f63SJim Harris (controller)->scu_registers->peg0.ptsg.reg \ 560f11c7f63SJim Harris ) 561f11c7f63SJim Harris 562f11c7f63SJim Harris #define scu_ptsg_register_write(controller, reg, value) \ 563f11c7f63SJim Harris scu_register_write( \ 564f11c7f63SJim Harris (controller), \ 565f11c7f63SJim Harris (controller)->scu_registers->peg0.ptsg.reg, \ 566f11c7f63SJim Harris (value) \ 567f11c7f63SJim Harris ) 568f11c7f63SJim Harris /*@}*/ 569f11c7f63SJim Harris 570f11c7f63SJim Harris /** 571f11c7f63SJim Harris * @name SCU_PTSG_REGISTERS 572f11c7f63SJim Harris */ 573f11c7f63SJim Harris /*@{*/ 574f11c7f63SJim Harris #define SCU_PTSGCR_READ(controller) \ 575f11c7f63SJim Harris scu_ptsg_register_read( \ 576f11c7f63SJim Harris (controller), \ 577f11c7f63SJim Harris control \ 578f11c7f63SJim Harris ) 579f11c7f63SJim Harris 580f11c7f63SJim Harris #define SCU_PTSGCR_WRITE(controller, value) \ 581f11c7f63SJim Harris scu_ptsg_register_write( \ 582f11c7f63SJim Harris (controller), \ 583f11c7f63SJim Harris control, \ 584f11c7f63SJim Harris value \ 585f11c7f63SJim Harris ) 586f11c7f63SJim Harris 587f11c7f63SJim Harris #define SCU_PTSGRTC_READ(controller) \ 588f11c7f63SJim Harris scu_ptsg_register_read( \ 58906152bf0SRavi Pokala controller, \ 590f11c7f63SJim Harris real_time_clock \ 591f11c7f63SJim Harris ) 592f11c7f63SJim Harris /*@}*/ 593f11c7f63SJim Harris 594f11c7f63SJim Harris #ifdef __cplusplus 595f11c7f63SJim Harris } 596f11c7f63SJim Harris #endif // __cplusplus 597f11c7f63SJim Harris 598f11c7f63SJim Harris #endif // _SCIC_SDS_CONTROLLER_REGISTERS_H_ 599