1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 23 * The full GNU General Public License is included in this distribution 24 * in the file called LICENSE.GPL. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 * $FreeBSD$ 55 */ 56 #ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_ 57 #define _SCIC_SDS_CONTROLLER_REGISTERS_H_ 58 59 /** 60 * @file 61 * 62 * @brief This file contains macros used to perform the register reads/writes 63 * to the SCU hardware. 64 */ 65 66 #ifdef __cplusplus 67 extern "C" { 68 #endif // __cplusplus 69 70 #include <dev/isci/scil/scu_registers.h> 71 #include <dev/isci/scil/scic_sds_controller.h> 72 73 /** 74 * @name SMU_REGISTER_ACCESS_MACROS 75 */ 76 /*@{*/ 77 #define scic_sds_controller_smu_register_read(controller, reg) \ 78 smu_register_read( \ 79 (controller), \ 80 (controller)->smu_registers->reg \ 81 ) 82 83 #define scic_sds_controller_smu_register_write(controller, reg, value) \ 84 smu_register_write( \ 85 (controller), \ 86 (controller)->smu_registers->reg, \ 87 (value) \ 88 ) 89 /*@}*/ 90 91 /** 92 * @name AFE_REGISTER_ACCESS_MACROS 93 */ 94 /*@{*/ 95 #define scu_afe_register_write(controller, reg, value) \ 96 scu_register_write( \ 97 (controller), \ 98 (controller)->scu_registers->afe.reg, \ 99 (value) \ 100 ) 101 102 #define scu_afe_register_read(controller, reg) \ 103 scu_register_read( \ 104 (controller), \ 105 (controller)->scu_registers->afe.reg \ 106 ) 107 /*@}*/ 108 109 /** 110 * @name SGPIO_PEG0_REGISTER_ACCESS_MACROS 111 */ 112 /*@{*/ 113 #define scu_sgpio_peg0_register_read(controller, reg) \ 114 scu_register_read( \ 115 (controller), \ 116 (controller)->scu_registers->peg0.sgpio.reg \ 117 ) 118 119 #define scu_sgpio_peg0_register_write(controller, reg, value) \ 120 scu_register_write( \ 121 (controller), \ 122 (controller)->scu_registers->peg0.sgpio.reg, \ 123 (value) \ 124 ) 125 /*@}*/ 126 127 /** 128 * @name VIIT_REGISTER_ACCESS_MACROS 129 */ 130 /*@{*/ 131 #define scu_controller_viit_register_write(controller, index, reg, value) \ 132 scu_register_write( \ 133 (controller), \ 134 (controller)->scu_registers->peg0.viit[index].reg, \ 135 value \ 136 ) 137 /*@}*/ 138 139 /** 140 * @name SCRATCH_RAM_REGISTER_ACCESS_MACROS 141 */ 142 /*@{*/ 143 // Scratch RAM access may be needed before the scu_registers pointer 144 // has been initialized. So instead, explicitly cast BAR1 to a 145 // SCU_REGISTERS_T data structure. 146 147 // Scratch RAM is stored in the Zoning Permission Table for OROM use. 148 #define scu_controller_scratch_ram_register_write(controller, index, value) \ 149 scu_register_write( \ 150 (controller), \ 151 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \ 152 value \ 153 ) 154 155 #define scu_controller_scratch_ram_register_read(controller, index) \ 156 scu_register_read( \ 157 (controller), \ 158 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \ 159 ) 160 161 #define scu_controller_scratch_ram_register_write_ext(controller, index, value) \ 162 scu_register_write( \ 163 (controller), \ 164 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \ 165 value \ 166 ) 167 168 #define scu_controller_scratch_ram_register_read_ext(controller, index) \ 169 scu_register_read( \ 170 (controller), \ 171 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \ 172 ) 173 /*@}*/ 174 175 176 //***************************************************************************** 177 //* SMU REGISTERS 178 //***************************************************************************** 179 180 /** 181 * @name SMU_REGISTERS 182 */ 183 /*@{*/ 184 #define SMU_PCP_WRITE(controller, value) \ 185 scic_sds_controller_smu_register_write( \ 186 controller, post_context_port, value \ 187 ) 188 189 #define SMU_TCR_READ(controller, value) \ 190 scic_sds_controller_smu_register_read( \ 191 controller, task_context_range \ 192 ) 193 194 #define SMU_TCR_WRITE(controller, value) \ 195 scic_sds_controller_smu_register_write( \ 196 controller, task_context_range, value \ 197 ) 198 199 #define SMU_HTTBAR_WRITE(controller, address) \ 200 { \ 201 scic_sds_controller_smu_register_write( \ 202 controller, \ 203 host_task_table_lower, \ 204 sci_cb_physical_address_lower(address) \ 205 );\ 206 scic_sds_controller_smu_register_write( \ 207 controller, \ 208 host_task_table_upper, \ 209 sci_cb_physical_address_upper(address) \ 210 ); \ 211 } 212 213 #define SMU_CQBAR_WRITE(controller, address) \ 214 { \ 215 scic_sds_controller_smu_register_write( \ 216 controller, \ 217 completion_queue_lower, \ 218 sci_cb_physical_address_lower(address) \ 219 ); \ 220 scic_sds_controller_smu_register_write( \ 221 controller, \ 222 completion_queue_upper, \ 223 sci_cb_physical_address_upper(address) \ 224 ); \ 225 } 226 227 #define SMU_CQGR_WRITE(controller, value) \ 228 scic_sds_controller_smu_register_write( \ 229 controller, completion_queue_get, value \ 230 ) 231 232 #define SMU_CQGR_READ(controller, value) \ 233 scic_sds_controller_smu_register_read( \ 234 controller, completion_queue_get \ 235 ) 236 237 #define SMU_CQPR_WRITE(controller, value) \ 238 scic_sds_controller_smu_register_write( \ 239 controller, completion_queue_put, value \ 240 ) 241 242 #define SMU_RNCBAR_WRITE(controller, address) \ 243 { \ 244 scic_sds_controller_smu_register_write( \ 245 controller, \ 246 remote_node_context_lower, \ 247 sci_cb_physical_address_lower(address) \ 248 ); \ 249 scic_sds_controller_smu_register_write( \ 250 controller, \ 251 remote_node_context_upper, \ 252 sci_cb_physical_address_upper(address) \ 253 ); \ 254 } 255 256 #define SMU_AMR_READ(controller) \ 257 scic_sds_controller_smu_register_read( \ 258 controller, address_modifier \ 259 ) 260 261 #define SMU_IMR_READ(controller) \ 262 scic_sds_controller_smu_register_read( \ 263 controller, interrupt_mask \ 264 ) 265 266 #define SMU_IMR_WRITE(controller, mask) \ 267 scic_sds_controller_smu_register_write( \ 268 controller, interrupt_mask, mask \ 269 ) 270 271 #define SMU_ISR_READ(controller) \ 272 scic_sds_controller_smu_register_read( \ 273 controller, interrupt_status \ 274 ) 275 276 #define SMU_ISR_WRITE(controller, status) \ 277 scic_sds_controller_smu_register_write( \ 278 controller, interrupt_status, status \ 279 ) 280 281 #define SMU_ICC_READ(controller) \ 282 scic_sds_controller_smu_register_read( \ 283 controller, interrupt_coalesce_control \ 284 ) 285 286 #define SMU_ICC_WRITE(controller, value) \ 287 scic_sds_controller_smu_register_write( \ 288 controller, interrupt_coalesce_control, value \ 289 ) 290 291 #define SMU_CQC_WRITE(controller, value) \ 292 scic_sds_controller_smu_register_write( \ 293 controller, completion_queue_control, value \ 294 ) 295 296 #define SMU_SMUSRCR_WRITE(controller, value) \ 297 scic_sds_controller_smu_register_write( \ 298 controller, soft_reset_control, value \ 299 ) 300 301 #define SMU_TCA_WRITE(controller, index, value) \ 302 scic_sds_controller_smu_register_write( \ 303 controller, task_context_assignment[index], value \ 304 ) 305 306 #define SMU_TCA_READ(controller, index) \ 307 scic_sds_controller_smu_register_read( \ 308 controller, task_context_assignment[index] \ 309 ) 310 311 #define SMU_DCC_READ(controller) \ 312 scic_sds_controller_smu_register_read( \ 313 controller, device_context_capacity \ 314 ) 315 316 #define SMU_DFC_READ(controller) \ 317 scic_sds_controller_smu_register_read( \ 318 controller, device_function_capacity \ 319 ) 320 321 #define SMU_SMUCSR_READ(controller) \ 322 scic_sds_controller_smu_register_read( \ 323 controller, control_status \ 324 ) 325 326 #define SMU_CGUCR_READ(controller) \ 327 scic_sds_controller_smu_register_read( \ 328 controller, clock_gating_control \ 329 ) 330 331 #define SMU_CGUCR_WRITE(controller, value) \ 332 scic_sds_controller_smu_register_write( \ 333 controller, clock_gating_control, value \ 334 ) 335 336 #define SMU_CQPR_READ(controller) \ 337 scic_sds_controller_smu_register_read( \ 338 controller, completion_queue_put \ 339 ) 340 341 /*@}*/ 342 343 /** 344 * @name SCU_REGISTER_ACCESS_MACROS 345 */ 346 /*@{*/ 347 #define scic_sds_controller_scu_register_read(controller, reg) \ 348 scu_register_read( \ 349 (controller), \ 350 (controller)->scu_registers->reg \ 351 ) 352 353 #define scic_sds_controller_scu_register_write(controller, reg, value) \ 354 scu_register_write( \ 355 (controller), \ 356 (controller)->scu_registers->reg, \ 357 (value) \ 358 ) 359 /*@}*/ 360 361 362 //**************************************************************************** 363 //* SCU SDMA REGISTERS 364 //**************************************************************************** 365 366 /** 367 * @name SCU_SDMA_REGISTER_ACCESS_MACROS 368 */ 369 /*@{*/ 370 #define scu_sdma_register_read(controller, reg) \ 371 scu_register_read( \ 372 (controller), \ 373 (controller)->scu_registers->sdma.reg \ 374 ) 375 376 #define scu_sdma_register_write(controller, reg, value) \ 377 scu_register_write( \ 378 (controller), \ 379 (controller)->scu_registers->sdma.reg, \ 380 (value) \ 381 ) 382 /*@}*/ 383 384 /** 385 * @name SCU_SDMA_REGISTERS 386 */ 387 /*@{*/ 388 #define SCU_PUFATHAR_WRITE(controller, address) \ 389 { \ 390 scu_sdma_register_write( \ 391 controller, \ 392 uf_address_table_lower, \ 393 sci_cb_physical_address_lower(address) \ 394 ); \ 395 scu_sdma_register_write( \ 396 controller, \ 397 uf_address_table_upper, \ 398 sci_cb_physical_address_upper(address) \ 399 ); \ 400 } 401 402 #define SCU_UFHBAR_WRITE(controller, address) \ 403 { \ 404 scu_sdma_register_write( \ 405 controller, \ 406 uf_header_base_address_lower, \ 407 sci_cb_physical_address_lower(address) \ 408 ); \ 409 scu_sdma_register_write( \ 410 controller, \ 411 uf_header_base_address_upper, \ 412 sci_cb_physical_address_upper(address) \ 413 ); \ 414 } 415 416 #define SCU_UFQC_READ(controller) \ 417 scu_sdma_register_read( \ 418 controller, \ 419 unsolicited_frame_queue_control \ 420 ) 421 422 #define SCU_UFQC_WRITE(controller, value) \ 423 scu_sdma_register_write( \ 424 controller, \ 425 unsolicited_frame_queue_control, \ 426 value \ 427 ) 428 429 #define SCU_UFQPP_READ(controller) \ 430 scu_sdma_register_read( \ 431 controller, \ 432 unsolicited_frame_put_pointer \ 433 ) 434 435 #define SCU_UFQPP_WRITE(controller, value) \ 436 scu_sdma_register_write( \ 437 controller, \ 438 unsolicited_frame_put_pointer, \ 439 value \ 440 ) 441 442 #define SCU_UFQGP_WRITE(controller, value) \ 443 scu_sdma_register_write( \ 444 controller, \ 445 unsolicited_frame_get_pointer, \ 446 value \ 447 ) 448 449 #define SCU_PDMACR_READ(controller) \ 450 scu_sdma_register_read( \ 451 controller, \ 452 pdma_configuration \ 453 ) 454 455 #define SCU_PDMACR_WRITE(controller, value) \ 456 scu_sdma_register_write( \ 457 controller, \ 458 pdma_configuration, \ 459 value \ 460 ) 461 462 #define SCU_CDMACR_READ(controller) \ 463 scu_sdma_register_read( \ 464 controller, \ 465 cdma_configuration \ 466 ) 467 468 #define SCU_CDMACR_WRITE(controller, value) \ 469 scu_sdma_register_write( \ 470 controller, \ 471 cdma_configuration, \ 472 value \ 473 ) 474 /*@}*/ 475 476 //***************************************************************************** 477 //* SCU CRAM AND FBRAM Registers 478 //***************************************************************************** 479 /** 480 * @name SCU_CRAM_REGISTER_ACCESS_MACROS 481 */ 482 /*@{*/ 483 #define scu_cram_register_read(controller, reg) \ 484 scu_register_read( \ 485 (controller), \ 486 (controller)->scu_registers->cram.reg \ 487 ) 488 489 #define scu_cram_register_write(controller, reg, value) \ 490 scu_register_write( \ 491 (controller), \ 492 (controller)->scu_registers->cram.reg, \ 493 (value) \ 494 ) 495 /*@}*/ 496 497 /** 498 * @name SCU_FBRAM_REGISTER_ACCESS_MACROS 499 */ 500 /*@{*/ 501 #define scu_fbram_register_read(controller, reg) \ 502 scu_register_read( \ 503 (controller), \ 504 (controller)->scu_registers->fbram.reg \ 505 ) 506 507 #define scu_fbram_register_write(controller, reg, value) \ 508 scu_register_write( \ 509 (controller), \ 510 (controller)->scu_registers->fbram.reg, \ 511 (value) \ 512 ) 513 /*@}*/ 514 515 516 /** 517 * @name SCU_CRAM_REGISTERS 518 */ 519 /*@{*/ 520 521 // SRAM ECC CONTROL REGISTER BITS 522 #define SIGNLE_BIT_ERROR_CORRECTION_ENABLE 0x00000001 523 #define MULTI_BIT_ERROR_REPORTING_ENABLE 0x00000002 524 #define SINGLE_BIT_ERROR_REPORTING_ENABLE 0x00000004 525 526 //SRAM ECC control register (SECR0) 527 #define SCU_SECR0_WRITE(controller, value) \ 528 scu_cram_register_write( \ 529 controller, \ 530 sram_ecc_control_0, \ 531 value \ 532 ) 533 /*@}*/ 534 535 /** 536 * @name SCU_FBRAM_REGISTERS 537 */ 538 /*@{*/ 539 540 //SRAM ECC control register (SECR1) 541 #define SCU_SECR1_WRITE(controller, value) \ 542 scu_fbram_register_write( \ 543 controller, \ 544 sram_ecc_control_1, \ 545 value \ 546 ) 547 /*@}*/ 548 549 550 //***************************************************************************** 551 //* SCU Port Task Scheduler Group Registers 552 //***************************************************************************** 553 554 /** 555 * @name SCU_PTSG_REGISTER_ACCESS_MACROS 556 */ 557 /*@{*/ 558 #define scu_ptsg_register_read(controller, reg) \ 559 scu_register_read( \ 560 (controller), \ 561 (controller)->scu_registers->peg0.ptsg.reg \ 562 ) 563 564 #define scu_ptsg_register_write(controller, reg, value) \ 565 scu_register_write( \ 566 (controller), \ 567 (controller)->scu_registers->peg0.ptsg.reg, \ 568 (value) \ 569 ) 570 /*@}*/ 571 572 /** 573 * @name SCU_PTSG_REGISTERS 574 */ 575 /*@{*/ 576 #define SCU_PTSGCR_READ(controller) \ 577 scu_ptsg_register_read( \ 578 (controller), \ 579 control \ 580 ) 581 582 #define SCU_PTSGCR_WRITE(controller, value) \ 583 scu_ptsg_register_write( \ 584 (controller), \ 585 control, \ 586 value \ 587 ) 588 589 #define SCU_PTSGRTC_READ(controller) \ 590 scu_ptsg_register_read( \ 591 controller, \ 592 real_time_clock \ 593 ) 594 /*@}*/ 595 596 #ifdef __cplusplus 597 } 598 #endif // __cplusplus 599 600 #endif // _SCIC_SDS_CONTROLLER_REGISTERS_H_ 601