1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 #include <sys/uio.h> 48 49 #ifdef __sparc64__ 50 #include <dev/ofw/openfirm.h> 51 #include <machine/ofw_machdep.h> 52 #endif 53 54 #include <dev/isp/isp_freebsd.h> 55 56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 62 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 63 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 64 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 65 static int isp_pci_mbxdma(ispsoftc_t *); 66 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 68 69 static void isp_pci_reset0(ispsoftc_t *); 70 static void isp_pci_reset1(ispsoftc_t *); 71 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 72 73 static struct ispmdvec mdvec = { 74 isp_pci_rd_isr, 75 isp_pci_rd_reg, 76 isp_pci_wr_reg, 77 isp_pci_mbxdma, 78 isp_pci_dmasetup, 79 isp_common_dmateardown, 80 isp_pci_reset0, 81 isp_pci_reset1, 82 isp_pci_dumpregs, 83 NULL, 84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 85 }; 86 87 static struct ispmdvec mdvec_1080 = { 88 isp_pci_rd_isr, 89 isp_pci_rd_reg_1080, 90 isp_pci_wr_reg_1080, 91 isp_pci_mbxdma, 92 isp_pci_dmasetup, 93 isp_common_dmateardown, 94 isp_pci_reset0, 95 isp_pci_reset1, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99 }; 100 101 static struct ispmdvec mdvec_12160 = { 102 isp_pci_rd_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_reset0, 109 isp_pci_reset1, 110 isp_pci_dumpregs, 111 NULL, 112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 113 }; 114 115 static struct ispmdvec mdvec_2100 = { 116 isp_pci_rd_isr, 117 isp_pci_rd_reg, 118 isp_pci_wr_reg, 119 isp_pci_mbxdma, 120 isp_pci_dmasetup, 121 isp_common_dmateardown, 122 isp_pci_reset0, 123 isp_pci_reset1, 124 isp_pci_dumpregs 125 }; 126 127 static struct ispmdvec mdvec_2200 = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_common_dmateardown, 134 isp_pci_reset0, 135 isp_pci_reset1, 136 isp_pci_dumpregs 137 }; 138 139 static struct ispmdvec mdvec_2300 = { 140 isp_pci_rd_isr_2300, 141 isp_pci_rd_reg, 142 isp_pci_wr_reg, 143 isp_pci_mbxdma, 144 isp_pci_dmasetup, 145 isp_common_dmateardown, 146 isp_pci_reset0, 147 isp_pci_reset1, 148 isp_pci_dumpregs 149 }; 150 151 static struct ispmdvec mdvec_2400 = { 152 isp_pci_rd_isr_2400, 153 isp_pci_rd_reg_2400, 154 isp_pci_wr_reg_2400, 155 isp_pci_mbxdma, 156 isp_pci_dmasetup, 157 isp_common_dmateardown, 158 isp_pci_reset0, 159 isp_pci_reset1, 160 NULL 161 }; 162 163 static struct ispmdvec mdvec_2500 = { 164 isp_pci_rd_isr_2400, 165 isp_pci_rd_reg_2400, 166 isp_pci_wr_reg_2400, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_common_dmateardown, 170 isp_pci_reset0, 171 isp_pci_reset1, 172 NULL 173 }; 174 175 #ifndef PCIM_CMD_INVEN 176 #define PCIM_CMD_INVEN 0x10 177 #endif 178 #ifndef PCIM_CMD_BUSMASTEREN 179 #define PCIM_CMD_BUSMASTEREN 0x0004 180 #endif 181 #ifndef PCIM_CMD_PERRESPEN 182 #define PCIM_CMD_PERRESPEN 0x0040 183 #endif 184 #ifndef PCIM_CMD_SEREN 185 #define PCIM_CMD_SEREN 0x0100 186 #endif 187 #ifndef PCIM_CMD_INTX_DISABLE 188 #define PCIM_CMD_INTX_DISABLE 0x0400 189 #endif 190 191 #ifndef PCIR_COMMAND 192 #define PCIR_COMMAND 0x04 193 #endif 194 195 #ifndef PCIR_CACHELNSZ 196 #define PCIR_CACHELNSZ 0x0c 197 #endif 198 199 #ifndef PCIR_LATTIMER 200 #define PCIR_LATTIMER 0x0d 201 #endif 202 203 #ifndef PCIR_ROMADDR 204 #define PCIR_ROMADDR 0x30 205 #endif 206 207 #ifndef PCI_VENDOR_QLOGIC 208 #define PCI_VENDOR_QLOGIC 0x1077 209 #endif 210 211 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 212 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 213 #endif 214 215 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 216 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 217 #endif 218 219 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 220 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 221 #endif 222 223 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 224 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 225 #endif 226 227 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 228 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 229 #endif 230 231 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 232 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 233 #endif 234 235 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 236 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 237 #endif 238 239 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 240 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 241 #endif 242 243 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 244 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 245 #endif 246 247 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 248 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 249 #endif 250 251 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 252 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 253 #endif 254 255 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 256 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 257 #endif 258 259 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 260 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 261 #endif 262 263 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 264 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 265 #endif 266 267 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 268 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 269 #endif 270 271 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 272 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 273 #endif 274 275 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 276 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 277 #endif 278 279 #define PCI_QLOGIC_ISP5432 \ 280 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP1020 \ 283 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP1080 \ 286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define PCI_QLOGIC_ISP10160 \ 289 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 290 291 #define PCI_QLOGIC_ISP12160 \ 292 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 293 294 #define PCI_QLOGIC_ISP1240 \ 295 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 296 297 #define PCI_QLOGIC_ISP1280 \ 298 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 299 300 #define PCI_QLOGIC_ISP2100 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 302 303 #define PCI_QLOGIC_ISP2200 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 305 306 #define PCI_QLOGIC_ISP2300 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 308 309 #define PCI_QLOGIC_ISP2312 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 311 312 #define PCI_QLOGIC_ISP2322 \ 313 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 314 315 #define PCI_QLOGIC_ISP2422 \ 316 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 317 318 #define PCI_QLOGIC_ISP2432 \ 319 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 320 321 #define PCI_QLOGIC_ISP2532 \ 322 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 323 324 #define PCI_QLOGIC_ISP6312 \ 325 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 326 327 #define PCI_QLOGIC_ISP6322 \ 328 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 329 330 /* 331 * Odd case for some AMI raid cards... We need to *not* attach to this. 332 */ 333 #define AMI_RAID_SUBVENDOR_ID 0x101e 334 335 #define IO_MAP_REG 0x10 336 #define MEM_MAP_REG 0x14 337 338 #define PCI_DFLT_LTNCY 0x40 339 #define PCI_DFLT_LNSZ 0x10 340 341 static int isp_pci_probe (device_t); 342 static int isp_pci_attach (device_t); 343 static int isp_pci_detach (device_t); 344 345 346 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 347 struct isp_pcisoftc { 348 ispsoftc_t pci_isp; 349 device_t pci_dev; 350 struct resource * regs; 351 void * irq; 352 int iqd; 353 int rtp; 354 int rgd; 355 void * ih; 356 int16_t pci_poff[_NREG_BLKS]; 357 bus_dma_tag_t dmat; 358 int msicount; 359 }; 360 361 362 static device_method_t isp_pci_methods[] = { 363 /* Device interface */ 364 DEVMETHOD(device_probe, isp_pci_probe), 365 DEVMETHOD(device_attach, isp_pci_attach), 366 DEVMETHOD(device_detach, isp_pci_detach), 367 { 0, 0 } 368 }; 369 370 static driver_t isp_pci_driver = { 371 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 372 }; 373 static devclass_t isp_devclass; 374 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 375 MODULE_DEPEND(isp, cam, 1, 1, 1); 376 MODULE_DEPEND(isp, firmware, 1, 1, 1); 377 static int isp_nvports = 0; 378 379 static int 380 isp_pci_probe(device_t dev) 381 { 382 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 383 case PCI_QLOGIC_ISP1020: 384 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 385 break; 386 case PCI_QLOGIC_ISP1080: 387 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 388 break; 389 case PCI_QLOGIC_ISP1240: 390 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 391 break; 392 case PCI_QLOGIC_ISP1280: 393 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 394 break; 395 case PCI_QLOGIC_ISP10160: 396 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 397 break; 398 case PCI_QLOGIC_ISP12160: 399 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 400 return (ENXIO); 401 } 402 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 403 break; 404 case PCI_QLOGIC_ISP2100: 405 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 406 break; 407 case PCI_QLOGIC_ISP2200: 408 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 409 break; 410 case PCI_QLOGIC_ISP2300: 411 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 412 break; 413 case PCI_QLOGIC_ISP2312: 414 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 415 break; 416 case PCI_QLOGIC_ISP2322: 417 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 418 break; 419 case PCI_QLOGIC_ISP2422: 420 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 421 break; 422 case PCI_QLOGIC_ISP2432: 423 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 424 break; 425 case PCI_QLOGIC_ISP2532: 426 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 427 break; 428 case PCI_QLOGIC_ISP5432: 429 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 430 break; 431 case PCI_QLOGIC_ISP6312: 432 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 433 break; 434 case PCI_QLOGIC_ISP6322: 435 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 436 break; 437 default: 438 return (ENXIO); 439 } 440 if (isp_announced == 0 && bootverbose) { 441 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 442 "Core Version %d.%d\n", 443 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 444 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 445 isp_announced++; 446 } 447 /* 448 * XXXX: Here is where we might load the f/w module 449 * XXXX: (or increase a reference count to it). 450 */ 451 return (BUS_PROBE_DEFAULT); 452 } 453 454 static void 455 isp_get_generic_options(device_t dev, ispsoftc_t *isp) 456 { 457 int tval; 458 459 /* 460 * Figure out if we're supposed to skip this one. 461 */ 462 tval = 0; 463 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 464 device_printf(dev, "disabled at user request\n"); 465 isp->isp_osinfo.disabled = 1; 466 return; 467 } 468 469 tval = 0; 470 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 471 isp->isp_confopts |= ISP_CFG_NORELOAD; 472 } 473 tval = 0; 474 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 475 isp->isp_confopts |= ISP_CFG_NONVRAM; 476 } 477 tval = 0; 478 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 479 if (tval) { 480 isp->isp_dblev = tval; 481 } else { 482 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 483 } 484 if (bootverbose) { 485 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 486 } 487 tval = -1; 488 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 489 if (tval > 0 && tval < 127) { 490 isp_nvports = tval; 491 } 492 tval = 1; 493 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 494 isp_autoconfig = tval; 495 tval = 7; 496 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 497 isp_quickboot_time = tval; 498 } 499 500 static void 501 isp_get_pci_options(device_t dev, int *m1, int *m2) 502 { 503 int tval; 504 /* 505 * Which we should try first - memory mapping or i/o mapping? 506 * 507 * We used to try memory first followed by i/o on alpha, otherwise 508 * the reverse, but we should just try memory first all the time now. 509 */ 510 *m1 = PCIM_CMD_MEMEN; 511 *m2 = PCIM_CMD_PORTEN; 512 513 tval = 0; 514 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 515 *m1 = PCIM_CMD_PORTEN; 516 *m2 = PCIM_CMD_MEMEN; 517 } 518 tval = 0; 519 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 520 *m1 = PCIM_CMD_MEMEN; 521 *m2 = PCIM_CMD_PORTEN; 522 } 523 } 524 525 static void 526 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 527 { 528 const char *sptr; 529 int tval = 0; 530 531 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 532 if (IS_FC(isp)) { 533 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 534 } else { 535 #ifdef __sparc64__ 536 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 537 #else 538 ISP_SPI_PC(isp, chan)->iid = 7; 539 #endif 540 } 541 } else { 542 if (IS_FC(isp)) { 543 ISP_FC_PC(isp, chan)->default_id = tval - chan; 544 } else { 545 ISP_SPI_PC(isp, chan)->iid = tval; 546 } 547 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 548 } 549 550 tval = -1; 551 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 552 switch (tval) { 553 case ISP_ROLE_NONE: 554 case ISP_ROLE_INITIATOR: 555 case ISP_ROLE_TARGET: 556 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 557 device_printf(dev, "setting role to 0x%x\n", tval); 558 break; 559 default: 560 tval = -1; 561 break; 562 } 563 } 564 if (tval == -1) { 565 tval = ISP_DEFAULT_ROLES; 566 } 567 568 if (IS_SCSI(isp)) { 569 ISP_SPI_PC(isp, chan)->def_role = tval; 570 return; 571 } 572 ISP_FC_PC(isp, chan)->def_role = tval; 573 574 tval = 0; 575 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 576 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 577 } 578 sptr = 0; 579 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", (const char **) &sptr) == 0 && sptr != 0) { 580 if (strcmp(sptr, "lport") == 0) { 581 isp->isp_confopts |= ISP_CFG_LPORT; 582 } else if (strcmp(sptr, "nport") == 0) { 583 isp->isp_confopts |= ISP_CFG_NPORT; 584 } else if (strcmp(sptr, "lport-only") == 0) { 585 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 586 } else if (strcmp(sptr, "nport-only") == 0) { 587 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 588 } 589 } 590 591 tval = 0; 592 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "nofctape", &tval); 593 if (tval) { 594 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 595 } 596 597 tval = 0; 598 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "fctape", &tval); 599 if (tval) { 600 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE; 601 isp->isp_confopts |= ISP_CFG_FCTAPE; 602 } 603 604 605 /* 606 * Because the resource_*_value functions can neither return 607 * 64 bit integer values, nor can they be directly coerced 608 * to interpret the right hand side of the assignment as 609 * you want them to interpret it, we have to force WWN 610 * hint replacement to specify WWN strings with a leading 611 * 'w' (e..g w50000000aaaa0001). Sigh. 612 */ 613 sptr = 0; 614 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", (const char **) &sptr); 615 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 616 char *eptr = 0; 617 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 618 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 619 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 620 ISP_FC_PC(isp, chan)->def_wwpn = 0; 621 } 622 } 623 624 sptr = 0; 625 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", (const char **) &sptr); 626 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 627 char *eptr = 0; 628 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 629 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 630 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 631 ISP_FC_PC(isp, chan)->def_wwnn = 0; 632 } 633 } 634 635 tval = 0; 636 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 637 if (tval >= 0 && tval < 256) { 638 ISP_FC_PC(isp, chan)->hysteresis = tval; 639 } else { 640 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 641 } 642 643 tval = -1; 644 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 645 if (tval >= 0 && tval < 0xffff) { 646 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 647 } else { 648 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 649 } 650 651 tval = -1; 652 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 653 if (tval >= 0 && tval < 0xffff) { 654 ISP_FC_PC(isp, chan)->gone_device_time = tval; 655 } else { 656 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 657 } 658 } 659 660 static int 661 isp_pci_attach(device_t dev) 662 { 663 int i, m1, m2, locksetup = 0; 664 uint32_t data, cmd, linesz, did; 665 struct isp_pcisoftc *pcs; 666 ispsoftc_t *isp; 667 size_t psize, xsize; 668 char fwname[32]; 669 670 pcs = device_get_softc(dev); 671 if (pcs == NULL) { 672 device_printf(dev, "cannot get softc\n"); 673 return (ENOMEM); 674 } 675 memset(pcs, 0, sizeof (*pcs)); 676 677 pcs->pci_dev = dev; 678 isp = &pcs->pci_isp; 679 isp->isp_dev = dev; 680 isp->isp_nchan = 1; 681 if (sizeof (bus_addr_t) > 4) 682 isp->isp_osinfo.sixtyfourbit = 1; 683 684 /* 685 * Get Generic Options 686 */ 687 isp_nvports = 0; 688 isp_get_generic_options(dev, isp); 689 690 /* 691 * Check to see if options have us disabled 692 */ 693 if (isp->isp_osinfo.disabled) { 694 /* 695 * But return zero to preserve unit numbering 696 */ 697 return (0); 698 } 699 700 /* 701 * Get PCI options- which in this case are just mapping preferences. 702 */ 703 isp_get_pci_options(dev, &m1, &m2); 704 705 linesz = PCI_DFLT_LNSZ; 706 pcs->irq = pcs->regs = NULL; 707 pcs->rgd = pcs->rtp = pcs->iqd = 0; 708 709 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 710 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 711 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 712 if (pcs->regs == NULL) { 713 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 714 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 715 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 716 } 717 if (pcs->regs == NULL) { 718 device_printf(dev, "unable to map any ports\n"); 719 goto bad; 720 } 721 if (bootverbose) { 722 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 723 } 724 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 725 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 726 727 pcs->pci_dev = dev; 728 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 729 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 730 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 731 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 732 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 733 734 switch (pci_get_devid(dev)) { 735 case PCI_QLOGIC_ISP1020: 736 did = 0x1040; 737 isp->isp_mdvec = &mdvec; 738 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 739 break; 740 case PCI_QLOGIC_ISP1080: 741 did = 0x1080; 742 isp->isp_mdvec = &mdvec_1080; 743 isp->isp_type = ISP_HA_SCSI_1080; 744 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 745 break; 746 case PCI_QLOGIC_ISP1240: 747 did = 0x1080; 748 isp->isp_mdvec = &mdvec_1080; 749 isp->isp_type = ISP_HA_SCSI_1240; 750 isp->isp_nchan = 2; 751 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 752 break; 753 case PCI_QLOGIC_ISP1280: 754 did = 0x1080; 755 isp->isp_mdvec = &mdvec_1080; 756 isp->isp_type = ISP_HA_SCSI_1280; 757 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 758 break; 759 case PCI_QLOGIC_ISP10160: 760 did = 0x12160; 761 isp->isp_mdvec = &mdvec_12160; 762 isp->isp_type = ISP_HA_SCSI_10160; 763 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 764 break; 765 case PCI_QLOGIC_ISP12160: 766 did = 0x12160; 767 isp->isp_nchan = 2; 768 isp->isp_mdvec = &mdvec_12160; 769 isp->isp_type = ISP_HA_SCSI_12160; 770 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 771 break; 772 case PCI_QLOGIC_ISP2100: 773 did = 0x2100; 774 isp->isp_mdvec = &mdvec_2100; 775 isp->isp_type = ISP_HA_FC_2100; 776 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 777 if (pci_get_revid(dev) < 3) { 778 /* 779 * XXX: Need to get the actual revision 780 * XXX: number of the 2100 FB. At any rate, 781 * XXX: lower cache line size for early revision 782 * XXX; boards. 783 */ 784 linesz = 1; 785 } 786 break; 787 case PCI_QLOGIC_ISP2200: 788 did = 0x2200; 789 isp->isp_mdvec = &mdvec_2200; 790 isp->isp_type = ISP_HA_FC_2200; 791 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 792 break; 793 case PCI_QLOGIC_ISP2300: 794 did = 0x2300; 795 isp->isp_mdvec = &mdvec_2300; 796 isp->isp_type = ISP_HA_FC_2300; 797 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 798 break; 799 case PCI_QLOGIC_ISP2312: 800 case PCI_QLOGIC_ISP6312: 801 did = 0x2300; 802 isp->isp_mdvec = &mdvec_2300; 803 isp->isp_type = ISP_HA_FC_2312; 804 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 805 break; 806 case PCI_QLOGIC_ISP2322: 807 case PCI_QLOGIC_ISP6322: 808 did = 0x2322; 809 isp->isp_mdvec = &mdvec_2300; 810 isp->isp_type = ISP_HA_FC_2322; 811 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 812 break; 813 case PCI_QLOGIC_ISP2422: 814 case PCI_QLOGIC_ISP2432: 815 did = 0x2400; 816 isp->isp_nchan += isp_nvports; 817 isp->isp_mdvec = &mdvec_2400; 818 isp->isp_type = ISP_HA_FC_2400; 819 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 820 break; 821 case PCI_QLOGIC_ISP2532: 822 did = 0x2500; 823 isp->isp_nchan += isp_nvports; 824 isp->isp_mdvec = &mdvec_2500; 825 isp->isp_type = ISP_HA_FC_2500; 826 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 827 break; 828 case PCI_QLOGIC_ISP5432: 829 did = 0x2500; 830 isp->isp_mdvec = &mdvec_2500; 831 isp->isp_type = ISP_HA_FC_2500; 832 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 833 break; 834 default: 835 device_printf(dev, "unknown device type\n"); 836 goto bad; 837 break; 838 } 839 isp->isp_revision = pci_get_revid(dev); 840 841 if (IS_FC(isp)) { 842 psize = sizeof (fcparam); 843 xsize = sizeof (struct isp_fc); 844 } else { 845 psize = sizeof (sdparam); 846 xsize = sizeof (struct isp_spi); 847 } 848 psize *= isp->isp_nchan; 849 xsize *= isp->isp_nchan; 850 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 851 if (isp->isp_param == NULL) { 852 device_printf(dev, "cannot allocate parameter data\n"); 853 goto bad; 854 } 855 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 856 if (isp->isp_osinfo.pc.ptr == NULL) { 857 device_printf(dev, "cannot allocate parameter data\n"); 858 goto bad; 859 } 860 861 /* 862 * Now that we know who we are (roughly) get/set specific options 863 */ 864 for (i = 0; i < isp->isp_nchan; i++) { 865 isp_get_specific_options(dev, i, isp); 866 } 867 868 /* 869 * The 'it' suffix really only matters for SCSI cards in target mode. 870 */ 871 isp->isp_osinfo.fw = NULL; 872 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 873 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 874 isp->isp_osinfo.fw = firmware_get(fwname); 875 } else if (IS_24XX(isp)) { 876 snprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 877 isp->isp_osinfo.fw = firmware_get(fwname); 878 } 879 if (isp->isp_osinfo.fw == NULL) { 880 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 881 isp->isp_osinfo.fw = firmware_get(fwname); 882 } 883 if (isp->isp_osinfo.fw != NULL) { 884 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 885 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 886 } 887 888 /* 889 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 890 */ 891 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 892 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 893 if (IS_2300(isp)) { /* per QLogic errata */ 894 cmd &= ~PCIM_CMD_INVEN; 895 } 896 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 897 cmd &= ~PCIM_CMD_INTX_DISABLE; 898 } 899 if (IS_24XX(isp)) { 900 cmd &= ~PCIM_CMD_INTX_DISABLE; 901 } 902 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 903 904 /* 905 * Make sure the Cache Line Size register is set sensibly. 906 */ 907 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 908 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 909 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 910 data = linesz; 911 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 912 } 913 914 /* 915 * Make sure the Latency Timer is sane. 916 */ 917 data = pci_read_config(dev, PCIR_LATTIMER, 1); 918 if (data < PCI_DFLT_LTNCY) { 919 data = PCI_DFLT_LTNCY; 920 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 921 pci_write_config(dev, PCIR_LATTIMER, data, 1); 922 } 923 924 /* 925 * Make sure we've disabled the ROM. 926 */ 927 data = pci_read_config(dev, PCIR_ROMADDR, 4); 928 data &= ~1; 929 pci_write_config(dev, PCIR_ROMADDR, data, 4); 930 931 /* 932 * Do MSI 933 * 934 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 935 */ 936 if (IS_24XX(isp) || IS_2322(isp)) { 937 pcs->msicount = pci_msi_count(dev); 938 if (pcs->msicount > 1) { 939 pcs->msicount = 1; 940 } 941 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 942 pcs->iqd = 1; 943 } else { 944 pcs->iqd = 0; 945 } 946 } 947 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE); 948 if (pcs->irq == NULL) { 949 device_printf(dev, "could not allocate interrupt\n"); 950 goto bad; 951 } 952 953 /* Make sure the lock is set up. */ 954 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 955 locksetup++; 956 957 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 958 device_printf(dev, "could not setup interrupt\n"); 959 goto bad; 960 } 961 962 /* 963 * Last minute checks... 964 */ 965 if (IS_23XX(isp) || IS_24XX(isp)) { 966 isp->isp_port = pci_get_function(dev); 967 } 968 969 /* 970 * Make sure we're in reset state. 971 */ 972 ISP_LOCK(isp); 973 isp_reset(isp, 1); 974 if (isp->isp_state != ISP_RESETSTATE) { 975 ISP_UNLOCK(isp); 976 goto bad; 977 } 978 isp_init(isp); 979 if (isp->isp_state == ISP_INITSTATE) { 980 isp->isp_state = ISP_RUNSTATE; 981 } 982 ISP_UNLOCK(isp); 983 if (isp_attach(isp)) { 984 ISP_LOCK(isp); 985 isp_uninit(isp); 986 ISP_UNLOCK(isp); 987 goto bad; 988 } 989 return (0); 990 991 bad: 992 if (pcs->ih) { 993 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 994 } 995 if (locksetup) { 996 mtx_destroy(&isp->isp_osinfo.lock); 997 } 998 if (pcs->irq) { 999 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1000 } 1001 if (pcs->msicount) { 1002 pci_release_msi(dev); 1003 } 1004 if (pcs->regs) { 1005 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1006 } 1007 if (pcs->pci_isp.isp_param) { 1008 free(pcs->pci_isp.isp_param, M_DEVBUF); 1009 pcs->pci_isp.isp_param = NULL; 1010 } 1011 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1012 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1013 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1014 } 1015 return (ENXIO); 1016 } 1017 1018 static int 1019 isp_pci_detach(device_t dev) 1020 { 1021 struct isp_pcisoftc *pcs; 1022 ispsoftc_t *isp; 1023 int status; 1024 1025 pcs = device_get_softc(dev); 1026 if (pcs == NULL) { 1027 return (ENXIO); 1028 } 1029 isp = (ispsoftc_t *) pcs; 1030 status = isp_detach(isp); 1031 if (status) 1032 return (status); 1033 ISP_LOCK(isp); 1034 isp_uninit(isp); 1035 if (pcs->ih) { 1036 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1037 } 1038 ISP_UNLOCK(isp); 1039 mtx_destroy(&isp->isp_osinfo.lock); 1040 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1041 if (pcs->msicount) { 1042 pci_release_msi(dev); 1043 } 1044 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1045 /* 1046 * XXX: THERE IS A LOT OF LEAKAGE HERE 1047 */ 1048 if (pcs->pci_isp.isp_param) { 1049 free(pcs->pci_isp.isp_param, M_DEVBUF); 1050 pcs->pci_isp.isp_param = NULL; 1051 } 1052 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1053 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1054 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1055 } 1056 return (0); 1057 } 1058 1059 #define IspVirt2Off(a, x) \ 1060 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1061 _BLK_REG_SHFT] + ((x) & 0xfff)) 1062 1063 #define BXR2(isp, off) \ 1064 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1065 #define BXW2(isp, off, v) \ 1066 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1067 #define BXR4(isp, off) \ 1068 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1069 #define BXW4(isp, off, v) \ 1070 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1071 1072 1073 static ISP_INLINE int 1074 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1075 { 1076 uint32_t val0, val1; 1077 int i = 0; 1078 1079 do { 1080 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1081 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1082 } while (val0 != val1 && ++i < 1000); 1083 if (val0 != val1) { 1084 return (1); 1085 } 1086 *rp = val0; 1087 return (0); 1088 } 1089 1090 static int 1091 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1092 { 1093 uint16_t isr, sema; 1094 1095 if (IS_2100(isp)) { 1096 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1097 return (0); 1098 } 1099 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1100 return (0); 1101 } 1102 } else { 1103 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1104 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1105 } 1106 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1107 isr &= INT_PENDING_MASK(isp); 1108 sema &= BIU_SEMA_LOCK; 1109 if (isr == 0 && sema == 0) { 1110 return (0); 1111 } 1112 *isrp = isr; 1113 if ((*semap = sema) != 0) { 1114 if (IS_2100(isp)) { 1115 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1116 return (0); 1117 } 1118 } else { 1119 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1120 } 1121 } 1122 return (1); 1123 } 1124 1125 static int 1126 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1127 { 1128 uint32_t hccr; 1129 uint32_t r2hisr; 1130 1131 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1132 *isrp = 0; 1133 return (0); 1134 } 1135 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1136 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1137 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1138 *isrp = 0; 1139 return (0); 1140 } 1141 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1142 case ISPR2HST_ROM_MBX_OK: 1143 case ISPR2HST_ROM_MBX_FAIL: 1144 case ISPR2HST_MBX_OK: 1145 case ISPR2HST_MBX_FAIL: 1146 case ISPR2HST_ASYNC_EVENT: 1147 *isrp = r2hisr & 0xffff; 1148 *mbox0p = (r2hisr >> 16); 1149 *semap = 1; 1150 return (1); 1151 case ISPR2HST_RIO_16: 1152 *isrp = r2hisr & 0xffff; 1153 *mbox0p = ASYNC_RIO16_1; 1154 *semap = 1; 1155 return (1); 1156 case ISPR2HST_FPOST: 1157 *isrp = r2hisr & 0xffff; 1158 *mbox0p = ASYNC_CMD_CMPLT; 1159 *semap = 1; 1160 return (1); 1161 case ISPR2HST_FPOST_CTIO: 1162 *isrp = r2hisr & 0xffff; 1163 *mbox0p = ASYNC_CTIO_DONE; 1164 *semap = 1; 1165 return (1); 1166 case ISPR2HST_RSPQ_UPDATE: 1167 *isrp = r2hisr & 0xffff; 1168 *mbox0p = 0; 1169 *semap = 0; 1170 return (1); 1171 default: 1172 hccr = ISP_READ(isp, HCCR); 1173 if (hccr & HCCR_PAUSE) { 1174 ISP_WRITE(isp, HCCR, HCCR_RESET); 1175 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1176 ISP_WRITE(isp, BIU_ICR, 0); 1177 } else { 1178 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1179 } 1180 return (0); 1181 } 1182 } 1183 1184 static int 1185 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1186 { 1187 uint32_t r2hisr; 1188 1189 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1190 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1191 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1192 *isrp = 0; 1193 return (0); 1194 } 1195 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1196 case ISP2400R2HST_ROM_MBX_OK: 1197 case ISP2400R2HST_ROM_MBX_FAIL: 1198 case ISP2400R2HST_MBX_OK: 1199 case ISP2400R2HST_MBX_FAIL: 1200 case ISP2400R2HST_ASYNC_EVENT: 1201 *isrp = r2hisr & 0xffff; 1202 *mbox0p = (r2hisr >> 16); 1203 *semap = 1; 1204 return (1); 1205 case ISP2400R2HST_RSPQ_UPDATE: 1206 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1207 case ISP2400R2HST_ATIO_RQST_UPDATE: 1208 *isrp = r2hisr & 0xffff; 1209 *mbox0p = 0; 1210 *semap = 0; 1211 return (1); 1212 default: 1213 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1214 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1215 return (0); 1216 } 1217 } 1218 1219 static uint32_t 1220 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1221 { 1222 uint16_t rv; 1223 int oldconf = 0; 1224 1225 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1226 /* 1227 * We will assume that someone has paused the RISC processor. 1228 */ 1229 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1230 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1231 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1232 } 1233 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1234 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1235 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1236 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1237 } 1238 return (rv); 1239 } 1240 1241 static void 1242 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1243 { 1244 int oldconf = 0; 1245 1246 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1247 /* 1248 * We will assume that someone has paused the RISC processor. 1249 */ 1250 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1251 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1252 oldconf | BIU_PCI_CONF1_SXP); 1253 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1254 } 1255 BXW2(isp, IspVirt2Off(isp, regoff), val); 1256 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1257 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1258 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1259 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1260 } 1261 1262 } 1263 1264 static uint32_t 1265 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1266 { 1267 uint32_t rv, oc = 0; 1268 1269 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1270 uint32_t tc; 1271 /* 1272 * We will assume that someone has paused the RISC processor. 1273 */ 1274 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1275 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1276 if (regoff & SXP_BANK1_SELECT) 1277 tc |= BIU_PCI1080_CONF1_SXP1; 1278 else 1279 tc |= BIU_PCI1080_CONF1_SXP0; 1280 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1281 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1282 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1283 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1284 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1285 oc | BIU_PCI1080_CONF1_DMA); 1286 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1287 } 1288 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1289 if (oc) { 1290 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1291 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1292 } 1293 return (rv); 1294 } 1295 1296 static void 1297 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1298 { 1299 int oc = 0; 1300 1301 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1302 uint32_t tc; 1303 /* 1304 * We will assume that someone has paused the RISC processor. 1305 */ 1306 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1307 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1308 if (regoff & SXP_BANK1_SELECT) 1309 tc |= BIU_PCI1080_CONF1_SXP1; 1310 else 1311 tc |= BIU_PCI1080_CONF1_SXP0; 1312 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1313 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1314 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1315 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1316 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1317 oc | BIU_PCI1080_CONF1_DMA); 1318 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1319 } 1320 BXW2(isp, IspVirt2Off(isp, regoff), val); 1321 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1322 if (oc) { 1323 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1324 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1325 } 1326 } 1327 1328 static uint32_t 1329 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1330 { 1331 uint32_t rv; 1332 int block = regoff & _BLK_REG_MASK; 1333 1334 switch (block) { 1335 case BIU_BLOCK: 1336 break; 1337 case MBOX_BLOCK: 1338 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1339 case SXP_BLOCK: 1340 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1341 return (0xffffffff); 1342 case RISC_BLOCK: 1343 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1344 return (0xffffffff); 1345 case DMA_BLOCK: 1346 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1347 return (0xffffffff); 1348 default: 1349 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1350 return (0xffffffff); 1351 } 1352 1353 1354 switch (regoff) { 1355 case BIU2400_FLASH_ADDR: 1356 case BIU2400_FLASH_DATA: 1357 case BIU2400_ICR: 1358 case BIU2400_ISR: 1359 case BIU2400_CSR: 1360 case BIU2400_REQINP: 1361 case BIU2400_REQOUTP: 1362 case BIU2400_RSPINP: 1363 case BIU2400_RSPOUTP: 1364 case BIU2400_PRI_REQINP: 1365 case BIU2400_PRI_REQOUTP: 1366 case BIU2400_ATIO_RSPINP: 1367 case BIU2400_ATIO_RSPOUTP: 1368 case BIU2400_HCCR: 1369 case BIU2400_GPIOD: 1370 case BIU2400_GPIOE: 1371 case BIU2400_HSEMA: 1372 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1373 break; 1374 case BIU2400_R2HSTSLO: 1375 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1376 break; 1377 case BIU2400_R2HSTSHI: 1378 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1379 break; 1380 default: 1381 isp_prt(isp, ISP_LOGERR, 1382 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1383 rv = 0xffffffff; 1384 break; 1385 } 1386 return (rv); 1387 } 1388 1389 static void 1390 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1391 { 1392 int block = regoff & _BLK_REG_MASK; 1393 1394 switch (block) { 1395 case BIU_BLOCK: 1396 break; 1397 case MBOX_BLOCK: 1398 BXW2(isp, IspVirt2Off(isp, regoff), val); 1399 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1400 return; 1401 case SXP_BLOCK: 1402 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1403 return; 1404 case RISC_BLOCK: 1405 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1406 return; 1407 case DMA_BLOCK: 1408 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1409 return; 1410 default: 1411 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1412 regoff); 1413 break; 1414 } 1415 1416 switch (regoff) { 1417 case BIU2400_FLASH_ADDR: 1418 case BIU2400_FLASH_DATA: 1419 case BIU2400_ICR: 1420 case BIU2400_ISR: 1421 case BIU2400_CSR: 1422 case BIU2400_REQINP: 1423 case BIU2400_REQOUTP: 1424 case BIU2400_RSPINP: 1425 case BIU2400_RSPOUTP: 1426 case BIU2400_PRI_REQINP: 1427 case BIU2400_PRI_REQOUTP: 1428 case BIU2400_ATIO_RSPINP: 1429 case BIU2400_ATIO_RSPOUTP: 1430 case BIU2400_HCCR: 1431 case BIU2400_GPIOD: 1432 case BIU2400_GPIOE: 1433 case BIU2400_HSEMA: 1434 BXW4(isp, IspVirt2Off(isp, regoff), val); 1435 #ifdef MEMORYBARRIERW 1436 if (regoff == BIU2400_REQINP || 1437 regoff == BIU2400_RSPOUTP || 1438 regoff == BIU2400_PRI_REQINP || 1439 regoff == BIU2400_ATIO_RSPOUTP) 1440 MEMORYBARRIERW(isp, SYNC_REG, 1441 IspVirt2Off(isp, regoff), 4, -1) 1442 else 1443 #endif 1444 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1445 break; 1446 default: 1447 isp_prt(isp, ISP_LOGERR, 1448 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1449 break; 1450 } 1451 } 1452 1453 1454 struct imush { 1455 ispsoftc_t *isp; 1456 caddr_t vbase; 1457 int chan; 1458 int error; 1459 }; 1460 1461 static void imc(void *, bus_dma_segment_t *, int, int); 1462 static void imc1(void *, bus_dma_segment_t *, int, int); 1463 1464 static void 1465 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1466 { 1467 struct imush *imushp = (struct imush *) arg; 1468 isp_ecmd_t *ecmd; 1469 1470 if (error) { 1471 imushp->error = error; 1472 return; 1473 } 1474 if (nseg != 1) { 1475 imushp->error = EINVAL; 1476 return; 1477 } 1478 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1479 1480 imushp->isp->isp_rquest = imushp->vbase; 1481 imushp->isp->isp_rquest_dma = segs->ds_addr; 1482 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1483 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1484 1485 imushp->isp->isp_result_dma = segs->ds_addr; 1486 imushp->isp->isp_result = imushp->vbase; 1487 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1488 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1489 1490 if (imushp->isp->isp_type >= ISP_HA_FC_2300) { 1491 imushp->isp->isp_osinfo.ecmd_dma = segs->ds_addr; 1492 imushp->isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)imushp->vbase; 1493 imushp->isp->isp_osinfo.ecmd_base = imushp->isp->isp_osinfo.ecmd_free; 1494 for (ecmd = imushp->isp->isp_osinfo.ecmd_free; ecmd < &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) { 1495 if (ecmd == &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) { 1496 ecmd->next = NULL; 1497 } else { 1498 ecmd->next = ecmd + 1; 1499 } 1500 } 1501 } 1502 #ifdef ISP_TARGET_MODE 1503 segs->ds_addr += (N_XCMDS * XCMD_SIZE); 1504 imushp->vbase += (N_XCMDS * XCMD_SIZE); 1505 if (IS_24XX(imushp->isp)) { 1506 imushp->isp->isp_atioq_dma = segs->ds_addr; 1507 imushp->isp->isp_atioq = imushp->vbase; 1508 } 1509 #endif 1510 } 1511 1512 static void 1513 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1514 { 1515 struct imush *imushp = (struct imush *) arg; 1516 if (error) { 1517 imushp->error = error; 1518 return; 1519 } 1520 if (nseg != 1) { 1521 imushp->error = EINVAL; 1522 return; 1523 } 1524 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1525 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1526 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1527 } 1528 1529 static int 1530 isp_pci_mbxdma(ispsoftc_t *isp) 1531 { 1532 caddr_t base; 1533 uint32_t len, nsegs; 1534 int i, error, cmap = 0; 1535 bus_size_t slim; /* segment size */ 1536 bus_addr_t llim; /* low limit of unavailable dma */ 1537 bus_addr_t hlim; /* high limit of unavailable dma */ 1538 struct imush im; 1539 1540 /* 1541 * Already been here? If so, leave... 1542 */ 1543 if (isp->isp_rquest) { 1544 return (0); 1545 } 1546 ISP_UNLOCK(isp); 1547 1548 if (isp->isp_maxcmds == 0) { 1549 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1550 ISP_LOCK(isp); 1551 return (1); 1552 } 1553 1554 hlim = BUS_SPACE_MAXADDR; 1555 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1556 if (sizeof (bus_size_t) > 4) { 1557 slim = (bus_size_t) (1ULL << 32); 1558 } else { 1559 slim = (bus_size_t) (1UL << 31); 1560 } 1561 llim = BUS_SPACE_MAXADDR; 1562 } else { 1563 llim = BUS_SPACE_MAXADDR_32BIT; 1564 slim = (1UL << 24); 1565 } 1566 1567 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1568 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1569 if (isp->isp_osinfo.pcmd_pool == NULL) { 1570 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1571 ISP_LOCK(isp); 1572 return (1); 1573 } 1574 1575 if (isp->isp_osinfo.sixtyfourbit) { 1576 nsegs = ISP_NSEG64_MAX; 1577 } else { 1578 nsegs = ISP_NSEG_MAX; 1579 } 1580 #ifdef ISP_TARGET_MODE 1581 /* 1582 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1583 */ 1584 if (IS_SCSI(isp) && isp->isp_osinfo.sixtyfourbit) { 1585 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1586 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1587 ISP_LOCK(isp); 1588 return (1); 1589 } 1590 #endif 1591 1592 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, &isp->isp_osinfo.dmat)) { 1593 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1594 ISP_LOCK(isp); 1595 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1596 return (1); 1597 } 1598 1599 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1600 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1601 if (isp->isp_xflist == NULL) { 1602 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1603 ISP_LOCK(isp); 1604 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1605 return (1); 1606 } 1607 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1608 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1609 } 1610 isp->isp_xffree = isp->isp_xflist; 1611 #ifdef ISP_TARGET_MODE 1612 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1613 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1614 if (isp->isp_tgtlist == NULL) { 1615 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1616 free(isp->isp_xflist, M_DEVBUF); 1617 ISP_LOCK(isp); 1618 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1619 return (1); 1620 } 1621 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1622 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1623 } 1624 isp->isp_tgtfree = isp->isp_tgtlist; 1625 #endif 1626 1627 /* 1628 * Allocate and map the request and result queues (and ATIO queue 1629 * if we're a 2400 supporting target mode), and a region for 1630 * external dma addressable command/status structures (23XX and 1631 * later). 1632 */ 1633 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1634 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1635 #ifdef ISP_TARGET_MODE 1636 if (IS_24XX(isp)) { 1637 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1638 } 1639 #endif 1640 if (isp->isp_type >= ISP_HA_FC_2300) { 1641 len += (N_XCMDS * XCMD_SIZE); 1642 } 1643 1644 /* 1645 * Create a tag for the control spaces. We don't always need this 1646 * to be 32 bits, but we do this for simplicity and speed's sake. 1647 */ 1648 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, slim, 0, &isp->isp_osinfo.cdmat)) { 1649 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1650 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1651 free(isp->isp_xflist, M_DEVBUF); 1652 #ifdef ISP_TARGET_MODE 1653 free(isp->isp_tgtlist, M_DEVBUF); 1654 #endif 1655 ISP_LOCK(isp); 1656 return (1); 1657 } 1658 1659 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1660 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1661 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1662 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1663 free(isp->isp_xflist, M_DEVBUF); 1664 #ifdef ISP_TARGET_MODE 1665 free(isp->isp_tgtlist, M_DEVBUF); 1666 #endif 1667 ISP_LOCK(isp); 1668 return (1); 1669 } 1670 1671 im.isp = isp; 1672 im.chan = 0; 1673 im.vbase = base; 1674 im.error = 0; 1675 1676 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1677 if (im.error) { 1678 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1679 goto bad; 1680 } 1681 1682 if (IS_FC(isp)) { 1683 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1684 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1685 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1686 goto bad; 1687 } 1688 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1689 bus_dma_tag_destroy(fc->tdmat); 1690 goto bad; 1691 } 1692 im.isp = isp; 1693 im.chan = cmap; 1694 im.vbase = base; 1695 im.error = 0; 1696 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1697 if (im.error) { 1698 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1699 bus_dma_tag_destroy(fc->tdmat); 1700 goto bad; 1701 } 1702 if (isp->isp_type >= ISP_HA_FC_2300) { 1703 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) { 1704 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO); 1705 if (n == NULL) { 1706 while (fc->nexus_free_list) { 1707 n = fc->nexus_free_list; 1708 fc->nexus_free_list = n->next; 1709 free(n, M_DEVBUF); 1710 } 1711 goto bad; 1712 } 1713 n->next = fc->nexus_free_list; 1714 fc->nexus_free_list = n; 1715 } 1716 } 1717 } 1718 } 1719 1720 for (i = 0; i < isp->isp_maxcmds; i++) { 1721 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1722 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1723 if (error) { 1724 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1725 while (--i >= 0) { 1726 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1727 } 1728 goto bad; 1729 } 1730 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1731 if (i == isp->isp_maxcmds-1) { 1732 pcmd->next = NULL; 1733 } else { 1734 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1735 } 1736 } 1737 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1738 ISP_LOCK(isp); 1739 return (0); 1740 1741 bad: 1742 while (--cmap >= 0) { 1743 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1744 bus_dmamap_unload(fc->tdmat, fc->tdmap); 1745 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1746 bus_dma_tag_destroy(fc->tdmat); 1747 while (fc->nexus_free_list) { 1748 struct isp_nexus *n = fc->nexus_free_list; 1749 fc->nexus_free_list = n->next; 1750 free(n, M_DEVBUF); 1751 } 1752 } 1753 if (isp->isp_rquest_dma != 0) 1754 bus_dmamap_unload(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap); 1755 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1756 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1757 free(isp->isp_xflist, M_DEVBUF); 1758 #ifdef ISP_TARGET_MODE 1759 free(isp->isp_tgtlist, M_DEVBUF); 1760 #endif 1761 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1762 isp->isp_rquest = NULL; 1763 ISP_LOCK(isp); 1764 return (1); 1765 } 1766 1767 typedef struct { 1768 ispsoftc_t *isp; 1769 void *cmd_token; 1770 void *rq; /* original request */ 1771 int error; 1772 bus_size_t mapsize; 1773 } mush_t; 1774 1775 #define MUSHERR_NOQENTRIES -2 1776 1777 #ifdef ISP_TARGET_MODE 1778 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1779 static void tdma2(void *, bus_dma_segment_t *, int, int); 1780 1781 static void 1782 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1783 { 1784 mush_t *mp; 1785 mp = (mush_t *)arg; 1786 mp->mapsize = mapsize; 1787 tdma2(arg, dm_segs, nseg, error); 1788 } 1789 1790 static void 1791 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1792 { 1793 mush_t *mp; 1794 ispsoftc_t *isp; 1795 struct ccb_scsiio *csio; 1796 isp_ddir_t ddir; 1797 ispreq_t *rq; 1798 1799 mp = (mush_t *) arg; 1800 if (error) { 1801 mp->error = error; 1802 return; 1803 } 1804 csio = mp->cmd_token; 1805 isp = mp->isp; 1806 rq = mp->rq; 1807 if (nseg) { 1808 if (isp->isp_osinfo.sixtyfourbit) { 1809 if (nseg >= ISP_NSEG64_MAX) { 1810 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1811 mp->error = EFAULT; 1812 return; 1813 } 1814 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1815 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1816 } 1817 } else { 1818 if (nseg >= ISP_NSEG_MAX) { 1819 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1820 mp->error = EFAULT; 1821 return; 1822 } 1823 } 1824 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1825 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1826 ddir = ISP_TO_DEVICE; 1827 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1828 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1829 ddir = ISP_FROM_DEVICE; 1830 } else { 1831 dm_segs = NULL; 1832 nseg = 0; 1833 ddir = ISP_NOXFR; 1834 } 1835 } else { 1836 dm_segs = NULL; 1837 nseg = 0; 1838 ddir = ISP_NOXFR; 1839 } 1840 1841 error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len); 1842 switch (error) { 1843 case CMD_EAGAIN: 1844 mp->error = MUSHERR_NOQENTRIES; 1845 case CMD_QUEUED: 1846 break; 1847 default: 1848 mp->error = EIO; 1849 } 1850 } 1851 #endif 1852 1853 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1854 static void dma2(void *, bus_dma_segment_t *, int, int); 1855 1856 static void 1857 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1858 { 1859 mush_t *mp; 1860 mp = (mush_t *)arg; 1861 mp->mapsize = mapsize; 1862 dma2(arg, dm_segs, nseg, error); 1863 } 1864 1865 static void 1866 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1867 { 1868 mush_t *mp; 1869 ispsoftc_t *isp; 1870 struct ccb_scsiio *csio; 1871 isp_ddir_t ddir; 1872 ispreq_t *rq; 1873 1874 mp = (mush_t *) arg; 1875 if (error) { 1876 mp->error = error; 1877 return; 1878 } 1879 csio = mp->cmd_token; 1880 isp = mp->isp; 1881 rq = mp->rq; 1882 if (nseg) { 1883 if (isp->isp_osinfo.sixtyfourbit) { 1884 if (nseg >= ISP_NSEG64_MAX) { 1885 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1886 mp->error = EFAULT; 1887 return; 1888 } 1889 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1890 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1891 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1892 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1893 } 1894 } else { 1895 if (nseg >= ISP_NSEG_MAX) { 1896 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1897 mp->error = EFAULT; 1898 return; 1899 } 1900 } 1901 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1902 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1903 ddir = ISP_FROM_DEVICE; 1904 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1905 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1906 ddir = ISP_TO_DEVICE; 1907 } else { 1908 ddir = ISP_NOXFR; 1909 } 1910 } else { 1911 dm_segs = NULL; 1912 nseg = 0; 1913 ddir = ISP_NOXFR; 1914 } 1915 1916 error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map); 1917 switch (error) { 1918 case CMD_EAGAIN: 1919 mp->error = MUSHERR_NOQENTRIES; 1920 break; 1921 case CMD_QUEUED: 1922 break; 1923 default: 1924 mp->error = EIO; 1925 break; 1926 } 1927 } 1928 1929 static int 1930 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1931 { 1932 mush_t mush, *mp; 1933 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1934 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1935 int error; 1936 1937 mp = &mush; 1938 mp->isp = isp; 1939 mp->cmd_token = csio; 1940 mp->rq = ff; 1941 mp->error = 0; 1942 mp->mapsize = 0; 1943 1944 #ifdef ISP_TARGET_MODE 1945 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1946 eptr = tdma2; 1947 eptr2 = tdma2_2; 1948 } else 1949 #endif 1950 { 1951 eptr = dma2; 1952 eptr2 = dma2_2; 1953 } 1954 1955 1956 error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, 1957 (union ccb *)csio, eptr, mp, 0); 1958 if (error == EINPROGRESS) { 1959 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1960 mp->error = EINVAL; 1961 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1962 } else if (error && mp->error == 0) { 1963 #ifdef DIAGNOSTIC 1964 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1965 #endif 1966 mp->error = error; 1967 } 1968 if (mp->error) { 1969 int retval = CMD_COMPLETE; 1970 if (mp->error == MUSHERR_NOQENTRIES) { 1971 retval = CMD_EAGAIN; 1972 } else if (mp->error == EFBIG) { 1973 csio->ccb_h.status = CAM_REQ_TOO_BIG; 1974 } else if (mp->error == EINVAL) { 1975 csio->ccb_h.status = CAM_REQ_INVALID; 1976 } else { 1977 csio->ccb_h.status = CAM_UNREC_HBA_ERROR; 1978 } 1979 return (retval); 1980 } 1981 return (CMD_QUEUED); 1982 } 1983 1984 static void 1985 isp_pci_reset0(ispsoftc_t *isp) 1986 { 1987 ISP_DISABLE_INTS(isp); 1988 } 1989 1990 static void 1991 isp_pci_reset1(ispsoftc_t *isp) 1992 { 1993 if (!IS_24XX(isp)) { 1994 /* Make sure the BIOS is disabled */ 1995 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1996 } 1997 /* and enable interrupts */ 1998 ISP_ENABLE_INTS(isp); 1999 } 2000 2001 static void 2002 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 2003 { 2004 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 2005 if (msg) 2006 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 2007 else 2008 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 2009 if (IS_SCSI(isp)) 2010 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 2011 else 2012 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 2013 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 2014 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 2015 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2016 2017 2018 if (IS_SCSI(isp)) { 2019 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2020 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2021 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2022 ISP_READ(isp, CDMA_FIFO_STS)); 2023 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2024 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2025 ISP_READ(isp, DDMA_FIFO_STS)); 2026 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2027 ISP_READ(isp, SXP_INTERRUPT), 2028 ISP_READ(isp, SXP_GROSS_ERR), 2029 ISP_READ(isp, SXP_PINS_CTRL)); 2030 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2031 } 2032 printf(" mbox regs: %x %x %x %x %x\n", 2033 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2034 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2035 ISP_READ(isp, OUTMAILBOX4)); 2036 printf(" PCI Status Command/Status=%x\n", 2037 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2038 } 2039