1 /* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 #include "opt_wlan.h" 107 #include "opt_iwm.h" 108 109 #include <sys/param.h> 110 #include <sys/bus.h> 111 #include <sys/conf.h> 112 #include <sys/endian.h> 113 #include <sys/firmware.h> 114 #include <sys/kernel.h> 115 #include <sys/malloc.h> 116 #include <sys/mbuf.h> 117 #include <sys/mutex.h> 118 #include <sys/module.h> 119 #include <sys/proc.h> 120 #include <sys/rman.h> 121 #include <sys/socket.h> 122 #include <sys/sockio.h> 123 #include <sys/sysctl.h> 124 #include <sys/linker.h> 125 126 #include <machine/bus.h> 127 #include <machine/endian.h> 128 #include <machine/resource.h> 129 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/pcireg.h> 132 133 #include <net/bpf.h> 134 135 #include <net/if.h> 136 #include <net/if_var.h> 137 #include <net/if_arp.h> 138 #include <net/if_dl.h> 139 #include <net/if_media.h> 140 #include <net/if_types.h> 141 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/if_ether.h> 145 #include <netinet/ip.h> 146 147 #include <net80211/ieee80211_var.h> 148 #include <net80211/ieee80211_regdomain.h> 149 #include <net80211/ieee80211_ratectl.h> 150 #include <net80211/ieee80211_radiotap.h> 151 152 #include <dev/iwm/if_iwmreg.h> 153 #include <dev/iwm/if_iwmvar.h> 154 #include <dev/iwm/if_iwm_config.h> 155 #include <dev/iwm/if_iwm_debug.h> 156 #include <dev/iwm/if_iwm_pcie_trans.h> 157 158 /* 159 * This is a subset of what's in linux iwlwifi/pcie/trans.c. 160 * The rest can be migrated out into here once they're no longer in 161 * if_iwm.c. 162 */ 163 164 /* 165 * basic device access 166 */ 167 168 uint32_t 169 iwm_read_prph(struct iwm_softc *sc, uint32_t addr) 170 { 171 IWM_WRITE(sc, 172 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 173 IWM_BARRIER_READ_WRITE(sc); 174 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 175 } 176 177 void 178 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 179 { 180 IWM_WRITE(sc, 181 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 182 IWM_BARRIER_WRITE(sc); 183 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 184 } 185 186 void 187 iwm_write_prph64(struct iwm_softc *sc, uint64_t addr, uint64_t val) 188 { 189 iwm_write_prph(sc, (uint32_t)addr, val & 0xffffffff); 190 iwm_write_prph(sc, (uint32_t)addr + 4, val >> 32); 191 } 192 193 int 194 iwm_poll_prph(struct iwm_softc *sc, uint32_t addr, uint32_t bits, uint32_t mask, 195 int timeout) 196 { 197 do { 198 if ((iwm_read_prph(sc, addr) & mask) == (bits & mask)) 199 return (0); 200 DELAY(10); 201 timeout -= 10; 202 } while (timeout > 0); 203 204 return (ETIMEDOUT); 205 } 206 207 #ifdef IWM_DEBUG 208 /* iwlwifi: pcie/trans.c */ 209 int 210 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 211 { 212 int offs, ret = 0; 213 uint32_t *vals = buf; 214 215 if (iwm_nic_lock(sc)) { 216 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 217 for (offs = 0; offs < dwords; offs++) 218 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 219 iwm_nic_unlock(sc); 220 } else { 221 ret = EBUSY; 222 } 223 return ret; 224 } 225 #endif 226 227 /* iwlwifi: pcie/trans.c */ 228 int 229 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 230 { 231 int offs; 232 const uint32_t *vals = buf; 233 234 if (iwm_nic_lock(sc)) { 235 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 236 /* WADDR auto-increments */ 237 for (offs = 0; offs < dwords; offs++) { 238 uint32_t val = vals ? vals[offs] : 0; 239 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 240 } 241 iwm_nic_unlock(sc); 242 } else { 243 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, 244 "%s: write_mem failed\n", __func__); 245 return EBUSY; 246 } 247 return 0; 248 } 249 250 int 251 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 252 { 253 return iwm_write_mem(sc, addr, &val, 1); 254 } 255 256 int 257 iwm_poll_bit(struct iwm_softc *sc, int reg, 258 uint32_t bits, uint32_t mask, int timo) 259 { 260 for (;;) { 261 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 262 return 1; 263 } 264 if (timo < 10) { 265 return 0; 266 } 267 timo -= 10; 268 DELAY(10); 269 } 270 } 271 272 int 273 iwm_nic_lock(struct iwm_softc *sc) 274 { 275 int rv = 0; 276 277 if (sc->cmd_hold_nic_awake) 278 return 1; 279 280 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 281 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 282 283 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) 284 DELAY(2); 285 286 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 287 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 288 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 289 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 290 rv = 1; 291 } else { 292 /* jolt */ 293 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 294 "%s: resetting device via NMI\n", __func__); 295 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 296 } 297 298 return rv; 299 } 300 301 void 302 iwm_nic_unlock(struct iwm_softc *sc) 303 { 304 if (sc->cmd_hold_nic_awake) 305 return; 306 307 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 308 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 309 } 310 311 void 312 iwm_set_bits_mask_prph(struct iwm_softc *sc, 313 uint32_t reg, uint32_t bits, uint32_t mask) 314 { 315 uint32_t val; 316 317 /* XXX: no error path? */ 318 if (iwm_nic_lock(sc)) { 319 val = iwm_read_prph(sc, reg) & mask; 320 val |= bits; 321 iwm_write_prph(sc, reg, val); 322 iwm_nic_unlock(sc); 323 } 324 } 325 326 void 327 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 328 { 329 iwm_set_bits_mask_prph(sc, reg, bits, ~0); 330 } 331 332 void 333 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 334 { 335 iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 336 } 337 338 /* 339 * High-level hardware frobbing routines 340 */ 341 342 void 343 iwm_enable_rfkill_int(struct iwm_softc *sc) 344 { 345 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL; 346 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 347 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 348 IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 349 } 350 351 int 352 iwm_check_rfkill(struct iwm_softc *sc) 353 { 354 uint32_t v; 355 int rv; 356 357 /* 358 * "documentation" is not really helpful here: 359 * 27: HW_RF_KILL_SW 360 * Indicates state of (platform's) hardware RF-Kill switch 361 * 362 * But apparently when it's off, it's on ... 363 */ 364 v = IWM_READ(sc, IWM_CSR_GP_CNTRL); 365 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; 366 if (rv) { 367 sc->sc_flags |= IWM_FLAG_RFKILL; 368 } else { 369 sc->sc_flags &= ~IWM_FLAG_RFKILL; 370 } 371 372 return rv; 373 } 374 375 376 #define IWM_HW_READY_TIMEOUT 50 377 int 378 iwm_set_hw_ready(struct iwm_softc *sc) 379 { 380 int ready; 381 382 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 383 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 384 385 ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG, 386 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 387 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 388 IWM_HW_READY_TIMEOUT); 389 if (ready) { 390 IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG, 391 IWM_CSR_MBOX_SET_REG_OS_ALIVE); 392 } 393 return ready; 394 } 395 #undef IWM_HW_READY_TIMEOUT 396 397 int 398 iwm_prepare_card_hw(struct iwm_softc *sc) 399 { 400 int rv = 0; 401 int t = 0; 402 403 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__); 404 if (iwm_set_hw_ready(sc)) 405 goto out; 406 407 IWM_SETBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG, 408 IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED); 409 DELAY(1000); 410 411 /* If HW is not ready, prepare the conditions to check again */ 412 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 413 IWM_CSR_HW_IF_CONFIG_REG_PREPARE); 414 415 do { 416 if (iwm_set_hw_ready(sc)) 417 goto out; 418 DELAY(200); 419 t += 200; 420 } while (t < 150000); 421 422 rv = ETIMEDOUT; 423 424 out: 425 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__); 426 return rv; 427 } 428 429 void 430 iwm_apm_config(struct iwm_softc *sc) 431 { 432 uint16_t lctl, cap; 433 int pcie_ptr; 434 435 /* 436 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 437 * Check if BIOS (or OS) enabled L1-ASPM on this device. 438 * If so (likely), disable L0S, so device moves directly L0->L1; 439 * costs negligible amount of power savings. 440 * If not (unlikely), enable L0S, so there is at least some 441 * power savings, even without L1. 442 */ 443 int error; 444 445 error = pci_find_cap(sc->sc_dev, PCIY_EXPRESS, &pcie_ptr); 446 if (error != 0) 447 return; 448 lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINK_CTL, 449 sizeof(lctl)); 450 if (lctl & PCIEM_LINK_CTL_ASPMC_L1) { 451 IWM_SETBITS(sc, IWM_CSR_GIO_REG, 452 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 453 } else { 454 IWM_CLRBITS(sc, IWM_CSR_GIO_REG, 455 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 456 } 457 458 cap = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_DEVICE_CTL2, 459 sizeof(cap)); 460 sc->sc_ltr_enabled = (cap & PCIEM_CTL2_LTR_ENABLE) ? 1 : 0; 461 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_PWRSAVE, 462 "L1 %sabled - LTR %sabled\n", 463 (lctl & PCIEM_LINK_CTL_ASPMC_L1) ? "En" : "Dis", 464 sc->sc_ltr_enabled ? "En" : "Dis"); 465 } 466 467 /* 468 * Start up NIC's basic functionality after it has been reset 469 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop()) 470 * NOTE: This does not load uCode nor start the embedded processor 471 */ 472 int 473 iwm_apm_init(struct iwm_softc *sc) 474 { 475 int error = 0; 476 477 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n"); 478 479 /* Disable L0S exit timer (platform NMI Work/Around) */ 480 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 481 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 482 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 483 } 484 485 /* 486 * Disable L0s without affecting L1; 487 * don't wait for ICH L0s (ICH bug W/A) 488 */ 489 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 490 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 491 492 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 493 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 494 495 /* 496 * Enable HAP INTA (interrupt from management bus) to 497 * wake device's PCI Express link L1a -> L0s 498 */ 499 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 500 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 501 502 iwm_apm_config(sc); 503 504 #if 0 /* not for 7k/8k */ 505 /* Configure analog phase-lock-loop before activating to D0A */ 506 if (trans->cfg->base_params->pll_cfg_val) 507 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG, 508 trans->cfg->base_params->pll_cfg_val); 509 #endif 510 511 /* 512 * Set "initialization complete" bit to move adapter from 513 * D0U* --> D0A* (powered-up active) state. 514 */ 515 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 516 517 /* 518 * Wait for clock stabilization; once stabilized, access to 519 * device-internal resources is supported, e.g. iwm_write_prph() 520 * and accesses to uCode SRAM. 521 */ 522 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 523 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 524 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) { 525 device_printf(sc->sc_dev, 526 "timeout waiting for clock stabilization\n"); 527 error = ETIMEDOUT; 528 goto out; 529 } 530 531 if (sc->cfg->host_interrupt_operation_mode) { 532 /* 533 * This is a bit of an abuse - This is needed for 7260 / 3160 534 * only check host_interrupt_operation_mode even if this is 535 * not related to host_interrupt_operation_mode. 536 * 537 * Enable the oscillator to count wake up time for L1 exit. This 538 * consumes slightly more power (100uA) - but allows to be sure 539 * that we wake up from L1 on time. 540 * 541 * This looks weird: read twice the same register, discard the 542 * value, set a bit, and yet again, read that same register 543 * just to discard the value. But that's the way the hardware 544 * seems to like it. 545 */ 546 if (iwm_nic_lock(sc)) { 547 iwm_read_prph(sc, IWM_OSC_CLK); 548 iwm_read_prph(sc, IWM_OSC_CLK); 549 iwm_nic_unlock(sc); 550 } 551 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL); 552 if (iwm_nic_lock(sc)) { 553 iwm_read_prph(sc, IWM_OSC_CLK); 554 iwm_read_prph(sc, IWM_OSC_CLK); 555 iwm_nic_unlock(sc); 556 } 557 } 558 559 /* 560 * Enable DMA clock and wait for it to stabilize. 561 * 562 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits 563 * do not disable clocks. This preserves any hardware bits already 564 * set by default in "CLK_CTRL_REG" after reset. 565 */ 566 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 567 if (iwm_nic_lock(sc)) { 568 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG, 569 IWM_APMG_CLK_VAL_DMA_CLK_RQT); 570 iwm_nic_unlock(sc); 571 } 572 DELAY(20); 573 574 /* Disable L1-Active */ 575 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 576 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 577 578 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 579 if (iwm_nic_lock(sc)) { 580 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG, 581 IWM_APMG_RTC_INT_STT_RFKILL); 582 iwm_nic_unlock(sc); 583 } 584 } 585 out: 586 if (error) 587 device_printf(sc->sc_dev, "apm init error %d\n", error); 588 return error; 589 } 590 591 /* iwlwifi/pcie/trans.c */ 592 void 593 iwm_apm_stop(struct iwm_softc *sc) 594 { 595 IWM_SETBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG, 596 IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED); 597 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 598 IWM_CSR_HW_IF_CONFIG_REG_PREPARE | 599 IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME); 600 DELAY(1000); 601 IWM_CLRBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG, 602 IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED); 603 DELAY(5000); 604 605 /* stop device's busmaster DMA activity */ 606 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER); 607 608 if (!iwm_poll_bit(sc, IWM_CSR_RESET, 609 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 610 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100)) 611 device_printf(sc->sc_dev, "timeout waiting for master\n"); 612 613 /* 614 * Clear "initialization complete" bit to move adapter from 615 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 616 */ 617 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 618 IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 619 620 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__); 621 } 622 623 /* iwlwifi pcie/trans.c */ 624 int 625 iwm_start_hw(struct iwm_softc *sc) 626 { 627 int error; 628 629 if ((error = iwm_prepare_card_hw(sc)) != 0) 630 return error; 631 632 /* Reset the entire device */ 633 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 634 DELAY(5000); 635 636 if ((error = iwm_apm_init(sc)) != 0) 637 return error; 638 639 /* On newer chipsets MSI is disabled by default. */ 640 if (sc->cfg->mqrx_supported) 641 iwm_write_prph(sc, IWM_UREG_CHICK, IWM_UREG_CHICK_MSI_ENABLE); 642 643 iwm_enable_rfkill_int(sc); 644 iwm_check_rfkill(sc); 645 646 return 0; 647 } 648 649 /* iwlwifi pcie/trans.c (always main power) */ 650 void 651 iwm_set_pwr(struct iwm_softc *sc) 652 { 653 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 654 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 655 } 656 657 /* iwlwifi pcie/rx.c */ 658 int 659 iwm_pcie_rx_stop(struct iwm_softc *sc) 660 { 661 int ret; 662 663 ret = 0; 664 if (iwm_nic_lock(sc)) { 665 if (sc->cfg->mqrx_supported) { 666 iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 0); 667 ret = iwm_poll_prph(sc, IWM_RFH_GEN_STATUS, 668 IWM_RXF_DMA_IDLE, IWM_RXF_DMA_IDLE, 1000); 669 } else { 670 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 671 ret = iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG, 672 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 673 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 674 1000); 675 } 676 iwm_nic_unlock(sc); 677 } 678 return ret; 679 } 680 681 void 682 iwm_pcie_clear_cmd_in_flight(struct iwm_softc *sc) 683 { 684 if (!sc->cfg->apmg_wake_up_wa) 685 return; 686 687 if (!sc->cmd_hold_nic_awake) { 688 device_printf(sc->sc_dev, 689 "%s: cmd_hold_nic_awake not set\n", __func__); 690 return; 691 } 692 693 sc->cmd_hold_nic_awake = 0; 694 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 695 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 696 } 697 698 int 699 iwm_pcie_set_cmd_in_flight(struct iwm_softc *sc) 700 { 701 int ret; 702 703 /* 704 * wake up the NIC to make sure that the firmware will see the host 705 * command - we will let the NIC sleep once all the host commands 706 * returned. This needs to be done only on NICs that have 707 * apmg_wake_up_wa set. 708 */ 709 if (sc->cfg->apmg_wake_up_wa && 710 !sc->cmd_hold_nic_awake) { 711 712 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 713 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 714 715 ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 716 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 717 (IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 718 IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 719 15000); 720 if (ret == 0) { 721 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 722 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 723 device_printf(sc->sc_dev, 724 "%s: Failed to wake NIC for hcmd\n", __func__); 725 return EIO; 726 } 727 sc->cmd_hold_nic_awake = 1; 728 } 729 730 return 0; 731 } 732