1 /* $FreeBSD$ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 #ifndef __IF_IWNREG_H__ 21 #define __IF_IWNREG_H__ 22 23 #define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 24 #define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 25 26 #define IWN_TX_RING_COUNT 256 27 #define IWN_TX_RING_LOMARK 192 28 #define IWN_TX_RING_HIMARK 224 29 #define IWN_RX_RING_COUNT_LOG 6 30 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31 32 #define IWN4965_NTXQUEUES 16 33 #define IWN5000_NTXQUEUES 20 34 35 #define IWN4965_FIRSTAGGQUEUE 7 36 #define IWN5000_FIRSTAGGQUEUE 10 37 38 #define IWN4965_NDMACHNLS 7 39 #define IWN5000_NDMACHNLS 8 40 41 #define IWN_SRVC_DMACHNL 9 42 43 #define IWN_ICT_SIZE 4096 44 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 45 46 /* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 47 #define IWN_CMD_QUEUE_NUM 4 48 #define IWN_PAN_CMD_QUEUE 9 49 50 /* Maximum number of DMA segments for TX. */ 51 #define IWN_MAX_SCATTER 20 52 53 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 54 #define IWN_RBUF_SIZE (4 * 1024) 55 56 #if defined(__LP64__) 57 /* HW supports 36-bit DMA addresses. */ 58 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 59 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 60 #else 61 #define IWN_LOADDR(paddr) (paddr) 62 #define IWN_HIADDR(paddr) (0) 63 #endif 64 65 /* 66 * Control and status registers. 67 */ 68 #define IWN_HW_IF_CONFIG 0x000 69 #define IWN_INT_COALESCING 0x004 70 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 71 #define IWN_INT 0x008 72 #define IWN_INT_MASK 0x00c 73 #define IWN_FH_INT 0x010 74 #define IWN_GPIO_IN 0x018 /* read external chip pins */ 75 #define IWN_RESET 0x020 76 #define IWN_GP_CNTRL 0x024 77 #define IWN_HW_REV 0x028 78 #define IWN_EEPROM 0x02c 79 #define IWN_EEPROM_GP 0x030 80 #define IWN_OTP_GP 0x034 81 #define IWN_GIO 0x03c 82 #define IWN_GP_UCODE 0x048 83 #define IWN_GP_DRIVER 0x050 84 #define IWN_UCODE_GP1 0x054 85 #define IWN_UCODE_GP1_SET 0x058 86 #define IWN_UCODE_GP1_CLR 0x05c 87 #define IWN_UCODE_GP2 0x060 88 #define IWN_LED 0x094 89 #define IWN_DRAM_INT_TBL 0x0a0 90 #define IWN_SHADOW_REG_CTRL 0x0a8 91 #define IWN_GIO_CHICKEN 0x100 92 #define IWN_ANA_PLL 0x20c 93 #define IWN_HW_REV_WA 0x22c 94 #define IWN_DBG_HPET_MEM 0x240 95 #define IWN_DBG_LINK_PWR_MGMT 0x250 96 /* Need nic_lock for use above */ 97 #define IWN_MEM_RADDR 0x40c 98 #define IWN_MEM_WADDR 0x410 99 #define IWN_MEM_WDATA 0x418 100 #define IWN_MEM_RDATA 0x41c 101 #define IWN_TARG_MBX_C 0x430 102 #define IWN_PRPH_WADDR 0x444 103 #define IWN_PRPH_RADDR 0x448 104 #define IWN_PRPH_WDATA 0x44c 105 #define IWN_PRPH_RDATA 0x450 106 #define IWN_HBUS_TARG_WRPTR 0x460 107 108 /* 109 * Flow-Handler registers. 110 */ 111 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 112 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 113 #define IWN_FH_KW_ADDR 0x197c 114 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 115 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 116 #define IWN_FH_STATUS_WPTR 0x1bc0 117 #define IWN_FH_RX_BASE 0x1bc4 118 #define IWN_FH_RX_WPTR 0x1bc8 119 #define IWN_FH_RX_CONFIG 0x1c00 120 #define IWN_FH_RX_STATUS 0x1c44 121 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 122 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 123 #define IWN_FH_TX_CHICKEN 0x1e98 124 #define IWN_FH_TX_STATUS 0x1eb0 125 126 /* 127 * TX scheduler registers. 128 */ 129 #define IWN_SCHED_BASE 0xa02c00 130 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 131 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 132 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 133 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 134 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 135 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 136 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 137 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 138 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 139 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 140 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 141 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 142 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 143 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 144 145 /* 146 * Offsets in TX scheduler's SRAM. 147 */ 148 #define IWN4965_SCHED_CTX_OFF 0x380 149 #define IWN4965_SCHED_CTX_LEN 416 150 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 151 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 152 #define IWN5000_SCHED_CTX_OFF 0x600 153 #define IWN5000_SCHED_CTX_LEN 520 154 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 155 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 156 157 /* 158 * NIC internal memory offsets. 159 */ 160 #define IWN_APMG_CLK_CTRL 0x3000 161 #define IWN_APMG_CLK_EN 0x3004 162 #define IWN_APMG_CLK_DIS 0x3008 163 #define IWN_APMG_PS 0x300c 164 #define IWN_APMG_DIGITAL_SVR 0x3058 165 #define IWN_APMG_ANALOG_SVR 0x306c 166 #define IWN_APMG_PCI_STT 0x3010 167 #define IWN_BSM_WR_CTRL 0x3400 168 #define IWN_BSM_WR_MEM_SRC 0x3404 169 #define IWN_BSM_WR_MEM_DST 0x3408 170 #define IWN_BSM_WR_DWCOUNT 0x340c 171 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 172 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 173 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 174 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 175 #define IWN_BSM_SRAM_BASE 0x3800 176 177 /* Possible flags for register IWN_HW_IF_CONFIG. */ 178 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 179 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 180 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 181 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 182 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 183 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 184 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 185 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 186 187 /* Possible values for register IWN_INT_PERIODIC. */ 188 #define IWN_INT_PERIODIC_DIS 0x00 189 #define IWN_INT_PERIODIC_ENA 0xff 190 191 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 192 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 193 194 /* Possible values for IWN_BSM_WR_MEM_DST. */ 195 #define IWN_FW_TEXT_BASE 0x00000000 196 #define IWN_FW_DATA_BASE 0x00800000 197 198 /* Possible flags for register IWN_RESET. */ 199 #define IWN_RESET_NEVO (1 << 0) 200 #define IWN_RESET_SW (1 << 7) 201 #define IWN_RESET_MASTER_DISABLED (1 << 8) 202 #define IWN_RESET_STOP_MASTER (1 << 9) 203 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 204 205 /* Possible flags for register IWN_GP_CNTRL. */ 206 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 207 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 208 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 209 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 210 #define IWN_GP_CNTRL_SLEEP (1 << 4) 211 #define IWN_GP_CNTRL_RFKILL (1 << 27) 212 213 /* Possible flags for register IWN_GIO_CHICKEN. */ 214 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 215 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 216 217 /* Possible flags for register IWN_GIO. */ 218 #define IWN_GIO_L0S_ENA (1 << 1) 219 220 /* Possible flags for register IWN_GP_DRIVER. */ 221 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 222 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 223 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 224 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 225 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 226 #define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 227 #define IWN_GP_DRIVER_NONE 0 228 229 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 230 #define IWN_UCODE_GP1_RFKILL (1 << 1) 231 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 232 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 233 #define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 234 235 /* Possible flags/values for register IWN_LED. */ 236 #define IWN_LED_BSM_CTRL (1 << 5) 237 #define IWN_LED_OFF 0x00000038 238 #define IWN_LED_ON 0x00000078 239 240 #define IWN_MAX_BLINK_TBL 10 241 #define IWN_LED_STATIC_ON 0 242 #define IWN_LED_STATIC_OFF 1 243 #define IWN_LED_SLOW_BLINK 2 244 #define IWN_LED_INT_BLINK 3 245 #define IWN_LED_UNIT 0x1388 /* 5 ms */ 246 247 static const struct { 248 uint16_t tpt; /* Mb/s */ 249 uint8_t on_time; 250 uint8_t off_time; 251 } blink_tbl[] = 252 { 253 {300, 5, 5}, 254 {200, 8, 8}, 255 {100, 11, 11}, 256 {70, 13, 13}, 257 {50, 15, 15}, 258 {20, 17, 17}, 259 {10, 19, 19}, 260 {5, 22, 22}, 261 {1, 26, 26}, 262 {0, 33, 33}, 263 /* SOLID_ON */ 264 }; 265 266 /* Possible flags for register IWN_DRAM_INT_TBL. */ 267 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 268 #define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 269 270 /* Possible values for register IWN_ANA_PLL. */ 271 #define IWN_ANA_PLL_INIT 0x00880300 272 273 /* Possible flags for register IWN_FH_RX_STATUS. */ 274 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 275 276 /* Possible flags for register IWN_BSM_WR_CTRL. */ 277 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 278 #define IWN_BSM_WR_CTRL_START (1U << 31) 279 280 /* Possible flags for register IWN_INT. */ 281 #define IWN_INT_ALIVE (1 << 0) 282 #define IWN_INT_WAKEUP (1 << 1) 283 #define IWN_INT_SW_RX (1 << 3) 284 #define IWN_INT_CT_REACHED (1 << 6) 285 #define IWN_INT_RF_TOGGLED (1 << 7) 286 #define IWN_INT_SW_ERR (1 << 25) 287 #define IWN_INT_SCHED (1 << 26) 288 #define IWN_INT_FH_TX (1 << 27) 289 #define IWN_INT_RX_PERIODIC (1 << 28) 290 #define IWN_INT_HW_ERR (1 << 29) 291 #define IWN_INT_FH_RX (1U << 31) 292 293 /* Shortcut. */ 294 #define IWN_INT_MASK_DEF \ 295 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 296 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 297 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 298 299 /* Possible flags for register IWN_FH_INT. */ 300 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 301 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 302 #define IWN_FH_INT_HI_PRIOR (1 << 30) 303 /* Shortcuts for the above. */ 304 #define IWN_FH_INT_TX \ 305 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 306 #define IWN_FH_INT_RX \ 307 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 308 309 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 310 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 311 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 312 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 313 314 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 315 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 316 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 317 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 318 319 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 320 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 321 322 /* Possible flags for register IWN_FH_TX_STATUS. */ 323 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 324 325 /* Possible flags for register IWN_FH_RX_CONFIG. */ 326 #define IWN_FH_RX_CONFIG_ENA (1U << 31) 327 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 328 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 329 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 330 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 331 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 332 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 333 334 /* Possible flags for register IWN_FH_TX_CONFIG. */ 335 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 336 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 337 338 /* Possible flags for register IWN_EEPROM. */ 339 #define IWN_EEPROM_READ_VALID (1 << 0) 340 #define IWN_EEPROM_CMD (1 << 1) 341 342 /* Possible flags for register IWN_EEPROM_GP. */ 343 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 344 345 /* Possible flags for register IWN_OTP_GP. */ 346 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 347 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 348 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 349 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 350 351 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 352 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 353 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 354 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 355 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 356 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 357 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 358 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 359 360 /* Possible flags for registers IWN_APMG_CLK_*. */ 361 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 362 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 363 364 /* Possible flags for register IWN_APMG_PS. */ 365 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 366 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 367 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 368 #define IWN_APMG_PS_PWR_SRC_VAUX 2 369 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 370 #define IWN_APMG_PS_RESET_REQ (1 << 26) 371 372 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 373 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 374 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 375 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 376 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 377 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 378 379 /* Possible flags for IWN_APMG_PCI_STT. */ 380 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 381 382 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 383 #define IWN_FW_UPDATED (1U << 31) 384 385 #define IWN_SCHED_WINSZ 64 386 #define IWN_SCHED_LIMIT 64 387 #define IWN4965_SCHED_COUNT 512 388 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 389 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 390 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 391 392 struct iwn_tx_desc { 393 uint8_t reserved1[3]; 394 uint8_t nsegs; 395 struct { 396 uint32_t addr; 397 uint16_t len; 398 } __packed segs[IWN_MAX_SCATTER]; 399 /* Pad to 128 bytes. */ 400 uint32_t reserved2; 401 } __packed; 402 403 struct iwn_rx_status { 404 uint16_t closed_count; 405 uint16_t closed_rx_count; 406 uint16_t finished_count; 407 uint16_t finished_rx_count; 408 uint32_t reserved[2]; 409 } __packed; 410 411 struct iwn_rx_desc { 412 /* 413 * The first 4 bytes of the RX frame header contain both the RX frame 414 * size and some flags. 415 * Bit fields: 416 * 31: flag flush RB request 417 * 30: flag ignore TC (terminal counter) request 418 * 29: flag fast IRQ request 419 * 28-14: Reserved 420 * 13-00: RX frame size 421 */ 422 uint32_t len; 423 uint8_t type; 424 #define IWN_UC_READY 1 425 #define IWN_ADD_NODE_DONE 24 426 #define IWN_TX_DONE 28 427 #define IWN_REPLY_LED_CMD 72 428 #define IWN5000_CALIBRATION_RESULT 102 429 #define IWN5000_CALIBRATION_DONE 103 430 #define IWN_START_SCAN 130 431 #define IWN_NOTIF_SCAN_RESULT 131 432 #define IWN_STOP_SCAN 132 433 #define IWN_RX_STATISTICS 156 434 #define IWN_BEACON_STATISTICS 157 435 #define IWN_STATE_CHANGED 161 436 #define IWN_BEACON_MISSED 162 437 #define IWN_RX_PHY 192 438 #define IWN_MPDU_RX_DONE 193 439 #define IWN_RX_DONE 195 440 #define IWN_RX_COMPRESSED_BA 197 441 442 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 443 uint8_t idx; /* position within TX queue */ 444 uint8_t qid; 445 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 446 * or uCode-originated notification 447 */ 448 } __packed; 449 450 #define IWN_RX_DESC_QID_MSK 0x1F 451 #define IWN_UNSOLICITED_RX_NOTIF 0x80 452 453 /* CARD_STATE_NOTIFICATION */ 454 #define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 455 #define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 456 #define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 457 #define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 458 459 /* Possible RX status flags. */ 460 #define IWN_RX_NO_CRC_ERR (1 << 0) 461 #define IWN_RX_NO_OVFL_ERR (1 << 1) 462 /* Shortcut for the above. */ 463 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 464 #define IWN_RX_MPDU_MIC_OK (1 << 6) 465 #define IWN_RX_CIPHER_MASK (7 << 8) 466 #define IWN_RX_CIPHER_CCMP (2 << 8) 467 #define IWN_RX_MPDU_DEC (1 << 11) 468 #define IWN_RX_DECRYPT_MASK (3 << 11) 469 #define IWN_RX_DECRYPT_OK (3 << 11) 470 471 struct iwn_tx_cmd { 472 uint8_t code; 473 #define IWN_CMD_RXON 16 474 #define IWN_CMD_RXON_ASSOC 17 475 #define IWN_CMD_EDCA_PARAMS 19 476 #define IWN_CMD_TIMING 20 477 #define IWN_CMD_ADD_NODE 24 478 #define IWN_CMD_TX_DATA 28 479 #define IWN_CMD_LINK_QUALITY 78 480 #define IWN_CMD_SET_LED 72 481 #define IWN5000_CMD_WIMAX_COEX 90 482 #define IWN_TEMP_NOTIFICATION 98 483 #define IWN5000_CMD_CALIB_CONFIG 101 484 #define IWN5000_CMD_CALIB_RESULT 102 485 #define IWN5000_CMD_CALIB_COMPLETE 103 486 #define IWN_CMD_SET_POWER_MODE 119 487 #define IWN_CMD_SCAN 128 488 #define IWN_CMD_SCAN_RESULTS 131 489 #define IWN_CMD_TXPOWER_DBM 149 490 #define IWN_CMD_TXPOWER 151 491 #define IWN5000_CMD_TX_ANT_CONFIG 152 492 #define IWN_CMD_BT_COEX 155 493 #define IWN_CMD_GET_STATISTICS 156 494 #define IWN_CMD_SET_CRITICAL_TEMP 164 495 #define IWN_CMD_SET_SENSITIVITY 168 496 #define IWN_CMD_PHY_CALIB 176 497 #define IWN_CMD_BT_COEX_PRIOTABLE 204 498 #define IWN_CMD_BT_COEX_PROT 205 499 #define IWN_CMD_BT_COEX_NOTIF 206 500 /* PAN commands */ 501 #define IWN_CMD_WIPAN_PARAMS 0xb2 502 #define IWN_CMD_WIPAN_RXON 0xb3 503 #define IWN_CMD_WIPAN_RXON_TIMING 0xb4 504 #define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 505 #define IWN_CMD_WIPAN_QOS_PARAM 0xb7 506 #define IWN_CMD_WIPAN_WEPKEY 0xb8 507 #define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 508 #define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 509 #define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 510 511 uint8_t flags; 512 uint8_t idx; 513 uint8_t qid; 514 uint8_t data[136]; 515 } __packed; 516 517 /* 518 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 519 * all devices identical. 520 * 521 * This command triggers an immediate response containing uCode statistics. 522 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 523 * 524 * If the CLEAR_STATS configuration flag is set, uCode will clear its 525 * internal copy of the statistics (counters) after issuing the response. 526 * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 527 * 528 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 529 * IWN_BEACON_STATISTICS after received beacons. This flag 530 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 531 */ 532 struct iwn_statistics_cmd { 533 uint32_t configuration_flags; 534 #define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 535 #define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 536 } __packed; 537 538 /* Antenna flags, used in various commands. */ 539 #define IWN_ANT_A (1 << 0) 540 #define IWN_ANT_B (1 << 1) 541 #define IWN_ANT_C (1 << 2) 542 /* Shortcuts. */ 543 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 544 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 545 #define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 546 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 547 548 /* Structure for command IWN_CMD_RXON. */ 549 struct iwn_rxon { 550 uint8_t myaddr[IEEE80211_ADDR_LEN]; 551 uint16_t reserved1; 552 uint8_t bssid[IEEE80211_ADDR_LEN]; 553 uint16_t reserved2; 554 uint8_t wlap[IEEE80211_ADDR_LEN]; 555 uint16_t reserved3; 556 uint8_t mode; 557 #define IWN_MODE_HOSTAP 1 558 #define IWN_MODE_STA 3 559 #define IWN_MODE_IBSS 4 560 #define IWN_MODE_MONITOR 6 561 #define IWN_MODE_2STA 8 562 #define IWN_MODE_P2P 9 563 564 uint8_t air; 565 uint16_t rxchain; 566 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 567 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 568 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 569 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 570 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 571 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 572 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 573 574 uint8_t ofdm_mask; 575 uint8_t cck_mask; 576 uint16_t associd; 577 uint32_t flags; 578 #define IWN_RXON_24GHZ (1 << 0) 579 #define IWN_RXON_CCK (1 << 1) 580 #define IWN_RXON_AUTO (1 << 2) 581 #define IWN_RXON_SHSLOT (1 << 4) 582 #define IWN_RXON_SHPREAMBLE (1 << 5) 583 #define IWN_RXON_NODIVERSITY (1 << 7) 584 #define IWN_RXON_ANTENNA_A (1 << 8) 585 #define IWN_RXON_ANTENNA_B (1 << 9) 586 #define IWN_RXON_TSF (1 << 15) 587 #define IWN_RXON_HT_HT40MINUS (1 << 22) 588 #define IWN_RXON_HT_PROTMODE(x) (x << 23) 589 #define IWN_RXON_HT_MODEPURE40 (1 << 25) 590 #define IWN_RXON_HT_MODEMIXED (2 << 25) 591 #define IWN_RXON_CTS_TO_SELF (1 << 30) 592 593 uint32_t filter; 594 #define IWN_FILTER_PROMISC (1 << 0) 595 #define IWN_FILTER_CTL (1 << 1) 596 #define IWN_FILTER_MULTICAST (1 << 2) 597 #define IWN_FILTER_NODECRYPT (1 << 3) 598 #define IWN_FILTER_BSS (1 << 5) 599 #define IWN_FILTER_BEACON (1 << 6) 600 601 uint8_t chan; 602 uint8_t reserved4; 603 uint8_t ht_single_mask; 604 uint8_t ht_dual_mask; 605 /* The following fields are for >=5000 Series only. */ 606 uint8_t ht_triple_mask; 607 uint8_t reserved5; 608 uint16_t acquisition; 609 uint16_t reserved6; 610 } __packed; 611 612 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 613 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 614 615 /* Structure for command IWN_CMD_ASSOCIATE. */ 616 struct iwn_assoc { 617 uint32_t flags; 618 uint32_t filter; 619 uint8_t ofdm_mask; 620 uint8_t cck_mask; 621 uint16_t reserved; 622 } __packed; 623 624 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 625 struct iwn_edca_params { 626 uint32_t flags; 627 #define IWN_EDCA_UPDATE (1 << 0) 628 #define IWN_EDCA_TXOP (1 << 4) 629 630 struct { 631 uint16_t cwmin; 632 uint16_t cwmax; 633 uint8_t aifsn; 634 uint8_t reserved; 635 uint16_t txoplimit; 636 } __packed ac[WME_NUM_AC]; 637 } __packed; 638 639 /* Structure for command IWN_CMD_TIMING. */ 640 struct iwn_cmd_timing { 641 uint64_t tstamp; 642 uint16_t bintval; 643 uint16_t atim; 644 uint32_t binitval; 645 uint16_t lintval; 646 uint8_t dtim_period; 647 uint8_t delta_cp_bss_tbtts; 648 } __packed; 649 650 /* Structure for command IWN_CMD_ADD_NODE. */ 651 struct iwn_node_info { 652 uint8_t control; 653 #define IWN_NODE_UPDATE (1 << 0) 654 655 uint8_t reserved1[3]; 656 657 uint8_t macaddr[IEEE80211_ADDR_LEN]; 658 uint16_t reserved2; 659 uint8_t id; 660 #define IWN_ID_BSS 0 661 #define IWN_STA_ID 1 662 663 #define IWN_PAN_ID_BCAST 14 664 #define IWN5000_ID_BROADCAST 15 665 #define IWN4965_ID_BROADCAST 31 666 667 uint8_t flags; 668 #define IWN_FLAG_SET_KEY (1 << 0) 669 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 670 #define IWN_FLAG_SET_TXRATE (1 << 2) 671 #define IWN_FLAG_SET_ADDBA (1 << 3) 672 #define IWN_FLAG_SET_DELBA (1 << 4) 673 674 uint16_t reserved3; 675 uint16_t kflags; 676 #define IWN_KFLAG_CCMP (1 << 1) 677 #define IWN_KFLAG_MAP (1 << 3) 678 #define IWN_KFLAG_KID(kid) ((kid) << 8) 679 #define IWN_KFLAG_INVALID (1 << 11) 680 #define IWN_KFLAG_GROUP (1 << 14) 681 682 uint8_t tsc2; /* TKIP TSC2 */ 683 uint8_t reserved4; 684 uint16_t ttak[5]; 685 uint8_t kid; 686 uint8_t reserved5; 687 uint8_t key[16]; 688 /* The following 3 fields are for 5000 Series only. */ 689 uint64_t tsc; 690 uint8_t rxmic[8]; 691 uint8_t txmic[8]; 692 693 uint32_t htflags; 694 #define IWN_SMPS_MIMO_PROT (1 << 17) 695 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 696 #define IWN_NODE_HT40 (1 << 21) 697 #define IWN_SMPS_MIMO_DIS (1 << 22) 698 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 699 700 uint32_t mask; 701 uint16_t disable_tid; 702 uint16_t reserved6; 703 uint8_t addba_tid; 704 uint8_t delba_tid; 705 uint16_t addba_ssn; 706 uint32_t reserved7; 707 } __packed; 708 709 struct iwn4965_node_info { 710 uint8_t control; 711 uint8_t reserved1[3]; 712 uint8_t macaddr[IEEE80211_ADDR_LEN]; 713 uint16_t reserved2; 714 uint8_t id; 715 uint8_t flags; 716 uint16_t reserved3; 717 uint16_t kflags; 718 uint8_t tsc2; /* TKIP TSC2 */ 719 uint8_t reserved4; 720 uint16_t ttak[5]; 721 uint8_t kid; 722 uint8_t reserved5; 723 uint8_t key[16]; 724 uint32_t htflags; 725 uint32_t mask; 726 uint16_t disable_tid; 727 uint16_t reserved6; 728 uint8_t addba_tid; 729 uint8_t delba_tid; 730 uint16_t addba_ssn; 731 uint32_t reserved7; 732 } __packed; 733 734 #define IWN_RFLAG_MCS (1 << 8) 735 #define IWN_RFLAG_CCK (1 << 9) 736 #define IWN_RFLAG_GREENFIELD (1 << 10) 737 #define IWN_RFLAG_HT40 (1 << 11) 738 #define IWN_RFLAG_DUPLICATE (1 << 12) 739 #define IWN_RFLAG_SGI (1 << 13) 740 #define IWN_RFLAG_ANT(x) ((x) << 14) 741 742 /* Structure for command IWN_CMD_TX_DATA. */ 743 struct iwn_cmd_data { 744 uint16_t len; 745 uint16_t lnext; 746 uint32_t flags; 747 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 748 #define IWN_TX_NEED_RTS (1 << 1) 749 #define IWN_TX_NEED_CTS (1 << 2) 750 #define IWN_TX_NEED_ACK (1 << 3) 751 #define IWN_TX_LINKQ (1 << 4) 752 #define IWN_TX_IMM_BA (1 << 6) 753 #define IWN_TX_FULL_TXOP (1 << 7) 754 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 755 #define IWN_TX_AUTO_SEQ (1 << 13) 756 #define IWN_TX_MORE_FRAG (1 << 14) 757 #define IWN_TX_INSERT_TSTAMP (1 << 16) 758 #define IWN_TX_NEED_PADDING (1 << 20) 759 760 uint32_t scratch; 761 uint32_t rate; 762 763 uint8_t id; 764 uint8_t security; 765 #define IWN_CIPHER_WEP40 1 766 #define IWN_CIPHER_CCMP 2 767 #define IWN_CIPHER_TKIP 3 768 #define IWN_CIPHER_WEP104 9 769 770 uint8_t linkq; 771 uint8_t reserved2; 772 uint8_t key[16]; 773 uint16_t fnext; 774 uint16_t reserved3; 775 uint32_t lifetime; 776 #define IWN_LIFETIME_INFINITE 0xffffffff 777 778 uint32_t loaddr; 779 uint8_t hiaddr; 780 uint8_t rts_ntries; 781 uint8_t data_ntries; 782 uint8_t tid; 783 uint16_t timeout; 784 uint16_t txop; 785 } __packed; 786 787 /* Structure for command IWN_CMD_LINK_QUALITY. */ 788 #define IWN_MAX_TX_RETRIES 16 789 struct iwn_cmd_link_quality { 790 uint8_t id; 791 uint8_t reserved1; 792 uint16_t ctl; 793 uint8_t flags; 794 uint8_t mimo; 795 uint8_t antmsk_1stream; 796 uint8_t antmsk_2stream; 797 uint8_t ridx[WME_NUM_AC]; 798 uint16_t ampdu_limit; 799 uint8_t ampdu_threshold; 800 uint8_t ampdu_max; 801 uint32_t reserved2; 802 uint32_t retry[IWN_MAX_TX_RETRIES]; 803 uint32_t reserved3; 804 } __packed; 805 806 /* Structure for command IWN_CMD_SET_LED. */ 807 struct iwn_cmd_led { 808 uint32_t unit; /* multiplier (in usecs) */ 809 uint8_t which; 810 #define IWN_LED_ACTIVITY 1 811 #define IWN_LED_LINK 2 812 813 uint8_t off; 814 uint8_t on; 815 uint8_t reserved; 816 } __packed; 817 818 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 819 struct iwn5000_wimax_coex { 820 uint32_t flags; 821 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 822 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 823 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 824 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 825 826 struct iwn5000_wimax_event { 827 uint8_t request; 828 uint8_t window; 829 uint8_t reserved; 830 uint8_t flags; 831 } __packed events[16]; 832 } __packed; 833 834 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 835 struct iwn5000_calib_elem { 836 uint32_t enable; 837 uint32_t start; 838 #define IWN5000_CALIB_DC (1 << 1) 839 840 uint32_t send; 841 uint32_t apply; 842 uint32_t reserved; 843 } __packed; 844 845 struct iwn5000_calib_status { 846 struct iwn5000_calib_elem once; 847 struct iwn5000_calib_elem perd; 848 uint32_t flags; 849 } __packed; 850 851 struct iwn5000_calib_config { 852 struct iwn5000_calib_status ucode; 853 struct iwn5000_calib_status driver; 854 uint32_t reserved; 855 } __packed; 856 857 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 858 struct iwn_pmgt_cmd { 859 uint16_t flags; 860 #define IWN_PS_ALLOW_SLEEP (1 << 0) 861 #define IWN_PS_NOTIFY (1 << 1) 862 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 863 #define IWN_PS_PCI_PMGT (1 << 3) 864 #define IWN_PS_FAST_PD (1 << 4) 865 #define IWN_PS_BEACON_FILTERING (1 << 5) 866 #define IWN_PS_SHADOW_REG (1 << 6) 867 #define IWN_PS_CT_KILL (1 << 7) 868 #define IWN_PS_BT_SCD (1 << 8) 869 #define IWN_PS_ADVANCED_PM (1 << 9) 870 871 uint8_t keepalive; 872 uint8_t debug; 873 uint32_t rxtimeout; 874 uint32_t txtimeout; 875 uint32_t intval[5]; 876 uint32_t beacons; 877 } __packed; 878 879 /* Structures for command IWN_CMD_SCAN. */ 880 struct iwn_scan_essid { 881 uint8_t id; 882 uint8_t len; 883 uint8_t data[IEEE80211_NWID_LEN]; 884 } __packed; 885 886 struct iwn_scan_hdr { 887 uint16_t len; 888 uint8_t scan_flags; 889 uint8_t nchan; 890 uint16_t quiet_time; 891 uint16_t quiet_threshold; 892 uint16_t crc_threshold; 893 uint16_t rxchain; 894 uint32_t max_svc; /* background scans */ 895 uint32_t pause_svc; /* background scans */ 896 uint32_t flags; 897 uint32_t filter; 898 899 /* Followed by a struct iwn_cmd_data. */ 900 /* Followed by an array of 20 structs iwn_scan_essid. */ 901 /* Followed by probe request body. */ 902 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 903 } __packed; 904 905 struct iwn_scan_chan { 906 uint32_t flags; 907 #define IWN_CHAN_PASSIVE (0 << 0) 908 #define IWN_CHAN_ACTIVE (1 << 0) 909 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 910 911 uint16_t chan; 912 uint8_t rf_gain; 913 uint8_t dsp_gain; 914 uint16_t active; /* msecs */ 915 uint16_t passive; /* msecs */ 916 } __packed; 917 918 #define IWN_SCAN_CRC_TH_DISABLED 0 919 #define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 920 #define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 921 922 /* Maximum size of a scan command. */ 923 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 924 925 /* 926 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 927 * sending probe req. This should be set long enough to hear probe responses 928 * from more than one AP. 929 */ 930 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 931 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 932 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 933 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 934 935 /* 936 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 937 * Must be set longer than active dwell time. 938 * For the most reliable scan, set > AP beacon interval (typically 100msec). 939 */ 940 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 941 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 942 #define IWN_PASSIVE_DWELL_BASE (100) 943 #define IWN_CHANNEL_TUNE_TIME (5) 944 945 #define IWN_SCAN_CHAN_TIMEOUT 2 946 #define IWN_MAX_SCAN_CHANNEL 50 947 948 /* 949 * If active scanning is requested but a certain channel is 950 * marked passive, we can do active scanning if we detect 951 * transmissions. 952 * 953 * There is an issue with some firmware versions that triggers 954 * a sysassert on a "good CRC threshold" of zero (== disabled), 955 * on a radar channel even though this means that we should NOT 956 * send probes. 957 * 958 * The "good CRC threshold" is the number of frames that we 959 * need to receive during our dwell time on a channel before 960 * sending out probes -- setting this to a huge value will 961 * mean we never reach it, but at the same time work around 962 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 963 * here instead of IWL_GOOD_CRC_TH_DISABLED. 964 * 965 * This was fixed in later versions along with some other 966 * scan changes, and the threshold behaves as a flag in those 967 * versions. 968 */ 969 #define IWN_GOOD_CRC_TH_DISABLED 0 970 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 971 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 972 973 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 974 #define IWN_RIDX_MAX 32 975 struct iwn4965_cmd_txpower { 976 uint8_t band; 977 uint8_t reserved1; 978 uint8_t chan; 979 uint8_t reserved2; 980 struct { 981 uint8_t rf_gain[2]; 982 uint8_t dsp_gain[2]; 983 } __packed power[IWN_RIDX_MAX + 1]; 984 } __packed; 985 986 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 987 struct iwn5000_cmd_txpower { 988 int8_t global_limit; /* in half-dBm */ 989 #define IWN5000_TXPOWER_AUTO 0x7f 990 #define IWN5000_TXPOWER_MAX_DBM 16 991 992 uint8_t flags; 993 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 994 995 int8_t srv_limit; /* in half-dBm */ 996 uint8_t reserved; 997 } __packed; 998 999 /* Structures for command IWN_CMD_BLUETOOTH. */ 1000 struct iwn_bluetooth { 1001 uint8_t flags; 1002 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 1003 #define IWN_BT_COEX_BT_PRIO (1 << 1) 1004 #define IWN_BT_COEX_2_WIRE (1 << 2) 1005 1006 uint8_t lead_time; 1007 #define IWN_BT_LEAD_TIME_DEF 30 1008 1009 uint8_t max_kill; 1010 #define IWN_BT_MAX_KILL_DEF 5 1011 1012 uint8_t reserved; 1013 uint32_t kill_ack; 1014 uint32_t kill_cts; 1015 } __packed; 1016 1017 struct iwn6000_btcoex_config { 1018 uint8_t flags; 1019 #define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 1020 #define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 1021 #define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 1022 #define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 1023 #define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 1024 #define IWN_BT_FLAG_COEX6000_MODE_3W 2 1025 #define IWN_BT_FLAG_COEX6000_MODE_4W 3 1026 1027 #define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 1028 #define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 1029 uint8_t lead_time; 1030 uint8_t max_kill; 1031 uint8_t bt3_t7_timer; 1032 uint32_t kill_ack; 1033 uint32_t kill_cts; 1034 uint8_t sample_time; 1035 uint8_t bt3_t2_timer; 1036 uint16_t bt4_reaction; 1037 uint32_t lookup_table[12]; 1038 uint16_t bt4_decision; 1039 uint16_t valid; 1040 uint8_t prio_boost; 1041 uint8_t tx_prio_boost; 1042 uint16_t rx_prio_boost; 1043 } __packed; 1044 1045 /* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1046 struct iwn2000_btcoex_config { 1047 uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1048 uint8_t lead_time; 1049 uint8_t max_kill; 1050 uint8_t bt3_t7_timer; 1051 uint32_t kill_ack; 1052 uint32_t kill_cts; 1053 uint8_t sample_time; 1054 uint8_t bt3_t2_timer; 1055 uint16_t bt4_reaction; 1056 uint32_t lookup_table[12]; 1057 uint16_t bt4_decision; 1058 uint16_t valid; 1059 1060 uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1061 uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1062 1063 uint8_t tx_prio_boost; 1064 uint16_t rx_prio_boost; 1065 } __packed; 1066 1067 struct iwn_btcoex_priotable { 1068 uint8_t calib_init1; 1069 uint8_t calib_init2; 1070 uint8_t calib_periodic_low1; 1071 uint8_t calib_periodic_low2; 1072 uint8_t calib_periodic_high1; 1073 uint8_t calib_periodic_high2; 1074 uint8_t dtim; 1075 uint8_t scan52; 1076 uint8_t scan24; 1077 uint8_t reserved[7]; 1078 } __packed; 1079 1080 struct iwn_btcoex_prot { 1081 uint8_t open; 1082 uint8_t type; 1083 uint8_t reserved[2]; 1084 } __packed; 1085 1086 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1087 struct iwn_critical_temp { 1088 uint32_t reserved; 1089 uint32_t tempM; 1090 uint32_t tempR; 1091 /* degK <-> degC conversion macros. */ 1092 #define IWN_CTOK(c) ((c) + 273) 1093 #define IWN_KTOC(k) ((k) - 273) 1094 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1095 } __packed; 1096 1097 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1098 struct iwn_sensitivity_cmd { 1099 uint16_t which; 1100 #define IWN_SENSITIVITY_DEFAULTTBL 0 1101 #define IWN_SENSITIVITY_WORKTBL 1 1102 1103 uint16_t energy_cck; 1104 uint16_t energy_ofdm; 1105 uint16_t corr_ofdm_x1; 1106 uint16_t corr_ofdm_mrc_x1; 1107 uint16_t corr_cck_mrc_x4; 1108 uint16_t corr_ofdm_x4; 1109 uint16_t corr_ofdm_mrc_x4; 1110 uint16_t corr_barker; 1111 uint16_t corr_barker_mrc; 1112 uint16_t corr_cck_x4; 1113 uint16_t energy_ofdm_th; 1114 } __packed; 1115 1116 struct iwn_enhanced_sensitivity_cmd { 1117 uint16_t which; 1118 uint16_t energy_cck; 1119 uint16_t energy_ofdm; 1120 uint16_t corr_ofdm_x1; 1121 uint16_t corr_ofdm_mrc_x1; 1122 uint16_t corr_cck_mrc_x4; 1123 uint16_t corr_ofdm_x4; 1124 uint16_t corr_ofdm_mrc_x4; 1125 uint16_t corr_barker; 1126 uint16_t corr_barker_mrc; 1127 uint16_t corr_cck_x4; 1128 uint16_t energy_ofdm_th; 1129 /* "Enhanced" part. */ 1130 uint16_t ina_det_ofdm; 1131 uint16_t ina_det_cck; 1132 uint16_t corr_11_9_en; 1133 uint16_t ofdm_det_slope_mrc; 1134 uint16_t ofdm_det_icept_mrc; 1135 uint16_t ofdm_det_slope; 1136 uint16_t ofdm_det_icept; 1137 uint16_t cck_det_slope_mrc; 1138 uint16_t cck_det_icept_mrc; 1139 uint16_t cck_det_slope; 1140 uint16_t cck_det_icept; 1141 uint16_t reserved; 1142 } __packed; 1143 1144 /* 1145 * Define maximal number of calib result send to runtime firmware 1146 * PS: TEMP_OFFSET count for 2 (std and v2) 1147 */ 1148 #define IWN5000_PHY_CALIB_MAX_RESULT 8 1149 1150 /* Structures for command IWN_CMD_PHY_CALIB. */ 1151 struct iwn_phy_calib { 1152 uint8_t code; 1153 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1154 #define IWN5000_PHY_CALIB_DC 8 1155 #define IWN5000_PHY_CALIB_LO 9 1156 #define IWN5000_PHY_CALIB_TX_IQ 11 1157 #define IWN5000_PHY_CALIB_CRYSTAL 15 1158 #define IWN5000_PHY_CALIB_BASE_BAND 16 1159 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1160 #define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1161 1162 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1163 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1164 1165 uint8_t group; 1166 uint8_t ngroups; 1167 uint8_t isvalid; 1168 } __packed; 1169 1170 struct iwn5000_phy_calib_crystal { 1171 uint8_t code; 1172 uint8_t group; 1173 uint8_t ngroups; 1174 uint8_t isvalid; 1175 1176 uint8_t cap_pin[2]; 1177 uint8_t reserved[2]; 1178 } __packed; 1179 1180 struct iwn5000_phy_calib_temp_offset { 1181 uint8_t code; 1182 uint8_t group; 1183 uint8_t ngroups; 1184 uint8_t isvalid; 1185 int16_t offset; 1186 #define IWN_DEFAULT_TEMP_OFFSET 2700 1187 1188 uint16_t reserved; 1189 } __packed; 1190 1191 struct iwn5000_phy_calib_temp_offsetv2 { 1192 uint8_t code; 1193 uint8_t group; 1194 uint8_t ngroups; 1195 uint8_t isvalid; 1196 int16_t offset_high; 1197 int16_t offset_low; 1198 int16_t burnt_voltage_ref; 1199 int16_t reserved; 1200 } __packed; 1201 1202 struct iwn_phy_calib_gain { 1203 uint8_t code; 1204 uint8_t group; 1205 uint8_t ngroups; 1206 uint8_t isvalid; 1207 1208 int8_t gain[3]; 1209 uint8_t reserved; 1210 } __packed; 1211 1212 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1213 struct iwn_spectrum_cmd { 1214 uint16_t len; 1215 uint8_t token; 1216 uint8_t id; 1217 uint8_t origin; 1218 uint8_t periodic; 1219 uint16_t timeout; 1220 uint32_t start; 1221 uint32_t reserved1; 1222 uint32_t flags; 1223 uint32_t filter; 1224 uint16_t nchan; 1225 uint16_t reserved2; 1226 struct { 1227 uint32_t duration; 1228 uint8_t chan; 1229 uint8_t type; 1230 #define IWN_MEASUREMENT_BASIC (1 << 0) 1231 #define IWN_MEASUREMENT_CCA (1 << 1) 1232 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1233 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1234 #define IWN_MEASUREMENT_FRAME (1 << 4) 1235 #define IWN_MEASUREMENT_IDLE (1 << 7) 1236 1237 uint16_t reserved; 1238 } __packed chan[10]; 1239 } __packed; 1240 1241 /* Structure for IWN_UC_READY notification. */ 1242 #define IWN_NATTEN_GROUPS 5 1243 struct iwn_ucode_info { 1244 uint8_t minor; 1245 uint8_t major; 1246 uint16_t reserved1; 1247 uint8_t revision[8]; 1248 uint8_t type; 1249 uint8_t subtype; 1250 #define IWN_UCODE_RUNTIME 0 1251 #define IWN_UCODE_INIT 9 1252 1253 uint16_t reserved2; 1254 uint32_t logptr; 1255 uint32_t errptr; 1256 uint32_t tstamp; 1257 uint32_t valid; 1258 1259 /* The following fields are for UCODE_INIT only. */ 1260 int32_t volt; 1261 struct { 1262 int32_t chan20MHz; 1263 int32_t chan40MHz; 1264 } __packed temp[4]; 1265 int32_t atten[IWN_NATTEN_GROUPS][2]; 1266 } __packed; 1267 1268 /* Structures for IWN_TX_DONE notification. */ 1269 #define IWN_TX_STATUS_MSK 0xff 1270 #define TX_STATUS_SUCCESS 0x01 1271 #define TX_STATUS_DIRECT_DONE 0x02 1272 1273 #define IWN_TX_SUCCESS 0x00 1274 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1275 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1276 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1277 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1278 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1279 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1280 #define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */ 1281 1282 struct iwn4965_tx_stat { 1283 uint8_t nframes; 1284 uint8_t btkillcnt; 1285 uint8_t rtsfailcnt; 1286 uint8_t ackfailcnt; 1287 uint32_t rate; 1288 uint16_t duration; 1289 uint16_t reserved; 1290 uint32_t power[2]; 1291 uint32_t status; 1292 } __packed; 1293 1294 struct iwn5000_tx_stat { 1295 uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1296 uint8_t btkillcnt; 1297 uint8_t rtsfailcnt; 1298 uint8_t ackfailcnt; 1299 uint32_t rate; 1300 uint16_t duration; 1301 uint16_t reserved; 1302 uint32_t power[2]; 1303 uint32_t info; 1304 uint16_t seq; 1305 uint16_t len; 1306 uint8_t tlc; 1307 uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1308 uint8_t fc[2]; 1309 uint16_t status; 1310 uint16_t sequence; 1311 } __packed; 1312 1313 /* Structure for IWN_BEACON_MISSED notification. */ 1314 struct iwn_beacon_missed { 1315 uint32_t consecutive; 1316 uint32_t total; 1317 uint32_t expected; 1318 uint32_t received; 1319 } __packed; 1320 1321 /* Structure for IWN_MPDU_RX_DONE notification. */ 1322 struct iwn_rx_mpdu { 1323 uint16_t len; 1324 uint16_t reserved; 1325 } __packed; 1326 1327 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1328 struct iwn4965_rx_phystat { 1329 uint16_t antenna; 1330 uint16_t agc; 1331 uint8_t rssi[6]; 1332 } __packed; 1333 1334 struct iwn5000_rx_phystat { 1335 uint32_t reserved1; 1336 uint32_t agc; 1337 uint16_t rssi[3]; 1338 } __packed; 1339 1340 struct iwn_rx_stat { 1341 uint8_t phy_len; 1342 uint8_t cfg_phy_len; 1343 #define IWN_STAT_MAXLEN 20 1344 1345 uint8_t id; 1346 uint8_t reserved1; 1347 uint64_t tstamp; 1348 uint32_t beacon; 1349 uint16_t flags; 1350 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1351 1352 uint16_t chan; 1353 uint8_t phybuf[32]; 1354 uint32_t rate; 1355 /* 1356 * rate bit fields 1357 * 1358 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1359 * 2-0: 0) 6 Mbps 1360 * 1) 12 Mbps 1361 * 2) 18 Mbps 1362 * 3) 24 Mbps 1363 * 4) 36 Mbps 1364 * 5) 48 Mbps 1365 * 6) 54 Mbps 1366 * 7) 60 Mbps 1367 * 1368 * 4-3: 0) Single stream (SISO) 1369 * 1) Dual stream (MIMO) 1370 * 2) Triple stream (MIMO) 1371 * 1372 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1373 * 1374 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1375 * 3-0: 0xD) 6 Mbps 1376 * 0xF) 9 Mbps 1377 * 0x5) 12 Mbps 1378 * 0x7) 18 Mbps 1379 * 0x9) 24 Mbps 1380 * 0xB) 36 Mbps 1381 * 0x1) 48 Mbps 1382 * 0x3) 54 Mbps 1383 * 1384 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1385 * 6-0: 10) 1 Mbps 1386 * 20) 2 Mbps 1387 * 55) 5.5 Mbps 1388 * 110) 11 Mbps 1389 * 1390 */ 1391 uint16_t len; 1392 uint16_t reserve3; 1393 } __packed; 1394 1395 #define IWN_RSSI_TO_DBM 44 1396 1397 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1398 struct iwn_compressed_ba { 1399 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1400 uint16_t reserved; 1401 uint8_t id; 1402 uint8_t tid; 1403 uint16_t seq; 1404 uint64_t bitmap; 1405 uint16_t qid; 1406 uint16_t ssn; 1407 } __packed; 1408 1409 /* Structure for IWN_START_SCAN notification. */ 1410 struct iwn_start_scan { 1411 uint64_t tstamp; 1412 uint32_t tbeacon; 1413 uint8_t chan; 1414 uint8_t band; 1415 uint16_t reserved; 1416 uint32_t status; 1417 } __packed; 1418 1419 /* Structure for IWN_STOP_SCAN notification. */ 1420 struct iwn_stop_scan { 1421 uint8_t nchan; 1422 uint8_t status; 1423 uint8_t reserved; 1424 uint8_t chan; 1425 uint64_t tsf; 1426 } __packed; 1427 1428 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1429 struct iwn_spectrum_notif { 1430 uint8_t id; 1431 uint8_t token; 1432 uint8_t idx; 1433 uint8_t state; 1434 #define IWN_MEASUREMENT_START 0 1435 #define IWN_MEASUREMENT_STOP 1 1436 1437 uint32_t start; 1438 uint8_t band; 1439 uint8_t chan; 1440 uint8_t type; 1441 uint8_t reserved1; 1442 uint32_t cca_ofdm; 1443 uint32_t cca_cck; 1444 uint32_t cca_time; 1445 uint8_t basic; 1446 uint8_t reserved2[3]; 1447 uint32_t ofdm[8]; 1448 uint32_t cck[8]; 1449 uint32_t stop; 1450 uint32_t status; 1451 #define IWN_MEASUREMENT_OK 0 1452 #define IWN_MEASUREMENT_CONCURRENT 1 1453 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1454 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1455 #define IWN_MEASUREMENT_STOPPED 6 1456 #define IWN_MEASUREMENT_TIMEOUT 7 1457 #define IWN_MEASUREMENT_FAILED 8 1458 } __packed; 1459 1460 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1461 struct iwn_rx_phy_stats { 1462 uint32_t ina; 1463 uint32_t fina; 1464 uint32_t bad_plcp; 1465 uint32_t bad_crc32; 1466 uint32_t overrun; 1467 uint32_t eoverrun; 1468 uint32_t good_crc32; 1469 uint32_t fa; 1470 uint32_t bad_fina_sync; 1471 uint32_t sfd_timeout; 1472 uint32_t fina_timeout; 1473 uint32_t no_rts_ack; 1474 uint32_t rxe_limit; 1475 uint32_t ack; 1476 uint32_t cts; 1477 uint32_t ba_resp; 1478 uint32_t dsp_kill; 1479 uint32_t bad_mh; 1480 uint32_t rssi_sum; 1481 uint32_t reserved; 1482 } __packed; 1483 1484 struct iwn_rx_general_stats { 1485 uint32_t bad_cts; 1486 uint32_t bad_ack; 1487 uint32_t not_bss; 1488 uint32_t filtered; 1489 uint32_t bad_chan; 1490 uint32_t beacons; 1491 uint32_t missed_beacons; 1492 uint32_t adc_saturated; /* time in 0.8us */ 1493 uint32_t ina_searched; /* time in 0.8us */ 1494 uint32_t noise[3]; 1495 uint32_t flags; 1496 uint32_t load; 1497 uint32_t fa; 1498 uint32_t rssi[3]; 1499 uint32_t energy[3]; 1500 } __packed; 1501 1502 struct iwn_rx_ht_phy_stats { 1503 uint32_t bad_plcp; 1504 uint32_t overrun; 1505 uint32_t eoverrun; 1506 uint32_t good_crc32; 1507 uint32_t bad_crc32; 1508 uint32_t bad_mh; 1509 uint32_t good_ampdu_crc32; 1510 uint32_t ampdu; 1511 uint32_t fragment; 1512 uint32_t reserved; 1513 } __packed; 1514 1515 struct iwn_rx_stats { 1516 struct iwn_rx_phy_stats ofdm; 1517 struct iwn_rx_phy_stats cck; 1518 struct iwn_rx_general_stats general; 1519 struct iwn_rx_ht_phy_stats ht; 1520 } __packed; 1521 1522 struct iwn_tx_stats { 1523 uint32_t preamble; 1524 uint32_t rx_detected; 1525 uint32_t bt_defer; 1526 uint32_t bt_kill; 1527 uint32_t short_len; 1528 uint32_t cts_timeout; 1529 uint32_t ack_timeout; 1530 uint32_t exp_ack; 1531 uint32_t ack; 1532 uint32_t msdu; 1533 uint32_t burst_err1; 1534 uint32_t burst_err2; 1535 uint32_t cts_collision; 1536 uint32_t ack_collision; 1537 uint32_t ba_timeout; 1538 uint32_t ba_resched; 1539 uint32_t query_ampdu; 1540 uint32_t query; 1541 uint32_t query_ampdu_frag; 1542 uint32_t query_mismatch; 1543 uint32_t not_ready; 1544 uint32_t underrun; 1545 uint32_t bt_ht_kill; 1546 uint32_t rx_ba_resp; 1547 uint32_t reserved[2]; 1548 } __packed; 1549 1550 struct iwn_general_stats { 1551 uint32_t temp; 1552 uint32_t temp_m; 1553 uint32_t burst_check; 1554 uint32_t burst; 1555 uint32_t reserved1[4]; 1556 uint32_t sleep; 1557 uint32_t slot_out; 1558 uint32_t slot_idle; 1559 uint32_t ttl_tstamp; 1560 uint32_t tx_ant_a; 1561 uint32_t tx_ant_b; 1562 uint32_t exec; 1563 uint32_t probe; 1564 uint32_t reserved2[2]; 1565 uint32_t rx_enabled; 1566 uint32_t reserved3[3]; 1567 } __packed; 1568 1569 struct iwn_stats { 1570 uint32_t flags; 1571 struct iwn_rx_stats rx; 1572 struct iwn_tx_stats tx; 1573 struct iwn_general_stats general; 1574 } __packed; 1575 1576 1577 /* Firmware error dump. */ 1578 struct iwn_fw_dump { 1579 uint32_t valid; 1580 uint32_t id; 1581 uint32_t pc; 1582 uint32_t branch_link[2]; 1583 uint32_t interrupt_link[2]; 1584 uint32_t error_data[2]; 1585 uint32_t src_line; 1586 uint32_t tsf; 1587 uint32_t time[2]; 1588 } __packed; 1589 1590 /* TLV firmware header. */ 1591 struct iwn_fw_tlv_hdr { 1592 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1593 uint32_t signature; 1594 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1595 1596 uint8_t descr[64]; 1597 uint32_t rev; 1598 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1599 1600 uint32_t build; 1601 uint64_t altmask; 1602 } __packed; 1603 1604 /* TLV header. */ 1605 struct iwn_fw_tlv { 1606 uint16_t type; 1607 #define IWN_FW_TLV_MAIN_TEXT 1 1608 #define IWN_FW_TLV_MAIN_DATA 2 1609 #define IWN_FW_TLV_INIT_TEXT 3 1610 #define IWN_FW_TLV_INIT_DATA 4 1611 #define IWN_FW_TLV_BOOT_TEXT 5 1612 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1613 #define IWN_FW_TLV_PAN 7 1614 #define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1615 #define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1616 #define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1617 #define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1618 #define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1619 #define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1620 #define IWN_FW_TLV_ENH_SENS 14 1621 #define IWN_FW_TLV_PHY_CALIB 15 1622 #define IWN_FW_TLV_WOWLAN_INST 16 1623 #define IWN_FW_TLV_WOWLAN_DATA 17 1624 #define IWN_FW_TLV_FLAGS 18 1625 1626 uint16_t alt; 1627 uint32_t len; 1628 } __packed; 1629 1630 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1631 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1632 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1633 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1634 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1635 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1636 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1637 1638 /* 1639 * Microcode flags TLV (18.) 1640 */ 1641 1642 /** 1643 * enum iwn_ucode_tlv_flag - ucode API flags 1644 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1645 * was a separate TLV but moved here to save space. 1646 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1647 * treats good CRC threshold as a boolean 1648 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1649 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1650 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1651 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1652 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1653 * offload profile config command. 1654 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1655 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1656 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1657 * (rather than two) IPv6 addresses 1658 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1659 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1660 * from the probe request template. 1661 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1662 * connection when going back to D0 1663 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1664 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1665 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1666 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1667 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1668 * containing CAM (Continuous Active Mode) indication. 1669 */ 1670 enum iwn_ucode_tlv_flag { 1671 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1672 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1673 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1674 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1675 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1676 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1677 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1678 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1679 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1680 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1681 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1682 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1683 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1684 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1685 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1686 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1687 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1688 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1689 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1690 }; 1691 1692 /* 1693 * Offsets into EEPROM. 1694 */ 1695 #define IWN_EEPROM_MAC 0x015 1696 #define IWN_EEPROM_SKU_CAP 0x045 1697 #define IWN_EEPROM_RFCFG 0x048 1698 #define IWN4965_EEPROM_DOMAIN 0x060 1699 #define IWN4965_EEPROM_BAND1 0x063 1700 #define IWN5000_EEPROM_REG 0x066 1701 #define IWN5000_EEPROM_CAL 0x067 1702 #define IWN4965_EEPROM_BAND2 0x072 1703 #define IWN4965_EEPROM_BAND3 0x080 1704 #define IWN4965_EEPROM_BAND4 0x08d 1705 #define IWN4965_EEPROM_BAND5 0x099 1706 #define IWN4965_EEPROM_BAND6 0x0a0 1707 #define IWN4965_EEPROM_BAND7 0x0a8 1708 #define IWN4965_EEPROM_MAXPOW 0x0e8 1709 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1710 #define IWN4965_EEPROM_BANDS 0x0ea 1711 /* Indirect offsets. */ 1712 #define IWN5000_EEPROM_NO_HT40 0x000 1713 #define IWN5000_EEPROM_DOMAIN 0x001 1714 #define IWN5000_EEPROM_BAND1 0x004 1715 #define IWN5000_EEPROM_BAND2 0x013 1716 #define IWN5000_EEPROM_BAND3 0x021 1717 #define IWN5000_EEPROM_BAND4 0x02e 1718 #define IWN5000_EEPROM_BAND5 0x03a 1719 #define IWN5000_EEPROM_BAND6 0x041 1720 #define IWN6000_EEPROM_BAND6 0x040 1721 #define IWN5000_EEPROM_BAND7 0x049 1722 #define IWN6000_EEPROM_ENHINFO 0x054 1723 #define IWN5000_EEPROM_CRYSTAL 0x128 1724 #define IWN5000_EEPROM_TEMP 0x12a 1725 #define IWN5000_EEPROM_VOLT 0x12b 1726 1727 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1728 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1729 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1730 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1731 1732 /* Possible flags for IWN_EEPROM_RFCFG. */ 1733 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1734 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1735 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1736 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1737 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1738 1739 struct iwn_eeprom_chan { 1740 uint8_t flags; 1741 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1742 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1743 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1744 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1745 1746 int8_t maxpwr; 1747 } __packed; 1748 1749 struct iwn_eeprom_enhinfo { 1750 uint8_t flags; 1751 #define IWN_ENHINFO_VALID 0x01 1752 #define IWN_ENHINFO_5GHZ 0x02 1753 #define IWN_ENHINFO_OFDM 0x04 1754 #define IWN_ENHINFO_HT40 0x08 1755 #define IWN_ENHINFO_HTAP 0x10 1756 #define IWN_ENHINFO_RES1 0x20 1757 #define IWN_ENHINFO_RES2 0x40 1758 #define IWN_ENHINFO_COMMON 0x80 1759 1760 uint8_t chan; 1761 int8_t chain[3]; /* max power in half-dBm */ 1762 uint8_t reserved; 1763 int8_t mimo2; /* max power in half-dBm */ 1764 int8_t mimo3; /* max power in half-dBm */ 1765 } __packed; 1766 1767 struct iwn5000_eeprom_calib_hdr { 1768 uint8_t version; 1769 uint8_t pa_type; 1770 uint16_t volt; 1771 } __packed; 1772 1773 #define IWN_NSAMPLES 3 1774 struct iwn4965_eeprom_chan_samples { 1775 uint8_t num; 1776 struct { 1777 uint8_t temp; 1778 uint8_t gain; 1779 uint8_t power; 1780 int8_t pa_det; 1781 } samples[2][IWN_NSAMPLES]; 1782 } __packed; 1783 1784 #define IWN_NBANDS 8 1785 struct iwn4965_eeprom_band { 1786 uint8_t lo; /* low channel number */ 1787 uint8_t hi; /* high channel number */ 1788 struct iwn4965_eeprom_chan_samples chans[2]; 1789 } __packed; 1790 1791 /* 1792 * Offsets of channels descriptions in EEPROM. 1793 */ 1794 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1795 IWN4965_EEPROM_BAND1, 1796 IWN4965_EEPROM_BAND2, 1797 IWN4965_EEPROM_BAND3, 1798 IWN4965_EEPROM_BAND4, 1799 IWN4965_EEPROM_BAND5, 1800 IWN4965_EEPROM_BAND6, 1801 IWN4965_EEPROM_BAND7 1802 }; 1803 1804 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1805 IWN5000_EEPROM_BAND1, 1806 IWN5000_EEPROM_BAND2, 1807 IWN5000_EEPROM_BAND3, 1808 IWN5000_EEPROM_BAND4, 1809 IWN5000_EEPROM_BAND5, 1810 IWN5000_EEPROM_BAND6, 1811 IWN5000_EEPROM_BAND7 1812 }; 1813 1814 static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1815 IWN5000_EEPROM_BAND1, 1816 IWN5000_EEPROM_BAND2, 1817 IWN5000_EEPROM_BAND3, 1818 IWN5000_EEPROM_BAND4, 1819 IWN5000_EEPROM_BAND5, 1820 IWN6000_EEPROM_BAND6, 1821 IWN5000_EEPROM_BAND7 1822 }; 1823 1824 static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1825 IWN5000_EEPROM_BAND1, 1826 IWN5000_EEPROM_BAND2, 1827 IWN5000_EEPROM_BAND3, 1828 IWN5000_EEPROM_BAND4, 1829 IWN5000_EEPROM_BAND5, 1830 IWN5000_EEPROM_BAND6, 1831 IWN5000_EEPROM_NO_HT40, 1832 }; 1833 1834 static const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = { 1835 IWN5000_EEPROM_BAND1, 1836 IWN5000_EEPROM_BAND2, 1837 IWN5000_EEPROM_BAND3, 1838 IWN5000_EEPROM_BAND4, 1839 IWN5000_EEPROM_BAND5, 1840 IWN6000_EEPROM_BAND6, 1841 IWN5000_EEPROM_BAND7 1842 }; 1843 1844 #define IWN_CHAN_BANDS_COUNT 7 1845 #define IWN_MAX_CHAN_PER_BAND 14 1846 static const struct iwn_chan_band { 1847 uint8_t nchan; 1848 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1849 } iwn_bands[] = { 1850 /* 20MHz channels, 2GHz band. */ 1851 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1852 /* 20MHz channels, 5GHz band. */ 1853 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1854 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1855 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1856 { 6, { 145, 149, 153, 157, 161, 165 } }, 1857 /* 40MHz channels (primary channels), 2GHz band. */ 1858 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1859 /* 40MHz channels (primary channels), 5GHz band. */ 1860 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1861 }; 1862 1863 static const uint8_t iwn_bss_ac_to_queue[] = { 1864 2, 3, 1, 0, 1865 }; 1866 1867 static const uint8_t iwn_pan_ac_to_queue[] = { 1868 5, 4, 6, 7, 1869 }; 1870 #define IWN1000_OTP_NBLOCKS 3 1871 #define IWN6000_OTP_NBLOCKS 4 1872 #define IWN6050_OTP_NBLOCKS 7 1873 1874 /* HW rate indices. */ 1875 #define IWN_RIDX_CCK1 0 1876 #define IWN_RIDX_OFDM6 4 1877 1878 #define IWN4965_MAX_PWR_INDEX 107 1879 #define IWN_POWERSAVE_LVL_NONE 0 1880 #define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 1881 #define IWN_POWERSAVE_LVL_MAX 5 1882 1883 #define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 1884 1885 /* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 1886 #define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 1887 1888 /* 1889 * RF Tx gain values from highest to lowest power (values obtained from 1890 * the reference driver.) 1891 */ 1892 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1893 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1894 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1895 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1896 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1897 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1898 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1899 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1900 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1901 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1902 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1903 }; 1904 1905 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1906 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1907 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1908 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1909 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1910 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1911 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1912 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1913 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1914 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1915 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1916 }; 1917 1918 /* 1919 * DSP pre-DAC gain values from highest to lowest power (values obtained 1920 * from the reference driver.) 1921 */ 1922 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1923 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1924 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1925 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1926 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1927 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1928 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1929 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1930 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1931 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1932 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1933 }; 1934 1935 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1936 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1937 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1938 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1939 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1940 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1941 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1942 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1943 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1944 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1945 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1946 }; 1947 1948 /* 1949 * Power saving settings (values obtained from the reference driver.) 1950 */ 1951 #define IWN_NDTIMRANGES 3 1952 #define IWN_NPOWERLEVELS 6 1953 static const struct iwn_pmgt { 1954 uint32_t rxtimeout; 1955 uint32_t txtimeout; 1956 uint32_t intval[5]; 1957 int skip_dtim; 1958 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1959 /* DTIM <= 2 */ 1960 { 1961 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1962 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1963 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1964 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1965 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1966 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1967 }, 1968 /* 3 <= DTIM <= 10 */ 1969 { 1970 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1971 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1972 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1973 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1974 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1975 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1976 }, 1977 /* DTIM >= 11 */ 1978 { 1979 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1980 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1981 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1982 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1983 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1984 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1985 } 1986 }; 1987 1988 struct iwn_sensitivity_limits { 1989 uint32_t min_ofdm_x1; 1990 uint32_t max_ofdm_x1; 1991 uint32_t min_ofdm_mrc_x1; 1992 uint32_t max_ofdm_mrc_x1; 1993 uint32_t min_ofdm_x4; 1994 uint32_t max_ofdm_x4; 1995 uint32_t min_ofdm_mrc_x4; 1996 uint32_t max_ofdm_mrc_x4; 1997 uint32_t min_cck_x4; 1998 uint32_t max_cck_x4; 1999 uint32_t min_cck_mrc_x4; 2000 uint32_t max_cck_mrc_x4; 2001 uint32_t min_energy_cck; 2002 uint32_t energy_cck; 2003 uint32_t energy_ofdm; 2004 uint32_t barker_mrc; 2005 }; 2006 2007 /* 2008 * RX sensitivity limits (values obtained from the reference driver.) 2009 */ 2010 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 2011 105, 140, 2012 220, 270, 2013 85, 120, 2014 170, 210, 2015 125, 200, 2016 200, 400, 2017 97, 2018 100, 2019 100, 2020 390 2021 }; 2022 2023 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 2024 120, 120, /* min = max for performance bug in DSP. */ 2025 240, 240, /* min = max for performance bug in DSP. */ 2026 90, 120, 2027 170, 210, 2028 125, 200, 2029 170, 400, 2030 95, 2031 95, 2032 95, 2033 390 2034 }; 2035 2036 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 2037 105, 105, /* min = max for performance bug in DSP. */ 2038 220, 220, /* min = max for performance bug in DSP. */ 2039 90, 120, 2040 170, 210, 2041 125, 200, 2042 170, 400, 2043 95, 2044 95, 2045 95, 2046 390, 2047 }; 2048 2049 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 2050 120, 155, 2051 240, 290, 2052 90, 120, 2053 170, 210, 2054 125, 200, 2055 170, 400, 2056 95, 2057 95, 2058 95, 2059 390, 2060 }; 2061 2062 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 2063 105, 110, 2064 192, 232, 2065 80, 145, 2066 128, 232, 2067 125, 175, 2068 160, 310, 2069 97, 2070 97, 2071 100, 2072 390 2073 }; 2074 2075 static const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = { 2076 105, 110, 2077 192, 232, 2078 80, 145, 2079 128, 232, 2080 125, 175, 2081 160, 310, 2082 100, 2083 110, 2084 110, 2085 336 2086 }; 2087 2088 2089 /* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 2090 static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 2091 105,110, 2092 128,232, 2093 80,145, 2094 128,232, 2095 125,175, 2096 160,310, 2097 97, 2098 97, 2099 110 2100 }; 2101 2102 /* Map TID to TX scheduler's FIFO. */ 2103 static const uint8_t iwn_tid2fifo[] = { 2104 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 2105 }; 2106 2107 /* WiFi/WiMAX coexist event priority table for 6050. */ 2108 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 2109 { 0x04, 0x03, 0x00, 0x00 }, 2110 { 0x04, 0x03, 0x00, 0x03 }, 2111 { 0x04, 0x03, 0x00, 0x03 }, 2112 { 0x04, 0x03, 0x00, 0x03 }, 2113 { 0x04, 0x03, 0x00, 0x00 }, 2114 { 0x04, 0x03, 0x00, 0x07 }, 2115 { 0x04, 0x03, 0x00, 0x00 }, 2116 { 0x04, 0x03, 0x00, 0x03 }, 2117 { 0x04, 0x03, 0x00, 0x03 }, 2118 { 0x04, 0x03, 0x00, 0x00 }, 2119 { 0x06, 0x03, 0x00, 0x07 }, 2120 { 0x04, 0x03, 0x00, 0x00 }, 2121 { 0x06, 0x06, 0x00, 0x03 }, 2122 { 0x04, 0x03, 0x00, 0x07 }, 2123 { 0x04, 0x03, 0x00, 0x00 }, 2124 { 0x04, 0x03, 0x00, 0x00 } 2125 }; 2126 2127 /* Firmware errors. */ 2128 static const char * const iwn_fw_errmsg[] = { 2129 "OK", 2130 "FAIL", 2131 "BAD_PARAM", 2132 "BAD_CHECKSUM", 2133 "NMI_INTERRUPT_WDG", 2134 "SYSASSERT", 2135 "FATAL_ERROR", 2136 "BAD_COMMAND", 2137 "HW_ERROR_TUNE_LOCK", 2138 "HW_ERROR_TEMPERATURE", 2139 "ILLEGAL_CHAN_FREQ", 2140 "VCC_NOT_STABLE", 2141 "FH_ERROR", 2142 "NMI_INTERRUPT_HOST", 2143 "NMI_INTERRUPT_ACTION_PT", 2144 "NMI_INTERRUPT_UNKNOWN", 2145 "UCODE_VERSION_MISMATCH", 2146 "HW_ERROR_ABS_LOCK", 2147 "HW_ERROR_CAL_LOCK_FAIL", 2148 "NMI_INTERRUPT_INST_ACTION_PT", 2149 "NMI_INTERRUPT_DATA_ACTION_PT", 2150 "NMI_TRM_HW_ER", 2151 "NMI_INTERRUPT_TRM", 2152 "NMI_INTERRUPT_BREAKPOINT" 2153 "DEBUG_0", 2154 "DEBUG_1", 2155 "DEBUG_2", 2156 "DEBUG_3", 2157 "ADVANCED_SYSASSERT" 2158 }; 2159 2160 /* Find least significant bit that is set. */ 2161 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2162 2163 #define IWN_READ(sc, reg) \ 2164 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2165 2166 #define IWN_WRITE(sc, reg, val) \ 2167 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2168 2169 #define IWN_WRITE_1(sc, reg, val) \ 2170 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2171 2172 #define IWN_SETBITS(sc, reg, mask) \ 2173 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2174 2175 #define IWN_CLRBITS(sc, reg, mask) \ 2176 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2177 2178 #define IWN_BARRIER_WRITE(sc) \ 2179 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2180 BUS_SPACE_BARRIER_WRITE) 2181 2182 #define IWN_BARRIER_READ_WRITE(sc) \ 2183 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2184 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2185 2186 #endif /* __IF_IWNREG_H__ */ 2187