1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_common.h" 36 #include "ixgbe_api.h" 37 38 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); 39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 45 u16 count); 46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 50 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 51 52 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); 53 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); 54 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 55 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); 56 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 57 58 /** 59 * ixgbe_init_ops_generic - Inits function ptrs 60 * @hw: pointer to the hardware structure 61 * 62 * Initialize the function pointers. 63 **/ 64 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 65 { 66 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 67 struct ixgbe_mac_info *mac = &hw->mac; 68 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 69 70 /* EEPROM */ 71 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 72 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 73 if (eec & (1 << 8)) 74 eeprom->ops.read = &ixgbe_read_eeprom_generic; 75 else 76 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 77 eeprom->ops.write = &ixgbe_write_eeprom_generic; 78 eeprom->ops.validate_checksum = 79 &ixgbe_validate_eeprom_checksum_generic; 80 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 81 82 /* MAC */ 83 mac->ops.init_hw = &ixgbe_init_hw_generic; 84 mac->ops.reset_hw = NULL; 85 mac->ops.start_hw = &ixgbe_start_hw_generic; 86 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 87 mac->ops.get_media_type = NULL; 88 mac->ops.get_supported_physical_layer = NULL; 89 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 90 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 91 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 92 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 93 94 /* LEDs */ 95 mac->ops.led_on = &ixgbe_led_on_generic; 96 mac->ops.led_off = &ixgbe_led_off_generic; 97 mac->ops.blink_led_start = NULL; 98 mac->ops.blink_led_stop = NULL; 99 100 /* RAR, Multicast, VLAN */ 101 mac->ops.set_rar = &ixgbe_set_rar_generic; 102 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 103 mac->ops.set_vmdq = NULL; 104 mac->ops.clear_vmdq = NULL; 105 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 106 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 107 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 108 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 109 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 110 mac->ops.clear_vfta = NULL; 111 mac->ops.set_vfta = NULL; 112 mac->ops.init_uta_tables = NULL; 113 114 115 /* Link */ 116 mac->ops.get_link_capabilities = NULL; 117 mac->ops.setup_link = NULL; 118 mac->ops.setup_link_speed = NULL; 119 mac->ops.check_link = NULL; 120 121 return IXGBE_SUCCESS; 122 } 123 124 /** 125 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 126 * @hw: pointer to hardware structure 127 * 128 * Starts the hardware by filling the bus info structure and media type, clears 129 * all on chip counters, initializes receive address registers, multicast 130 * table, VLAN filter table, calls routine to set up link and flow control 131 * settings, and leaves transmit and receive units disabled and uninitialized 132 **/ 133 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 134 { 135 u32 ctrl_ext; 136 137 /* Set the media type */ 138 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 139 140 /* Set bus info */ 141 hw->mac.ops.get_bus_info(hw); 142 143 /* Identify the PHY */ 144 hw->phy.ops.identify(hw); 145 146 /* 147 * Store MAC address from RAR0, clear receive address registers, and 148 * clear the multicast table 149 */ 150 hw->mac.ops.init_rx_addrs(hw); 151 152 /* Clear the VLAN filter table */ 153 hw->mac.ops.clear_vfta(hw); 154 155 /* Set up link */ 156 hw->mac.ops.setup_link(hw); 157 158 /* Clear statistics registers */ 159 hw->mac.ops.clear_hw_cntrs(hw); 160 161 /* Set No Snoop Disable */ 162 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 163 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 164 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 165 IXGBE_WRITE_FLUSH(hw); 166 167 /* Clear adapter stopped flag */ 168 hw->adapter_stopped = FALSE; 169 170 return IXGBE_SUCCESS; 171 } 172 173 /** 174 * ixgbe_init_hw_generic - Generic hardware initialization 175 * @hw: pointer to hardware structure 176 * 177 * Initialize the hardware by resetting the hardware, filling the bus info 178 * structure and media type, clears all on chip counters, initializes receive 179 * address registers, multicast table, VLAN filter table, calls routine to set 180 * up link and flow control settings, and leaves transmit and receive units 181 * disabled and uninitialized 182 **/ 183 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 184 { 185 /* Reset the hardware */ 186 hw->mac.ops.reset_hw(hw); 187 188 /* Start the HW */ 189 hw->mac.ops.start_hw(hw); 190 191 return IXGBE_SUCCESS; 192 } 193 194 /** 195 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 196 * @hw: pointer to hardware structure 197 * 198 * Clears all hardware statistics counters by reading them from the hardware 199 * Statistics counters are clear on read. 200 **/ 201 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 202 { 203 u16 i = 0; 204 205 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 206 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 207 IXGBE_READ_REG(hw, IXGBE_ERRBC); 208 IXGBE_READ_REG(hw, IXGBE_MSPDC); 209 for (i = 0; i < 8; i++) 210 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 211 212 IXGBE_READ_REG(hw, IXGBE_MLFC); 213 IXGBE_READ_REG(hw, IXGBE_MRFC); 214 IXGBE_READ_REG(hw, IXGBE_RLEC); 215 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 216 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 217 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 218 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 219 220 for (i = 0; i < 8; i++) { 221 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 222 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 223 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 224 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 225 } 226 IXGBE_READ_REG(hw, IXGBE_PRC64); 227 IXGBE_READ_REG(hw, IXGBE_PRC127); 228 IXGBE_READ_REG(hw, IXGBE_PRC255); 229 IXGBE_READ_REG(hw, IXGBE_PRC511); 230 IXGBE_READ_REG(hw, IXGBE_PRC1023); 231 IXGBE_READ_REG(hw, IXGBE_PRC1522); 232 IXGBE_READ_REG(hw, IXGBE_GPRC); 233 IXGBE_READ_REG(hw, IXGBE_BPRC); 234 IXGBE_READ_REG(hw, IXGBE_MPRC); 235 IXGBE_READ_REG(hw, IXGBE_GPTC); 236 IXGBE_READ_REG(hw, IXGBE_GORCL); 237 IXGBE_READ_REG(hw, IXGBE_GORCH); 238 IXGBE_READ_REG(hw, IXGBE_GOTCL); 239 IXGBE_READ_REG(hw, IXGBE_GOTCH); 240 for (i = 0; i < 8; i++) 241 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 242 IXGBE_READ_REG(hw, IXGBE_RUC); 243 IXGBE_READ_REG(hw, IXGBE_RFC); 244 IXGBE_READ_REG(hw, IXGBE_ROC); 245 IXGBE_READ_REG(hw, IXGBE_RJC); 246 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 247 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 248 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 249 IXGBE_READ_REG(hw, IXGBE_TORL); 250 IXGBE_READ_REG(hw, IXGBE_TORH); 251 IXGBE_READ_REG(hw, IXGBE_TPR); 252 IXGBE_READ_REG(hw, IXGBE_TPT); 253 IXGBE_READ_REG(hw, IXGBE_PTC64); 254 IXGBE_READ_REG(hw, IXGBE_PTC127); 255 IXGBE_READ_REG(hw, IXGBE_PTC255); 256 IXGBE_READ_REG(hw, IXGBE_PTC511); 257 IXGBE_READ_REG(hw, IXGBE_PTC1023); 258 IXGBE_READ_REG(hw, IXGBE_PTC1522); 259 IXGBE_READ_REG(hw, IXGBE_MPTC); 260 IXGBE_READ_REG(hw, IXGBE_BPTC); 261 for (i = 0; i < 16; i++) { 262 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 263 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 264 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 265 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 266 } 267 268 return IXGBE_SUCCESS; 269 } 270 271 /** 272 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 273 * @hw: pointer to hardware structure 274 * @pba_num: stores the part number from the EEPROM 275 * 276 * Reads the part number from the EEPROM. 277 **/ 278 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 279 { 280 s32 ret_val; 281 u16 data; 282 283 DEBUGFUNC("ixgbe_read_pba_num_generic"); 284 285 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 286 if (ret_val) { 287 DEBUGOUT("NVM Read Error\n"); 288 return ret_val; 289 } 290 *pba_num = (u32)(data << 16); 291 292 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 293 if (ret_val) { 294 DEBUGOUT("NVM Read Error\n"); 295 return ret_val; 296 } 297 *pba_num |= data; 298 299 return IXGBE_SUCCESS; 300 } 301 302 /** 303 * ixgbe_get_mac_addr_generic - Generic get MAC address 304 * @hw: pointer to hardware structure 305 * @mac_addr: Adapter MAC address 306 * 307 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 308 * A reset of the adapter must be performed prior to calling this function 309 * in order for the MAC address to have been loaded from the EEPROM into RAR0 310 **/ 311 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 312 { 313 u32 rar_high; 314 u32 rar_low; 315 u16 i; 316 317 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 318 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 319 320 for (i = 0; i < 4; i++) 321 mac_addr[i] = (u8)(rar_low >> (i*8)); 322 323 for (i = 0; i < 2; i++) 324 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 325 326 return IXGBE_SUCCESS; 327 } 328 329 /** 330 * ixgbe_get_bus_info_generic - Generic set PCI bus info 331 * @hw: pointer to hardware structure 332 * 333 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 334 **/ 335 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 336 { 337 struct ixgbe_mac_info *mac = &hw->mac; 338 u16 link_status; 339 340 hw->bus.type = ixgbe_bus_type_pci_express; 341 342 /* Get the negotiated link width and speed from PCI config space */ 343 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 344 345 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 346 case IXGBE_PCI_LINK_WIDTH_1: 347 hw->bus.width = ixgbe_bus_width_pcie_x1; 348 break; 349 case IXGBE_PCI_LINK_WIDTH_2: 350 hw->bus.width = ixgbe_bus_width_pcie_x2; 351 break; 352 case IXGBE_PCI_LINK_WIDTH_4: 353 hw->bus.width = ixgbe_bus_width_pcie_x4; 354 break; 355 case IXGBE_PCI_LINK_WIDTH_8: 356 hw->bus.width = ixgbe_bus_width_pcie_x8; 357 break; 358 default: 359 hw->bus.width = ixgbe_bus_width_unknown; 360 break; 361 } 362 363 switch (link_status & IXGBE_PCI_LINK_SPEED) { 364 case IXGBE_PCI_LINK_SPEED_2500: 365 hw->bus.speed = ixgbe_bus_speed_2500; 366 break; 367 case IXGBE_PCI_LINK_SPEED_5000: 368 hw->bus.speed = ixgbe_bus_speed_5000; 369 break; 370 default: 371 hw->bus.speed = ixgbe_bus_speed_unknown; 372 break; 373 } 374 375 mac->ops.set_lan_id(hw); 376 377 return IXGBE_SUCCESS; 378 } 379 380 /** 381 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 382 * @hw: pointer to the HW structure 383 * 384 * Determines the LAN function id by reading memory-mapped registers 385 * and swaps the port value if requested. 386 **/ 387 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 388 { 389 struct ixgbe_bus_info *bus = &hw->bus; 390 u32 reg; 391 392 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 393 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 394 395 /* check for a port swap */ 396 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 397 if (reg & IXGBE_FACTPS_LFS) 398 bus->func ^= 0x1; 399 } 400 401 /** 402 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 403 * @hw: pointer to hardware structure 404 * 405 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 406 * disables transmit and receive units. The adapter_stopped flag is used by 407 * the shared code and drivers to determine if the adapter is in a stopped 408 * state and should not touch the hardware. 409 **/ 410 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 411 { 412 u32 number_of_queues; 413 u32 reg_val; 414 u16 i; 415 416 /* 417 * Set the adapter_stopped flag so other driver functions stop touching 418 * the hardware 419 */ 420 hw->adapter_stopped = TRUE; 421 422 /* Disable the receive unit */ 423 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 424 reg_val &= ~(IXGBE_RXCTRL_RXEN); 425 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 426 IXGBE_WRITE_FLUSH(hw); 427 msec_delay(2); 428 429 /* Clear interrupt mask to stop from interrupts being generated */ 430 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 431 432 /* Clear any pending interrupts */ 433 IXGBE_READ_REG(hw, IXGBE_EICR); 434 435 /* Disable the transmit unit. Each queue must be disabled. */ 436 number_of_queues = hw->mac.max_tx_queues; 437 for (i = 0; i < number_of_queues; i++) { 438 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 439 if (reg_val & IXGBE_TXDCTL_ENABLE) { 440 reg_val &= ~IXGBE_TXDCTL_ENABLE; 441 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 442 } 443 } 444 445 /* 446 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 447 * access and verify no pending requests 448 */ 449 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) 450 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 451 452 return IXGBE_SUCCESS; 453 } 454 455 /** 456 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 457 * @hw: pointer to hardware structure 458 * @index: led number to turn on 459 **/ 460 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 461 { 462 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 463 464 /* To turn on the LED, set mode to ON. */ 465 led_reg &= ~IXGBE_LED_MODE_MASK(index); 466 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 467 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 468 IXGBE_WRITE_FLUSH(hw); 469 470 return IXGBE_SUCCESS; 471 } 472 473 /** 474 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 475 * @hw: pointer to hardware structure 476 * @index: led number to turn off 477 **/ 478 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 479 { 480 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 481 482 /* To turn off the LED, set mode to OFF. */ 483 led_reg &= ~IXGBE_LED_MODE_MASK(index); 484 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 485 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 486 IXGBE_WRITE_FLUSH(hw); 487 488 return IXGBE_SUCCESS; 489 } 490 491 /** 492 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 493 * @hw: pointer to hardware structure 494 * 495 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 496 * ixgbe_hw struct in order to set up EEPROM access. 497 **/ 498 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 499 { 500 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 501 u32 eec; 502 u16 eeprom_size; 503 504 if (eeprom->type == ixgbe_eeprom_uninitialized) { 505 eeprom->type = ixgbe_eeprom_none; 506 /* Set default semaphore delay to 10ms which is a well 507 * tested value */ 508 eeprom->semaphore_delay = 10; 509 510 /* 511 * Check for EEPROM present first. 512 * If not present leave as none 513 */ 514 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 515 if (eec & IXGBE_EEC_PRES) { 516 eeprom->type = ixgbe_eeprom_spi; 517 518 /* 519 * SPI EEPROM is assumed here. This code would need to 520 * change if a future EEPROM is not SPI. 521 */ 522 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 523 IXGBE_EEC_SIZE_SHIFT); 524 eeprom->word_size = 1 << (eeprom_size + 525 IXGBE_EEPROM_WORD_SIZE_SHIFT); 526 } 527 528 if (eec & IXGBE_EEC_ADDR_SIZE) 529 eeprom->address_bits = 16; 530 else 531 eeprom->address_bits = 8; 532 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 533 "%d\n", eeprom->type, eeprom->word_size, 534 eeprom->address_bits); 535 } 536 537 return IXGBE_SUCCESS; 538 } 539 540 /** 541 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 542 * @hw: pointer to hardware structure 543 * @offset: offset within the EEPROM to be written to 544 * @data: 16 bit word to be written to the EEPROM 545 * 546 * If ixgbe_eeprom_update_checksum is not called after this function, the 547 * EEPROM will most likely contain an invalid checksum. 548 **/ 549 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 550 { 551 s32 status; 552 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 553 554 hw->eeprom.ops.init_params(hw); 555 556 if (offset >= hw->eeprom.word_size) { 557 status = IXGBE_ERR_EEPROM; 558 goto out; 559 } 560 561 /* Prepare the EEPROM for writing */ 562 status = ixgbe_acquire_eeprom(hw); 563 564 if (status == IXGBE_SUCCESS) { 565 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 566 ixgbe_release_eeprom(hw); 567 status = IXGBE_ERR_EEPROM; 568 } 569 } 570 571 if (status == IXGBE_SUCCESS) { 572 ixgbe_standby_eeprom(hw); 573 574 /* Send the WRITE ENABLE command (8 bit opcode ) */ 575 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 576 IXGBE_EEPROM_OPCODE_BITS); 577 578 ixgbe_standby_eeprom(hw); 579 580 /* 581 * Some SPI eeproms use the 8th address bit embedded in the 582 * opcode 583 */ 584 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 585 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 586 587 /* Send the Write command (8-bit opcode + addr) */ 588 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 589 IXGBE_EEPROM_OPCODE_BITS); 590 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 591 hw->eeprom.address_bits); 592 593 /* Send the data */ 594 data = (data >> 8) | (data << 8); 595 ixgbe_shift_out_eeprom_bits(hw, data, 16); 596 ixgbe_standby_eeprom(hw); 597 598 msec_delay(hw->eeprom.semaphore_delay); 599 /* Done with writing - release the EEPROM */ 600 ixgbe_release_eeprom(hw); 601 } 602 603 out: 604 return status; 605 } 606 607 /** 608 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 609 * @hw: pointer to hardware structure 610 * @offset: offset within the EEPROM to be read 611 * @data: read 16 bit value from EEPROM 612 * 613 * Reads 16 bit value from EEPROM through bit-bang method 614 **/ 615 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 616 u16 *data) 617 { 618 s32 status; 619 u16 word_in; 620 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 621 622 hw->eeprom.ops.init_params(hw); 623 624 if (offset >= hw->eeprom.word_size) { 625 status = IXGBE_ERR_EEPROM; 626 goto out; 627 } 628 629 /* Prepare the EEPROM for reading */ 630 status = ixgbe_acquire_eeprom(hw); 631 632 if (status == IXGBE_SUCCESS) { 633 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 634 ixgbe_release_eeprom(hw); 635 status = IXGBE_ERR_EEPROM; 636 } 637 } 638 639 if (status == IXGBE_SUCCESS) { 640 ixgbe_standby_eeprom(hw); 641 642 /* 643 * Some SPI eeproms use the 8th address bit embedded in the 644 * opcode 645 */ 646 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 647 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 648 649 /* Send the READ command (opcode + addr) */ 650 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 651 IXGBE_EEPROM_OPCODE_BITS); 652 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 653 hw->eeprom.address_bits); 654 655 /* Read the data. */ 656 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 657 *data = (word_in >> 8) | (word_in << 8); 658 659 /* End this read operation */ 660 ixgbe_release_eeprom(hw); 661 } 662 663 out: 664 return status; 665 } 666 667 /** 668 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 669 * @hw: pointer to hardware structure 670 * @offset: offset of word in the EEPROM to read 671 * @data: word read from the EEPROM 672 * 673 * Reads a 16 bit word from the EEPROM using the EERD register. 674 **/ 675 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 676 { 677 u32 eerd; 678 s32 status; 679 680 hw->eeprom.ops.init_params(hw); 681 682 if (offset >= hw->eeprom.word_size) { 683 status = IXGBE_ERR_EEPROM; 684 goto out; 685 } 686 687 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 688 IXGBE_EEPROM_READ_REG_START; 689 690 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 691 status = ixgbe_poll_eeprom_eerd_done(hw); 692 693 if (status == IXGBE_SUCCESS) 694 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 695 IXGBE_EEPROM_READ_REG_DATA); 696 else 697 DEBUGOUT("Eeprom read timed out\n"); 698 699 out: 700 return status; 701 } 702 703 /** 704 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 705 * @hw: pointer to hardware structure 706 * 707 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 708 **/ 709 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 710 { 711 u32 i; 712 u32 reg; 713 s32 status = IXGBE_ERR_EEPROM; 714 715 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 716 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 717 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 718 status = IXGBE_SUCCESS; 719 break; 720 } 721 usec_delay(5); 722 } 723 return status; 724 } 725 726 /** 727 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 728 * @hw: pointer to hardware structure 729 * 730 * Prepares EEPROM for access using bit-bang method. This function should 731 * be called before issuing a command to the EEPROM. 732 **/ 733 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 734 { 735 s32 status = IXGBE_SUCCESS; 736 u32 eec; 737 u32 i; 738 739 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 740 status = IXGBE_ERR_SWFW_SYNC; 741 742 if (status == IXGBE_SUCCESS) { 743 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 744 745 /* Request EEPROM Access */ 746 eec |= IXGBE_EEC_REQ; 747 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 748 749 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 750 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 751 if (eec & IXGBE_EEC_GNT) 752 break; 753 usec_delay(5); 754 } 755 756 /* Release if grant not acquired */ 757 if (!(eec & IXGBE_EEC_GNT)) { 758 eec &= ~IXGBE_EEC_REQ; 759 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 760 DEBUGOUT("Could not acquire EEPROM grant\n"); 761 762 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 763 status = IXGBE_ERR_EEPROM; 764 } 765 } 766 767 /* Setup EEPROM for Read/Write */ 768 if (status == IXGBE_SUCCESS) { 769 /* Clear CS and SK */ 770 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 771 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 772 IXGBE_WRITE_FLUSH(hw); 773 usec_delay(1); 774 } 775 return status; 776 } 777 778 /** 779 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 780 * @hw: pointer to hardware structure 781 * 782 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 783 **/ 784 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 785 { 786 s32 status = IXGBE_ERR_EEPROM; 787 u32 timeout; 788 u32 i; 789 u32 swsm; 790 791 /* Set timeout value based on size of EEPROM */ 792 timeout = hw->eeprom.word_size + 1; 793 794 /* Get SMBI software semaphore between device drivers first */ 795 for (i = 0; i < timeout; i++) { 796 /* 797 * If the SMBI bit is 0 when we read it, then the bit will be 798 * set and we have the semaphore 799 */ 800 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 801 if (!(swsm & IXGBE_SWSM_SMBI)) { 802 status = IXGBE_SUCCESS; 803 break; 804 } 805 msec_delay(1); 806 } 807 808 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 809 if (status == IXGBE_SUCCESS) { 810 for (i = 0; i < timeout; i++) { 811 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 812 813 /* Set the SW EEPROM semaphore bit to request access */ 814 swsm |= IXGBE_SWSM_SWESMBI; 815 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 816 817 /* 818 * If we set the bit successfully then we got the 819 * semaphore. 820 */ 821 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 822 if (swsm & IXGBE_SWSM_SWESMBI) 823 break; 824 825 usec_delay(50); 826 } 827 828 /* 829 * Release semaphores and return error if SW EEPROM semaphore 830 * was not granted because we don't have access to the EEPROM 831 */ 832 if (i >= timeout) { 833 DEBUGOUT("Driver can't access the Eeprom - Semaphore " 834 "not granted.\n"); 835 ixgbe_release_eeprom_semaphore(hw); 836 status = IXGBE_ERR_EEPROM; 837 } 838 } 839 840 return status; 841 } 842 843 /** 844 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 845 * @hw: pointer to hardware structure 846 * 847 * This function clears hardware semaphore bits. 848 **/ 849 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 850 { 851 u32 swsm; 852 853 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 854 855 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 856 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 857 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 858 IXGBE_WRITE_FLUSH(hw); 859 } 860 861 /** 862 * ixgbe_ready_eeprom - Polls for EEPROM ready 863 * @hw: pointer to hardware structure 864 **/ 865 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 866 { 867 s32 status = IXGBE_SUCCESS; 868 u16 i; 869 u8 spi_stat_reg; 870 871 /* 872 * Read "Status Register" repeatedly until the LSB is cleared. The 873 * EEPROM will signal that the command has been completed by clearing 874 * bit 0 of the internal status register. If it's not cleared within 875 * 5 milliseconds, then error out. 876 */ 877 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 878 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 879 IXGBE_EEPROM_OPCODE_BITS); 880 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 881 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 882 break; 883 884 usec_delay(5); 885 ixgbe_standby_eeprom(hw); 886 }; 887 888 /* 889 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 890 * devices (and only 0-5mSec on 5V devices) 891 */ 892 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 893 DEBUGOUT("SPI EEPROM Status error\n"); 894 status = IXGBE_ERR_EEPROM; 895 } 896 897 return status; 898 } 899 900 /** 901 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 902 * @hw: pointer to hardware structure 903 **/ 904 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 905 { 906 u32 eec; 907 908 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 909 910 /* Toggle CS to flush commands */ 911 eec |= IXGBE_EEC_CS; 912 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 913 IXGBE_WRITE_FLUSH(hw); 914 usec_delay(1); 915 eec &= ~IXGBE_EEC_CS; 916 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 917 IXGBE_WRITE_FLUSH(hw); 918 usec_delay(1); 919 } 920 921 /** 922 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 923 * @hw: pointer to hardware structure 924 * @data: data to send to the EEPROM 925 * @count: number of bits to shift out 926 **/ 927 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 928 u16 count) 929 { 930 u32 eec; 931 u32 mask; 932 u32 i; 933 934 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 935 936 /* 937 * Mask is used to shift "count" bits of "data" out to the EEPROM 938 * one bit at a time. Determine the starting bit based on count 939 */ 940 mask = 0x01 << (count - 1); 941 942 for (i = 0; i < count; i++) { 943 /* 944 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 945 * "1", and then raising and then lowering the clock (the SK 946 * bit controls the clock input to the EEPROM). A "0" is 947 * shifted out to the EEPROM by setting "DI" to "0" and then 948 * raising and then lowering the clock. 949 */ 950 if (data & mask) 951 eec |= IXGBE_EEC_DI; 952 else 953 eec &= ~IXGBE_EEC_DI; 954 955 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 956 IXGBE_WRITE_FLUSH(hw); 957 958 usec_delay(1); 959 960 ixgbe_raise_eeprom_clk(hw, &eec); 961 ixgbe_lower_eeprom_clk(hw, &eec); 962 963 /* 964 * Shift mask to signify next bit of data to shift in to the 965 * EEPROM 966 */ 967 mask = mask >> 1; 968 }; 969 970 /* We leave the "DI" bit set to "0" when we leave this routine. */ 971 eec &= ~IXGBE_EEC_DI; 972 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 973 IXGBE_WRITE_FLUSH(hw); 974 } 975 976 /** 977 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 978 * @hw: pointer to hardware structure 979 **/ 980 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 981 { 982 u32 eec; 983 u32 i; 984 u16 data = 0; 985 986 /* 987 * In order to read a register from the EEPROM, we need to shift 988 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 989 * the clock input to the EEPROM (setting the SK bit), and then reading 990 * the value of the "DO" bit. During this "shifting in" process the 991 * "DI" bit should always be clear. 992 */ 993 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 994 995 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 996 997 for (i = 0; i < count; i++) { 998 data = data << 1; 999 ixgbe_raise_eeprom_clk(hw, &eec); 1000 1001 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1002 1003 eec &= ~(IXGBE_EEC_DI); 1004 if (eec & IXGBE_EEC_DO) 1005 data |= 1; 1006 1007 ixgbe_lower_eeprom_clk(hw, &eec); 1008 } 1009 1010 return data; 1011 } 1012 1013 /** 1014 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1015 * @hw: pointer to hardware structure 1016 * @eec: EEC register's current value 1017 **/ 1018 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1019 { 1020 /* 1021 * Raise the clock input to the EEPROM 1022 * (setting the SK bit), then delay 1023 */ 1024 *eec = *eec | IXGBE_EEC_SK; 1025 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1026 IXGBE_WRITE_FLUSH(hw); 1027 usec_delay(1); 1028 } 1029 1030 /** 1031 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1032 * @hw: pointer to hardware structure 1033 * @eecd: EECD's current value 1034 **/ 1035 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1036 { 1037 /* 1038 * Lower the clock input to the EEPROM (clearing the SK bit), then 1039 * delay 1040 */ 1041 *eec = *eec & ~IXGBE_EEC_SK; 1042 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1043 IXGBE_WRITE_FLUSH(hw); 1044 usec_delay(1); 1045 } 1046 1047 /** 1048 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1049 * @hw: pointer to hardware structure 1050 **/ 1051 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1052 { 1053 u32 eec; 1054 1055 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1056 1057 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1058 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1059 1060 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1061 IXGBE_WRITE_FLUSH(hw); 1062 1063 usec_delay(1); 1064 1065 /* Stop requesting EEPROM access */ 1066 eec &= ~IXGBE_EEC_REQ; 1067 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1068 1069 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1070 } 1071 1072 /** 1073 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1074 * @hw: pointer to hardware structure 1075 **/ 1076 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 1077 { 1078 u16 i; 1079 u16 j; 1080 u16 checksum = 0; 1081 u16 length = 0; 1082 u16 pointer = 0; 1083 u16 word = 0; 1084 1085 /* Include 0x0-0x3F in the checksum */ 1086 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1087 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1088 DEBUGOUT("EEPROM read failed\n"); 1089 break; 1090 } 1091 checksum += word; 1092 } 1093 1094 /* Include all data from pointers except for the fw pointer */ 1095 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1096 hw->eeprom.ops.read(hw, i, &pointer); 1097 1098 /* Make sure the pointer seems valid */ 1099 if (pointer != 0xFFFF && pointer != 0) { 1100 hw->eeprom.ops.read(hw, pointer, &length); 1101 1102 if (length != 0xFFFF && length != 0) { 1103 for (j = pointer+1; j <= pointer+length; j++) { 1104 hw->eeprom.ops.read(hw, j, &word); 1105 checksum += word; 1106 } 1107 } 1108 } 1109 } 1110 1111 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1112 1113 return checksum; 1114 } 1115 1116 /** 1117 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1118 * @hw: pointer to hardware structure 1119 * @checksum_val: calculated checksum 1120 * 1121 * Performs checksum calculation and validates the EEPROM checksum. If the 1122 * caller does not need checksum_val, the value can be NULL. 1123 **/ 1124 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1125 u16 *checksum_val) 1126 { 1127 s32 status; 1128 u16 checksum; 1129 u16 read_checksum = 0; 1130 1131 /* 1132 * Read the first word from the EEPROM. If this times out or fails, do 1133 * not continue or we could be in for a very long wait while every 1134 * EEPROM read fails 1135 */ 1136 status = hw->eeprom.ops.read(hw, 0, &checksum); 1137 1138 if (status == IXGBE_SUCCESS) { 1139 checksum = ixgbe_calc_eeprom_checksum(hw); 1140 1141 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1142 1143 /* 1144 * Verify read checksum from EEPROM is the same as 1145 * calculated checksum 1146 */ 1147 if (read_checksum != checksum) 1148 status = IXGBE_ERR_EEPROM_CHECKSUM; 1149 1150 /* If the user cares, return the calculated checksum */ 1151 if (checksum_val) 1152 *checksum_val = checksum; 1153 } else { 1154 DEBUGOUT("EEPROM read failed\n"); 1155 } 1156 1157 return status; 1158 } 1159 1160 /** 1161 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1162 * @hw: pointer to hardware structure 1163 **/ 1164 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1165 { 1166 s32 status; 1167 u16 checksum; 1168 1169 /* 1170 * Read the first word from the EEPROM. If this times out or fails, do 1171 * not continue or we could be in for a very long wait while every 1172 * EEPROM read fails 1173 */ 1174 status = hw->eeprom.ops.read(hw, 0, &checksum); 1175 1176 if (status == IXGBE_SUCCESS) { 1177 checksum = ixgbe_calc_eeprom_checksum(hw); 1178 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1179 checksum); 1180 } else { 1181 DEBUGOUT("EEPROM read failed\n"); 1182 } 1183 1184 return status; 1185 } 1186 1187 /** 1188 * ixgbe_validate_mac_addr - Validate MAC address 1189 * @mac_addr: pointer to MAC address. 1190 * 1191 * Tests a MAC address to ensure it is a valid Individual Address 1192 **/ 1193 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1194 { 1195 s32 status = IXGBE_SUCCESS; 1196 1197 /* Make sure it is not a multicast address */ 1198 if (IXGBE_IS_MULTICAST(mac_addr)) { 1199 DEBUGOUT("MAC address is multicast\n"); 1200 status = IXGBE_ERR_INVALID_MAC_ADDR; 1201 /* Not a broadcast address */ 1202 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1203 DEBUGOUT("MAC address is broadcast\n"); 1204 status = IXGBE_ERR_INVALID_MAC_ADDR; 1205 /* Reject the zero address */ 1206 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1207 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1208 DEBUGOUT("MAC address is all zeros\n"); 1209 status = IXGBE_ERR_INVALID_MAC_ADDR; 1210 } 1211 return status; 1212 } 1213 1214 /** 1215 * ixgbe_set_rar_generic - Set Rx address register 1216 * @hw: pointer to hardware structure 1217 * @index: Receive address register to write 1218 * @addr: Address to put into receive address register 1219 * @vmdq: VMDq "set" or "pool" index 1220 * @enable_addr: set flag that address is active 1221 * 1222 * Puts an ethernet address into a receive address register. 1223 **/ 1224 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1225 u32 enable_addr) 1226 { 1227 u32 rar_low, rar_high; 1228 u32 rar_entries = hw->mac.num_rar_entries; 1229 1230 /* setup VMDq pool selection before this RAR gets enabled */ 1231 hw->mac.ops.set_vmdq(hw, index, vmdq); 1232 1233 /* Make sure we are using a valid rar index range */ 1234 if (index < rar_entries) { 1235 /* 1236 * HW expects these in little endian so we reverse the byte 1237 * order from network order (big endian) to little endian 1238 */ 1239 rar_low = ((u32)addr[0] | 1240 ((u32)addr[1] << 8) | 1241 ((u32)addr[2] << 16) | 1242 ((u32)addr[3] << 24)); 1243 /* 1244 * Some parts put the VMDq setting in the extra RAH bits, 1245 * so save everything except the lower 16 bits that hold part 1246 * of the address and the address valid bit. 1247 */ 1248 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1249 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1250 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1251 1252 if (enable_addr != 0) 1253 rar_high |= IXGBE_RAH_AV; 1254 1255 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1256 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1257 } else { 1258 DEBUGOUT1("RAR index %d is out of range.\n", index); 1259 } 1260 1261 return IXGBE_SUCCESS; 1262 } 1263 1264 /** 1265 * ixgbe_clear_rar_generic - Remove Rx address register 1266 * @hw: pointer to hardware structure 1267 * @index: Receive address register to write 1268 * 1269 * Clears an ethernet address from a receive address register. 1270 **/ 1271 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1272 { 1273 u32 rar_high; 1274 u32 rar_entries = hw->mac.num_rar_entries; 1275 1276 /* Make sure we are using a valid rar index range */ 1277 if (index < rar_entries) { 1278 /* 1279 * Some parts put the VMDq setting in the extra RAH bits, 1280 * so save everything except the lower 16 bits that hold part 1281 * of the address and the address valid bit. 1282 */ 1283 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1284 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1285 1286 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1287 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1288 } else { 1289 DEBUGOUT1("RAR index %d is out of range.\n", index); 1290 } 1291 1292 /* clear VMDq pool/queue selection for this RAR */ 1293 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1294 1295 return IXGBE_SUCCESS; 1296 } 1297 1298 /** 1299 * ixgbe_enable_rar - Enable Rx address register 1300 * @hw: pointer to hardware structure 1301 * @index: index into the RAR table 1302 * 1303 * Enables the select receive address register. 1304 **/ 1305 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) 1306 { 1307 u32 rar_high; 1308 1309 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1310 rar_high |= IXGBE_RAH_AV; 1311 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1312 } 1313 1314 /** 1315 * ixgbe_disable_rar - Disable Rx address register 1316 * @hw: pointer to hardware structure 1317 * @index: index into the RAR table 1318 * 1319 * Disables the select receive address register. 1320 **/ 1321 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) 1322 { 1323 u32 rar_high; 1324 1325 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1326 rar_high &= (~IXGBE_RAH_AV); 1327 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1328 } 1329 1330 /** 1331 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1332 * @hw: pointer to hardware structure 1333 * 1334 * Places the MAC address in receive address register 0 and clears the rest 1335 * of the receive address registers. Clears the multicast table. Assumes 1336 * the receiver is in reset when the routine is called. 1337 **/ 1338 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1339 { 1340 u32 i; 1341 u32 rar_entries = hw->mac.num_rar_entries; 1342 1343 /* 1344 * If the current mac address is valid, assume it is a software override 1345 * to the permanent address. 1346 * Otherwise, use the permanent address from the eeprom. 1347 */ 1348 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1349 IXGBE_ERR_INVALID_MAC_ADDR) { 1350 /* Get the MAC address from the RAR0 for later reference */ 1351 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1352 1353 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1354 hw->mac.addr[0], hw->mac.addr[1], 1355 hw->mac.addr[2]); 1356 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1357 hw->mac.addr[4], hw->mac.addr[5]); 1358 } else { 1359 /* Setup the receive address. */ 1360 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1361 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1362 hw->mac.addr[0], hw->mac.addr[1], 1363 hw->mac.addr[2]); 1364 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1365 hw->mac.addr[4], hw->mac.addr[5]); 1366 1367 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1368 } 1369 hw->addr_ctrl.overflow_promisc = 0; 1370 1371 hw->addr_ctrl.rar_used_count = 1; 1372 1373 /* Zero out the other receive addresses. */ 1374 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1375 for (i = 1; i < rar_entries; i++) { 1376 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1377 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1378 } 1379 1380 /* Clear the MTA */ 1381 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1382 hw->addr_ctrl.mta_in_use = 0; 1383 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1384 1385 DEBUGOUT(" Clearing MTA\n"); 1386 for (i = 0; i < hw->mac.mcft_size; i++) 1387 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1388 1389 ixgbe_init_uta_tables(hw); 1390 1391 return IXGBE_SUCCESS; 1392 } 1393 1394 /** 1395 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1396 * @hw: pointer to hardware structure 1397 * @addr: new address 1398 * 1399 * Adds it to unused receive address register or goes into promiscuous mode. 1400 **/ 1401 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1402 { 1403 u32 rar_entries = hw->mac.num_rar_entries; 1404 u32 rar; 1405 1406 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1407 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1408 1409 /* 1410 * Place this address in the RAR if there is room, 1411 * else put the controller into promiscuous mode 1412 */ 1413 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1414 rar = hw->addr_ctrl.rar_used_count - 1415 hw->addr_ctrl.mc_addr_in_rar_count; 1416 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1417 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1418 hw->addr_ctrl.rar_used_count++; 1419 } else { 1420 hw->addr_ctrl.overflow_promisc++; 1421 } 1422 1423 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1424 } 1425 1426 /** 1427 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1428 * @hw: pointer to hardware structure 1429 * @addr_list: the list of new addresses 1430 * @addr_count: number of addresses 1431 * @next: iterator function to walk the address list 1432 * 1433 * The given list replaces any existing list. Clears the secondary addrs from 1434 * receive address registers. Uses unused receive address registers for the 1435 * first secondary addresses, and falls back to promiscuous mode as needed. 1436 * 1437 * Drivers using secondary unicast addresses must set user_set_promisc when 1438 * manually putting the device into promiscuous mode. 1439 **/ 1440 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1441 u32 addr_count, ixgbe_mc_addr_itr next) 1442 { 1443 u8 *addr; 1444 u32 i; 1445 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1446 u32 uc_addr_in_use; 1447 u32 fctrl; 1448 u32 vmdq; 1449 1450 /* 1451 * Clear accounting of old secondary address list, 1452 * don't count RAR[0] 1453 */ 1454 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1455 hw->addr_ctrl.mc_addr_in_rar_count - 1; 1456 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1457 hw->addr_ctrl.overflow_promisc = 0; 1458 1459 /* Zero out the other receive addresses */ 1460 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use); 1461 for (i = 1; i <= uc_addr_in_use; i++) { 1462 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1463 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1464 } 1465 1466 /* Add the new addresses */ 1467 for (i = 0; i < addr_count; i++) { 1468 DEBUGOUT(" Adding the secondary addresses:\n"); 1469 addr = next(hw, &addr_list, &vmdq); 1470 ixgbe_add_uc_addr(hw, addr, vmdq); 1471 } 1472 1473 if (hw->addr_ctrl.overflow_promisc) { 1474 /* enable promisc if not already in overflow or set by user */ 1475 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1476 DEBUGOUT(" Entering address overflow promisc mode\n"); 1477 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1478 fctrl |= IXGBE_FCTRL_UPE; 1479 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1480 } 1481 } else { 1482 /* only disable if set by overflow, not by user */ 1483 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1484 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1485 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1486 fctrl &= ~IXGBE_FCTRL_UPE; 1487 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1488 } 1489 } 1490 1491 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1492 return IXGBE_SUCCESS; 1493 } 1494 1495 /** 1496 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1497 * @hw: pointer to hardware structure 1498 * @mc_addr: the multicast address 1499 * 1500 * Extracts the 12 bits, from a multicast address, to determine which 1501 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1502 * incoming rx multicast addresses, to determine the bit-vector to check in 1503 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1504 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1505 * to mc_filter_type. 1506 **/ 1507 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1508 { 1509 u32 vector = 0; 1510 1511 switch (hw->mac.mc_filter_type) { 1512 case 0: /* use bits [47:36] of the address */ 1513 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1514 break; 1515 case 1: /* use bits [46:35] of the address */ 1516 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1517 break; 1518 case 2: /* use bits [45:34] of the address */ 1519 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1520 break; 1521 case 3: /* use bits [43:32] of the address */ 1522 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1523 break; 1524 default: /* Invalid mc_filter_type */ 1525 DEBUGOUT("MC filter type param set incorrectly\n"); 1526 ASSERT(0); 1527 break; 1528 } 1529 1530 /* vector can only be 12-bits or boundary will be exceeded */ 1531 vector &= 0xFFF; 1532 return vector; 1533 } 1534 1535 /** 1536 * ixgbe_set_mta - Set bit-vector in multicast table 1537 * @hw: pointer to hardware structure 1538 * @hash_value: Multicast address hash value 1539 * 1540 * Sets the bit-vector in the multicast table. 1541 **/ 1542 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1543 { 1544 u32 vector; 1545 u32 vector_bit; 1546 u32 vector_reg; 1547 u32 mta_reg; 1548 1549 hw->addr_ctrl.mta_in_use++; 1550 1551 vector = ixgbe_mta_vector(hw, mc_addr); 1552 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1553 1554 /* 1555 * The MTA is a register array of 128 32-bit registers. It is treated 1556 * like an array of 4096 bits. We want to set bit 1557 * BitArray[vector_value]. So we figure out what register the bit is 1558 * in, read it, OR in the new bit, then write back the new value. The 1559 * register is determined by the upper 7 bits of the vector value and 1560 * the bit within that register are determined by the lower 5 bits of 1561 * the value. 1562 */ 1563 vector_reg = (vector >> 5) & 0x7F; 1564 vector_bit = vector & 0x1F; 1565 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1566 mta_reg |= (1 << vector_bit); 1567 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1568 } 1569 1570 /** 1571 * ixgbe_add_mc_addr - Adds a multicast address. 1572 * @hw: pointer to hardware structure 1573 * @mc_addr: new multicast address 1574 * 1575 * Adds it to unused receive address register or to the multicast table. 1576 **/ 1577 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) 1578 { 1579 u32 rar_entries = hw->mac.num_rar_entries; 1580 u32 rar; 1581 1582 DEBUGOUT6(" MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", 1583 mc_addr[0], mc_addr[1], mc_addr[2], 1584 mc_addr[3], mc_addr[4], mc_addr[5]); 1585 1586 /* 1587 * Place this multicast address in the RAR if there is room, 1588 * else put it in the MTA 1589 */ 1590 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1591 /* use RAR from the end up for multicast */ 1592 rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; 1593 hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); 1594 DEBUGOUT1("Added a multicast address to RAR[%d]\n", rar); 1595 hw->addr_ctrl.rar_used_count++; 1596 hw->addr_ctrl.mc_addr_in_rar_count++; 1597 } else { 1598 ixgbe_set_mta(hw, mc_addr); 1599 } 1600 1601 DEBUGOUT("ixgbe_add_mc_addr Complete\n"); 1602 } 1603 1604 /** 1605 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1606 * @hw: pointer to hardware structure 1607 * @mc_addr_list: the list of new multicast addresses 1608 * @mc_addr_count: number of addresses 1609 * @next: iterator function to walk the multicast address list 1610 * 1611 * The given list replaces any existing list. Clears the MC addrs from receive 1612 * address registers and the multicast table. Uses unused receive address 1613 * registers for the first multicast addresses, and hashes the rest into the 1614 * multicast table. 1615 **/ 1616 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1617 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1618 { 1619 u32 i; 1620 u32 rar_entries = hw->mac.num_rar_entries; 1621 u32 vmdq; 1622 1623 /* 1624 * Set the new number of MC addresses that we are being requested to 1625 * use. 1626 */ 1627 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1628 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; 1629 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1630 hw->addr_ctrl.mta_in_use = 0; 1631 1632 /* Zero out the other receive addresses. */ 1633 DEBUGOUT2("Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count, 1634 rar_entries - 1); 1635 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { 1636 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1637 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1638 } 1639 1640 /* Clear the MTA */ 1641 DEBUGOUT(" Clearing MTA\n"); 1642 for (i = 0; i < hw->mac.mcft_size; i++) 1643 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1644 1645 /* Add the new addresses */ 1646 for (i = 0; i < mc_addr_count; i++) { 1647 DEBUGOUT(" Adding the multicast addresses:\n"); 1648 ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); 1649 } 1650 1651 /* Enable mta */ 1652 if (hw->addr_ctrl.mta_in_use > 0) 1653 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1654 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1655 1656 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1657 return IXGBE_SUCCESS; 1658 } 1659 1660 /** 1661 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1662 * @hw: pointer to hardware structure 1663 * 1664 * Enables multicast address in RAR and the use of the multicast hash table. 1665 **/ 1666 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1667 { 1668 u32 i; 1669 u32 rar_entries = hw->mac.num_rar_entries; 1670 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1671 1672 if (a->mc_addr_in_rar_count > 0) 1673 for (i = (rar_entries - a->mc_addr_in_rar_count); 1674 i < rar_entries; i++) 1675 ixgbe_enable_rar(hw, i); 1676 1677 if (a->mta_in_use > 0) 1678 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1679 hw->mac.mc_filter_type); 1680 1681 return IXGBE_SUCCESS; 1682 } 1683 1684 /** 1685 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1686 * @hw: pointer to hardware structure 1687 * 1688 * Disables multicast address in RAR and the use of the multicast hash table. 1689 **/ 1690 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1691 { 1692 u32 i; 1693 u32 rar_entries = hw->mac.num_rar_entries; 1694 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1695 1696 if (a->mc_addr_in_rar_count > 0) 1697 for (i = (rar_entries - a->mc_addr_in_rar_count); 1698 i < rar_entries; i++) 1699 ixgbe_disable_rar(hw, i); 1700 1701 if (a->mta_in_use > 0) 1702 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1703 1704 return IXGBE_SUCCESS; 1705 } 1706 1707 1708 /** 1709 * ixgbe_fc_autoneg - Configure flow control 1710 * @hw: pointer to hardware structure 1711 * 1712 * Negotiates flow control capabilities with link partner using autoneg and 1713 * applies the results. 1714 **/ 1715 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1716 { 1717 s32 ret_val = IXGBE_SUCCESS; 1718 u32 i, reg, pcs_anadv_reg, pcs_lpab_reg; 1719 1720 DEBUGFUNC("ixgbe_fc_autoneg"); 1721 1722 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1723 1724 /* 1725 * The possible values of fc.current_mode are: 1726 * 0: Flow control is completely disabled 1727 * 1: Rx flow control is enabled (we can receive pause frames, 1728 * but not send pause frames). 1729 * 2: Tx flow control is enabled (we can send pause frames but 1730 * we do not support receiving pause frames). 1731 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1732 * other: Invalid. 1733 */ 1734 switch (hw->fc.current_mode) { 1735 case ixgbe_fc_none: 1736 /* Flow control completely disabled by software override. */ 1737 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1738 break; 1739 case ixgbe_fc_rx_pause: 1740 /* 1741 * Rx Flow control is enabled and Tx Flow control is 1742 * disabled by software override. Since there really 1743 * isn't a way to advertise that we are capable of RX 1744 * Pause ONLY, we will advertise that we support both 1745 * symmetric and asymmetric Rx PAUSE. Later, we will 1746 * disable the adapter's ability to send PAUSE frames. 1747 */ 1748 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1749 break; 1750 case ixgbe_fc_tx_pause: 1751 /* 1752 * Tx Flow control is enabled, and Rx Flow control is 1753 * disabled by software override. 1754 */ 1755 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 1756 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 1757 break; 1758 case ixgbe_fc_full: 1759 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1760 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1761 break; 1762 default: 1763 DEBUGOUT("Flow control param set incorrectly\n"); 1764 ret_val = -IXGBE_ERR_CONFIG; 1765 goto out; 1766 break; 1767 } 1768 1769 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 1770 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 1771 1772 /* Set PCS register for autoneg */ 1773 /* Enable and restart autoneg */ 1774 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; 1775 1776 /* Disable AN timeout */ 1777 if (hw->fc.strict_ieee) 1778 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 1779 1780 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 1781 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 1782 1783 /* See if autonegotiation has succeeded */ 1784 hw->mac.autoneg_succeeded = 0; 1785 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1786 msec_delay(10); 1787 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1788 if ((reg & (IXGBE_PCS1GLSTA_LINK_OK | 1789 IXGBE_PCS1GLSTA_AN_COMPLETE)) == 1790 (IXGBE_PCS1GLSTA_LINK_OK | 1791 IXGBE_PCS1GLSTA_AN_COMPLETE)) { 1792 if (!(reg & IXGBE_PCS1GLSTA_AN_TIMED_OUT)) 1793 hw->mac.autoneg_succeeded = 1; 1794 break; 1795 } 1796 } 1797 1798 if (!hw->mac.autoneg_succeeded) { 1799 /* Autoneg failed to achieve a link, so we turn fc off */ 1800 hw->fc.current_mode = ixgbe_fc_none; 1801 DEBUGOUT("Flow Control = NONE.\n"); 1802 goto out; 1803 } 1804 1805 /* 1806 * Read the AN advertisement and LP ability registers and resolve 1807 * local flow control settings accordingly 1808 */ 1809 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1810 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1811 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1812 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1813 /* 1814 * Now we need to check if the user selected Rx ONLY 1815 * of pause frames. In this case, we had to advertise 1816 * FULL flow control because we could not advertise RX 1817 * ONLY. Hence, we must now check to see if we need to 1818 * turn OFF the TRANSMISSION of PAUSE frames. 1819 */ 1820 if (hw->fc.requested_mode == ixgbe_fc_full) { 1821 hw->fc.current_mode = ixgbe_fc_full; 1822 DEBUGOUT("Flow Control = FULL.\n"); 1823 } else { 1824 hw->fc.current_mode = ixgbe_fc_rx_pause; 1825 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1826 } 1827 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1828 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1829 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1830 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1831 hw->fc.current_mode = ixgbe_fc_tx_pause; 1832 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1833 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1834 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1835 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1836 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1837 hw->fc.current_mode = ixgbe_fc_rx_pause; 1838 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1839 } else { 1840 hw->fc.current_mode = ixgbe_fc_none; 1841 DEBUGOUT("Flow Control = NONE.\n"); 1842 } 1843 1844 out: 1845 return ret_val; 1846 } 1847 1848 1849 /** 1850 * ixgbe_disable_pcie_master - Disable PCI-express master access 1851 * @hw: pointer to hardware structure 1852 * 1853 * Disables PCI-Express master access and verifies there are no pending 1854 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 1855 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 1856 * is returned signifying master requests disabled. 1857 **/ 1858 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 1859 { 1860 u32 i; 1861 u32 reg_val; 1862 u32 number_of_queues; 1863 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 1864 1865 /* Disable the receive unit by stopping each queue */ 1866 number_of_queues = hw->mac.max_rx_queues; 1867 for (i = 0; i < number_of_queues; i++) { 1868 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1869 if (reg_val & IXGBE_RXDCTL_ENABLE) { 1870 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1871 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1872 } 1873 } 1874 1875 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 1876 reg_val |= IXGBE_CTRL_GIO_DIS; 1877 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 1878 1879 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 1880 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 1881 status = IXGBE_SUCCESS; 1882 break; 1883 } 1884 usec_delay(100); 1885 } 1886 1887 return status; 1888 } 1889 1890 1891 /** 1892 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 1893 * @hw: pointer to hardware structure 1894 * @mask: Mask to specify which semaphore to acquire 1895 * 1896 * Acquires the SWFW semaphore thought the GSSR register for the specified 1897 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1898 **/ 1899 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 1900 { 1901 u32 gssr; 1902 u32 swmask = mask; 1903 u32 fwmask = mask << 5; 1904 s32 timeout = 200; 1905 1906 while (timeout) { 1907 if (ixgbe_get_eeprom_semaphore(hw)) 1908 return -IXGBE_ERR_SWFW_SYNC; 1909 1910 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1911 if (!(gssr & (fwmask | swmask))) 1912 break; 1913 1914 /* 1915 * Firmware currently using resource (fwmask) or other software 1916 * thread currently using resource (swmask) 1917 */ 1918 ixgbe_release_eeprom_semaphore(hw); 1919 msec_delay(5); 1920 timeout--; 1921 } 1922 1923 if (!timeout) { 1924 DEBUGOUT("Driver can't access resource, GSSR timeout.\n"); 1925 return -IXGBE_ERR_SWFW_SYNC; 1926 } 1927 1928 gssr |= swmask; 1929 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1930 1931 ixgbe_release_eeprom_semaphore(hw); 1932 return IXGBE_SUCCESS; 1933 } 1934 1935 /** 1936 * ixgbe_release_swfw_sync - Release SWFW semaphore 1937 * @hw: pointer to hardware structure 1938 * @mask: Mask to specify which semaphore to release 1939 * 1940 * Releases the SWFW semaphore thought the GSSR register for the specified 1941 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1942 **/ 1943 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 1944 { 1945 u32 gssr; 1946 u32 swmask = mask; 1947 1948 ixgbe_get_eeprom_semaphore(hw); 1949 1950 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1951 gssr &= ~swmask; 1952 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1953 1954 ixgbe_release_eeprom_semaphore(hw); 1955 } 1956 1957