1fd75b91dSJack F Vogel /****************************************************************************** 27282444bSPedro F. Giffuni SPDX-License-Identifier: BSD-3-Clause 3fd75b91dSJack F Vogel 48eb6488eSEric Joyner Copyright (c) 2001-2017, Intel Corporation 5fd75b91dSJack F Vogel All rights reserved. 6fd75b91dSJack F Vogel 7fd75b91dSJack F Vogel Redistribution and use in source and binary forms, with or without 8fd75b91dSJack F Vogel modification, are permitted provided that the following conditions are met: 9fd75b91dSJack F Vogel 10fd75b91dSJack F Vogel 1. Redistributions of source code must retain the above copyright notice, 11fd75b91dSJack F Vogel this list of conditions and the following disclaimer. 12fd75b91dSJack F Vogel 13fd75b91dSJack F Vogel 2. Redistributions in binary form must reproduce the above copyright 14fd75b91dSJack F Vogel notice, this list of conditions and the following disclaimer in the 15fd75b91dSJack F Vogel documentation and/or other materials provided with the distribution. 16fd75b91dSJack F Vogel 17fd75b91dSJack F Vogel 3. Neither the name of the Intel Corporation nor the names of its 18fd75b91dSJack F Vogel contributors may be used to endorse or promote products derived from 19fd75b91dSJack F Vogel this software without specific prior written permission. 20fd75b91dSJack F Vogel 21fd75b91dSJack F Vogel THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22fd75b91dSJack F Vogel AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23fd75b91dSJack F Vogel IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24fd75b91dSJack F Vogel ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25fd75b91dSJack F Vogel LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26fd75b91dSJack F Vogel CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27fd75b91dSJack F Vogel SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28fd75b91dSJack F Vogel INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29fd75b91dSJack F Vogel CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30fd75b91dSJack F Vogel ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31fd75b91dSJack F Vogel POSSIBILITY OF SUCH DAMAGE. 32fd75b91dSJack F Vogel 33fd75b91dSJack F Vogel ******************************************************************************/ 34fd75b91dSJack F Vogel /*$FreeBSD$*/ 35fd75b91dSJack F Vogel 36fd75b91dSJack F Vogel 37fd75b91dSJack F Vogel #include "ixgbe_type.h" 38fd75b91dSJack F Vogel #include "ixgbe_dcb.h" 39fd75b91dSJack F Vogel #include "ixgbe_dcb_82598.h" 40fd75b91dSJack F Vogel 41fd75b91dSJack F Vogel /** 42fd75b91dSJack F Vogel * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class 43fd75b91dSJack F Vogel * @hw: pointer to hardware structure 44fd75b91dSJack F Vogel * @stats: pointer to statistics structure 45fd75b91dSJack F Vogel * @tc_count: Number of elements in bwg_array. 46fd75b91dSJack F Vogel * 47fd75b91dSJack F Vogel * This function returns the status data for each of the Traffic Classes in use. 48fd75b91dSJack F Vogel */ 49fd75b91dSJack F Vogel s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw, 50fd75b91dSJack F Vogel struct ixgbe_hw_stats *stats, 51fd75b91dSJack F Vogel u8 tc_count) 52fd75b91dSJack F Vogel { 53fd75b91dSJack F Vogel int tc; 54fd75b91dSJack F Vogel 55fd75b91dSJack F Vogel DEBUGFUNC("dcb_get_tc_stats"); 56fd75b91dSJack F Vogel 57fd75b91dSJack F Vogel if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS) 58fd75b91dSJack F Vogel return IXGBE_ERR_PARAM; 59fd75b91dSJack F Vogel 60fd75b91dSJack F Vogel /* Statistics pertaining to each traffic class */ 61fd75b91dSJack F Vogel for (tc = 0; tc < tc_count; tc++) { 62fd75b91dSJack F Vogel /* Transmitted Packets */ 63fd75b91dSJack F Vogel stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); 64fd75b91dSJack F Vogel /* Transmitted Bytes */ 65fd75b91dSJack F Vogel stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc)); 66fd75b91dSJack F Vogel /* Received Packets */ 67fd75b91dSJack F Vogel stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); 68fd75b91dSJack F Vogel /* Received Bytes */ 69fd75b91dSJack F Vogel stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc)); 70fd75b91dSJack F Vogel 71fd75b91dSJack F Vogel #if 0 72fd75b91dSJack F Vogel /* Can we get rid of these?? Consequently, getting rid 73fd75b91dSJack F Vogel * of the tc_stats structure. 74fd75b91dSJack F Vogel */ 75fd75b91dSJack F Vogel tc_stats_array[up]->in_overflow_discards = 0; 76fd75b91dSJack F Vogel tc_stats_array[up]->out_overflow_discards = 0; 77fd75b91dSJack F Vogel #endif 78fd75b91dSJack F Vogel } 79fd75b91dSJack F Vogel 80fd75b91dSJack F Vogel return IXGBE_SUCCESS; 81fd75b91dSJack F Vogel } 82fd75b91dSJack F Vogel 83fd75b91dSJack F Vogel /** 84fd75b91dSJack F Vogel * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data 85fd75b91dSJack F Vogel * @hw: pointer to hardware structure 86fd75b91dSJack F Vogel * @stats: pointer to statistics structure 87fd75b91dSJack F Vogel * @tc_count: Number of elements in bwg_array. 88fd75b91dSJack F Vogel * 89fd75b91dSJack F Vogel * This function returns the CBFC status data for each of the Traffic Classes. 90fd75b91dSJack F Vogel */ 91fd75b91dSJack F Vogel s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw, 92fd75b91dSJack F Vogel struct ixgbe_hw_stats *stats, 93fd75b91dSJack F Vogel u8 tc_count) 94fd75b91dSJack F Vogel { 95fd75b91dSJack F Vogel int tc; 96fd75b91dSJack F Vogel 97fd75b91dSJack F Vogel DEBUGFUNC("dcb_get_pfc_stats"); 98fd75b91dSJack F Vogel 99fd75b91dSJack F Vogel if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS) 100fd75b91dSJack F Vogel return IXGBE_ERR_PARAM; 101fd75b91dSJack F Vogel 102fd75b91dSJack F Vogel for (tc = 0; tc < tc_count; tc++) { 103fd75b91dSJack F Vogel /* Priority XOFF Transmitted */ 104fd75b91dSJack F Vogel stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc)); 105fd75b91dSJack F Vogel /* Priority XOFF Received */ 106fd75b91dSJack F Vogel stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc)); 107fd75b91dSJack F Vogel } 108fd75b91dSJack F Vogel 109fd75b91dSJack F Vogel return IXGBE_SUCCESS; 110fd75b91dSJack F Vogel } 111fd75b91dSJack F Vogel 112fd75b91dSJack F Vogel /** 113fd75b91dSJack F Vogel * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter 114fd75b91dSJack F Vogel * @hw: pointer to hardware structure 1157d48aa4cSEric Joyner * @refill: refill credits index by traffic class 1167d48aa4cSEric Joyner * @max: max credits index by traffic class 1177d48aa4cSEric Joyner * @tsa: transmission selection algorithm indexed by traffic class 118fd75b91dSJack F Vogel * 119fd75b91dSJack F Vogel * Configure Rx Data Arbiter and credits for each traffic class. 120fd75b91dSJack F Vogel */ 121fd75b91dSJack F Vogel s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill, 122fd75b91dSJack F Vogel u16 *max, u8 *tsa) 123fd75b91dSJack F Vogel { 124fd75b91dSJack F Vogel u32 reg = 0; 125fd75b91dSJack F Vogel u32 credit_refill = 0; 126fd75b91dSJack F Vogel u32 credit_max = 0; 127fd75b91dSJack F Vogel u8 i = 0; 128fd75b91dSJack F Vogel 129fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; 130fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); 131fd75b91dSJack F Vogel 132fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 133fd75b91dSJack F Vogel /* Enable Arbiter */ 134fd75b91dSJack F Vogel reg &= ~IXGBE_RMCS_ARBDIS; 135fd75b91dSJack F Vogel /* Enable Receive Recycle within the BWG */ 136fd75b91dSJack F Vogel reg |= IXGBE_RMCS_RRM; 137fd75b91dSJack F Vogel /* Enable Deficit Fixed Priority arbitration*/ 138fd75b91dSJack F Vogel reg |= IXGBE_RMCS_DFP; 139fd75b91dSJack F Vogel 140fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 141fd75b91dSJack F Vogel 142fd75b91dSJack F Vogel /* Configure traffic class credits and priority */ 143fd75b91dSJack F Vogel for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 144fd75b91dSJack F Vogel credit_refill = refill[i]; 145fd75b91dSJack F Vogel credit_max = max[i]; 146fd75b91dSJack F Vogel 147fd75b91dSJack F Vogel reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 148fd75b91dSJack F Vogel 149fd75b91dSJack F Vogel if (tsa[i] == ixgbe_dcb_tsa_strict) 150fd75b91dSJack F Vogel reg |= IXGBE_RT2CR_LSP; 151fd75b91dSJack F Vogel 152fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); 153fd75b91dSJack F Vogel } 154fd75b91dSJack F Vogel 155fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 156fd75b91dSJack F Vogel reg |= IXGBE_RDRXCTL_RDMTS_1_2; 157fd75b91dSJack F Vogel reg |= IXGBE_RDRXCTL_MPBEN; 158fd75b91dSJack F Vogel reg |= IXGBE_RDRXCTL_MCEN; 159fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 160fd75b91dSJack F Vogel 161fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 162fd75b91dSJack F Vogel /* Make sure there is enough descriptors before arbitration */ 163fd75b91dSJack F Vogel reg &= ~IXGBE_RXCTRL_DMBYPS; 164fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); 165fd75b91dSJack F Vogel 166fd75b91dSJack F Vogel return IXGBE_SUCCESS; 167fd75b91dSJack F Vogel } 168fd75b91dSJack F Vogel 169fd75b91dSJack F Vogel /** 170fd75b91dSJack F Vogel * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter 171fd75b91dSJack F Vogel * @hw: pointer to hardware structure 1727d48aa4cSEric Joyner * @refill: refill credits index by traffic class 1737d48aa4cSEric Joyner * @max: max credits index by traffic class 1747d48aa4cSEric Joyner * @bwg_id: bandwidth grouping indexed by traffic class 1757d48aa4cSEric Joyner * @tsa: transmission selection algorithm indexed by traffic class 176fd75b91dSJack F Vogel * 177fd75b91dSJack F Vogel * Configure Tx Descriptor Arbiter and credits for each traffic class. 178fd75b91dSJack F Vogel */ 179fd75b91dSJack F Vogel s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 180fd75b91dSJack F Vogel u16 *refill, u16 *max, u8 *bwg_id, 181fd75b91dSJack F Vogel u8 *tsa) 182fd75b91dSJack F Vogel { 183fd75b91dSJack F Vogel u32 reg, max_credits; 184fd75b91dSJack F Vogel u8 i; 185fd75b91dSJack F Vogel 186fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); 187fd75b91dSJack F Vogel 188fd75b91dSJack F Vogel /* Enable arbiter */ 189fd75b91dSJack F Vogel reg &= ~IXGBE_DPMCS_ARBDIS; 190fd75b91dSJack F Vogel reg |= IXGBE_DPMCS_TSOEF; 191fd75b91dSJack F Vogel 192fd75b91dSJack F Vogel /* Configure Max TSO packet size 34KB including payload and headers */ 193fd75b91dSJack F Vogel reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); 194fd75b91dSJack F Vogel 195fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); 196fd75b91dSJack F Vogel 197fd75b91dSJack F Vogel /* Configure traffic class credits and priority */ 198fd75b91dSJack F Vogel for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 199fd75b91dSJack F Vogel max_credits = max[i]; 200fd75b91dSJack F Vogel reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; 201fd75b91dSJack F Vogel reg |= refill[i]; 202fd75b91dSJack F Vogel reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; 203fd75b91dSJack F Vogel 204fd75b91dSJack F Vogel if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee) 205fd75b91dSJack F Vogel reg |= IXGBE_TDTQ2TCCR_GSP; 206fd75b91dSJack F Vogel 207fd75b91dSJack F Vogel if (tsa[i] == ixgbe_dcb_tsa_strict) 208fd75b91dSJack F Vogel reg |= IXGBE_TDTQ2TCCR_LSP; 209fd75b91dSJack F Vogel 210fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); 211fd75b91dSJack F Vogel } 212fd75b91dSJack F Vogel 213fd75b91dSJack F Vogel return IXGBE_SUCCESS; 214fd75b91dSJack F Vogel } 215fd75b91dSJack F Vogel 216fd75b91dSJack F Vogel /** 217fd75b91dSJack F Vogel * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter 218fd75b91dSJack F Vogel * @hw: pointer to hardware structure 2197d48aa4cSEric Joyner * @refill: refill credits index by traffic class 2207d48aa4cSEric Joyner * @max: max credits index by traffic class 2217d48aa4cSEric Joyner * @bwg_id: bandwidth grouping indexed by traffic class 2227d48aa4cSEric Joyner * @tsa: transmission selection algorithm indexed by traffic class 223fd75b91dSJack F Vogel * 224fd75b91dSJack F Vogel * Configure Tx Data Arbiter and credits for each traffic class. 225fd75b91dSJack F Vogel */ 226fd75b91dSJack F Vogel s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 227fd75b91dSJack F Vogel u16 *refill, u16 *max, u8 *bwg_id, 228fd75b91dSJack F Vogel u8 *tsa) 229fd75b91dSJack F Vogel { 230fd75b91dSJack F Vogel u32 reg; 231fd75b91dSJack F Vogel u8 i; 232fd75b91dSJack F Vogel 233fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 234fd75b91dSJack F Vogel /* Enable Data Plane Arbiter */ 235fd75b91dSJack F Vogel reg &= ~IXGBE_PDPMCS_ARBDIS; 236fd75b91dSJack F Vogel /* Enable DFP and Transmit Recycle Mode */ 237fd75b91dSJack F Vogel reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); 238fd75b91dSJack F Vogel 239fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); 240fd75b91dSJack F Vogel 241fd75b91dSJack F Vogel /* Configure traffic class credits and priority */ 242fd75b91dSJack F Vogel for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 243fd75b91dSJack F Vogel reg = refill[i]; 244fd75b91dSJack F Vogel reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; 245fd75b91dSJack F Vogel reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; 246fd75b91dSJack F Vogel 247fd75b91dSJack F Vogel if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee) 248fd75b91dSJack F Vogel reg |= IXGBE_TDPT2TCCR_GSP; 249fd75b91dSJack F Vogel 250fd75b91dSJack F Vogel if (tsa[i] == ixgbe_dcb_tsa_strict) 251fd75b91dSJack F Vogel reg |= IXGBE_TDPT2TCCR_LSP; 252fd75b91dSJack F Vogel 253fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); 254fd75b91dSJack F Vogel } 255fd75b91dSJack F Vogel 256fd75b91dSJack F Vogel /* Enable Tx packet buffer division */ 257fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 258fd75b91dSJack F Vogel reg |= IXGBE_DTXCTL_ENDBUBD; 259fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); 260fd75b91dSJack F Vogel 261fd75b91dSJack F Vogel return IXGBE_SUCCESS; 262fd75b91dSJack F Vogel } 263fd75b91dSJack F Vogel 264fd75b91dSJack F Vogel /** 265fd75b91dSJack F Vogel * ixgbe_dcb_config_pfc_82598 - Config priority flow control 266fd75b91dSJack F Vogel * @hw: pointer to hardware structure 2677d48aa4cSEric Joyner * @pfc_en: enabled pfc bitmask 268fd75b91dSJack F Vogel * 269fd75b91dSJack F Vogel * Configure Priority Flow Control for each traffic class. 270fd75b91dSJack F Vogel */ 271fd75b91dSJack F Vogel s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 272fd75b91dSJack F Vogel { 273fd75b91dSJack F Vogel u32 fcrtl, reg; 274fd75b91dSJack F Vogel u8 i; 275fd75b91dSJack F Vogel 276fd75b91dSJack F Vogel /* Enable Transmit Priority Flow Control */ 277fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 278fd75b91dSJack F Vogel reg &= ~IXGBE_RMCS_TFCE_802_3X; 279fd75b91dSJack F Vogel reg |= IXGBE_RMCS_TFCE_PRIORITY; 280fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 281fd75b91dSJack F Vogel 282fd75b91dSJack F Vogel /* Enable Receive Priority Flow Control */ 283fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 284fd75b91dSJack F Vogel reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); 285fd75b91dSJack F Vogel 286fd75b91dSJack F Vogel if (pfc_en) 287fd75b91dSJack F Vogel reg |= IXGBE_FCTRL_RPFCE; 288fd75b91dSJack F Vogel 289fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 290fd75b91dSJack F Vogel 291fd75b91dSJack F Vogel /* Configure PFC Tx thresholds per TC */ 292fd75b91dSJack F Vogel for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 293fd75b91dSJack F Vogel if (!(pfc_en & (1 << i))) { 294fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 295fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 296fd75b91dSJack F Vogel continue; 297fd75b91dSJack F Vogel } 298fd75b91dSJack F Vogel 299fd75b91dSJack F Vogel fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 300fd75b91dSJack F Vogel reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 301fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 302fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 303fd75b91dSJack F Vogel } 304fd75b91dSJack F Vogel 305fd75b91dSJack F Vogel /* Configure pause time */ 306fd75b91dSJack F Vogel reg = hw->fc.pause_time | (hw->fc.pause_time << 16); 307fd75b91dSJack F Vogel for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 308fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 309fd75b91dSJack F Vogel 310fd75b91dSJack F Vogel /* Configure flow control refresh threshold value */ 311fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 312fd75b91dSJack F Vogel 313fd75b91dSJack F Vogel return IXGBE_SUCCESS; 314fd75b91dSJack F Vogel } 315fd75b91dSJack F Vogel 316fd75b91dSJack F Vogel /** 317fd75b91dSJack F Vogel * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics 318fd75b91dSJack F Vogel * @hw: pointer to hardware structure 319fd75b91dSJack F Vogel * 320fd75b91dSJack F Vogel * Configure queue statistics registers, all queues belonging to same traffic 321fd75b91dSJack F Vogel * class uses a single set of queue statistics counters. 322fd75b91dSJack F Vogel */ 323fd75b91dSJack F Vogel s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) 324fd75b91dSJack F Vogel { 325fd75b91dSJack F Vogel u32 reg = 0; 326fd75b91dSJack F Vogel u8 i = 0; 327fd75b91dSJack F Vogel u8 j = 0; 328fd75b91dSJack F Vogel 329fd75b91dSJack F Vogel /* Receive Queues stats setting - 8 queues per statistics reg */ 330fd75b91dSJack F Vogel for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { 331fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); 332fd75b91dSJack F Vogel reg |= ((0x1010101) * j); 333fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 334fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); 335fd75b91dSJack F Vogel reg |= ((0x1010101) * j); 336fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); 337fd75b91dSJack F Vogel } 338fd75b91dSJack F Vogel /* Transmit Queues stats setting - 4 queues per statistics reg*/ 339fd75b91dSJack F Vogel for (i = 0; i < 8; i++) { 340fd75b91dSJack F Vogel reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); 341fd75b91dSJack F Vogel reg |= ((0x1010101) * i); 342fd75b91dSJack F Vogel IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); 343fd75b91dSJack F Vogel } 344fd75b91dSJack F Vogel 345fd75b91dSJack F Vogel return IXGBE_SUCCESS; 346fd75b91dSJack F Vogel } 347fd75b91dSJack F Vogel 348fd75b91dSJack F Vogel /** 349fd75b91dSJack F Vogel * ixgbe_dcb_hw_config_82598 - Config and enable DCB 350fd75b91dSJack F Vogel * @hw: pointer to hardware structure 3517d48aa4cSEric Joyner * @link_speed: unused 3527d48aa4cSEric Joyner * @refill: refill credits index by traffic class 3537d48aa4cSEric Joyner * @max: max credits index by traffic class 3547d48aa4cSEric Joyner * @bwg_id: bandwidth grouping indexed by traffic class 3557d48aa4cSEric Joyner * @tsa: transmission selection algorithm indexed by traffic class 356fd75b91dSJack F Vogel * 357fd75b91dSJack F Vogel * Configure dcb settings and enable dcb mode. 358fd75b91dSJack F Vogel */ 359fd75b91dSJack F Vogel s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed, 360fd75b91dSJack F Vogel u16 *refill, u16 *max, u8 *bwg_id, 361fd75b91dSJack F Vogel u8 *tsa) 362fd75b91dSJack F Vogel { 363758cc3dcSJack F Vogel UNREFERENCED_1PARAMETER(link_speed); 364758cc3dcSJack F Vogel 365fd75b91dSJack F Vogel ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 366fd75b91dSJack F Vogel ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, 367fd75b91dSJack F Vogel tsa); 368fd75b91dSJack F Vogel ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, 369fd75b91dSJack F Vogel tsa); 370fd75b91dSJack F Vogel ixgbe_dcb_config_tc_stats_82598(hw); 371fd75b91dSJack F Vogel 372fd75b91dSJack F Vogel 373fd75b91dSJack F Vogel return IXGBE_SUCCESS; 374fd75b91dSJack F Vogel } 375