1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(u32 *i2cctl); 50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 54 * @hw: pointer to the hardware structure 55 * 56 * Initialize the function pointers. 57 **/ 58 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 63 64 /* PHY */ 65 phy->ops.identify = &ixgbe_identify_phy_generic; 66 phy->ops.reset = &ixgbe_reset_phy_generic; 67 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 68 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 69 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 70 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 71 phy->ops.check_link = NULL; 72 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 73 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 74 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 75 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 76 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 77 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 78 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 79 phy->sfp_type = ixgbe_sfp_type_unknown; 80 81 return IXGBE_SUCCESS; 82 } 83 84 /** 85 * ixgbe_identify_phy_generic - Get physical layer module 86 * @hw: pointer to hardware structure 87 * 88 * Determines the physical layer module found on the current adapter. 89 **/ 90 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 91 { 92 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 93 u32 phy_addr; 94 u16 ext_ability = 0; 95 96 DEBUGFUNC("ixgbe_identify_phy_generic"); 97 98 if (hw->phy.type == ixgbe_phy_unknown) { 99 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 100 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 101 hw->phy.addr = phy_addr; 102 ixgbe_get_phy_id(hw); 103 hw->phy.type = 104 ixgbe_get_phy_type_from_id(hw->phy.id); 105 106 if (hw->phy.type == ixgbe_phy_unknown) { 107 hw->phy.ops.read_reg(hw, 108 IXGBE_MDIO_PHY_EXT_ABILITY, 109 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 110 &ext_ability); 111 if (ext_ability & 112 IXGBE_MDIO_PHY_10GBASET_ABILITY || 113 ext_ability & 114 IXGBE_MDIO_PHY_1000BASET_ABILITY) 115 hw->phy.type = 116 ixgbe_phy_cu_unknown; 117 else 118 hw->phy.type = 119 ixgbe_phy_generic; 120 } 121 122 status = IXGBE_SUCCESS; 123 break; 124 } 125 } 126 if (status != IXGBE_SUCCESS) 127 hw->phy.addr = 0; 128 } else { 129 status = IXGBE_SUCCESS; 130 } 131 132 return status; 133 } 134 135 /** 136 * ixgbe_validate_phy_addr - Determines phy address is valid 137 * @hw: pointer to hardware structure 138 * 139 **/ 140 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 141 { 142 u16 phy_id = 0; 143 bool valid = FALSE; 144 145 DEBUGFUNC("ixgbe_validate_phy_addr"); 146 147 hw->phy.addr = phy_addr; 148 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 149 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 150 151 if (phy_id != 0xFFFF && phy_id != 0x0) 152 valid = TRUE; 153 154 return valid; 155 } 156 157 /** 158 * ixgbe_get_phy_id - Get the phy type 159 * @hw: pointer to hardware structure 160 * 161 **/ 162 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 163 { 164 u32 status; 165 u16 phy_id_high = 0; 166 u16 phy_id_low = 0; 167 168 DEBUGFUNC("ixgbe_get_phy_id"); 169 170 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 171 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 172 &phy_id_high); 173 174 if (status == IXGBE_SUCCESS) { 175 hw->phy.id = (u32)(phy_id_high << 16); 176 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 177 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 178 &phy_id_low); 179 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 180 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 181 } 182 return status; 183 } 184 185 /** 186 * ixgbe_get_phy_type_from_id - Get the phy type 187 * @hw: pointer to hardware structure 188 * 189 **/ 190 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 191 { 192 enum ixgbe_phy_type phy_type; 193 194 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 195 196 switch (phy_id) { 197 case TN1010_PHY_ID: 198 phy_type = ixgbe_phy_tn; 199 break; 200 case AQ1002_PHY_ID: 201 phy_type = ixgbe_phy_aq; 202 break; 203 case QT2022_PHY_ID: 204 phy_type = ixgbe_phy_qt; 205 break; 206 case ATH_PHY_ID: 207 phy_type = ixgbe_phy_nl; 208 break; 209 default: 210 phy_type = ixgbe_phy_unknown; 211 break; 212 } 213 214 DEBUGOUT1("phy type found is %d\n", phy_type); 215 return phy_type; 216 } 217 218 /** 219 * ixgbe_reset_phy_generic - Performs a PHY reset 220 * @hw: pointer to hardware structure 221 **/ 222 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 223 { 224 u32 i; 225 u16 ctrl = 0; 226 s32 status = IXGBE_SUCCESS; 227 228 DEBUGFUNC("ixgbe_reset_phy_generic"); 229 230 if (hw->phy.type == ixgbe_phy_unknown) 231 status = ixgbe_identify_phy_generic(hw); 232 233 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 234 goto out; 235 236 /* 237 * Perform soft PHY reset to the PHY_XS. 238 * This will cause a soft reset to the PHY 239 */ 240 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 241 IXGBE_MDIO_PHY_XS_DEV_TYPE, 242 IXGBE_MDIO_PHY_XS_RESET); 243 244 /* Poll for reset bit to self-clear indicating reset is complete */ 245 for (i = 0; i < 500; i++) { 246 msec_delay(1); 247 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 248 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 249 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) 250 break; 251 } 252 253 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 254 status = IXGBE_ERR_RESET_FAILED; 255 DEBUGOUT("PHY reset polling failed to complete.\n"); 256 } 257 258 out: 259 return status; 260 } 261 262 /** 263 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 264 * @hw: pointer to hardware structure 265 * @reg_addr: 32 bit address of PHY register to read 266 * @phy_data: Pointer to read data from PHY register 267 **/ 268 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 269 u32 device_type, u16 *phy_data) 270 { 271 u32 command; 272 u32 i; 273 u32 data; 274 s32 status = IXGBE_SUCCESS; 275 u16 gssr; 276 277 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 278 279 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 280 gssr = IXGBE_GSSR_PHY1_SM; 281 else 282 gssr = IXGBE_GSSR_PHY0_SM; 283 284 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 285 status = IXGBE_ERR_SWFW_SYNC; 286 287 if (status == IXGBE_SUCCESS) { 288 /* Setup and write the address cycle command */ 289 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 290 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 291 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 292 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 293 294 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 295 296 /* 297 * Check every 10 usec to see if the address cycle completed. 298 * The MDI Command bit will clear when the operation is 299 * complete 300 */ 301 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 302 usec_delay(10); 303 304 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 305 306 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 307 break; 308 } 309 310 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 311 DEBUGOUT("PHY address command did not complete.\n"); 312 status = IXGBE_ERR_PHY; 313 } 314 315 if (status == IXGBE_SUCCESS) { 316 /* 317 * Address cycle complete, setup and write the read 318 * command 319 */ 320 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 321 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 322 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 323 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 324 325 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 326 327 /* 328 * Check every 10 usec to see if the address cycle 329 * completed. The MDI Command bit will clear when the 330 * operation is complete 331 */ 332 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 333 usec_delay(10); 334 335 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 336 337 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 338 break; 339 } 340 341 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 342 DEBUGOUT("PHY read command didn't complete\n"); 343 status = IXGBE_ERR_PHY; 344 } else { 345 /* 346 * Read operation is complete. Get the data 347 * from MSRWD 348 */ 349 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 350 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 351 *phy_data = (u16)(data); 352 } 353 } 354 355 ixgbe_release_swfw_sync(hw, gssr); 356 } 357 358 return status; 359 } 360 361 /** 362 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 363 * @hw: pointer to hardware structure 364 * @reg_addr: 32 bit PHY register to write 365 * @device_type: 5 bit device type 366 * @phy_data: Data to write to the PHY register 367 **/ 368 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 369 u32 device_type, u16 phy_data) 370 { 371 u32 command; 372 u32 i; 373 s32 status = IXGBE_SUCCESS; 374 u16 gssr; 375 376 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 377 378 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 379 gssr = IXGBE_GSSR_PHY1_SM; 380 else 381 gssr = IXGBE_GSSR_PHY0_SM; 382 383 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 384 status = IXGBE_ERR_SWFW_SYNC; 385 386 if (status == IXGBE_SUCCESS) { 387 /* Put the data in the MDI single read and write data register*/ 388 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 389 390 /* Setup and write the address cycle command */ 391 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 392 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 393 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 394 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 395 396 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 397 398 /* 399 * Check every 10 usec to see if the address cycle completed. 400 * The MDI Command bit will clear when the operation is 401 * complete 402 */ 403 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 404 usec_delay(10); 405 406 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 407 408 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 409 break; 410 } 411 412 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 413 DEBUGOUT("PHY address cmd didn't complete\n"); 414 status = IXGBE_ERR_PHY; 415 } 416 417 if (status == IXGBE_SUCCESS) { 418 /* 419 * Address cycle complete, setup and write the write 420 * command 421 */ 422 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 423 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 424 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 425 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 426 427 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 428 429 /* 430 * Check every 10 usec to see if the address cycle 431 * completed. The MDI Command bit will clear when the 432 * operation is complete 433 */ 434 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 435 usec_delay(10); 436 437 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 438 439 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 440 break; 441 } 442 443 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 444 DEBUGOUT("PHY address cmd didn't complete\n"); 445 status = IXGBE_ERR_PHY; 446 } 447 } 448 449 ixgbe_release_swfw_sync(hw, gssr); 450 } 451 452 return status; 453 } 454 455 /** 456 * ixgbe_setup_phy_link_generic - Set and restart autoneg 457 * @hw: pointer to hardware structure 458 * 459 * Restart autonegotiation and PHY and waits for completion. 460 **/ 461 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 462 { 463 s32 status = IXGBE_SUCCESS; 464 u32 time_out; 465 u32 max_time_out = 10; 466 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 467 bool autoneg = FALSE; 468 ixgbe_link_speed speed; 469 470 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 471 472 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 473 474 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 475 /* Set or unset auto-negotiation 10G advertisement */ 476 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 477 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 478 &autoneg_reg); 479 480 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 481 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 482 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 483 484 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 485 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 486 autoneg_reg); 487 } 488 489 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 490 /* Set or unset auto-negotiation 1G advertisement */ 491 hw->phy.ops.read_reg(hw, 492 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 493 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 494 &autoneg_reg); 495 496 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 497 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 498 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 499 500 hw->phy.ops.write_reg(hw, 501 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 502 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 503 autoneg_reg); 504 } 505 506 if (speed & IXGBE_LINK_SPEED_100_FULL) { 507 /* Set or unset auto-negotiation 100M advertisement */ 508 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 509 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 510 &autoneg_reg); 511 512 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 513 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 514 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 515 516 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 517 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 518 autoneg_reg); 519 } 520 521 /* Restart PHY autonegotiation and wait for completion */ 522 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 523 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 524 525 autoneg_reg |= IXGBE_MII_RESTART; 526 527 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 528 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 529 530 /* Wait for autonegotiation to finish */ 531 for (time_out = 0; time_out < max_time_out; time_out++) { 532 usec_delay(10); 533 /* Restart PHY autonegotiation and wait for completion */ 534 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 535 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 536 &autoneg_reg); 537 538 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 539 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 540 break; 541 } 542 } 543 544 if (time_out == max_time_out) { 545 status = IXGBE_ERR_LINK_SETUP; 546 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 547 } 548 549 return status; 550 } 551 552 /** 553 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 554 * @hw: pointer to hardware structure 555 * @speed: new link speed 556 * @autoneg: TRUE if autonegotiation enabled 557 **/ 558 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 559 ixgbe_link_speed speed, 560 bool autoneg, 561 bool autoneg_wait_to_complete) 562 { 563 UNREFERENCED_PARAMETER(autoneg); 564 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 565 566 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 567 568 /* 569 * Clear autoneg_advertised and set new values based on input link 570 * speed. 571 */ 572 hw->phy.autoneg_advertised = 0; 573 574 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 575 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 576 577 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 578 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 579 580 if (speed & IXGBE_LINK_SPEED_100_FULL) 581 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 582 583 /* Setup link based on the new speed settings */ 584 hw->phy.ops.setup_link(hw); 585 586 return IXGBE_SUCCESS; 587 } 588 589 /** 590 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 591 * @hw: pointer to hardware structure 592 * @speed: pointer to link speed 593 * @autoneg: boolean auto-negotiation value 594 * 595 * Determines the link capabilities by reading the AUTOC register. 596 **/ 597 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 598 ixgbe_link_speed *speed, 599 bool *autoneg) 600 { 601 s32 status = IXGBE_ERR_LINK_SETUP; 602 u16 speed_ability; 603 604 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 605 606 *speed = 0; 607 *autoneg = TRUE; 608 609 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 610 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 611 &speed_ability); 612 613 if (status == IXGBE_SUCCESS) { 614 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 615 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 616 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 617 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 618 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 619 *speed |= IXGBE_LINK_SPEED_100_FULL; 620 } 621 622 return status; 623 } 624 625 /** 626 * ixgbe_check_phy_link_tnx - Determine link and speed status 627 * @hw: pointer to hardware structure 628 * 629 * Reads the VS1 register to determine if link is up and the current speed for 630 * the PHY. 631 **/ 632 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 633 bool *link_up) 634 { 635 s32 status = IXGBE_SUCCESS; 636 u32 time_out; 637 u32 max_time_out = 10; 638 u16 phy_link = 0; 639 u16 phy_speed = 0; 640 u16 phy_data = 0; 641 642 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 643 644 /* Initialize speed and link to default case */ 645 *link_up = FALSE; 646 *speed = IXGBE_LINK_SPEED_10GB_FULL; 647 648 /* 649 * Check current speed and link status of the PHY register. 650 * This is a vendor specific register and may have to 651 * be changed for other copper PHYs. 652 */ 653 for (time_out = 0; time_out < max_time_out; time_out++) { 654 usec_delay(10); 655 status = hw->phy.ops.read_reg(hw, 656 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 657 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 658 &phy_data); 659 phy_link = phy_data & 660 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 661 phy_speed = phy_data & 662 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 663 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 664 *link_up = TRUE; 665 if (phy_speed == 666 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 667 *speed = IXGBE_LINK_SPEED_1GB_FULL; 668 break; 669 } 670 } 671 672 return status; 673 } 674 675 /** 676 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 677 * @hw: pointer to hardware structure 678 * 679 * Restart autonegotiation and PHY and waits for completion. 680 **/ 681 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 682 { 683 s32 status = IXGBE_SUCCESS; 684 u32 time_out; 685 u32 max_time_out = 10; 686 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 687 bool autoneg = FALSE; 688 ixgbe_link_speed speed; 689 690 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 691 692 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 693 694 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 695 /* Set or unset auto-negotiation 10G advertisement */ 696 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 697 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 698 &autoneg_reg); 699 700 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 701 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 702 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 703 704 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 705 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 706 autoneg_reg); 707 } 708 709 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 710 /* Set or unset auto-negotiation 1G advertisement */ 711 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 712 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 713 &autoneg_reg); 714 715 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 716 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 717 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 718 719 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 720 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 721 autoneg_reg); 722 } 723 724 if (speed & IXGBE_LINK_SPEED_100_FULL) { 725 /* Set or unset auto-negotiation 100M advertisement */ 726 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 727 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 728 &autoneg_reg); 729 730 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 731 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 732 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 733 734 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 735 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 736 autoneg_reg); 737 } 738 739 /* Restart PHY autonegotiation and wait for completion */ 740 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 741 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 742 743 autoneg_reg |= IXGBE_MII_RESTART; 744 745 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 746 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 747 748 /* Wait for autonegotiation to finish */ 749 for (time_out = 0; time_out < max_time_out; time_out++) { 750 usec_delay(10); 751 /* Restart PHY autonegotiation and wait for completion */ 752 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 753 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 754 &autoneg_reg); 755 756 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 757 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 758 break; 759 } 760 } 761 762 if (time_out == max_time_out) { 763 status = IXGBE_ERR_LINK_SETUP; 764 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 765 } 766 767 return status; 768 } 769 770 771 /** 772 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 773 * @hw: pointer to hardware structure 774 * @firmware_version: pointer to the PHY Firmware Version 775 **/ 776 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 777 u16 *firmware_version) 778 { 779 s32 status = IXGBE_SUCCESS; 780 781 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 782 783 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 784 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 785 firmware_version); 786 787 return status; 788 } 789 790 791 /** 792 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 793 * @hw: pointer to hardware structure 794 * @firmware_version: pointer to the PHY Firmware Version 795 **/ 796 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 797 u16 *firmware_version) 798 { 799 s32 status = IXGBE_SUCCESS; 800 801 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 802 803 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 804 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 805 firmware_version); 806 807 return status; 808 } 809 810 /** 811 * ixgbe_reset_phy_nl - Performs a PHY reset 812 * @hw: pointer to hardware structure 813 **/ 814 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 815 { 816 u16 phy_offset, control, eword, edata, block_crc; 817 bool end_data = FALSE; 818 u16 list_offset, data_offset; 819 u16 phy_data = 0; 820 s32 ret_val = IXGBE_SUCCESS; 821 u32 i; 822 823 DEBUGFUNC("ixgbe_reset_phy_nl"); 824 825 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 826 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 827 828 /* reset the PHY and poll for completion */ 829 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 830 IXGBE_MDIO_PHY_XS_DEV_TYPE, 831 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 832 833 for (i = 0; i < 100; i++) { 834 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 835 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 836 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 837 break; 838 msec_delay(10); 839 } 840 841 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 842 DEBUGOUT("PHY reset did not complete.\n"); 843 ret_val = IXGBE_ERR_PHY; 844 goto out; 845 } 846 847 /* Get init offsets */ 848 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 849 &data_offset); 850 if (ret_val != IXGBE_SUCCESS) 851 goto out; 852 853 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 854 data_offset++; 855 while (!end_data) { 856 /* 857 * Read control word from PHY init contents offset 858 */ 859 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 860 control = (eword & IXGBE_CONTROL_MASK_NL) >> 861 IXGBE_CONTROL_SHIFT_NL; 862 edata = eword & IXGBE_DATA_MASK_NL; 863 switch (control) { 864 case IXGBE_DELAY_NL: 865 data_offset++; 866 DEBUGOUT1("DELAY: %d MS\n", edata); 867 msec_delay(edata); 868 break; 869 case IXGBE_DATA_NL: 870 DEBUGOUT("DATA: \n"); 871 data_offset++; 872 hw->eeprom.ops.read(hw, data_offset++, 873 &phy_offset); 874 for (i = 0; i < edata; i++) { 875 hw->eeprom.ops.read(hw, data_offset, &eword); 876 hw->phy.ops.write_reg(hw, phy_offset, 877 IXGBE_TWINAX_DEV, eword); 878 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 879 phy_offset); 880 data_offset++; 881 phy_offset++; 882 } 883 break; 884 case IXGBE_CONTROL_NL: 885 data_offset++; 886 DEBUGOUT("CONTROL: \n"); 887 if (edata == IXGBE_CONTROL_EOL_NL) { 888 DEBUGOUT("EOL\n"); 889 end_data = TRUE; 890 } else if (edata == IXGBE_CONTROL_SOL_NL) { 891 DEBUGOUT("SOL\n"); 892 } else { 893 DEBUGOUT("Bad control value\n"); 894 ret_val = IXGBE_ERR_PHY; 895 goto out; 896 } 897 break; 898 default: 899 DEBUGOUT("Bad control type\n"); 900 ret_val = IXGBE_ERR_PHY; 901 goto out; 902 } 903 } 904 905 out: 906 return ret_val; 907 } 908 909 /** 910 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 911 * @hw: pointer to hardware structure 912 * 913 * Searches for and identifies the SFP module and assigns appropriate PHY type. 914 **/ 915 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 916 { 917 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 918 u32 vendor_oui = 0; 919 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 920 u8 identifier = 0; 921 u8 comp_codes_1g = 0; 922 u8 comp_codes_10g = 0; 923 u8 oui_bytes[3] = {0, 0, 0}; 924 u8 cable_tech = 0; 925 u16 enforce_sfp = 0; 926 927 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 928 929 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 930 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 931 status = IXGBE_ERR_SFP_NOT_PRESENT; 932 goto out; 933 } 934 935 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 936 &identifier); 937 938 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 939 status = IXGBE_ERR_SFP_NOT_PRESENT; 940 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 941 if (hw->phy.type != ixgbe_phy_nl) { 942 hw->phy.id = 0; 943 hw->phy.type = ixgbe_phy_unknown; 944 } 945 goto out; 946 } 947 948 /* LAN ID is needed for sfp_type determination */ 949 hw->mac.ops.set_lan_id(hw); 950 951 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 952 hw->phy.type = ixgbe_phy_sfp_unsupported; 953 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 954 } else { 955 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 956 &comp_codes_1g); 957 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 958 &comp_codes_10g); 959 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, 960 &cable_tech); 961 962 /* ID Module 963 * ========= 964 * 0 SFP_DA_CU 965 * 1 SFP_SR 966 * 2 SFP_LR 967 * 3 SFP_DA_CORE0 - 82599-specific 968 * 4 SFP_DA_CORE1 - 82599-specific 969 * 5 SFP_SR/LR_CORE0 - 82599-specific 970 * 6 SFP_SR/LR_CORE1 - 82599-specific 971 */ 972 if (hw->mac.type == ixgbe_mac_82598EB) { 973 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 974 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 975 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 976 hw->phy.sfp_type = ixgbe_sfp_type_sr; 977 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 978 hw->phy.sfp_type = ixgbe_sfp_type_lr; 979 else 980 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 981 } else if (hw->mac.type == ixgbe_mac_82599EB) { 982 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 983 if (hw->bus.lan_id == 0) 984 hw->phy.sfp_type = 985 ixgbe_sfp_type_da_cu_core0; 986 else 987 hw->phy.sfp_type = 988 ixgbe_sfp_type_da_cu_core1; 989 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 990 if (hw->bus.lan_id == 0) 991 hw->phy.sfp_type = 992 ixgbe_sfp_type_srlr_core0; 993 else 994 hw->phy.sfp_type = 995 ixgbe_sfp_type_srlr_core1; 996 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 997 if (hw->bus.lan_id == 0) 998 hw->phy.sfp_type = 999 ixgbe_sfp_type_srlr_core0; 1000 else 1001 hw->phy.sfp_type = 1002 ixgbe_sfp_type_srlr_core1; 1003 else 1004 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1005 } 1006 1007 if (hw->phy.sfp_type != stored_sfp_type) 1008 hw->phy.sfp_setup_needed = TRUE; 1009 1010 /* Determine if the SFP+ PHY is dual speed or not. */ 1011 hw->phy.multispeed_fiber = FALSE; 1012 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1013 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1014 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1015 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1016 hw->phy.multispeed_fiber = TRUE; 1017 1018 /* Determine PHY vendor */ 1019 if (hw->phy.type != ixgbe_phy_nl) { 1020 hw->phy.id = identifier; 1021 hw->phy.ops.read_i2c_eeprom(hw, 1022 IXGBE_SFF_VENDOR_OUI_BYTE0, 1023 &oui_bytes[0]); 1024 hw->phy.ops.read_i2c_eeprom(hw, 1025 IXGBE_SFF_VENDOR_OUI_BYTE1, 1026 &oui_bytes[1]); 1027 hw->phy.ops.read_i2c_eeprom(hw, 1028 IXGBE_SFF_VENDOR_OUI_BYTE2, 1029 &oui_bytes[2]); 1030 1031 vendor_oui = 1032 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1033 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1034 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1035 1036 switch (vendor_oui) { 1037 case IXGBE_SFF_VENDOR_OUI_TYCO: 1038 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1039 hw->phy.type = ixgbe_phy_tw_tyco; 1040 break; 1041 case IXGBE_SFF_VENDOR_OUI_FTL: 1042 hw->phy.type = ixgbe_phy_sfp_ftl; 1043 break; 1044 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1045 hw->phy.type = ixgbe_phy_sfp_avago; 1046 break; 1047 case IXGBE_SFF_VENDOR_OUI_INTEL: 1048 hw->phy.type = ixgbe_phy_sfp_intel; 1049 break; 1050 default: 1051 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1052 hw->phy.type = ixgbe_phy_tw_unknown; 1053 else 1054 hw->phy.type = ixgbe_phy_sfp_unknown; 1055 break; 1056 } 1057 } 1058 1059 /* All passive DA cables are supported */ 1060 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1061 status = IXGBE_SUCCESS; 1062 goto out; 1063 } 1064 1065 /* 1G SFP modules are not supported */ 1066 if (comp_codes_10g == 0) { 1067 hw->phy.type = ixgbe_phy_sfp_unsupported; 1068 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1069 goto out; 1070 } 1071 1072 /* Anything else 82598-based is supported */ 1073 if (hw->mac.type == ixgbe_mac_82598EB) { 1074 status = IXGBE_SUCCESS; 1075 goto out; 1076 } 1077 1078 ixgbe_get_device_caps(hw, &enforce_sfp); 1079 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1080 /* Make sure we're a supported PHY type */ 1081 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1082 status = IXGBE_SUCCESS; 1083 } else { 1084 DEBUGOUT("SFP+ module not supported\n"); 1085 hw->phy.type = ixgbe_phy_sfp_unsupported; 1086 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1087 } 1088 } else { 1089 status = IXGBE_SUCCESS; 1090 } 1091 } 1092 1093 out: 1094 return status; 1095 } 1096 1097 /** 1098 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1099 * @hw: pointer to hardware structure 1100 * @list_offset: offset to the SFP ID list 1101 * @data_offset: offset to the SFP data block 1102 * 1103 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1104 * so it returns the offsets to the phy init sequence block. 1105 **/ 1106 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1107 u16 *list_offset, 1108 u16 *data_offset) 1109 { 1110 u16 sfp_id; 1111 1112 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1113 1114 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1115 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1116 1117 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1118 return IXGBE_ERR_SFP_NOT_PRESENT; 1119 1120 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1121 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1122 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1123 1124 /* Read offset to PHY init contents */ 1125 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1126 1127 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1128 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1129 1130 /* Shift offset to first ID word */ 1131 (*list_offset)++; 1132 1133 /* 1134 * Find the matching SFP ID in the EEPROM 1135 * and program the init sequence 1136 */ 1137 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1138 1139 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1140 if (sfp_id == hw->phy.sfp_type) { 1141 (*list_offset)++; 1142 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1143 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1144 DEBUGOUT("SFP+ module not supported\n"); 1145 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1146 } else { 1147 break; 1148 } 1149 } else { 1150 (*list_offset) += 2; 1151 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1152 return IXGBE_ERR_PHY; 1153 } 1154 } 1155 1156 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1157 DEBUGOUT("No matching SFP+ module found\n"); 1158 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1159 } 1160 1161 return IXGBE_SUCCESS; 1162 } 1163 1164 /** 1165 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1166 * @hw: pointer to hardware structure 1167 * @byte_offset: EEPROM byte offset to read 1168 * @eeprom_data: value read 1169 * 1170 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1171 **/ 1172 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1173 u8 *eeprom_data) 1174 { 1175 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1176 1177 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1178 IXGBE_I2C_EEPROM_DEV_ADDR, 1179 eeprom_data); 1180 } 1181 1182 /** 1183 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1184 * @hw: pointer to hardware structure 1185 * @byte_offset: EEPROM byte offset to write 1186 * @eeprom_data: value to write 1187 * 1188 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1189 **/ 1190 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1191 u8 eeprom_data) 1192 { 1193 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1194 1195 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1196 IXGBE_I2C_EEPROM_DEV_ADDR, 1197 eeprom_data); 1198 } 1199 1200 /** 1201 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1202 * @hw: pointer to hardware structure 1203 * @byte_offset: byte offset to read 1204 * @data: value read 1205 * 1206 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1207 * a specified deivce address. 1208 **/ 1209 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1210 u8 dev_addr, u8 *data) 1211 { 1212 s32 status = IXGBE_SUCCESS; 1213 u32 max_retry = 10; 1214 u32 retry = 0; 1215 u16 swfw_mask = 0; 1216 bool nack = 1; 1217 1218 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1219 1220 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1221 swfw_mask = IXGBE_GSSR_PHY1_SM; 1222 else 1223 swfw_mask = IXGBE_GSSR_PHY0_SM; 1224 1225 1226 do { 1227 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1228 status = IXGBE_ERR_SWFW_SYNC; 1229 goto read_byte_out; 1230 } 1231 1232 ixgbe_i2c_start(hw); 1233 1234 /* Device Address and write indication */ 1235 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1236 if (status != IXGBE_SUCCESS) 1237 goto fail; 1238 1239 status = ixgbe_get_i2c_ack(hw); 1240 if (status != IXGBE_SUCCESS) 1241 goto fail; 1242 1243 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1244 if (status != IXGBE_SUCCESS) 1245 goto fail; 1246 1247 status = ixgbe_get_i2c_ack(hw); 1248 if (status != IXGBE_SUCCESS) 1249 goto fail; 1250 1251 ixgbe_i2c_start(hw); 1252 1253 /* Device Address and read indication */ 1254 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1255 if (status != IXGBE_SUCCESS) 1256 goto fail; 1257 1258 status = ixgbe_get_i2c_ack(hw); 1259 if (status != IXGBE_SUCCESS) 1260 goto fail; 1261 1262 status = ixgbe_clock_in_i2c_byte(hw, data); 1263 if (status != IXGBE_SUCCESS) 1264 goto fail; 1265 1266 status = ixgbe_clock_out_i2c_bit(hw, nack); 1267 if (status != IXGBE_SUCCESS) 1268 goto fail; 1269 1270 ixgbe_i2c_stop(hw); 1271 break; 1272 1273 fail: 1274 ixgbe_release_swfw_sync(hw, swfw_mask); 1275 msec_delay(100); 1276 ixgbe_i2c_bus_clear(hw); 1277 retry++; 1278 if (retry < max_retry) 1279 DEBUGOUT("I2C byte read error - Retrying.\n"); 1280 else 1281 DEBUGOUT("I2C byte read error.\n"); 1282 1283 } while (retry < max_retry); 1284 1285 ixgbe_release_swfw_sync(hw, swfw_mask); 1286 1287 read_byte_out: 1288 return status; 1289 } 1290 1291 /** 1292 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1293 * @hw: pointer to hardware structure 1294 * @byte_offset: byte offset to write 1295 * @data: value to write 1296 * 1297 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1298 * a specified device address. 1299 **/ 1300 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1301 u8 dev_addr, u8 data) 1302 { 1303 s32 status = IXGBE_SUCCESS; 1304 u32 max_retry = 1; 1305 u32 retry = 0; 1306 u16 swfw_mask = 0; 1307 1308 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1309 1310 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1311 swfw_mask = IXGBE_GSSR_PHY1_SM; 1312 else 1313 swfw_mask = IXGBE_GSSR_PHY0_SM; 1314 1315 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1316 status = IXGBE_ERR_SWFW_SYNC; 1317 goto write_byte_out; 1318 } 1319 1320 do { 1321 ixgbe_i2c_start(hw); 1322 1323 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1324 if (status != IXGBE_SUCCESS) 1325 goto fail; 1326 1327 status = ixgbe_get_i2c_ack(hw); 1328 if (status != IXGBE_SUCCESS) 1329 goto fail; 1330 1331 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1332 if (status != IXGBE_SUCCESS) 1333 goto fail; 1334 1335 status = ixgbe_get_i2c_ack(hw); 1336 if (status != IXGBE_SUCCESS) 1337 goto fail; 1338 1339 status = ixgbe_clock_out_i2c_byte(hw, data); 1340 if (status != IXGBE_SUCCESS) 1341 goto fail; 1342 1343 status = ixgbe_get_i2c_ack(hw); 1344 if (status != IXGBE_SUCCESS) 1345 goto fail; 1346 1347 ixgbe_i2c_stop(hw); 1348 break; 1349 1350 fail: 1351 ixgbe_i2c_bus_clear(hw); 1352 retry++; 1353 if (retry < max_retry) 1354 DEBUGOUT("I2C byte write error - Retrying.\n"); 1355 else 1356 DEBUGOUT("I2C byte write error.\n"); 1357 } while (retry < max_retry); 1358 1359 ixgbe_release_swfw_sync(hw, swfw_mask); 1360 1361 write_byte_out: 1362 return status; 1363 } 1364 1365 /** 1366 * ixgbe_i2c_start - Sets I2C start condition 1367 * @hw: pointer to hardware structure 1368 * 1369 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1370 **/ 1371 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1372 { 1373 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1374 1375 DEBUGFUNC("ixgbe_i2c_start"); 1376 1377 /* Start condition must begin with data and clock high */ 1378 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1379 ixgbe_raise_i2c_clk(hw, &i2cctl); 1380 1381 /* Setup time for start condition (4.7us) */ 1382 usec_delay(IXGBE_I2C_T_SU_STA); 1383 1384 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1385 1386 /* Hold time for start condition (4us) */ 1387 usec_delay(IXGBE_I2C_T_HD_STA); 1388 1389 ixgbe_lower_i2c_clk(hw, &i2cctl); 1390 1391 /* Minimum low period of clock is 4.7 us */ 1392 usec_delay(IXGBE_I2C_T_LOW); 1393 1394 } 1395 1396 /** 1397 * ixgbe_i2c_stop - Sets I2C stop condition 1398 * @hw: pointer to hardware structure 1399 * 1400 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1401 **/ 1402 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1403 { 1404 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1405 1406 DEBUGFUNC("ixgbe_i2c_stop"); 1407 1408 /* Stop condition must begin with data low and clock high */ 1409 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1410 ixgbe_raise_i2c_clk(hw, &i2cctl); 1411 1412 /* Setup time for stop condition (4us) */ 1413 usec_delay(IXGBE_I2C_T_SU_STO); 1414 1415 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1416 1417 /* bus free time between stop and start (4.7us)*/ 1418 usec_delay(IXGBE_I2C_T_BUF); 1419 } 1420 1421 /** 1422 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1423 * @hw: pointer to hardware structure 1424 * @data: data byte to clock in 1425 * 1426 * Clocks in one byte data via I2C data/clock 1427 **/ 1428 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1429 { 1430 s32 status = IXGBE_SUCCESS; 1431 s32 i; 1432 bool bit = 0; 1433 1434 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1435 1436 for (i = 7; i >= 0; i--) { 1437 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1438 *data |= bit<<i; 1439 1440 if (status != IXGBE_SUCCESS) 1441 break; 1442 } 1443 1444 return status; 1445 } 1446 1447 /** 1448 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1449 * @hw: pointer to hardware structure 1450 * @data: data byte clocked out 1451 * 1452 * Clocks out one byte data via I2C data/clock 1453 **/ 1454 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1455 { 1456 s32 status = IXGBE_SUCCESS; 1457 s32 i; 1458 u32 i2cctl; 1459 bool bit = 0; 1460 1461 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1462 1463 for (i = 7; i >= 0; i--) { 1464 bit = (data >> i) & 0x1; 1465 status = ixgbe_clock_out_i2c_bit(hw, bit); 1466 1467 if (status != IXGBE_SUCCESS) 1468 break; 1469 } 1470 1471 /* Release SDA line (set high) */ 1472 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1473 i2cctl |= IXGBE_I2C_DATA_OUT; 1474 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1475 1476 return status; 1477 } 1478 1479 /** 1480 * ixgbe_get_i2c_ack - Polls for I2C ACK 1481 * @hw: pointer to hardware structure 1482 * 1483 * Clocks in/out one bit via I2C data/clock 1484 **/ 1485 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1486 { 1487 s32 status; 1488 u32 i = 0; 1489 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1490 u32 timeout = 10; 1491 bool ack = 1; 1492 1493 DEBUGFUNC("ixgbe_get_i2c_ack"); 1494 1495 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1496 1497 if (status != IXGBE_SUCCESS) 1498 goto out; 1499 1500 /* Minimum high period of clock is 4us */ 1501 usec_delay(IXGBE_I2C_T_HIGH); 1502 1503 /* Poll for ACK. Note that ACK in I2C spec is 1504 * transition from 1 to 0 */ 1505 for (i = 0; i < timeout; i++) { 1506 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1507 ack = ixgbe_get_i2c_data(&i2cctl); 1508 1509 usec_delay(1); 1510 if (ack == 0) 1511 break; 1512 } 1513 1514 if (ack == 1) { 1515 DEBUGOUT("I2C ack was not received.\n"); 1516 status = IXGBE_ERR_I2C; 1517 } 1518 1519 ixgbe_lower_i2c_clk(hw, &i2cctl); 1520 1521 /* Minimum low period of clock is 4.7 us */ 1522 usec_delay(IXGBE_I2C_T_LOW); 1523 1524 out: 1525 return status; 1526 } 1527 1528 /** 1529 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1530 * @hw: pointer to hardware structure 1531 * @data: read data value 1532 * 1533 * Clocks in one bit via I2C data/clock 1534 **/ 1535 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1536 { 1537 s32 status; 1538 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1539 1540 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1541 1542 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1543 1544 /* Minimum high period of clock is 4us */ 1545 usec_delay(IXGBE_I2C_T_HIGH); 1546 1547 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1548 *data = ixgbe_get_i2c_data(&i2cctl); 1549 1550 ixgbe_lower_i2c_clk(hw, &i2cctl); 1551 1552 /* Minimum low period of clock is 4.7 us */ 1553 usec_delay(IXGBE_I2C_T_LOW); 1554 1555 return status; 1556 } 1557 1558 /** 1559 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1560 * @hw: pointer to hardware structure 1561 * @data: data value to write 1562 * 1563 * Clocks out one bit via I2C data/clock 1564 **/ 1565 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1566 { 1567 s32 status; 1568 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1569 1570 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1571 1572 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1573 if (status == IXGBE_SUCCESS) { 1574 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1575 1576 /* Minimum high period of clock is 4us */ 1577 usec_delay(IXGBE_I2C_T_HIGH); 1578 1579 ixgbe_lower_i2c_clk(hw, &i2cctl); 1580 1581 /* Minimum low period of clock is 4.7 us. 1582 * This also takes care of the data hold time. 1583 */ 1584 usec_delay(IXGBE_I2C_T_LOW); 1585 } else { 1586 status = IXGBE_ERR_I2C; 1587 DEBUGOUT1("I2C data was not set to %X\n", data); 1588 } 1589 1590 return status; 1591 } 1592 /** 1593 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1594 * @hw: pointer to hardware structure 1595 * @i2cctl: Current value of I2CCTL register 1596 * 1597 * Raises the I2C clock line '0'->'1' 1598 **/ 1599 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1600 { 1601 s32 status = IXGBE_SUCCESS; 1602 1603 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1604 1605 *i2cctl |= IXGBE_I2C_CLK_OUT; 1606 1607 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1608 1609 /* SCL rise time (1000ns) */ 1610 usec_delay(IXGBE_I2C_T_RISE); 1611 1612 return status; 1613 } 1614 1615 /** 1616 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1617 * @hw: pointer to hardware structure 1618 * @i2cctl: Current value of I2CCTL register 1619 * 1620 * Lowers the I2C clock line '1'->'0' 1621 **/ 1622 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1623 { 1624 1625 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1626 1627 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1628 1629 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1630 1631 /* SCL fall time (300ns) */ 1632 usec_delay(IXGBE_I2C_T_FALL); 1633 } 1634 1635 /** 1636 * ixgbe_set_i2c_data - Sets the I2C data bit 1637 * @hw: pointer to hardware structure 1638 * @i2cctl: Current value of I2CCTL register 1639 * @data: I2C data value (0 or 1) to set 1640 * 1641 * Sets the I2C data bit 1642 **/ 1643 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1644 { 1645 s32 status = IXGBE_SUCCESS; 1646 1647 DEBUGFUNC("ixgbe_set_i2c_data"); 1648 1649 if (data) 1650 *i2cctl |= IXGBE_I2C_DATA_OUT; 1651 else 1652 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1653 1654 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1655 1656 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1657 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1658 1659 /* Verify data was set correctly */ 1660 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1661 if (data != ixgbe_get_i2c_data(i2cctl)) { 1662 status = IXGBE_ERR_I2C; 1663 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1664 } 1665 1666 return status; 1667 } 1668 1669 /** 1670 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1671 * @hw: pointer to hardware structure 1672 * @i2cctl: Current value of I2CCTL register 1673 * 1674 * Returns the I2C data bit value 1675 **/ 1676 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1677 { 1678 bool data; 1679 1680 DEBUGFUNC("ixgbe_get_i2c_data"); 1681 1682 if (*i2cctl & IXGBE_I2C_DATA_IN) 1683 data = 1; 1684 else 1685 data = 0; 1686 1687 return data; 1688 } 1689 1690 /** 1691 * ixgbe_i2c_bus_clear - Clears the I2C bus 1692 * @hw: pointer to hardware structure 1693 * 1694 * Clears the I2C bus by sending nine clock pulses. 1695 * Used when data line is stuck low. 1696 **/ 1697 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1698 { 1699 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1700 u32 i; 1701 1702 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1703 1704 ixgbe_i2c_start(hw); 1705 1706 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1707 1708 for (i = 0; i < 9; i++) { 1709 ixgbe_raise_i2c_clk(hw, &i2cctl); 1710 1711 /* Min high period of clock is 4us */ 1712 usec_delay(IXGBE_I2C_T_HIGH); 1713 1714 ixgbe_lower_i2c_clk(hw, &i2cctl); 1715 1716 /* Min low period of clock is 4.7us*/ 1717 usec_delay(IXGBE_I2C_T_LOW); 1718 } 1719 1720 ixgbe_i2c_start(hw); 1721 1722 /* Put the i2c bus back to default state */ 1723 ixgbe_i2c_stop(hw); 1724 } 1725