1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 /** 40 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 41 * @hw: pointer to the hardware structure 42 * 43 * Initialize the function pointers. 44 **/ 45 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 46 { 47 struct ixgbe_phy_info *phy = &hw->phy; 48 49 /* PHY */ 50 phy->ops.identify = &ixgbe_identify_phy_generic; 51 phy->ops.reset = &ixgbe_reset_phy_generic; 52 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 53 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 54 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 55 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 56 phy->ops.check_link = NULL; 57 phy->ops.get_firmware_version = NULL; 58 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 59 phy->sfp_type = ixgbe_sfp_type_unknown; 60 61 return IXGBE_SUCCESS; 62 } 63 64 /** 65 * ixgbe_identify_phy_generic - Get physical layer module 66 * @hw: pointer to hardware structure 67 * 68 * Determines the physical layer module found on the current adapter. 69 **/ 70 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 71 { 72 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 73 u32 phy_addr; 74 75 if (hw->phy.type == ixgbe_phy_unknown) { 76 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 77 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 78 hw->phy.addr = phy_addr; 79 ixgbe_get_phy_id(hw); 80 hw->phy.type = 81 ixgbe_get_phy_type_from_id(hw->phy.id); 82 status = IXGBE_SUCCESS; 83 break; 84 } 85 } 86 } else { 87 status = IXGBE_SUCCESS; 88 } 89 90 return status; 91 } 92 93 /** 94 * ixgbe_validate_phy_addr - Determines phy address is valid 95 * @hw: pointer to hardware structure 96 * 97 **/ 98 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 99 { 100 u16 phy_id = 0; 101 bool valid = FALSE; 102 103 hw->phy.addr = phy_addr; 104 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 105 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 106 107 if (phy_id != 0xFFFF && phy_id != 0x0) 108 valid = TRUE; 109 110 return valid; 111 } 112 113 /** 114 * ixgbe_get_phy_id - Get the phy type 115 * @hw: pointer to hardware structure 116 * 117 **/ 118 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 119 { 120 u32 status; 121 u16 phy_id_high = 0; 122 u16 phy_id_low = 0; 123 124 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 125 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 126 &phy_id_high); 127 128 if (status == IXGBE_SUCCESS) { 129 hw->phy.id = (u32)(phy_id_high << 16); 130 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 131 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 132 &phy_id_low); 133 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 134 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 135 } 136 return status; 137 } 138 139 /** 140 * ixgbe_get_phy_type_from_id - Get the phy type 141 * @hw: pointer to hardware structure 142 * 143 **/ 144 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 145 { 146 enum ixgbe_phy_type phy_type; 147 148 switch (phy_id) { 149 case TN1010_PHY_ID: 150 phy_type = ixgbe_phy_tn; 151 break; 152 case QT2022_PHY_ID: 153 phy_type = ixgbe_phy_qt; 154 break; 155 case ATH_PHY_ID: 156 phy_type = ixgbe_phy_nl; 157 break; 158 default: 159 phy_type = ixgbe_phy_unknown; 160 break; 161 } 162 163 DEBUGOUT1("phy type found is %d\n", phy_type); 164 return phy_type; 165 } 166 167 /** 168 * ixgbe_reset_phy_generic - Performs a PHY reset 169 * @hw: pointer to hardware structure 170 **/ 171 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 172 { 173 /* 174 * Perform soft PHY reset to the PHY_XS. 175 * This will cause a soft reset to the PHY 176 */ 177 return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 178 IXGBE_MDIO_PHY_XS_DEV_TYPE, 179 IXGBE_MDIO_PHY_XS_RESET); 180 } 181 182 /** 183 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 184 * @hw: pointer to hardware structure 185 * @reg_addr: 32 bit address of PHY register to read 186 * @phy_data: Pointer to read data from PHY register 187 **/ 188 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 189 u32 device_type, u16 *phy_data) 190 { 191 u32 command; 192 u32 i; 193 u32 data; 194 s32 status = IXGBE_SUCCESS; 195 u16 gssr; 196 197 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 198 gssr = IXGBE_GSSR_PHY1_SM; 199 else 200 gssr = IXGBE_GSSR_PHY0_SM; 201 202 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 203 status = IXGBE_ERR_SWFW_SYNC; 204 205 if (status == IXGBE_SUCCESS) { 206 /* Setup and write the address cycle command */ 207 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 208 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 209 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 210 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 211 212 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 213 214 /* 215 * Check every 10 usec to see if the address cycle completed. 216 * The MDI Command bit will clear when the operation is 217 * complete 218 */ 219 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 220 usec_delay(10); 221 222 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 223 224 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 225 break; 226 } 227 228 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 229 DEBUGOUT("PHY address command did not complete.\n"); 230 status = IXGBE_ERR_PHY; 231 } 232 233 if (status == IXGBE_SUCCESS) { 234 /* 235 * Address cycle complete, setup and write the read 236 * command 237 */ 238 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 239 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 240 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 241 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 242 243 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 244 245 /* 246 * Check every 10 usec to see if the address cycle 247 * completed. The MDI Command bit will clear when the 248 * operation is complete 249 */ 250 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 251 usec_delay(10); 252 253 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 254 255 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 256 break; 257 } 258 259 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 260 DEBUGOUT("PHY read command didn't complete\n"); 261 status = IXGBE_ERR_PHY; 262 } else { 263 /* 264 * Read operation is complete. Get the data 265 * from MSRWD 266 */ 267 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 268 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 269 *phy_data = (u16)(data); 270 } 271 } 272 273 ixgbe_release_swfw_sync(hw, gssr); 274 } 275 276 return status; 277 } 278 279 /** 280 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 281 * @hw: pointer to hardware structure 282 * @reg_addr: 32 bit PHY register to write 283 * @device_type: 5 bit device type 284 * @phy_data: Data to write to the PHY register 285 **/ 286 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 287 u32 device_type, u16 phy_data) 288 { 289 u32 command; 290 u32 i; 291 s32 status = IXGBE_SUCCESS; 292 u16 gssr; 293 294 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 295 gssr = IXGBE_GSSR_PHY1_SM; 296 else 297 gssr = IXGBE_GSSR_PHY0_SM; 298 299 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 300 status = IXGBE_ERR_SWFW_SYNC; 301 302 if (status == IXGBE_SUCCESS) { 303 /* Put the data in the MDI single read and write data register*/ 304 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 305 306 /* Setup and write the address cycle command */ 307 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 308 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 309 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 310 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 311 312 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 313 314 /* 315 * Check every 10 usec to see if the address cycle completed. 316 * The MDI Command bit will clear when the operation is 317 * complete 318 */ 319 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 320 usec_delay(10); 321 322 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 323 324 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 325 break; 326 } 327 328 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 329 DEBUGOUT("PHY address cmd didn't complete\n"); 330 status = IXGBE_ERR_PHY; 331 } 332 333 if (status == IXGBE_SUCCESS) { 334 /* 335 * Address cycle complete, setup and write the write 336 * command 337 */ 338 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 339 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 340 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 341 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 342 343 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 344 345 /* 346 * Check every 10 usec to see if the address cycle 347 * completed. The MDI Command bit will clear when the 348 * operation is complete 349 */ 350 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 351 usec_delay(10); 352 353 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 354 355 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 356 break; 357 } 358 359 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 360 DEBUGOUT("PHY address cmd didn't complete\n"); 361 status = IXGBE_ERR_PHY; 362 } 363 } 364 365 ixgbe_release_swfw_sync(hw, gssr); 366 } 367 368 return status; 369 } 370 371 /** 372 * ixgbe_setup_phy_link_generic - Set and restart autoneg 373 * @hw: pointer to hardware structure 374 * 375 * Restart autonegotiation and PHY and waits for completion. 376 **/ 377 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 378 { 379 s32 status = IXGBE_NOT_IMPLEMENTED; 380 u32 time_out; 381 u32 max_time_out = 10; 382 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 383 384 /* 385 * Set advertisement settings in PHY based on autoneg_advertised 386 * settings. If autoneg_advertised = 0, then advertise default values 387 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can 388 * for a 1G. 389 */ 390 hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 391 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 392 393 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) 394 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */ 395 else 396 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */ 397 398 hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 399 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 400 401 /* Restart PHY autonegotiation and wait for completion */ 402 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 403 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 404 405 autoneg_reg |= IXGBE_MII_RESTART; 406 407 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 408 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 409 410 /* Wait for autonegotiation to finish */ 411 for (time_out = 0; time_out < max_time_out; time_out++) { 412 usec_delay(10); 413 /* Restart PHY autonegotiation and wait for completion */ 414 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 415 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 416 &autoneg_reg); 417 418 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 419 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 420 status = IXGBE_SUCCESS; 421 break; 422 } 423 } 424 425 if (time_out == max_time_out) 426 status = IXGBE_ERR_LINK_SETUP; 427 428 return status; 429 } 430 431 /** 432 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 433 * @hw: pointer to hardware structure 434 * @speed: new link speed 435 * @autoneg: TRUE if autonegotiation enabled 436 **/ 437 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 438 ixgbe_link_speed speed, 439 bool autoneg, 440 bool autoneg_wait_to_complete) 441 { 442 UNREFERENCED_PARAMETER(autoneg); 443 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 444 445 /* 446 * Clear autoneg_advertised and set new values based on input link 447 * speed. 448 */ 449 hw->phy.autoneg_advertised = 0; 450 451 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 452 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 453 454 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 455 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 456 457 /* Setup link based on the new speed settings */ 458 hw->phy.ops.setup_link(hw); 459 460 return IXGBE_SUCCESS; 461 } 462 463 /** 464 * ixgbe_check_phy_link_tnx - Determine link and speed status 465 * @hw: pointer to hardware structure 466 * 467 * Reads the VS1 register to determine if link is up and the current speed for 468 * the PHY. 469 **/ 470 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 471 bool *link_up) 472 { 473 s32 status = IXGBE_SUCCESS; 474 u32 time_out; 475 u32 max_time_out = 10; 476 u16 phy_link = 0; 477 u16 phy_speed = 0; 478 u16 phy_data = 0; 479 480 /* Initialize speed and link to default case */ 481 *link_up = FALSE; 482 *speed = IXGBE_LINK_SPEED_10GB_FULL; 483 484 /* 485 * Check current speed and link status of the PHY register. 486 * This is a vendor specific register and may have to 487 * be changed for other copper PHYs. 488 */ 489 for (time_out = 0; time_out < max_time_out; time_out++) { 490 usec_delay(10); 491 status = hw->phy.ops.read_reg(hw, 492 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 493 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 494 &phy_data); 495 phy_link = phy_data & 496 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 497 phy_speed = phy_data & 498 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 499 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 500 *link_up = TRUE; 501 if (phy_speed == 502 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 503 *speed = IXGBE_LINK_SPEED_1GB_FULL; 504 break; 505 } 506 } 507 508 return status; 509 } 510 511 /** 512 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 513 * @hw: pointer to hardware structure 514 * @firmware_version: pointer to the PHY Firmware Version 515 **/ 516 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 517 u16 *firmware_version) 518 { 519 s32 status = IXGBE_SUCCESS; 520 521 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 522 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 523 firmware_version); 524 525 return status; 526 } 527 528 /** 529 * ixgbe_reset_phy_nl - Performs a PHY reset 530 * @hw: pointer to hardware structure 531 **/ 532 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 533 { 534 u16 phy_offset, control, eword, edata, block_crc; 535 bool end_data = FALSE; 536 u16 list_offset, data_offset; 537 u16 phy_data = 0; 538 s32 ret_val = IXGBE_SUCCESS; 539 u32 i; 540 541 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 542 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 543 544 /* reset the PHY and poll for completion */ 545 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 546 IXGBE_MDIO_PHY_XS_DEV_TYPE, 547 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 548 549 for (i = 0; i < 100; i++) { 550 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 551 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 552 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 553 break; 554 msec_delay(10); 555 } 556 557 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 558 DEBUGOUT("PHY reset did not complete.\n"); 559 ret_val = IXGBE_ERR_PHY; 560 goto out; 561 } 562 563 /* Get init offsets */ 564 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 565 &data_offset); 566 if (ret_val != IXGBE_SUCCESS) 567 goto out; 568 569 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 570 data_offset++; 571 while (!end_data) { 572 /* 573 * Read control word from PHY init contents offset 574 */ 575 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 576 control = (eword & IXGBE_CONTROL_MASK_NL) >> 577 IXGBE_CONTROL_SHIFT_NL; 578 edata = eword & IXGBE_DATA_MASK_NL; 579 switch (control) { 580 case IXGBE_DELAY_NL: 581 data_offset++; 582 DEBUGOUT1("DELAY: %d MS\n", edata); 583 msec_delay(edata); 584 break; 585 case IXGBE_DATA_NL: 586 DEBUGOUT("DATA: \n"); 587 data_offset++; 588 hw->eeprom.ops.read(hw, data_offset++, 589 &phy_offset); 590 for (i = 0; i < edata; i++) { 591 hw->eeprom.ops.read(hw, data_offset, &eword); 592 hw->phy.ops.write_reg(hw, phy_offset, 593 IXGBE_TWINAX_DEV, eword); 594 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 595 phy_offset); 596 data_offset++; 597 phy_offset++; 598 } 599 break; 600 case IXGBE_CONTROL_NL: 601 data_offset++; 602 DEBUGOUT("CONTROL: \n"); 603 if (edata == IXGBE_CONTROL_EOL_NL) { 604 DEBUGOUT("EOL\n"); 605 end_data = TRUE; 606 } else if (edata == IXGBE_CONTROL_SOL_NL) { 607 DEBUGOUT("SOL\n"); 608 } else { 609 DEBUGOUT("Bad control value\n"); 610 ret_val = IXGBE_ERR_PHY; 611 goto out; 612 } 613 break; 614 default: 615 DEBUGOUT("Bad control type\n"); 616 ret_val = IXGBE_ERR_PHY; 617 goto out; 618 } 619 } 620 621 out: 622 return ret_val; 623 } 624 625 /** 626 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 627 * @hw: pointer to hardware structure 628 * 629 * Searches for and identifies the SFP module and assigns appropriate PHY type. 630 **/ 631 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 632 { 633 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 634 u32 vendor_oui = 0; 635 u8 identifier = 0; 636 u8 comp_codes_1g = 0; 637 u8 comp_codes_10g = 0; 638 u8 oui_bytes[4] = {0, 0, 0, 0}; 639 u8 transmission_media = 0; 640 641 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 642 &identifier); 643 644 if (status == IXGBE_ERR_SFP_NOT_PRESENT) { 645 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 646 goto out; 647 } 648 649 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { 650 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 651 &comp_codes_1g); 652 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 653 &comp_codes_10g); 654 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA, 655 &transmission_media); 656 657 /* ID Module 658 * ========= 659 * 0 SFP_DA_CU 660 * 1 SFP_SR 661 * 2 SFP_LR 662 */ 663 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) 664 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 665 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 666 hw->phy.sfp_type = ixgbe_sfp_type_sr; 667 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 668 hw->phy.sfp_type = ixgbe_sfp_type_lr; 669 else 670 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 671 672 /* Determine if the SFP+ PHY is dual speed or not. */ 673 if ((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 674 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) 675 hw->phy.multispeed_fiber = TRUE; 676 /* Determine PHY vendor */ 677 if (hw->phy.type == ixgbe_phy_unknown) { 678 hw->phy.id = identifier; 679 hw->phy.ops.read_i2c_eeprom(hw, 680 IXGBE_SFF_VENDOR_OUI_BYTE0, 681 &oui_bytes[0]); 682 hw->phy.ops.read_i2c_eeprom(hw, 683 IXGBE_SFF_VENDOR_OUI_BYTE1, 684 &oui_bytes[1]); 685 hw->phy.ops.read_i2c_eeprom(hw, 686 IXGBE_SFF_VENDOR_OUI_BYTE2, 687 &oui_bytes[2]); 688 689 vendor_oui = 690 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 691 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 692 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 693 694 switch (vendor_oui) { 695 case IXGBE_SFF_VENDOR_OUI_TYCO: 696 if (transmission_media & 697 IXGBE_SFF_TWIN_AX_CAPABLE) 698 hw->phy.type = ixgbe_phy_tw_tyco; 699 break; 700 case IXGBE_SFF_VENDOR_OUI_FTL: 701 hw->phy.type = ixgbe_phy_sfp_ftl; 702 break; 703 case IXGBE_SFF_VENDOR_OUI_AVAGO: 704 hw->phy.type = ixgbe_phy_sfp_avago; 705 break; 706 default: 707 if (transmission_media & 708 IXGBE_SFF_TWIN_AX_CAPABLE) 709 hw->phy.type = ixgbe_phy_tw_unknown; 710 else 711 hw->phy.type = ixgbe_phy_sfp_unknown; 712 break; 713 } 714 } 715 status = IXGBE_SUCCESS; 716 } 717 718 out: 719 return status; 720 } 721 722 /** 723 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 724 * @hw: pointer to hardware structure 725 * @list_offset: offset to the SFP ID list 726 * @data_offset: offset to the SFP data block 727 * 728 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 729 * so it returns the offsets to the phy init sequence block. 730 **/ 731 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 732 u16 *list_offset, 733 u16 *data_offset) 734 { 735 u16 sfp_id; 736 737 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 738 return IXGBE_ERR_SFP_NOT_SUPPORTED; 739 740 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 741 return IXGBE_ERR_SFP_NOT_PRESENT; 742 743 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 744 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 745 return IXGBE_ERR_SFP_NOT_SUPPORTED; 746 747 /* Read offset to PHY init contents */ 748 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 749 750 if ((!*list_offset) || (*list_offset == 0xFFFF)) 751 return IXGBE_ERR_PHY; 752 753 /* Shift offset to first ID word */ 754 (*list_offset)++; 755 756 /* 757 * Find the matching SFP ID in the EEPROM 758 * and program the init sequence 759 */ 760 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 761 762 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 763 if (sfp_id == hw->phy.sfp_type) { 764 (*list_offset)++; 765 hw->eeprom.ops.read(hw, *list_offset, data_offset); 766 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 767 DEBUGOUT("SFP+ module not supported\n"); 768 return IXGBE_ERR_SFP_NOT_SUPPORTED; 769 } else { 770 break; 771 } 772 } else { 773 (*list_offset) += 2; 774 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 775 return IXGBE_ERR_PHY; 776 } 777 } 778 779 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 780 DEBUGOUT("No matching SFP+ module found\n"); 781 return IXGBE_ERR_SFP_NOT_SUPPORTED; 782 } 783 784 return IXGBE_SUCCESS; 785 } 786 787