1 /****************************************************************************** 2 3 Copyright (c) 2013-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "i40e_virtchnl.h" 39 40 /** 41 * i40e_set_mac_type - Sets MAC type 42 * @hw: pointer to the HW structure 43 * 44 * This function sets the mac type of the adapter based on the 45 * vendor ID and device ID stored in the hw structure. 46 **/ 47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 48 { 49 enum i40e_status_code status = I40E_SUCCESS; 50 51 DEBUGFUNC("i40e_set_mac_type\n"); 52 53 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 54 switch (hw->device_id) { 55 case I40E_DEV_ID_SFP_XL710: 56 case I40E_DEV_ID_QEMU: 57 case I40E_DEV_ID_KX_A: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 hw->mac.type = I40E_MAC_XL710; 65 break; 66 case I40E_DEV_ID_VF: 67 case I40E_DEV_ID_VF_HV: 68 hw->mac.type = I40E_MAC_VF; 69 break; 70 default: 71 hw->mac.type = I40E_MAC_GENERIC; 72 break; 73 } 74 } else { 75 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 76 } 77 78 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 79 hw->mac.type, status); 80 return status; 81 } 82 83 /** 84 * i40e_debug_aq 85 * @hw: debug mask related to admin queue 86 * @mask: debug mask 87 * @desc: pointer to admin queue descriptor 88 * @buffer: pointer to command buffer 89 * @buf_len: max length of buffer 90 * 91 * Dumps debug log about adminq command with descriptor contents. 92 **/ 93 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 94 void *buffer, u16 buf_len) 95 { 96 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 97 u16 len = LE16_TO_CPU(aq_desc->datalen); 98 u8 *aq_buffer = (u8 *)buffer; 99 u32 data[4]; 100 u32 i = 0; 101 102 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 103 return; 104 105 i40e_debug(hw, mask, 106 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 107 aq_desc->opcode, aq_desc->flags, aq_desc->datalen, 108 aq_desc->retval); 109 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 110 aq_desc->cookie_high, aq_desc->cookie_low); 111 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 112 aq_desc->params.internal.param0, 113 aq_desc->params.internal.param1); 114 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 115 aq_desc->params.external.addr_high, 116 aq_desc->params.external.addr_low); 117 118 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 119 i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM); 120 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 121 if (buf_len < len) 122 len = buf_len; 123 for (i = 0; i < len; i++) { 124 data[((i % 16) / 4)] |= 125 ((u32)aq_buffer[i]) << (8 * (i % 4)); 126 if ((i % 16) == 15) { 127 i40e_debug(hw, mask, 128 "\t0x%04X %08X %08X %08X %08X\n", 129 i - 15, data[0], data[1], data[2], 130 data[3]); 131 i40e_memset(data, 0, sizeof(data), 132 I40E_NONDMA_MEM); 133 } 134 } 135 if ((i % 16) != 0) 136 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n", 137 i - (i % 16), data[0], data[1], data[2], 138 data[3]); 139 } 140 } 141 142 /** 143 * i40e_check_asq_alive 144 * @hw: pointer to the hw struct 145 * 146 * Returns TRUE if Queue is enabled else FALSE. 147 **/ 148 bool i40e_check_asq_alive(struct i40e_hw *hw) 149 { 150 if (hw->aq.asq.len) 151 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK); 152 else 153 return FALSE; 154 } 155 156 /** 157 * i40e_aq_queue_shutdown 158 * @hw: pointer to the hw struct 159 * @unloading: is the driver unloading itself 160 * 161 * Tell the Firmware that we're shutting down the AdminQ and whether 162 * or not the driver is unloading as well. 163 **/ 164 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 165 bool unloading) 166 { 167 struct i40e_aq_desc desc; 168 struct i40e_aqc_queue_shutdown *cmd = 169 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 170 enum i40e_status_code status; 171 172 i40e_fill_default_direct_cmd_desc(&desc, 173 i40e_aqc_opc_queue_shutdown); 174 175 if (unloading) 176 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 177 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 178 179 return status; 180 } 181 182 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 183 * hardware to a bit-field that can be used by SW to more easily determine the 184 * packet type. 185 * 186 * Macros are used to shorten the table lines and make this table human 187 * readable. 188 * 189 * We store the PTYPE in the top byte of the bit field - this is just so that 190 * we can check that the table doesn't have a row missing, as the index into 191 * the table should be the PTYPE. 192 * 193 * Typical work flow: 194 * 195 * IF NOT i40e_ptype_lookup[ptype].known 196 * THEN 197 * Packet is unknown 198 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 199 * Use the rest of the fields to look at the tunnels, inner protocols, etc 200 * ELSE 201 * Use the enum i40e_rx_l2_ptype to decode the packet type 202 * ENDIF 203 */ 204 205 /* macro to make the table lines short */ 206 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 207 { PTYPE, \ 208 1, \ 209 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 210 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 211 I40E_RX_PTYPE_##OUTER_FRAG, \ 212 I40E_RX_PTYPE_TUNNEL_##T, \ 213 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 214 I40E_RX_PTYPE_##TEF, \ 215 I40E_RX_PTYPE_INNER_PROT_##I, \ 216 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 217 218 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 219 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 220 221 /* shorter macros makes the table fit but are terse */ 222 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 223 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 224 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 225 226 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 227 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 228 /* L2 Packet types */ 229 I40E_PTT_UNUSED_ENTRY(0), 230 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 231 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 232 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 233 I40E_PTT_UNUSED_ENTRY(4), 234 I40E_PTT_UNUSED_ENTRY(5), 235 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 236 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 237 I40E_PTT_UNUSED_ENTRY(8), 238 I40E_PTT_UNUSED_ENTRY(9), 239 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 240 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 241 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 242 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 243 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 244 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 245 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 246 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 247 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 248 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 249 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 250 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 251 252 /* Non Tunneled IPv4 */ 253 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 254 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 255 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 256 I40E_PTT_UNUSED_ENTRY(25), 257 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 258 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 259 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 260 261 /* IPv4 --> IPv4 */ 262 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 263 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 264 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 265 I40E_PTT_UNUSED_ENTRY(32), 266 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 267 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 268 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 269 270 /* IPv4 --> IPv6 */ 271 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 272 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 273 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 274 I40E_PTT_UNUSED_ENTRY(39), 275 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 276 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 277 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 278 279 /* IPv4 --> GRE/NAT */ 280 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 281 282 /* IPv4 --> GRE/NAT --> IPv4 */ 283 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 284 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 285 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 286 I40E_PTT_UNUSED_ENTRY(47), 287 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 288 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 289 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 290 291 /* IPv4 --> GRE/NAT --> IPv6 */ 292 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 293 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 294 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 295 I40E_PTT_UNUSED_ENTRY(54), 296 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 297 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 298 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 299 300 /* IPv4 --> GRE/NAT --> MAC */ 301 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 302 303 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 304 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 305 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 306 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 307 I40E_PTT_UNUSED_ENTRY(62), 308 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 309 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 310 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 311 312 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 313 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 314 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 315 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 316 I40E_PTT_UNUSED_ENTRY(69), 317 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 318 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 319 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 320 321 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 322 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 323 324 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 325 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 326 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 327 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 328 I40E_PTT_UNUSED_ENTRY(77), 329 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 330 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 331 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 332 333 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 334 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 335 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 336 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 337 I40E_PTT_UNUSED_ENTRY(84), 338 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 339 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 340 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 341 342 /* Non Tunneled IPv6 */ 343 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 344 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 345 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 346 I40E_PTT_UNUSED_ENTRY(91), 347 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 348 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 349 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 350 351 /* IPv6 --> IPv4 */ 352 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 353 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 354 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 355 I40E_PTT_UNUSED_ENTRY(98), 356 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 357 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 358 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 359 360 /* IPv6 --> IPv6 */ 361 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 362 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 363 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 364 I40E_PTT_UNUSED_ENTRY(105), 365 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 366 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 367 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 368 369 /* IPv6 --> GRE/NAT */ 370 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 371 372 /* IPv6 --> GRE/NAT -> IPv4 */ 373 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 374 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 375 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 376 I40E_PTT_UNUSED_ENTRY(113), 377 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 378 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 379 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 380 381 /* IPv6 --> GRE/NAT -> IPv6 */ 382 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 383 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 384 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 385 I40E_PTT_UNUSED_ENTRY(120), 386 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 387 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 388 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 389 390 /* IPv6 --> GRE/NAT -> MAC */ 391 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 392 393 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 394 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 395 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 396 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 397 I40E_PTT_UNUSED_ENTRY(128), 398 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 399 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 400 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 401 402 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 403 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 404 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 405 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 406 I40E_PTT_UNUSED_ENTRY(135), 407 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 408 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 409 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 410 411 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 412 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 413 414 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 415 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 416 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 417 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 418 I40E_PTT_UNUSED_ENTRY(143), 419 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 420 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 421 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 422 423 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 424 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 425 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 426 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 427 I40E_PTT_UNUSED_ENTRY(150), 428 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 429 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 430 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 431 432 /* unused entries */ 433 I40E_PTT_UNUSED_ENTRY(154), 434 I40E_PTT_UNUSED_ENTRY(155), 435 I40E_PTT_UNUSED_ENTRY(156), 436 I40E_PTT_UNUSED_ENTRY(157), 437 I40E_PTT_UNUSED_ENTRY(158), 438 I40E_PTT_UNUSED_ENTRY(159), 439 440 I40E_PTT_UNUSED_ENTRY(160), 441 I40E_PTT_UNUSED_ENTRY(161), 442 I40E_PTT_UNUSED_ENTRY(162), 443 I40E_PTT_UNUSED_ENTRY(163), 444 I40E_PTT_UNUSED_ENTRY(164), 445 I40E_PTT_UNUSED_ENTRY(165), 446 I40E_PTT_UNUSED_ENTRY(166), 447 I40E_PTT_UNUSED_ENTRY(167), 448 I40E_PTT_UNUSED_ENTRY(168), 449 I40E_PTT_UNUSED_ENTRY(169), 450 451 I40E_PTT_UNUSED_ENTRY(170), 452 I40E_PTT_UNUSED_ENTRY(171), 453 I40E_PTT_UNUSED_ENTRY(172), 454 I40E_PTT_UNUSED_ENTRY(173), 455 I40E_PTT_UNUSED_ENTRY(174), 456 I40E_PTT_UNUSED_ENTRY(175), 457 I40E_PTT_UNUSED_ENTRY(176), 458 I40E_PTT_UNUSED_ENTRY(177), 459 I40E_PTT_UNUSED_ENTRY(178), 460 I40E_PTT_UNUSED_ENTRY(179), 461 462 I40E_PTT_UNUSED_ENTRY(180), 463 I40E_PTT_UNUSED_ENTRY(181), 464 I40E_PTT_UNUSED_ENTRY(182), 465 I40E_PTT_UNUSED_ENTRY(183), 466 I40E_PTT_UNUSED_ENTRY(184), 467 I40E_PTT_UNUSED_ENTRY(185), 468 I40E_PTT_UNUSED_ENTRY(186), 469 I40E_PTT_UNUSED_ENTRY(187), 470 I40E_PTT_UNUSED_ENTRY(188), 471 I40E_PTT_UNUSED_ENTRY(189), 472 473 I40E_PTT_UNUSED_ENTRY(190), 474 I40E_PTT_UNUSED_ENTRY(191), 475 I40E_PTT_UNUSED_ENTRY(192), 476 I40E_PTT_UNUSED_ENTRY(193), 477 I40E_PTT_UNUSED_ENTRY(194), 478 I40E_PTT_UNUSED_ENTRY(195), 479 I40E_PTT_UNUSED_ENTRY(196), 480 I40E_PTT_UNUSED_ENTRY(197), 481 I40E_PTT_UNUSED_ENTRY(198), 482 I40E_PTT_UNUSED_ENTRY(199), 483 484 I40E_PTT_UNUSED_ENTRY(200), 485 I40E_PTT_UNUSED_ENTRY(201), 486 I40E_PTT_UNUSED_ENTRY(202), 487 I40E_PTT_UNUSED_ENTRY(203), 488 I40E_PTT_UNUSED_ENTRY(204), 489 I40E_PTT_UNUSED_ENTRY(205), 490 I40E_PTT_UNUSED_ENTRY(206), 491 I40E_PTT_UNUSED_ENTRY(207), 492 I40E_PTT_UNUSED_ENTRY(208), 493 I40E_PTT_UNUSED_ENTRY(209), 494 495 I40E_PTT_UNUSED_ENTRY(210), 496 I40E_PTT_UNUSED_ENTRY(211), 497 I40E_PTT_UNUSED_ENTRY(212), 498 I40E_PTT_UNUSED_ENTRY(213), 499 I40E_PTT_UNUSED_ENTRY(214), 500 I40E_PTT_UNUSED_ENTRY(215), 501 I40E_PTT_UNUSED_ENTRY(216), 502 I40E_PTT_UNUSED_ENTRY(217), 503 I40E_PTT_UNUSED_ENTRY(218), 504 I40E_PTT_UNUSED_ENTRY(219), 505 506 I40E_PTT_UNUSED_ENTRY(220), 507 I40E_PTT_UNUSED_ENTRY(221), 508 I40E_PTT_UNUSED_ENTRY(222), 509 I40E_PTT_UNUSED_ENTRY(223), 510 I40E_PTT_UNUSED_ENTRY(224), 511 I40E_PTT_UNUSED_ENTRY(225), 512 I40E_PTT_UNUSED_ENTRY(226), 513 I40E_PTT_UNUSED_ENTRY(227), 514 I40E_PTT_UNUSED_ENTRY(228), 515 I40E_PTT_UNUSED_ENTRY(229), 516 517 I40E_PTT_UNUSED_ENTRY(230), 518 I40E_PTT_UNUSED_ENTRY(231), 519 I40E_PTT_UNUSED_ENTRY(232), 520 I40E_PTT_UNUSED_ENTRY(233), 521 I40E_PTT_UNUSED_ENTRY(234), 522 I40E_PTT_UNUSED_ENTRY(235), 523 I40E_PTT_UNUSED_ENTRY(236), 524 I40E_PTT_UNUSED_ENTRY(237), 525 I40E_PTT_UNUSED_ENTRY(238), 526 I40E_PTT_UNUSED_ENTRY(239), 527 528 I40E_PTT_UNUSED_ENTRY(240), 529 I40E_PTT_UNUSED_ENTRY(241), 530 I40E_PTT_UNUSED_ENTRY(242), 531 I40E_PTT_UNUSED_ENTRY(243), 532 I40E_PTT_UNUSED_ENTRY(244), 533 I40E_PTT_UNUSED_ENTRY(245), 534 I40E_PTT_UNUSED_ENTRY(246), 535 I40E_PTT_UNUSED_ENTRY(247), 536 I40E_PTT_UNUSED_ENTRY(248), 537 I40E_PTT_UNUSED_ENTRY(249), 538 539 I40E_PTT_UNUSED_ENTRY(250), 540 I40E_PTT_UNUSED_ENTRY(251), 541 I40E_PTT_UNUSED_ENTRY(252), 542 I40E_PTT_UNUSED_ENTRY(253), 543 I40E_PTT_UNUSED_ENTRY(254), 544 I40E_PTT_UNUSED_ENTRY(255) 545 }; 546 547 548 /** 549 * i40e_init_shared_code - Initialize the shared code 550 * @hw: pointer to hardware structure 551 * 552 * This assigns the MAC type and PHY code and inits the NVM. 553 * Does not touch the hardware. This function must be called prior to any 554 * other function in the shared code. The i40e_hw structure should be 555 * memset to 0 prior to calling this function. The following fields in 556 * hw structure should be filled in prior to calling this function: 557 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 558 * subsystem_vendor_id, and revision_id 559 **/ 560 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 561 { 562 enum i40e_status_code status = I40E_SUCCESS; 563 u32 reg; 564 565 DEBUGFUNC("i40e_init_shared_code"); 566 567 i40e_set_mac_type(hw); 568 569 switch (hw->mac.type) { 570 case I40E_MAC_XL710: 571 break; 572 default: 573 return I40E_ERR_DEVICE_NOT_SUPPORTED; 574 } 575 576 hw->phy.get_link_info = TRUE; 577 578 /* Determine port number */ 579 reg = rd32(hw, I40E_PFGEN_PORTNUM); 580 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >> 581 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT); 582 hw->port = (u8)reg; 583 584 /* Determine the PF number based on the PCI fn */ 585 reg = rd32(hw, I40E_GLPCI_CAPSUP); 586 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK) 587 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func); 588 else 589 hw->pf_id = (u8)hw->bus.func; 590 591 status = i40e_init_nvm(hw); 592 return status; 593 } 594 595 /** 596 * i40e_aq_mac_address_read - Retrieve the MAC addresses 597 * @hw: pointer to the hw struct 598 * @flags: a return indicator of what addresses were added to the addr store 599 * @addrs: the requestor's mac addr store 600 * @cmd_details: pointer to command details structure or NULL 601 **/ 602 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 603 u16 *flags, 604 struct i40e_aqc_mac_address_read_data *addrs, 605 struct i40e_asq_cmd_details *cmd_details) 606 { 607 struct i40e_aq_desc desc; 608 struct i40e_aqc_mac_address_read *cmd_data = 609 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 610 enum i40e_status_code status; 611 612 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 613 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 614 615 status = i40e_asq_send_command(hw, &desc, addrs, 616 sizeof(*addrs), cmd_details); 617 *flags = LE16_TO_CPU(cmd_data->command_flags); 618 619 return status; 620 } 621 622 /** 623 * i40e_aq_mac_address_write - Change the MAC addresses 624 * @hw: pointer to the hw struct 625 * @flags: indicates which MAC to be written 626 * @mac_addr: address to write 627 * @cmd_details: pointer to command details structure or NULL 628 **/ 629 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 630 u16 flags, u8 *mac_addr, 631 struct i40e_asq_cmd_details *cmd_details) 632 { 633 struct i40e_aq_desc desc; 634 struct i40e_aqc_mac_address_write *cmd_data = 635 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 636 enum i40e_status_code status; 637 638 i40e_fill_default_direct_cmd_desc(&desc, 639 i40e_aqc_opc_mac_address_write); 640 cmd_data->command_flags = CPU_TO_LE16(flags); 641 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 642 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 643 ((u32)mac_addr[3] << 16) | 644 ((u32)mac_addr[4] << 8) | 645 mac_addr[5]); 646 647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 648 649 return status; 650 } 651 652 /** 653 * i40e_get_mac_addr - get MAC address 654 * @hw: pointer to the HW structure 655 * @mac_addr: pointer to MAC address 656 * 657 * Reads the adapter's MAC address from register 658 **/ 659 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 660 { 661 struct i40e_aqc_mac_address_read_data addrs; 662 enum i40e_status_code status; 663 u16 flags = 0; 664 665 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 666 667 if (flags & I40E_AQC_LAN_ADDR_VALID) 668 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 669 670 return status; 671 } 672 673 /** 674 * i40e_get_port_mac_addr - get Port MAC address 675 * @hw: pointer to the HW structure 676 * @mac_addr: pointer to Port MAC address 677 * 678 * Reads the adapter's Port MAC address 679 **/ 680 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 681 { 682 struct i40e_aqc_mac_address_read_data addrs; 683 enum i40e_status_code status; 684 u16 flags = 0; 685 686 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 687 if (status) 688 return status; 689 690 if (flags & I40E_AQC_PORT_ADDR_VALID) 691 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 692 else 693 status = I40E_ERR_INVALID_MAC_ADDR; 694 695 return status; 696 } 697 698 /** 699 * i40e_pre_tx_queue_cfg - pre tx queue configure 700 * @hw: pointer to the HW structure 701 * @queue: target pf queue index 702 * @enable: state change request 703 * 704 * Handles hw requirement to indicate intention to enable 705 * or disable target queue. 706 **/ 707 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 708 { 709 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 710 u32 reg_block = 0; 711 u32 reg_val; 712 713 if (abs_queue_idx >= 128) { 714 reg_block = abs_queue_idx / 128; 715 abs_queue_idx %= 128; 716 } 717 718 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 719 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 720 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 721 722 if (enable) 723 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 724 else 725 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 726 727 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 728 } 729 730 /** 731 * i40e_validate_mac_addr - Validate unicast MAC address 732 * @mac_addr: pointer to MAC address 733 * 734 * Tests a MAC address to ensure it is a valid Individual Address 735 **/ 736 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 737 { 738 enum i40e_status_code status = I40E_SUCCESS; 739 740 DEBUGFUNC("i40e_validate_mac_addr"); 741 742 /* Broadcast addresses ARE multicast addresses 743 * Make sure it is not a multicast address 744 * Reject the zero address 745 */ 746 if (I40E_IS_MULTICAST(mac_addr) || 747 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 748 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 749 status = I40E_ERR_INVALID_MAC_ADDR; 750 751 return status; 752 } 753 754 /** 755 * i40e_get_media_type - Gets media type 756 * @hw: pointer to the hardware structure 757 **/ 758 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 759 { 760 enum i40e_media_type media; 761 762 switch (hw->phy.link_info.phy_type) { 763 case I40E_PHY_TYPE_10GBASE_SR: 764 case I40E_PHY_TYPE_10GBASE_LR: 765 case I40E_PHY_TYPE_1000BASE_SX: 766 case I40E_PHY_TYPE_1000BASE_LX: 767 case I40E_PHY_TYPE_40GBASE_SR4: 768 case I40E_PHY_TYPE_40GBASE_LR4: 769 media = I40E_MEDIA_TYPE_FIBER; 770 break; 771 case I40E_PHY_TYPE_100BASE_TX: 772 case I40E_PHY_TYPE_1000BASE_T: 773 case I40E_PHY_TYPE_10GBASE_T: 774 media = I40E_MEDIA_TYPE_BASET; 775 break; 776 case I40E_PHY_TYPE_10GBASE_CR1_CU: 777 case I40E_PHY_TYPE_40GBASE_CR4_CU: 778 case I40E_PHY_TYPE_10GBASE_CR1: 779 case I40E_PHY_TYPE_40GBASE_CR4: 780 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 781 media = I40E_MEDIA_TYPE_DA; 782 break; 783 case I40E_PHY_TYPE_1000BASE_KX: 784 case I40E_PHY_TYPE_10GBASE_KX4: 785 case I40E_PHY_TYPE_10GBASE_KR: 786 case I40E_PHY_TYPE_40GBASE_KR4: 787 media = I40E_MEDIA_TYPE_BACKPLANE; 788 break; 789 case I40E_PHY_TYPE_SGMII: 790 case I40E_PHY_TYPE_XAUI: 791 case I40E_PHY_TYPE_XFI: 792 case I40E_PHY_TYPE_XLAUI: 793 case I40E_PHY_TYPE_XLPPI: 794 default: 795 media = I40E_MEDIA_TYPE_UNKNOWN; 796 break; 797 } 798 799 return media; 800 } 801 802 #define I40E_PF_RESET_WAIT_COUNT 100 803 /** 804 * i40e_pf_reset - Reset the PF 805 * @hw: pointer to the hardware structure 806 * 807 * Assuming someone else has triggered a global reset, 808 * assure the global reset is complete and then reset the PF 809 **/ 810 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 811 { 812 u32 cnt = 0; 813 u32 cnt1 = 0; 814 u32 reg = 0; 815 u32 grst_del; 816 817 /* Poll for Global Reset steady state in case of recent GRST. 818 * The grst delay value is in 100ms units, and we'll wait a 819 * couple counts longer to be sure we don't just miss the end. 820 */ 821 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK 822 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 823 for (cnt = 0; cnt < grst_del + 2; cnt++) { 824 reg = rd32(hw, I40E_GLGEN_RSTAT); 825 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 826 break; 827 i40e_msec_delay(100); 828 } 829 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 830 DEBUGOUT("Global reset polling failed to complete.\n"); 831 return I40E_ERR_RESET_FAILED; 832 } 833 834 /* Now Wait for the FW to be ready */ 835 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 836 reg = rd32(hw, I40E_GLNVM_ULD); 837 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 838 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 839 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 840 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 841 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 842 break; 843 } 844 i40e_msec_delay(10); 845 } 846 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 847 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 848 DEBUGOUT("wait for FW Reset complete timedout\n"); 849 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 850 return I40E_ERR_RESET_FAILED; 851 } 852 853 /* If there was a Global Reset in progress when we got here, 854 * we don't need to do the PF Reset 855 */ 856 if (!cnt) { 857 reg = rd32(hw, I40E_PFGEN_CTRL); 858 wr32(hw, I40E_PFGEN_CTRL, 859 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 860 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 861 reg = rd32(hw, I40E_PFGEN_CTRL); 862 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 863 break; 864 i40e_msec_delay(1); 865 } 866 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 867 DEBUGOUT("PF reset polling failed to complete.\n"); 868 return I40E_ERR_RESET_FAILED; 869 } 870 } 871 872 i40e_clear_pxe_mode(hw); 873 874 875 return I40E_SUCCESS; 876 } 877 878 /** 879 * i40e_clear_hw - clear out any left over hw state 880 * @hw: pointer to the hw struct 881 * 882 * Clear queues and interrupts, typically called at init time, 883 * but after the capabilities have been found so we know how many 884 * queues and msix vectors have been allocated. 885 **/ 886 void i40e_clear_hw(struct i40e_hw *hw) 887 { 888 u32 num_queues, base_queue; 889 u32 num_pf_int; 890 u32 num_vf_int; 891 u32 num_vfs; 892 u32 i, j; 893 u32 val; 894 u32 eol = 0x7ff; 895 896 /* get number of interrupts, queues, and vfs */ 897 val = rd32(hw, I40E_GLPCI_CNF2); 898 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 899 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 900 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 901 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 902 903 val = rd32(hw, I40E_PFLAN_QALLOC); 904 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 905 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 906 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 907 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 908 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 909 num_queues = (j - base_queue) + 1; 910 else 911 num_queues = 0; 912 913 val = rd32(hw, I40E_PF_VT_PFALLOC); 914 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 915 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 916 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 917 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 918 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 919 num_vfs = (j - i) + 1; 920 else 921 num_vfs = 0; 922 923 /* stop all the interrupts */ 924 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 925 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 926 for (i = 0; i < num_pf_int - 2; i++) 927 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 928 929 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 930 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 931 wr32(hw, I40E_PFINT_LNKLST0, val); 932 for (i = 0; i < num_pf_int - 2; i++) 933 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 934 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 935 for (i = 0; i < num_vfs; i++) 936 wr32(hw, I40E_VPINT_LNKLST0(i), val); 937 for (i = 0; i < num_vf_int - 2; i++) 938 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 939 940 /* warn the HW of the coming Tx disables */ 941 for (i = 0; i < num_queues; i++) { 942 u32 abs_queue_idx = base_queue + i; 943 u32 reg_block = 0; 944 945 if (abs_queue_idx >= 128) { 946 reg_block = abs_queue_idx / 128; 947 abs_queue_idx %= 128; 948 } 949 950 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 951 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 952 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 953 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 954 955 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 956 } 957 i40e_usec_delay(400); 958 959 /* stop all the queues */ 960 for (i = 0; i < num_queues; i++) { 961 wr32(hw, I40E_QINT_TQCTL(i), 0); 962 wr32(hw, I40E_QTX_ENA(i), 0); 963 wr32(hw, I40E_QINT_RQCTL(i), 0); 964 wr32(hw, I40E_QRX_ENA(i), 0); 965 } 966 967 /* short wait for all queue disables to settle */ 968 i40e_usec_delay(50); 969 } 970 971 /** 972 * i40e_clear_pxe_mode - clear pxe operations mode 973 * @hw: pointer to the hw struct 974 * 975 * Make sure all PXE mode settings are cleared, including things 976 * like descriptor fetch/write-back mode. 977 **/ 978 void i40e_clear_pxe_mode(struct i40e_hw *hw) 979 { 980 if (i40e_check_asq_alive(hw)) 981 i40e_aq_clear_pxe_mode(hw, NULL); 982 } 983 984 /** 985 * i40e_led_is_mine - helper to find matching led 986 * @hw: pointer to the hw struct 987 * @idx: index into GPIO registers 988 * 989 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 990 */ 991 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 992 { 993 u32 gpio_val = 0; 994 u32 port; 995 996 if (!hw->func_caps.led[idx]) 997 return 0; 998 999 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1000 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1001 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1002 1003 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1004 * if it is not our port then ignore 1005 */ 1006 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1007 (port != hw->port)) 1008 return 0; 1009 1010 return gpio_val; 1011 } 1012 1013 #define I40E_LED0 22 1014 #define I40E_LINK_ACTIVITY 0xC 1015 1016 /** 1017 * i40e_led_get - return current on/off mode 1018 * @hw: pointer to the hw struct 1019 * 1020 * The value returned is the 'mode' field as defined in the 1021 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1022 * values are variations of possible behaviors relating to 1023 * blink, link, and wire. 1024 **/ 1025 u32 i40e_led_get(struct i40e_hw *hw) 1026 { 1027 u32 mode = 0; 1028 int i; 1029 1030 /* as per the documentation GPIO 22-29 are the LED 1031 * GPIO pins named LED0..LED7 1032 */ 1033 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1034 u32 gpio_val = i40e_led_is_mine(hw, i); 1035 1036 if (!gpio_val) 1037 continue; 1038 1039 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1040 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1041 break; 1042 } 1043 1044 return mode; 1045 } 1046 1047 /** 1048 * i40e_led_set - set new on/off mode 1049 * @hw: pointer to the hw struct 1050 * @mode: 0=off, 0xf=on (else see manual for mode details) 1051 * @blink: TRUE if the LED should blink when on, FALSE if steady 1052 * 1053 * if this function is used to turn on the blink it should 1054 * be used to disable the blink when restoring the original state. 1055 **/ 1056 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1057 { 1058 int i; 1059 1060 if (mode & 0xfffffff0) 1061 DEBUGOUT1("invalid mode passed in %X\n", mode); 1062 1063 /* as per the documentation GPIO 22-29 are the LED 1064 * GPIO pins named LED0..LED7 1065 */ 1066 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1067 u32 gpio_val = i40e_led_is_mine(hw, i); 1068 1069 if (!gpio_val) 1070 continue; 1071 1072 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1073 /* this & is a bit of paranoia, but serves as a range check */ 1074 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1075 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1076 1077 if (mode == I40E_LINK_ACTIVITY) 1078 blink = FALSE; 1079 1080 gpio_val |= (blink ? 1 : 0) << 1081 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT; 1082 1083 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1084 break; 1085 } 1086 } 1087 1088 /* Admin command wrappers */ 1089 1090 /** 1091 * i40e_aq_get_phy_capabilities 1092 * @hw: pointer to the hw struct 1093 * @abilities: structure for PHY capabilities to be filled 1094 * @qualified_modules: report Qualified Modules 1095 * @report_init: report init capabilities (active are default) 1096 * @cmd_details: pointer to command details structure or NULL 1097 * 1098 * Returns the various PHY abilities supported on the Port. 1099 **/ 1100 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1101 bool qualified_modules, bool report_init, 1102 struct i40e_aq_get_phy_abilities_resp *abilities, 1103 struct i40e_asq_cmd_details *cmd_details) 1104 { 1105 struct i40e_aq_desc desc; 1106 enum i40e_status_code status; 1107 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1108 1109 if (!abilities) 1110 return I40E_ERR_PARAM; 1111 1112 i40e_fill_default_direct_cmd_desc(&desc, 1113 i40e_aqc_opc_get_phy_abilities); 1114 1115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1116 if (abilities_size > I40E_AQ_LARGE_BUF) 1117 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1118 1119 if (qualified_modules) 1120 desc.params.external.param0 |= 1121 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1122 1123 if (report_init) 1124 desc.params.external.param0 |= 1125 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1126 1127 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1128 cmd_details); 1129 1130 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1131 status = I40E_ERR_UNKNOWN_PHY; 1132 1133 return status; 1134 } 1135 1136 /** 1137 * i40e_aq_set_phy_config 1138 * @hw: pointer to the hw struct 1139 * @config: structure with PHY configuration to be set 1140 * @cmd_details: pointer to command details structure or NULL 1141 * 1142 * Set the various PHY configuration parameters 1143 * supported on the Port.One or more of the Set PHY config parameters may be 1144 * ignored in an MFP mode as the PF may not have the privilege to set some 1145 * of the PHY Config parameters. This status will be indicated by the 1146 * command response. 1147 **/ 1148 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1149 struct i40e_aq_set_phy_config *config, 1150 struct i40e_asq_cmd_details *cmd_details) 1151 { 1152 struct i40e_aq_desc desc; 1153 struct i40e_aq_set_phy_config *cmd = 1154 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1155 enum i40e_status_code status; 1156 1157 if (!config) 1158 return I40E_ERR_PARAM; 1159 1160 i40e_fill_default_direct_cmd_desc(&desc, 1161 i40e_aqc_opc_set_phy_config); 1162 1163 *cmd = *config; 1164 1165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1166 1167 return status; 1168 } 1169 1170 /** 1171 * i40e_set_fc 1172 * @hw: pointer to the hw struct 1173 * 1174 * Set the requested flow control mode using set_phy_config. 1175 **/ 1176 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1177 bool atomic_restart) 1178 { 1179 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1180 struct i40e_aq_get_phy_abilities_resp abilities; 1181 struct i40e_aq_set_phy_config config; 1182 enum i40e_status_code status; 1183 u8 pause_mask = 0x0; 1184 1185 *aq_failures = 0x0; 1186 1187 switch (fc_mode) { 1188 case I40E_FC_FULL: 1189 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1190 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1191 break; 1192 case I40E_FC_RX_PAUSE: 1193 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1194 break; 1195 case I40E_FC_TX_PAUSE: 1196 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1197 break; 1198 default: 1199 break; 1200 } 1201 1202 /* Get the current phy config */ 1203 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1204 NULL); 1205 if (status) { 1206 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1207 return status; 1208 } 1209 1210 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1211 /* clear the old pause settings */ 1212 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1213 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1214 /* set the new abilities */ 1215 config.abilities |= pause_mask; 1216 /* If the abilities have changed, then set the new config */ 1217 if (config.abilities != abilities.abilities) { 1218 /* Auto restart link so settings take effect */ 1219 if (atomic_restart) 1220 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1221 /* Copy over all the old settings */ 1222 config.phy_type = abilities.phy_type; 1223 config.link_speed = abilities.link_speed; 1224 config.eee_capability = abilities.eee_capability; 1225 config.eeer = abilities.eeer_val; 1226 config.low_power_ctrl = abilities.d3_lpan; 1227 status = i40e_aq_set_phy_config(hw, &config, NULL); 1228 1229 if (status) 1230 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1231 } 1232 /* Update the link info */ 1233 status = i40e_update_link_info(hw, TRUE); 1234 if (status) { 1235 /* Wait a little bit (on 40G cards it sometimes takes a really 1236 * long time for link to come back from the atomic reset) 1237 * and try once more 1238 */ 1239 i40e_msec_delay(1000); 1240 status = i40e_update_link_info(hw, TRUE); 1241 } 1242 if (status) 1243 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1244 1245 return status; 1246 } 1247 1248 /** 1249 * i40e_aq_set_mac_config 1250 * @hw: pointer to the hw struct 1251 * @max_frame_size: Maximum Frame Size to be supported by the port 1252 * @crc_en: Tell HW to append a CRC to outgoing frames 1253 * @pacing: Pacing configurations 1254 * @cmd_details: pointer to command details structure or NULL 1255 * 1256 * Configure MAC settings for frame size, jumbo frame support and the 1257 * addition of a CRC by the hardware. 1258 **/ 1259 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1260 u16 max_frame_size, 1261 bool crc_en, u16 pacing, 1262 struct i40e_asq_cmd_details *cmd_details) 1263 { 1264 struct i40e_aq_desc desc; 1265 struct i40e_aq_set_mac_config *cmd = 1266 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1267 enum i40e_status_code status; 1268 1269 if (max_frame_size == 0) 1270 return I40E_ERR_PARAM; 1271 1272 i40e_fill_default_direct_cmd_desc(&desc, 1273 i40e_aqc_opc_set_mac_config); 1274 1275 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1276 cmd->params = ((u8)pacing & 0x0F) << 3; 1277 if (crc_en) 1278 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1279 1280 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1281 1282 return status; 1283 } 1284 1285 /** 1286 * i40e_aq_clear_pxe_mode 1287 * @hw: pointer to the hw struct 1288 * @cmd_details: pointer to command details structure or NULL 1289 * 1290 * Tell the firmware that the driver is taking over from PXE 1291 **/ 1292 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1293 struct i40e_asq_cmd_details *cmd_details) 1294 { 1295 enum i40e_status_code status; 1296 struct i40e_aq_desc desc; 1297 struct i40e_aqc_clear_pxe *cmd = 1298 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1299 1300 i40e_fill_default_direct_cmd_desc(&desc, 1301 i40e_aqc_opc_clear_pxe_mode); 1302 1303 cmd->rx_cnt = 0x2; 1304 1305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1306 1307 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1308 1309 return status; 1310 } 1311 1312 /** 1313 * i40e_aq_set_link_restart_an 1314 * @hw: pointer to the hw struct 1315 * @enable_link: if TRUE: enable link, if FALSE: disable link 1316 * @cmd_details: pointer to command details structure or NULL 1317 * 1318 * Sets up the link and restarts the Auto-Negotiation over the link. 1319 **/ 1320 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1321 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1322 { 1323 struct i40e_aq_desc desc; 1324 struct i40e_aqc_set_link_restart_an *cmd = 1325 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1326 enum i40e_status_code status; 1327 1328 i40e_fill_default_direct_cmd_desc(&desc, 1329 i40e_aqc_opc_set_link_restart_an); 1330 1331 cmd->command = I40E_AQ_PHY_RESTART_AN; 1332 if (enable_link) 1333 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1334 else 1335 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1336 1337 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1338 1339 return status; 1340 } 1341 1342 /** 1343 * i40e_aq_get_link_info 1344 * @hw: pointer to the hw struct 1345 * @enable_lse: enable/disable LinkStatusEvent reporting 1346 * @link: pointer to link status structure - optional 1347 * @cmd_details: pointer to command details structure or NULL 1348 * 1349 * Returns the link status of the adapter. 1350 **/ 1351 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1352 bool enable_lse, struct i40e_link_status *link, 1353 struct i40e_asq_cmd_details *cmd_details) 1354 { 1355 struct i40e_aq_desc desc; 1356 struct i40e_aqc_get_link_status *resp = 1357 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1358 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1359 enum i40e_status_code status; 1360 bool tx_pause, rx_pause; 1361 u16 command_flags; 1362 1363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1364 1365 if (enable_lse) 1366 command_flags = I40E_AQ_LSE_ENABLE; 1367 else 1368 command_flags = I40E_AQ_LSE_DISABLE; 1369 resp->command_flags = CPU_TO_LE16(command_flags); 1370 1371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1372 1373 if (status != I40E_SUCCESS) 1374 goto aq_get_link_info_exit; 1375 1376 /* save off old link status information */ 1377 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1378 sizeof(struct i40e_link_status), I40E_NONDMA_TO_NONDMA); 1379 1380 /* update link status */ 1381 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1382 hw->phy.media_type = i40e_get_media_type(hw); 1383 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1384 hw_link_info->link_info = resp->link_info; 1385 hw_link_info->an_info = resp->an_info; 1386 hw_link_info->ext_info = resp->ext_info; 1387 hw_link_info->loopback = resp->loopback; 1388 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1389 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1390 1391 /* update fc info */ 1392 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1393 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1394 if (tx_pause & rx_pause) 1395 hw->fc.current_mode = I40E_FC_FULL; 1396 else if (tx_pause) 1397 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1398 else if (rx_pause) 1399 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1400 else 1401 hw->fc.current_mode = I40E_FC_NONE; 1402 1403 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1404 hw_link_info->crc_enable = TRUE; 1405 else 1406 hw_link_info->crc_enable = FALSE; 1407 1408 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE)) 1409 hw_link_info->lse_enable = TRUE; 1410 else 1411 hw_link_info->lse_enable = FALSE; 1412 1413 /* save link status information */ 1414 if (link) 1415 i40e_memcpy(link, hw_link_info, sizeof(struct i40e_link_status), 1416 I40E_NONDMA_TO_NONDMA); 1417 1418 /* flag cleared so helper functions don't call AQ again */ 1419 hw->phy.get_link_info = FALSE; 1420 1421 aq_get_link_info_exit: 1422 return status; 1423 } 1424 1425 /** 1426 * i40e_update_link_info 1427 * @hw: pointer to the hw struct 1428 * @enable_lse: enable/disable LinkStatusEvent reporting 1429 * 1430 * Returns the link status of the adapter 1431 **/ 1432 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw, 1433 bool enable_lse) 1434 { 1435 struct i40e_aq_get_phy_abilities_resp abilities; 1436 enum i40e_status_code status; 1437 1438 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL); 1439 if (status) 1440 return status; 1441 1442 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 1443 &abilities, NULL); 1444 if (status) 1445 return status; 1446 1447 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED) 1448 hw->phy.link_info.an_enabled = TRUE; 1449 else 1450 hw->phy.link_info.an_enabled = FALSE; 1451 1452 return status; 1453 } 1454 1455 /** 1456 * i40e_aq_set_phy_int_mask 1457 * @hw: pointer to the hw struct 1458 * @mask: interrupt mask to be set 1459 * @cmd_details: pointer to command details structure or NULL 1460 * 1461 * Set link interrupt mask. 1462 **/ 1463 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1464 u16 mask, 1465 struct i40e_asq_cmd_details *cmd_details) 1466 { 1467 struct i40e_aq_desc desc; 1468 struct i40e_aqc_set_phy_int_mask *cmd = 1469 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1470 enum i40e_status_code status; 1471 1472 i40e_fill_default_direct_cmd_desc(&desc, 1473 i40e_aqc_opc_set_phy_int_mask); 1474 1475 cmd->event_mask = CPU_TO_LE16(mask); 1476 1477 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1478 1479 return status; 1480 } 1481 1482 /** 1483 * i40e_aq_get_local_advt_reg 1484 * @hw: pointer to the hw struct 1485 * @advt_reg: local AN advertisement register value 1486 * @cmd_details: pointer to command details structure or NULL 1487 * 1488 * Get the Local AN advertisement register value. 1489 **/ 1490 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1491 u64 *advt_reg, 1492 struct i40e_asq_cmd_details *cmd_details) 1493 { 1494 struct i40e_aq_desc desc; 1495 struct i40e_aqc_an_advt_reg *resp = 1496 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1497 enum i40e_status_code status; 1498 1499 i40e_fill_default_direct_cmd_desc(&desc, 1500 i40e_aqc_opc_get_local_advt_reg); 1501 1502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1503 1504 if (status != I40E_SUCCESS) 1505 goto aq_get_local_advt_reg_exit; 1506 1507 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1508 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1509 1510 aq_get_local_advt_reg_exit: 1511 return status; 1512 } 1513 1514 /** 1515 * i40e_aq_set_local_advt_reg 1516 * @hw: pointer to the hw struct 1517 * @advt_reg: local AN advertisement register value 1518 * @cmd_details: pointer to command details structure or NULL 1519 * 1520 * Get the Local AN advertisement register value. 1521 **/ 1522 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 1523 u64 advt_reg, 1524 struct i40e_asq_cmd_details *cmd_details) 1525 { 1526 struct i40e_aq_desc desc; 1527 struct i40e_aqc_an_advt_reg *cmd = 1528 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1529 enum i40e_status_code status; 1530 1531 i40e_fill_default_direct_cmd_desc(&desc, 1532 i40e_aqc_opc_get_local_advt_reg); 1533 1534 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 1535 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 1536 1537 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1538 1539 return status; 1540 } 1541 1542 /** 1543 * i40e_aq_get_partner_advt 1544 * @hw: pointer to the hw struct 1545 * @advt_reg: AN partner advertisement register value 1546 * @cmd_details: pointer to command details structure or NULL 1547 * 1548 * Get the link partner AN advertisement register value. 1549 **/ 1550 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 1551 u64 *advt_reg, 1552 struct i40e_asq_cmd_details *cmd_details) 1553 { 1554 struct i40e_aq_desc desc; 1555 struct i40e_aqc_an_advt_reg *resp = 1556 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1557 enum i40e_status_code status; 1558 1559 i40e_fill_default_direct_cmd_desc(&desc, 1560 i40e_aqc_opc_get_partner_advt); 1561 1562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1563 1564 if (status != I40E_SUCCESS) 1565 goto aq_get_partner_advt_exit; 1566 1567 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1568 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1569 1570 aq_get_partner_advt_exit: 1571 return status; 1572 } 1573 1574 /** 1575 * i40e_aq_set_lb_modes 1576 * @hw: pointer to the hw struct 1577 * @lb_modes: loopback mode to be set 1578 * @cmd_details: pointer to command details structure or NULL 1579 * 1580 * Sets loopback modes. 1581 **/ 1582 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 1583 u16 lb_modes, 1584 struct i40e_asq_cmd_details *cmd_details) 1585 { 1586 struct i40e_aq_desc desc; 1587 struct i40e_aqc_set_lb_mode *cmd = 1588 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 1589 enum i40e_status_code status; 1590 1591 i40e_fill_default_direct_cmd_desc(&desc, 1592 i40e_aqc_opc_set_lb_modes); 1593 1594 cmd->lb_mode = CPU_TO_LE16(lb_modes); 1595 1596 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1597 1598 return status; 1599 } 1600 1601 /** 1602 * i40e_aq_set_phy_debug 1603 * @hw: pointer to the hw struct 1604 * @cmd_flags: debug command flags 1605 * @cmd_details: pointer to command details structure or NULL 1606 * 1607 * Reset the external PHY. 1608 **/ 1609 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1610 struct i40e_asq_cmd_details *cmd_details) 1611 { 1612 struct i40e_aq_desc desc; 1613 struct i40e_aqc_set_phy_debug *cmd = 1614 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1615 enum i40e_status_code status; 1616 1617 i40e_fill_default_direct_cmd_desc(&desc, 1618 i40e_aqc_opc_set_phy_debug); 1619 1620 cmd->command_flags = cmd_flags; 1621 1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1623 1624 return status; 1625 } 1626 1627 /** 1628 * i40e_aq_add_vsi 1629 * @hw: pointer to the hw struct 1630 * @vsi_ctx: pointer to a vsi context struct 1631 * @cmd_details: pointer to command details structure or NULL 1632 * 1633 * Add a VSI context to the hardware. 1634 **/ 1635 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 1636 struct i40e_vsi_context *vsi_ctx, 1637 struct i40e_asq_cmd_details *cmd_details) 1638 { 1639 struct i40e_aq_desc desc; 1640 struct i40e_aqc_add_get_update_vsi *cmd = 1641 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1642 struct i40e_aqc_add_get_update_vsi_completion *resp = 1643 (struct i40e_aqc_add_get_update_vsi_completion *) 1644 &desc.params.raw; 1645 enum i40e_status_code status; 1646 1647 i40e_fill_default_direct_cmd_desc(&desc, 1648 i40e_aqc_opc_add_vsi); 1649 1650 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 1651 cmd->connection_type = vsi_ctx->connection_type; 1652 cmd->vf_id = vsi_ctx->vf_num; 1653 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 1654 1655 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1656 1657 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1658 sizeof(vsi_ctx->info), cmd_details); 1659 1660 if (status != I40E_SUCCESS) 1661 goto aq_add_vsi_exit; 1662 1663 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 1664 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 1665 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 1666 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 1667 1668 aq_add_vsi_exit: 1669 return status; 1670 } 1671 1672 /** 1673 * i40e_aq_set_default_vsi 1674 * @hw: pointer to the hw struct 1675 * @seid: vsi number 1676 * @cmd_details: pointer to command details structure or NULL 1677 **/ 1678 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 1679 u16 seid, 1680 struct i40e_asq_cmd_details *cmd_details) 1681 { 1682 struct i40e_aq_desc desc; 1683 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1684 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1685 &desc.params.raw; 1686 enum i40e_status_code status; 1687 1688 i40e_fill_default_direct_cmd_desc(&desc, 1689 i40e_aqc_opc_set_vsi_promiscuous_modes); 1690 1691 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1692 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1693 cmd->seid = CPU_TO_LE16(seid); 1694 1695 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1696 1697 return status; 1698 } 1699 1700 /** 1701 * i40e_aq_set_vsi_unicast_promiscuous 1702 * @hw: pointer to the hw struct 1703 * @seid: vsi number 1704 * @set: set unicast promiscuous enable/disable 1705 * @cmd_details: pointer to command details structure or NULL 1706 **/ 1707 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1708 u16 seid, bool set, 1709 struct i40e_asq_cmd_details *cmd_details) 1710 { 1711 struct i40e_aq_desc desc; 1712 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1713 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1714 enum i40e_status_code status; 1715 u16 flags = 0; 1716 1717 i40e_fill_default_direct_cmd_desc(&desc, 1718 i40e_aqc_opc_set_vsi_promiscuous_modes); 1719 1720 if (set) 1721 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1722 1723 cmd->promiscuous_flags = CPU_TO_LE16(flags); 1724 1725 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1726 1727 cmd->seid = CPU_TO_LE16(seid); 1728 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1729 1730 return status; 1731 } 1732 1733 /** 1734 * i40e_aq_set_vsi_multicast_promiscuous 1735 * @hw: pointer to the hw struct 1736 * @seid: vsi number 1737 * @set: set multicast promiscuous enable/disable 1738 * @cmd_details: pointer to command details structure or NULL 1739 **/ 1740 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1741 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 1742 { 1743 struct i40e_aq_desc desc; 1744 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1745 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1746 enum i40e_status_code status; 1747 u16 flags = 0; 1748 1749 i40e_fill_default_direct_cmd_desc(&desc, 1750 i40e_aqc_opc_set_vsi_promiscuous_modes); 1751 1752 if (set) 1753 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1754 1755 cmd->promiscuous_flags = CPU_TO_LE16(flags); 1756 1757 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1758 1759 cmd->seid = CPU_TO_LE16(seid); 1760 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1761 1762 return status; 1763 } 1764 1765 /** 1766 * i40e_aq_set_vsi_broadcast 1767 * @hw: pointer to the hw struct 1768 * @seid: vsi number 1769 * @set_filter: TRUE to set filter, FALSE to clear filter 1770 * @cmd_details: pointer to command details structure or NULL 1771 * 1772 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1773 **/ 1774 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1775 u16 seid, bool set_filter, 1776 struct i40e_asq_cmd_details *cmd_details) 1777 { 1778 struct i40e_aq_desc desc; 1779 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1780 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1781 enum i40e_status_code status; 1782 1783 i40e_fill_default_direct_cmd_desc(&desc, 1784 i40e_aqc_opc_set_vsi_promiscuous_modes); 1785 1786 if (set_filter) 1787 cmd->promiscuous_flags 1788 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1789 else 1790 cmd->promiscuous_flags 1791 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1792 1793 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1794 cmd->seid = CPU_TO_LE16(seid); 1795 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1796 1797 return status; 1798 } 1799 1800 /** 1801 * i40e_get_vsi_params - get VSI configuration info 1802 * @hw: pointer to the hw struct 1803 * @vsi_ctx: pointer to a vsi context struct 1804 * @cmd_details: pointer to command details structure or NULL 1805 **/ 1806 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 1807 struct i40e_vsi_context *vsi_ctx, 1808 struct i40e_asq_cmd_details *cmd_details) 1809 { 1810 struct i40e_aq_desc desc; 1811 struct i40e_aqc_add_get_update_vsi *cmd = 1812 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1813 struct i40e_aqc_add_get_update_vsi_completion *resp = 1814 (struct i40e_aqc_add_get_update_vsi_completion *) 1815 &desc.params.raw; 1816 enum i40e_status_code status; 1817 1818 i40e_fill_default_direct_cmd_desc(&desc, 1819 i40e_aqc_opc_get_vsi_parameters); 1820 1821 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 1822 1823 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1824 1825 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1826 sizeof(vsi_ctx->info), NULL); 1827 1828 if (status != I40E_SUCCESS) 1829 goto aq_get_vsi_params_exit; 1830 1831 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 1832 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 1833 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 1834 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 1835 1836 aq_get_vsi_params_exit: 1837 return status; 1838 } 1839 1840 /** 1841 * i40e_aq_update_vsi_params 1842 * @hw: pointer to the hw struct 1843 * @vsi_ctx: pointer to a vsi context struct 1844 * @cmd_details: pointer to command details structure or NULL 1845 * 1846 * Update a VSI context. 1847 **/ 1848 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 1849 struct i40e_vsi_context *vsi_ctx, 1850 struct i40e_asq_cmd_details *cmd_details) 1851 { 1852 struct i40e_aq_desc desc; 1853 struct i40e_aqc_add_get_update_vsi *cmd = 1854 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1855 enum i40e_status_code status; 1856 1857 i40e_fill_default_direct_cmd_desc(&desc, 1858 i40e_aqc_opc_update_vsi_parameters); 1859 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 1860 1861 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1862 1863 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1864 sizeof(vsi_ctx->info), cmd_details); 1865 1866 return status; 1867 } 1868 1869 /** 1870 * i40e_aq_get_switch_config 1871 * @hw: pointer to the hardware structure 1872 * @buf: pointer to the result buffer 1873 * @buf_size: length of input buffer 1874 * @start_seid: seid to start for the report, 0 == beginning 1875 * @cmd_details: pointer to command details structure or NULL 1876 * 1877 * Fill the buf with switch configuration returned from AdminQ command 1878 **/ 1879 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 1880 struct i40e_aqc_get_switch_config_resp *buf, 1881 u16 buf_size, u16 *start_seid, 1882 struct i40e_asq_cmd_details *cmd_details) 1883 { 1884 struct i40e_aq_desc desc; 1885 struct i40e_aqc_switch_seid *scfg = 1886 (struct i40e_aqc_switch_seid *)&desc.params.raw; 1887 enum i40e_status_code status; 1888 1889 i40e_fill_default_direct_cmd_desc(&desc, 1890 i40e_aqc_opc_get_switch_config); 1891 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1892 if (buf_size > I40E_AQ_LARGE_BUF) 1893 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1894 scfg->seid = CPU_TO_LE16(*start_seid); 1895 1896 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1897 *start_seid = LE16_TO_CPU(scfg->seid); 1898 1899 return status; 1900 } 1901 1902 /** 1903 * i40e_aq_get_firmware_version 1904 * @hw: pointer to the hw struct 1905 * @fw_major_version: firmware major version 1906 * @fw_minor_version: firmware minor version 1907 * @api_major_version: major queue version 1908 * @api_minor_version: minor queue version 1909 * @cmd_details: pointer to command details structure or NULL 1910 * 1911 * Get the firmware version from the admin queue commands 1912 **/ 1913 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 1914 u16 *fw_major_version, u16 *fw_minor_version, 1915 u16 *api_major_version, u16 *api_minor_version, 1916 struct i40e_asq_cmd_details *cmd_details) 1917 { 1918 struct i40e_aq_desc desc; 1919 struct i40e_aqc_get_version *resp = 1920 (struct i40e_aqc_get_version *)&desc.params.raw; 1921 enum i40e_status_code status; 1922 1923 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1924 1925 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1926 1927 if (status == I40E_SUCCESS) { 1928 if (fw_major_version != NULL) 1929 *fw_major_version = LE16_TO_CPU(resp->fw_major); 1930 if (fw_minor_version != NULL) 1931 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 1932 if (api_major_version != NULL) 1933 *api_major_version = LE16_TO_CPU(resp->api_major); 1934 if (api_minor_version != NULL) 1935 *api_minor_version = LE16_TO_CPU(resp->api_minor); 1936 1937 /* A workaround to fix the API version in SW */ 1938 if (api_major_version && api_minor_version && 1939 fw_major_version && fw_minor_version && 1940 ((*api_major_version == 1) && (*api_minor_version == 1)) && 1941 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 1942 (*fw_major_version > 4))) 1943 *api_minor_version = 2; 1944 } 1945 1946 return status; 1947 } 1948 1949 /** 1950 * i40e_aq_send_driver_version 1951 * @hw: pointer to the hw struct 1952 * @dv: driver's major, minor version 1953 * @cmd_details: pointer to command details structure or NULL 1954 * 1955 * Send the driver version to the firmware 1956 **/ 1957 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 1958 struct i40e_driver_version *dv, 1959 struct i40e_asq_cmd_details *cmd_details) 1960 { 1961 struct i40e_aq_desc desc; 1962 struct i40e_aqc_driver_version *cmd = 1963 (struct i40e_aqc_driver_version *)&desc.params.raw; 1964 enum i40e_status_code status; 1965 u16 len; 1966 1967 if (dv == NULL) 1968 return I40E_ERR_PARAM; 1969 1970 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 1971 1972 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_SI); 1973 cmd->driver_major_ver = dv->major_version; 1974 cmd->driver_minor_ver = dv->minor_version; 1975 cmd->driver_build_ver = dv->build_version; 1976 cmd->driver_subbuild_ver = dv->subbuild_version; 1977 1978 len = 0; 1979 while (len < sizeof(dv->driver_string) && 1980 (dv->driver_string[len] < 0x80) && 1981 dv->driver_string[len]) 1982 len++; 1983 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 1984 len, cmd_details); 1985 1986 return status; 1987 } 1988 1989 /** 1990 * i40e_get_link_status - get status of the HW network link 1991 * @hw: pointer to the hw struct 1992 * 1993 * Returns TRUE if link is up, FALSE if link is down. 1994 * 1995 * Side effect: LinkStatusEvent reporting becomes enabled 1996 **/ 1997 bool i40e_get_link_status(struct i40e_hw *hw) 1998 { 1999 enum i40e_status_code status = I40E_SUCCESS; 2000 bool link_status = FALSE; 2001 2002 if (hw->phy.get_link_info) { 2003 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2004 2005 if (status != I40E_SUCCESS) 2006 goto i40e_get_link_status_exit; 2007 } 2008 2009 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2010 2011 i40e_get_link_status_exit: 2012 return link_status; 2013 } 2014 2015 /** 2016 * i40e_get_link_speed 2017 * @hw: pointer to the hw struct 2018 * 2019 * Returns the link speed of the adapter. 2020 **/ 2021 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2022 { 2023 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2024 enum i40e_status_code status = I40E_SUCCESS; 2025 2026 if (hw->phy.get_link_info) { 2027 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2028 2029 if (status != I40E_SUCCESS) 2030 goto i40e_link_speed_exit; 2031 } 2032 2033 speed = hw->phy.link_info.link_speed; 2034 2035 i40e_link_speed_exit: 2036 return speed; 2037 } 2038 2039 /** 2040 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2041 * @hw: pointer to the hw struct 2042 * @uplink_seid: the MAC or other gizmo SEID 2043 * @downlink_seid: the VSI SEID 2044 * @enabled_tc: bitmap of TCs to be enabled 2045 * @default_port: TRUE for default port VSI, FALSE for control port 2046 * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support 2047 * @veb_seid: pointer to where to put the resulting VEB SEID 2048 * @cmd_details: pointer to command details structure or NULL 2049 * 2050 * This asks the FW to add a VEB between the uplink and downlink 2051 * elements. If the uplink SEID is 0, this will be a floating VEB. 2052 **/ 2053 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2054 u16 downlink_seid, u8 enabled_tc, 2055 bool default_port, bool enable_l2_filtering, 2056 u16 *veb_seid, 2057 struct i40e_asq_cmd_details *cmd_details) 2058 { 2059 struct i40e_aq_desc desc; 2060 struct i40e_aqc_add_veb *cmd = 2061 (struct i40e_aqc_add_veb *)&desc.params.raw; 2062 struct i40e_aqc_add_veb_completion *resp = 2063 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2064 enum i40e_status_code status; 2065 u16 veb_flags = 0; 2066 2067 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2068 if (!!uplink_seid != !!downlink_seid) 2069 return I40E_ERR_PARAM; 2070 2071 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2072 2073 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2074 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2075 cmd->enable_tcs = enabled_tc; 2076 if (!uplink_seid) 2077 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2078 if (default_port) 2079 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2080 else 2081 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2082 2083 if (enable_l2_filtering) 2084 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 2085 2086 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2087 2088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2089 2090 if (!status && veb_seid) 2091 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2092 2093 return status; 2094 } 2095 2096 /** 2097 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2098 * @hw: pointer to the hw struct 2099 * @veb_seid: the SEID of the VEB to query 2100 * @switch_id: the uplink switch id 2101 * @floating: set to TRUE if the VEB is floating 2102 * @statistic_index: index of the stats counter block for this VEB 2103 * @vebs_used: number of VEB's used by function 2104 * @vebs_free: total VEB's not reserved by any function 2105 * @cmd_details: pointer to command details structure or NULL 2106 * 2107 * This retrieves the parameters for a particular VEB, specified by 2108 * uplink_seid, and returns them to the caller. 2109 **/ 2110 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2111 u16 veb_seid, u16 *switch_id, 2112 bool *floating, u16 *statistic_index, 2113 u16 *vebs_used, u16 *vebs_free, 2114 struct i40e_asq_cmd_details *cmd_details) 2115 { 2116 struct i40e_aq_desc desc; 2117 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2118 (struct i40e_aqc_get_veb_parameters_completion *) 2119 &desc.params.raw; 2120 enum i40e_status_code status; 2121 2122 if (veb_seid == 0) 2123 return I40E_ERR_PARAM; 2124 2125 i40e_fill_default_direct_cmd_desc(&desc, 2126 i40e_aqc_opc_get_veb_parameters); 2127 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2128 2129 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2130 if (status) 2131 goto get_veb_exit; 2132 2133 if (switch_id) 2134 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2135 if (statistic_index) 2136 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2137 if (vebs_used) 2138 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2139 if (vebs_free) 2140 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2141 if (floating) { 2142 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2143 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2144 *floating = TRUE; 2145 else 2146 *floating = FALSE; 2147 } 2148 2149 get_veb_exit: 2150 return status; 2151 } 2152 2153 /** 2154 * i40e_aq_add_macvlan 2155 * @hw: pointer to the hw struct 2156 * @seid: VSI for the mac address 2157 * @mv_list: list of macvlans to be added 2158 * @count: length of the list 2159 * @cmd_details: pointer to command details structure or NULL 2160 * 2161 * Add MAC/VLAN addresses to the HW filtering 2162 **/ 2163 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2164 struct i40e_aqc_add_macvlan_element_data *mv_list, 2165 u16 count, struct i40e_asq_cmd_details *cmd_details) 2166 { 2167 struct i40e_aq_desc desc; 2168 struct i40e_aqc_macvlan *cmd = 2169 (struct i40e_aqc_macvlan *)&desc.params.raw; 2170 enum i40e_status_code status; 2171 u16 buf_size; 2172 2173 if (count == 0 || !mv_list || !hw) 2174 return I40E_ERR_PARAM; 2175 2176 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data); 2177 2178 /* prep the rest of the request */ 2179 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2180 cmd->num_addresses = CPU_TO_LE16(count); 2181 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2182 cmd->seid[1] = 0; 2183 cmd->seid[2] = 0; 2184 2185 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2186 if (buf_size > I40E_AQ_LARGE_BUF) 2187 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2188 2189 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2190 cmd_details); 2191 2192 return status; 2193 } 2194 2195 /** 2196 * i40e_aq_remove_macvlan 2197 * @hw: pointer to the hw struct 2198 * @seid: VSI for the mac address 2199 * @mv_list: list of macvlans to be removed 2200 * @count: length of the list 2201 * @cmd_details: pointer to command details structure or NULL 2202 * 2203 * Remove MAC/VLAN addresses from the HW filtering 2204 **/ 2205 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2206 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2207 u16 count, struct i40e_asq_cmd_details *cmd_details) 2208 { 2209 struct i40e_aq_desc desc; 2210 struct i40e_aqc_macvlan *cmd = 2211 (struct i40e_aqc_macvlan *)&desc.params.raw; 2212 enum i40e_status_code status; 2213 u16 buf_size; 2214 2215 if (count == 0 || !mv_list || !hw) 2216 return I40E_ERR_PARAM; 2217 2218 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data); 2219 2220 /* prep the rest of the request */ 2221 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2222 cmd->num_addresses = CPU_TO_LE16(count); 2223 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2224 cmd->seid[1] = 0; 2225 cmd->seid[2] = 0; 2226 2227 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2228 if (buf_size > I40E_AQ_LARGE_BUF) 2229 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2230 2231 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2232 cmd_details); 2233 2234 return status; 2235 } 2236 2237 /** 2238 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 2239 * @hw: pointer to the hw struct 2240 * @seid: VSI for the vlan filters 2241 * @v_list: list of vlan filters to be added 2242 * @count: length of the list 2243 * @cmd_details: pointer to command details structure or NULL 2244 **/ 2245 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 2246 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2247 u8 count, struct i40e_asq_cmd_details *cmd_details) 2248 { 2249 struct i40e_aq_desc desc; 2250 struct i40e_aqc_macvlan *cmd = 2251 (struct i40e_aqc_macvlan *)&desc.params.raw; 2252 enum i40e_status_code status; 2253 u16 buf_size; 2254 2255 if (count == 0 || !v_list || !hw) 2256 return I40E_ERR_PARAM; 2257 2258 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data); 2259 2260 /* prep the rest of the request */ 2261 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 2262 cmd->num_addresses = CPU_TO_LE16(count); 2263 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2264 cmd->seid[1] = 0; 2265 cmd->seid[2] = 0; 2266 2267 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2268 if (buf_size > I40E_AQ_LARGE_BUF) 2269 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2270 2271 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2272 cmd_details); 2273 2274 return status; 2275 } 2276 2277 /** 2278 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 2279 * @hw: pointer to the hw struct 2280 * @seid: VSI for the vlan filters 2281 * @v_list: list of macvlans to be removed 2282 * @count: length of the list 2283 * @cmd_details: pointer to command details structure or NULL 2284 **/ 2285 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 2286 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2287 u8 count, struct i40e_asq_cmd_details *cmd_details) 2288 { 2289 struct i40e_aq_desc desc; 2290 struct i40e_aqc_macvlan *cmd = 2291 (struct i40e_aqc_macvlan *)&desc.params.raw; 2292 enum i40e_status_code status; 2293 u16 buf_size; 2294 2295 if (count == 0 || !v_list || !hw) 2296 return I40E_ERR_PARAM; 2297 2298 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data); 2299 2300 /* prep the rest of the request */ 2301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 2302 cmd->num_addresses = CPU_TO_LE16(count); 2303 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2304 cmd->seid[1] = 0; 2305 cmd->seid[2] = 0; 2306 2307 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2308 if (buf_size > I40E_AQ_LARGE_BUF) 2309 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2310 2311 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2312 cmd_details); 2313 2314 return status; 2315 } 2316 2317 /** 2318 * i40e_aq_send_msg_to_vf 2319 * @hw: pointer to the hardware structure 2320 * @vfid: vf id to send msg 2321 * @v_opcode: opcodes for VF-PF communication 2322 * @v_retval: return error code 2323 * @msg: pointer to the msg buffer 2324 * @msglen: msg length 2325 * @cmd_details: pointer to command details 2326 * 2327 * send msg to vf 2328 **/ 2329 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2330 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2331 struct i40e_asq_cmd_details *cmd_details) 2332 { 2333 struct i40e_aq_desc desc; 2334 struct i40e_aqc_pf_vf_message *cmd = 2335 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2336 enum i40e_status_code status; 2337 2338 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2339 cmd->id = CPU_TO_LE32(vfid); 2340 desc.cookie_high = CPU_TO_LE32(v_opcode); 2341 desc.cookie_low = CPU_TO_LE32(v_retval); 2342 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 2343 if (msglen) { 2344 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 2345 I40E_AQ_FLAG_RD)); 2346 if (msglen > I40E_AQ_LARGE_BUF) 2347 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2348 desc.datalen = CPU_TO_LE16(msglen); 2349 } 2350 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2351 2352 return status; 2353 } 2354 2355 /** 2356 * i40e_aq_debug_write_register 2357 * @hw: pointer to the hw struct 2358 * @reg_addr: register address 2359 * @reg_val: register value 2360 * @cmd_details: pointer to command details structure or NULL 2361 * 2362 * Write to a register using the admin queue commands 2363 **/ 2364 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 2365 u32 reg_addr, u64 reg_val, 2366 struct i40e_asq_cmd_details *cmd_details) 2367 { 2368 struct i40e_aq_desc desc; 2369 struct i40e_aqc_debug_reg_read_write *cmd = 2370 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2371 enum i40e_status_code status; 2372 2373 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2374 2375 cmd->address = CPU_TO_LE32(reg_addr); 2376 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 2377 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 2378 2379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2380 2381 return status; 2382 } 2383 2384 /** 2385 * i40e_aq_get_hmc_resource_profile 2386 * @hw: pointer to the hw struct 2387 * @profile: type of profile the HMC is to be set as 2388 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2389 * @cmd_details: pointer to command details structure or NULL 2390 * 2391 * query the HMC profile of the device. 2392 **/ 2393 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw, 2394 enum i40e_aq_hmc_profile *profile, 2395 u8 *pe_vf_enabled_count, 2396 struct i40e_asq_cmd_details *cmd_details) 2397 { 2398 struct i40e_aq_desc desc; 2399 struct i40e_aq_get_set_hmc_resource_profile *resp = 2400 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2401 enum i40e_status_code status; 2402 2403 i40e_fill_default_direct_cmd_desc(&desc, 2404 i40e_aqc_opc_query_hmc_resource_profile); 2405 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2406 2407 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile & 2408 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK); 2409 *pe_vf_enabled_count = resp->pe_vf_enabled & 2410 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK; 2411 2412 return status; 2413 } 2414 2415 /** 2416 * i40e_aq_set_hmc_resource_profile 2417 * @hw: pointer to the hw struct 2418 * @profile: type of profile the HMC is to be set as 2419 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2420 * @cmd_details: pointer to command details structure or NULL 2421 * 2422 * set the HMC profile of the device. 2423 **/ 2424 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2425 enum i40e_aq_hmc_profile profile, 2426 u8 pe_vf_enabled_count, 2427 struct i40e_asq_cmd_details *cmd_details) 2428 { 2429 struct i40e_aq_desc desc; 2430 struct i40e_aq_get_set_hmc_resource_profile *cmd = 2431 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2432 enum i40e_status_code status; 2433 2434 i40e_fill_default_direct_cmd_desc(&desc, 2435 i40e_aqc_opc_set_hmc_resource_profile); 2436 2437 cmd->pm_profile = (u8)profile; 2438 cmd->pe_vf_enabled = pe_vf_enabled_count; 2439 2440 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2441 2442 return status; 2443 } 2444 2445 /** 2446 * i40e_aq_request_resource 2447 * @hw: pointer to the hw struct 2448 * @resource: resource id 2449 * @access: access type 2450 * @sdp_number: resource number 2451 * @timeout: the maximum time in ms that the driver may hold the resource 2452 * @cmd_details: pointer to command details structure or NULL 2453 * 2454 * requests common resource using the admin queue commands 2455 **/ 2456 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 2457 enum i40e_aq_resources_ids resource, 2458 enum i40e_aq_resource_access_type access, 2459 u8 sdp_number, u64 *timeout, 2460 struct i40e_asq_cmd_details *cmd_details) 2461 { 2462 struct i40e_aq_desc desc; 2463 struct i40e_aqc_request_resource *cmd_resp = 2464 (struct i40e_aqc_request_resource *)&desc.params.raw; 2465 enum i40e_status_code status; 2466 2467 DEBUGFUNC("i40e_aq_request_resource"); 2468 2469 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2470 2471 cmd_resp->resource_id = CPU_TO_LE16(resource); 2472 cmd_resp->access_type = CPU_TO_LE16(access); 2473 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 2474 2475 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2476 /* The completion specifies the maximum time in ms that the driver 2477 * may hold the resource in the Timeout field. 2478 * If the resource is held by someone else, the command completes with 2479 * busy return value and the timeout field indicates the maximum time 2480 * the current owner of the resource has to free it. 2481 */ 2482 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2483 *timeout = LE32_TO_CPU(cmd_resp->timeout); 2484 2485 return status; 2486 } 2487 2488 /** 2489 * i40e_aq_release_resource 2490 * @hw: pointer to the hw struct 2491 * @resource: resource id 2492 * @sdp_number: resource number 2493 * @cmd_details: pointer to command details structure or NULL 2494 * 2495 * release common resource using the admin queue commands 2496 **/ 2497 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 2498 enum i40e_aq_resources_ids resource, 2499 u8 sdp_number, 2500 struct i40e_asq_cmd_details *cmd_details) 2501 { 2502 struct i40e_aq_desc desc; 2503 struct i40e_aqc_request_resource *cmd = 2504 (struct i40e_aqc_request_resource *)&desc.params.raw; 2505 enum i40e_status_code status; 2506 2507 DEBUGFUNC("i40e_aq_release_resource"); 2508 2509 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2510 2511 cmd->resource_id = CPU_TO_LE16(resource); 2512 cmd->resource_number = CPU_TO_LE32(sdp_number); 2513 2514 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2515 2516 return status; 2517 } 2518 2519 /** 2520 * i40e_aq_read_nvm 2521 * @hw: pointer to the hw struct 2522 * @module_pointer: module pointer location in words from the NVM beginning 2523 * @offset: byte offset from the module beginning 2524 * @length: length of the section to be read (in bytes from the offset) 2525 * @data: command buffer (size [bytes] = length) 2526 * @last_command: tells if this is the last command in a series 2527 * @cmd_details: pointer to command details structure or NULL 2528 * 2529 * Read the NVM using the admin queue commands 2530 **/ 2531 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2532 u32 offset, u16 length, void *data, 2533 bool last_command, 2534 struct i40e_asq_cmd_details *cmd_details) 2535 { 2536 struct i40e_aq_desc desc; 2537 struct i40e_aqc_nvm_update *cmd = 2538 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2539 enum i40e_status_code status; 2540 2541 DEBUGFUNC("i40e_aq_read_nvm"); 2542 2543 /* In offset the highest byte must be zeroed. */ 2544 if (offset & 0xFF000000) { 2545 status = I40E_ERR_PARAM; 2546 goto i40e_aq_read_nvm_exit; 2547 } 2548 2549 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2550 2551 /* If this is the last command in a series, set the proper flag. */ 2552 if (last_command) 2553 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2554 cmd->module_pointer = module_pointer; 2555 cmd->offset = CPU_TO_LE32(offset); 2556 cmd->length = CPU_TO_LE16(length); 2557 2558 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2559 if (length > I40E_AQ_LARGE_BUF) 2560 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2561 2562 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2563 2564 i40e_aq_read_nvm_exit: 2565 return status; 2566 } 2567 2568 /** 2569 * i40e_aq_erase_nvm 2570 * @hw: pointer to the hw struct 2571 * @module_pointer: module pointer location in words from the NVM beginning 2572 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2573 * @length: length of the section to be erased (expressed in 4 KB) 2574 * @last_command: tells if this is the last command in a series 2575 * @cmd_details: pointer to command details structure or NULL 2576 * 2577 * Erase the NVM sector using the admin queue commands 2578 **/ 2579 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2580 u32 offset, u16 length, bool last_command, 2581 struct i40e_asq_cmd_details *cmd_details) 2582 { 2583 struct i40e_aq_desc desc; 2584 struct i40e_aqc_nvm_update *cmd = 2585 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2586 enum i40e_status_code status; 2587 2588 DEBUGFUNC("i40e_aq_erase_nvm"); 2589 2590 /* In offset the highest byte must be zeroed. */ 2591 if (offset & 0xFF000000) { 2592 status = I40E_ERR_PARAM; 2593 goto i40e_aq_erase_nvm_exit; 2594 } 2595 2596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2597 2598 /* If this is the last command in a series, set the proper flag. */ 2599 if (last_command) 2600 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2601 cmd->module_pointer = module_pointer; 2602 cmd->offset = CPU_TO_LE32(offset); 2603 cmd->length = CPU_TO_LE16(length); 2604 2605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2606 2607 i40e_aq_erase_nvm_exit: 2608 return status; 2609 } 2610 2611 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 2612 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 2613 #define I40E_DEV_FUNC_CAP_NPAR 0x03 2614 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04 2615 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 2616 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 2617 #define I40E_DEV_FUNC_CAP_VF 0x13 2618 #define I40E_DEV_FUNC_CAP_VMDQ 0x14 2619 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 2620 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 2621 #define I40E_DEV_FUNC_CAP_VSI 0x17 2622 #define I40E_DEV_FUNC_CAP_DCB 0x18 2623 #define I40E_DEV_FUNC_CAP_FCOE 0x21 2624 #define I40E_DEV_FUNC_CAP_RSS 0x40 2625 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 2626 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 2627 #define I40E_DEV_FUNC_CAP_MSIX 0x43 2628 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 2629 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 2630 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 2631 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1 2632 #define I40E_DEV_FUNC_CAP_CEM 0xF2 2633 #define I40E_DEV_FUNC_CAP_IWARP 0x51 2634 #define I40E_DEV_FUNC_CAP_LED 0x61 2635 #define I40E_DEV_FUNC_CAP_SDP 0x62 2636 #define I40E_DEV_FUNC_CAP_MDIO 0x63 2637 2638 /** 2639 * i40e_parse_discover_capabilities 2640 * @hw: pointer to the hw struct 2641 * @buff: pointer to a buffer containing device/function capability records 2642 * @cap_count: number of capability records in the list 2643 * @list_type_opc: type of capabilities list to parse 2644 * 2645 * Parse the device/function capabilities list. 2646 **/ 2647 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2648 u32 cap_count, 2649 enum i40e_admin_queue_opc list_type_opc) 2650 { 2651 struct i40e_aqc_list_capabilities_element_resp *cap; 2652 u32 number, logical_id, phys_id; 2653 struct i40e_hw_capabilities *p; 2654 u32 i = 0; 2655 u16 id; 2656 2657 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2658 2659 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2660 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 2661 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2662 p = (struct i40e_hw_capabilities *)&hw->func_caps; 2663 else 2664 return; 2665 2666 for (i = 0; i < cap_count; i++, cap++) { 2667 id = LE16_TO_CPU(cap->id); 2668 number = LE32_TO_CPU(cap->number); 2669 logical_id = LE32_TO_CPU(cap->logical_id); 2670 phys_id = LE32_TO_CPU(cap->phys_id); 2671 2672 switch (id) { 2673 case I40E_DEV_FUNC_CAP_SWITCH_MODE: 2674 p->switch_mode = number; 2675 break; 2676 case I40E_DEV_FUNC_CAP_MGMT_MODE: 2677 p->management_mode = number; 2678 break; 2679 case I40E_DEV_FUNC_CAP_NPAR: 2680 p->npar_enable = number; 2681 break; 2682 case I40E_DEV_FUNC_CAP_OS2BMC: 2683 p->os2bmc = number; 2684 break; 2685 case I40E_DEV_FUNC_CAP_VALID_FUNC: 2686 p->valid_functions = number; 2687 break; 2688 case I40E_DEV_FUNC_CAP_SRIOV_1_1: 2689 if (number == 1) 2690 p->sr_iov_1_1 = TRUE; 2691 break; 2692 case I40E_DEV_FUNC_CAP_VF: 2693 p->num_vfs = number; 2694 p->vf_base_id = logical_id; 2695 break; 2696 case I40E_DEV_FUNC_CAP_VMDQ: 2697 if (number == 1) 2698 p->vmdq = TRUE; 2699 break; 2700 case I40E_DEV_FUNC_CAP_802_1_QBG: 2701 if (number == 1) 2702 p->evb_802_1_qbg = TRUE; 2703 break; 2704 case I40E_DEV_FUNC_CAP_802_1_QBH: 2705 if (number == 1) 2706 p->evb_802_1_qbh = TRUE; 2707 break; 2708 case I40E_DEV_FUNC_CAP_VSI: 2709 p->num_vsis = number; 2710 break; 2711 case I40E_DEV_FUNC_CAP_DCB: 2712 if (number == 1) { 2713 p->dcb = TRUE; 2714 p->enabled_tcmap = logical_id; 2715 p->maxtc = phys_id; 2716 } 2717 break; 2718 case I40E_DEV_FUNC_CAP_FCOE: 2719 if (number == 1) 2720 p->fcoe = TRUE; 2721 break; 2722 case I40E_DEV_FUNC_CAP_RSS: 2723 p->rss = TRUE; 2724 p->rss_table_size = number; 2725 p->rss_table_entry_width = logical_id; 2726 break; 2727 case I40E_DEV_FUNC_CAP_RX_QUEUES: 2728 p->num_rx_qp = number; 2729 p->base_queue = phys_id; 2730 break; 2731 case I40E_DEV_FUNC_CAP_TX_QUEUES: 2732 p->num_tx_qp = number; 2733 p->base_queue = phys_id; 2734 break; 2735 case I40E_DEV_FUNC_CAP_MSIX: 2736 p->num_msix_vectors = number; 2737 break; 2738 case I40E_DEV_FUNC_CAP_MSIX_VF: 2739 p->num_msix_vectors_vf = number; 2740 break; 2741 case I40E_DEV_FUNC_CAP_MFP_MODE_1: 2742 if (number == 1) 2743 p->mfp_mode_1 = TRUE; 2744 break; 2745 case I40E_DEV_FUNC_CAP_CEM: 2746 if (number == 1) 2747 p->mgmt_cem = TRUE; 2748 break; 2749 case I40E_DEV_FUNC_CAP_IWARP: 2750 if (number == 1) 2751 p->iwarp = TRUE; 2752 break; 2753 case I40E_DEV_FUNC_CAP_LED: 2754 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2755 p->led[phys_id] = TRUE; 2756 break; 2757 case I40E_DEV_FUNC_CAP_SDP: 2758 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2759 p->sdp[phys_id] = TRUE; 2760 break; 2761 case I40E_DEV_FUNC_CAP_MDIO: 2762 if (number == 1) { 2763 p->mdio_port_num = phys_id; 2764 p->mdio_port_mode = logical_id; 2765 } 2766 break; 2767 case I40E_DEV_FUNC_CAP_IEEE_1588: 2768 if (number == 1) 2769 p->ieee_1588 = TRUE; 2770 break; 2771 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 2772 p->fd = TRUE; 2773 p->fd_filters_guaranteed = number; 2774 p->fd_filters_best_effort = logical_id; 2775 break; 2776 default: 2777 break; 2778 } 2779 } 2780 2781 /* Software override ensuring FCoE is disabled if npar or mfp 2782 * mode because it is not supported in these modes. 2783 */ 2784 if (p->npar_enable || p->mfp_mode_1) 2785 p->fcoe = FALSE; 2786 2787 /* additional HW specific goodies that might 2788 * someday be HW version specific 2789 */ 2790 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2791 } 2792 2793 /** 2794 * i40e_aq_discover_capabilities 2795 * @hw: pointer to the hw struct 2796 * @buff: a virtual buffer to hold the capabilities 2797 * @buff_size: Size of the virtual buffer 2798 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2799 * @list_type_opc: capabilities type to discover - pass in the command opcode 2800 * @cmd_details: pointer to command details structure or NULL 2801 * 2802 * Get the device capabilities descriptions from the firmware 2803 **/ 2804 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 2805 void *buff, u16 buff_size, u16 *data_size, 2806 enum i40e_admin_queue_opc list_type_opc, 2807 struct i40e_asq_cmd_details *cmd_details) 2808 { 2809 struct i40e_aqc_list_capabilites *cmd; 2810 struct i40e_aq_desc desc; 2811 enum i40e_status_code status = I40E_SUCCESS; 2812 2813 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 2814 2815 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2816 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2817 status = I40E_ERR_PARAM; 2818 goto exit; 2819 } 2820 2821 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2822 2823 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2824 if (buff_size > I40E_AQ_LARGE_BUF) 2825 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2826 2827 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2828 *data_size = LE16_TO_CPU(desc.datalen); 2829 2830 if (status) 2831 goto exit; 2832 2833 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 2834 list_type_opc); 2835 2836 exit: 2837 return status; 2838 } 2839 2840 /** 2841 * i40e_aq_update_nvm 2842 * @hw: pointer to the hw struct 2843 * @module_pointer: module pointer location in words from the NVM beginning 2844 * @offset: byte offset from the module beginning 2845 * @length: length of the section to be written (in bytes from the offset) 2846 * @data: command buffer (size [bytes] = length) 2847 * @last_command: tells if this is the last command in a series 2848 * @cmd_details: pointer to command details structure or NULL 2849 * 2850 * Update the NVM using the admin queue commands 2851 **/ 2852 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2853 u32 offset, u16 length, void *data, 2854 bool last_command, 2855 struct i40e_asq_cmd_details *cmd_details) 2856 { 2857 struct i40e_aq_desc desc; 2858 struct i40e_aqc_nvm_update *cmd = 2859 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2860 enum i40e_status_code status; 2861 2862 DEBUGFUNC("i40e_aq_update_nvm"); 2863 2864 /* In offset the highest byte must be zeroed. */ 2865 if (offset & 0xFF000000) { 2866 status = I40E_ERR_PARAM; 2867 goto i40e_aq_update_nvm_exit; 2868 } 2869 2870 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2871 2872 /* If this is the last command in a series, set the proper flag. */ 2873 if (last_command) 2874 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2875 cmd->module_pointer = module_pointer; 2876 cmd->offset = CPU_TO_LE32(offset); 2877 cmd->length = CPU_TO_LE16(length); 2878 2879 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2880 if (length > I40E_AQ_LARGE_BUF) 2881 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2882 2883 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2884 2885 i40e_aq_update_nvm_exit: 2886 return status; 2887 } 2888 2889 /** 2890 * i40e_aq_get_lldp_mib 2891 * @hw: pointer to the hw struct 2892 * @bridge_type: type of bridge requested 2893 * @mib_type: Local, Remote or both Local and Remote MIBs 2894 * @buff: pointer to a user supplied buffer to store the MIB block 2895 * @buff_size: size of the buffer (in bytes) 2896 * @local_len : length of the returned Local LLDP MIB 2897 * @remote_len: length of the returned Remote LLDP MIB 2898 * @cmd_details: pointer to command details structure or NULL 2899 * 2900 * Requests the complete LLDP MIB (entire packet). 2901 **/ 2902 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 2903 u8 mib_type, void *buff, u16 buff_size, 2904 u16 *local_len, u16 *remote_len, 2905 struct i40e_asq_cmd_details *cmd_details) 2906 { 2907 struct i40e_aq_desc desc; 2908 struct i40e_aqc_lldp_get_mib *cmd = 2909 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2910 struct i40e_aqc_lldp_get_mib *resp = 2911 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2912 enum i40e_status_code status; 2913 2914 if (buff_size == 0 || !buff) 2915 return I40E_ERR_PARAM; 2916 2917 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 2918 /* Indirect Command */ 2919 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2920 2921 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 2922 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 2923 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 2924 2925 desc.datalen = CPU_TO_LE16(buff_size); 2926 2927 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2928 if (buff_size > I40E_AQ_LARGE_BUF) 2929 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2930 2931 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2932 if (!status) { 2933 if (local_len != NULL) 2934 *local_len = LE16_TO_CPU(resp->local_len); 2935 if (remote_len != NULL) 2936 *remote_len = LE16_TO_CPU(resp->remote_len); 2937 } 2938 2939 return status; 2940 } 2941 2942 /** 2943 * i40e_aq_cfg_lldp_mib_change_event 2944 * @hw: pointer to the hw struct 2945 * @enable_update: Enable or Disable event posting 2946 * @cmd_details: pointer to command details structure or NULL 2947 * 2948 * Enable or Disable posting of an event on ARQ when LLDP MIB 2949 * associated with the interface changes 2950 **/ 2951 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 2952 bool enable_update, 2953 struct i40e_asq_cmd_details *cmd_details) 2954 { 2955 struct i40e_aq_desc desc; 2956 struct i40e_aqc_lldp_update_mib *cmd = 2957 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 2958 enum i40e_status_code status; 2959 2960 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 2961 2962 if (!enable_update) 2963 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 2964 2965 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2966 2967 return status; 2968 } 2969 2970 /** 2971 * i40e_aq_add_lldp_tlv 2972 * @hw: pointer to the hw struct 2973 * @bridge_type: type of bridge 2974 * @buff: buffer with TLV to add 2975 * @buff_size: length of the buffer 2976 * @tlv_len: length of the TLV to be added 2977 * @mib_len: length of the LLDP MIB returned in response 2978 * @cmd_details: pointer to command details structure or NULL 2979 * 2980 * Add the specified TLV to LLDP Local MIB for the given bridge type, 2981 * it is responsibility of the caller to make sure that the TLV is not 2982 * already present in the LLDPDU. 2983 * In return firmware will write the complete LLDP MIB with the newly 2984 * added TLV in the response buffer. 2985 **/ 2986 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 2987 void *buff, u16 buff_size, u16 tlv_len, 2988 u16 *mib_len, 2989 struct i40e_asq_cmd_details *cmd_details) 2990 { 2991 struct i40e_aq_desc desc; 2992 struct i40e_aqc_lldp_add_tlv *cmd = 2993 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 2994 enum i40e_status_code status; 2995 2996 if (buff_size == 0 || !buff || tlv_len == 0) 2997 return I40E_ERR_PARAM; 2998 2999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 3000 3001 /* Indirect Command */ 3002 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3003 if (buff_size > I40E_AQ_LARGE_BUF) 3004 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3005 desc.datalen = CPU_TO_LE16(buff_size); 3006 3007 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3008 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3009 cmd->len = CPU_TO_LE16(tlv_len); 3010 3011 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3012 if (!status) { 3013 if (mib_len != NULL) 3014 *mib_len = LE16_TO_CPU(desc.datalen); 3015 } 3016 3017 return status; 3018 } 3019 3020 /** 3021 * i40e_aq_update_lldp_tlv 3022 * @hw: pointer to the hw struct 3023 * @bridge_type: type of bridge 3024 * @buff: buffer with TLV to update 3025 * @buff_size: size of the buffer holding original and updated TLVs 3026 * @old_len: Length of the Original TLV 3027 * @new_len: Length of the Updated TLV 3028 * @offset: offset of the updated TLV in the buff 3029 * @mib_len: length of the returned LLDP MIB 3030 * @cmd_details: pointer to command details structure or NULL 3031 * 3032 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 3033 * Firmware will place the complete LLDP MIB in response buffer with the 3034 * updated TLV. 3035 **/ 3036 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 3037 u8 bridge_type, void *buff, u16 buff_size, 3038 u16 old_len, u16 new_len, u16 offset, 3039 u16 *mib_len, 3040 struct i40e_asq_cmd_details *cmd_details) 3041 { 3042 struct i40e_aq_desc desc; 3043 struct i40e_aqc_lldp_update_tlv *cmd = 3044 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 3045 enum i40e_status_code status; 3046 3047 if (buff_size == 0 || !buff || offset == 0 || 3048 old_len == 0 || new_len == 0) 3049 return I40E_ERR_PARAM; 3050 3051 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 3052 3053 /* Indirect Command */ 3054 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3055 if (buff_size > I40E_AQ_LARGE_BUF) 3056 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3057 desc.datalen = CPU_TO_LE16(buff_size); 3058 3059 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3060 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3061 cmd->old_len = CPU_TO_LE16(old_len); 3062 cmd->new_offset = CPU_TO_LE16(offset); 3063 cmd->new_len = CPU_TO_LE16(new_len); 3064 3065 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3066 if (!status) { 3067 if (mib_len != NULL) 3068 *mib_len = LE16_TO_CPU(desc.datalen); 3069 } 3070 3071 return status; 3072 } 3073 3074 /** 3075 * i40e_aq_delete_lldp_tlv 3076 * @hw: pointer to the hw struct 3077 * @bridge_type: type of bridge 3078 * @buff: pointer to a user supplied buffer that has the TLV 3079 * @buff_size: length of the buffer 3080 * @tlv_len: length of the TLV to be deleted 3081 * @mib_len: length of the returned LLDP MIB 3082 * @cmd_details: pointer to command details structure or NULL 3083 * 3084 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 3085 * The firmware places the entire LLDP MIB in the response buffer. 3086 **/ 3087 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 3088 u8 bridge_type, void *buff, u16 buff_size, 3089 u16 tlv_len, u16 *mib_len, 3090 struct i40e_asq_cmd_details *cmd_details) 3091 { 3092 struct i40e_aq_desc desc; 3093 struct i40e_aqc_lldp_add_tlv *cmd = 3094 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3095 enum i40e_status_code status; 3096 3097 if (buff_size == 0 || !buff) 3098 return I40E_ERR_PARAM; 3099 3100 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 3101 3102 /* Indirect Command */ 3103 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3104 if (buff_size > I40E_AQ_LARGE_BUF) 3105 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3106 desc.datalen = CPU_TO_LE16(buff_size); 3107 cmd->len = CPU_TO_LE16(tlv_len); 3108 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3109 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3110 3111 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3112 if (!status) { 3113 if (mib_len != NULL) 3114 *mib_len = LE16_TO_CPU(desc.datalen); 3115 } 3116 3117 return status; 3118 } 3119 3120 /** 3121 * i40e_aq_stop_lldp 3122 * @hw: pointer to the hw struct 3123 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3124 * @cmd_details: pointer to command details structure or NULL 3125 * 3126 * Stop or Shutdown the embedded LLDP Agent 3127 **/ 3128 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3129 struct i40e_asq_cmd_details *cmd_details) 3130 { 3131 struct i40e_aq_desc desc; 3132 struct i40e_aqc_lldp_stop *cmd = 3133 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3134 enum i40e_status_code status; 3135 3136 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3137 3138 if (shutdown_agent) 3139 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3140 3141 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3142 3143 return status; 3144 } 3145 3146 /** 3147 * i40e_aq_start_lldp 3148 * @hw: pointer to the hw struct 3149 * @cmd_details: pointer to command details structure or NULL 3150 * 3151 * Start the embedded LLDP Agent on all ports. 3152 **/ 3153 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 3154 struct i40e_asq_cmd_details *cmd_details) 3155 { 3156 struct i40e_aq_desc desc; 3157 struct i40e_aqc_lldp_start *cmd = 3158 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3159 enum i40e_status_code status; 3160 3161 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3162 3163 cmd->command = I40E_AQ_LLDP_AGENT_START; 3164 3165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3166 3167 return status; 3168 } 3169 3170 /** 3171 * i40e_aq_add_udp_tunnel 3172 * @hw: pointer to the hw struct 3173 * @udp_port: the UDP port to add 3174 * @header_len: length of the tunneling header length in DWords 3175 * @protocol_index: protocol index type 3176 * @filter_index: pointer to filter index 3177 * @cmd_details: pointer to command details structure or NULL 3178 **/ 3179 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3180 u16 udp_port, u8 protocol_index, 3181 u8 *filter_index, 3182 struct i40e_asq_cmd_details *cmd_details) 3183 { 3184 struct i40e_aq_desc desc; 3185 struct i40e_aqc_add_udp_tunnel *cmd = 3186 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3187 struct i40e_aqc_del_udp_tunnel_completion *resp = 3188 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3189 enum i40e_status_code status; 3190 3191 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3192 3193 cmd->udp_port = CPU_TO_LE16(udp_port); 3194 cmd->protocol_type = protocol_index; 3195 3196 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3197 3198 if (!status) 3199 *filter_index = resp->index; 3200 3201 return status; 3202 } 3203 3204 /** 3205 * i40e_aq_del_udp_tunnel 3206 * @hw: pointer to the hw struct 3207 * @index: filter index 3208 * @cmd_details: pointer to command details structure or NULL 3209 **/ 3210 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3211 struct i40e_asq_cmd_details *cmd_details) 3212 { 3213 struct i40e_aq_desc desc; 3214 struct i40e_aqc_remove_udp_tunnel *cmd = 3215 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3216 enum i40e_status_code status; 3217 3218 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3219 3220 cmd->index = index; 3221 3222 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3223 3224 return status; 3225 } 3226 3227 /** 3228 * i40e_aq_get_switch_resource_alloc (0x0204) 3229 * @hw: pointer to the hw struct 3230 * @num_entries: pointer to u8 to store the number of resource entries returned 3231 * @buf: pointer to a user supplied buffer. This buffer must be large enough 3232 * to store the resource information for all resource types. Each 3233 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 3234 * @count: size, in bytes, of the buffer provided 3235 * @cmd_details: pointer to command details structure or NULL 3236 * 3237 * Query the resources allocated to a function. 3238 **/ 3239 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 3240 u8 *num_entries, 3241 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 3242 u16 count, 3243 struct i40e_asq_cmd_details *cmd_details) 3244 { 3245 struct i40e_aq_desc desc; 3246 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 3247 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 3248 enum i40e_status_code status; 3249 u16 length = count 3250 * sizeof(struct i40e_aqc_switch_resource_alloc_element_resp); 3251 3252 i40e_fill_default_direct_cmd_desc(&desc, 3253 i40e_aqc_opc_get_switch_resource_alloc); 3254 3255 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3256 if (length > I40E_AQ_LARGE_BUF) 3257 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3258 3259 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 3260 3261 if (!status) 3262 *num_entries = cmd_resp->num_entries; 3263 3264 return status; 3265 } 3266 3267 /** 3268 * i40e_aq_delete_element - Delete switch element 3269 * @hw: pointer to the hw struct 3270 * @seid: the SEID to delete from the switch 3271 * @cmd_details: pointer to command details structure or NULL 3272 * 3273 * This deletes a switch element from the switch. 3274 **/ 3275 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3276 struct i40e_asq_cmd_details *cmd_details) 3277 { 3278 struct i40e_aq_desc desc; 3279 struct i40e_aqc_switch_seid *cmd = 3280 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3281 enum i40e_status_code status; 3282 3283 if (seid == 0) 3284 return I40E_ERR_PARAM; 3285 3286 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3287 3288 cmd->seid = CPU_TO_LE16(seid); 3289 3290 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3291 3292 return status; 3293 } 3294 3295 /** 3296 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port 3297 * @hw: pointer to the hw struct 3298 * @flags: component flags 3299 * @mac_seid: uplink seid (MAC SEID) 3300 * @vsi_seid: connected vsi seid 3301 * @ret_seid: seid of create pv component 3302 * 3303 * This instantiates an i40e port virtualizer with specified flags. 3304 * Depending on specified flags the port virtualizer can act as a 3305 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 3306 */ 3307 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 3308 u16 mac_seid, u16 vsi_seid, 3309 u16 *ret_seid) 3310 { 3311 struct i40e_aq_desc desc; 3312 struct i40e_aqc_add_update_pv *cmd = 3313 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 3314 struct i40e_aqc_add_update_pv_completion *resp = 3315 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 3316 enum i40e_status_code status; 3317 3318 if (vsi_seid == 0) 3319 return I40E_ERR_PARAM; 3320 3321 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 3322 cmd->command_flags = CPU_TO_LE16(flags); 3323 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 3324 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 3325 3326 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3327 if (!status && ret_seid) 3328 *ret_seid = LE16_TO_CPU(resp->pv_seid); 3329 3330 return status; 3331 } 3332 3333 /** 3334 * i40e_aq_add_tag - Add an S/E-tag 3335 * @hw: pointer to the hw struct 3336 * @direct_to_queue: should s-tag direct flow to a specific queue 3337 * @vsi_seid: VSI SEID to use this tag 3338 * @tag: value of the tag 3339 * @queue_num: queue number, only valid is direct_to_queue is TRUE 3340 * @tags_used: return value, number of tags in use by this PF 3341 * @tags_free: return value, number of unallocated tags 3342 * @cmd_details: pointer to command details structure or NULL 3343 * 3344 * This associates an S- or E-tag to a VSI in the switch complex. It returns 3345 * the number of tags allocated by the PF, and the number of unallocated 3346 * tags available. 3347 **/ 3348 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 3349 u16 vsi_seid, u16 tag, u16 queue_num, 3350 u16 *tags_used, u16 *tags_free, 3351 struct i40e_asq_cmd_details *cmd_details) 3352 { 3353 struct i40e_aq_desc desc; 3354 struct i40e_aqc_add_tag *cmd = 3355 (struct i40e_aqc_add_tag *)&desc.params.raw; 3356 struct i40e_aqc_add_remove_tag_completion *resp = 3357 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 3358 enum i40e_status_code status; 3359 3360 if (vsi_seid == 0) 3361 return I40E_ERR_PARAM; 3362 3363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 3364 3365 cmd->seid = CPU_TO_LE16(vsi_seid); 3366 cmd->tag = CPU_TO_LE16(tag); 3367 if (direct_to_queue) { 3368 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 3369 cmd->queue_number = CPU_TO_LE16(queue_num); 3370 } 3371 3372 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3373 3374 if (!status) { 3375 if (tags_used != NULL) 3376 *tags_used = LE16_TO_CPU(resp->tags_used); 3377 if (tags_free != NULL) 3378 *tags_free = LE16_TO_CPU(resp->tags_free); 3379 } 3380 3381 return status; 3382 } 3383 3384 /** 3385 * i40e_aq_remove_tag - Remove an S- or E-tag 3386 * @hw: pointer to the hw struct 3387 * @vsi_seid: VSI SEID this tag is associated with 3388 * @tag: value of the S-tag to delete 3389 * @tags_used: return value, number of tags in use by this PF 3390 * @tags_free: return value, number of unallocated tags 3391 * @cmd_details: pointer to command details structure or NULL 3392 * 3393 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 3394 * the number of tags allocated by the PF, and the number of unallocated 3395 * tags available. 3396 **/ 3397 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 3398 u16 tag, u16 *tags_used, u16 *tags_free, 3399 struct i40e_asq_cmd_details *cmd_details) 3400 { 3401 struct i40e_aq_desc desc; 3402 struct i40e_aqc_remove_tag *cmd = 3403 (struct i40e_aqc_remove_tag *)&desc.params.raw; 3404 struct i40e_aqc_add_remove_tag_completion *resp = 3405 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 3406 enum i40e_status_code status; 3407 3408 if (vsi_seid == 0) 3409 return I40E_ERR_PARAM; 3410 3411 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 3412 3413 cmd->seid = CPU_TO_LE16(vsi_seid); 3414 cmd->tag = CPU_TO_LE16(tag); 3415 3416 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3417 3418 if (!status) { 3419 if (tags_used != NULL) 3420 *tags_used = LE16_TO_CPU(resp->tags_used); 3421 if (tags_free != NULL) 3422 *tags_free = LE16_TO_CPU(resp->tags_free); 3423 } 3424 3425 return status; 3426 } 3427 3428 /** 3429 * i40e_aq_add_mcast_etag - Add a multicast E-tag 3430 * @hw: pointer to the hw struct 3431 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 3432 * @etag: value of E-tag to add 3433 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 3434 * @buf: address of indirect buffer 3435 * @tags_used: return value, number of E-tags in use by this port 3436 * @tags_free: return value, number of unallocated M-tags 3437 * @cmd_details: pointer to command details structure or NULL 3438 * 3439 * This associates a multicast E-tag to a port virtualizer. It will return 3440 * the number of tags allocated by the PF, and the number of unallocated 3441 * tags available. 3442 * 3443 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 3444 * num_tags_in_buf long. 3445 **/ 3446 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 3447 u16 etag, u8 num_tags_in_buf, void *buf, 3448 u16 *tags_used, u16 *tags_free, 3449 struct i40e_asq_cmd_details *cmd_details) 3450 { 3451 struct i40e_aq_desc desc; 3452 struct i40e_aqc_add_remove_mcast_etag *cmd = 3453 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 3454 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 3455 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 3456 enum i40e_status_code status; 3457 u16 length = sizeof(u16) * num_tags_in_buf; 3458 3459 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 3460 return I40E_ERR_PARAM; 3461 3462 i40e_fill_default_direct_cmd_desc(&desc, 3463 i40e_aqc_opc_add_multicast_etag); 3464 3465 cmd->pv_seid = CPU_TO_LE16(pv_seid); 3466 cmd->etag = CPU_TO_LE16(etag); 3467 cmd->num_unicast_etags = num_tags_in_buf; 3468 3469 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3470 if (length > I40E_AQ_LARGE_BUF) 3471 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3472 3473 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 3474 3475 if (!status) { 3476 if (tags_used != NULL) 3477 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 3478 if (tags_free != NULL) 3479 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 3480 } 3481 3482 return status; 3483 } 3484 3485 /** 3486 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 3487 * @hw: pointer to the hw struct 3488 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 3489 * @etag: value of the E-tag to remove 3490 * @tags_used: return value, number of tags in use by this port 3491 * @tags_free: return value, number of unallocated tags 3492 * @cmd_details: pointer to command details structure or NULL 3493 * 3494 * This deletes an E-tag from the port virtualizer. It will return 3495 * the number of tags allocated by the port, and the number of unallocated 3496 * tags available. 3497 **/ 3498 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 3499 u16 etag, u16 *tags_used, u16 *tags_free, 3500 struct i40e_asq_cmd_details *cmd_details) 3501 { 3502 struct i40e_aq_desc desc; 3503 struct i40e_aqc_add_remove_mcast_etag *cmd = 3504 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 3505 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 3506 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 3507 enum i40e_status_code status; 3508 3509 3510 if (pv_seid == 0) 3511 return I40E_ERR_PARAM; 3512 3513 i40e_fill_default_direct_cmd_desc(&desc, 3514 i40e_aqc_opc_remove_multicast_etag); 3515 3516 cmd->pv_seid = CPU_TO_LE16(pv_seid); 3517 cmd->etag = CPU_TO_LE16(etag); 3518 3519 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3520 3521 if (!status) { 3522 if (tags_used != NULL) 3523 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 3524 if (tags_free != NULL) 3525 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 3526 } 3527 3528 return status; 3529 } 3530 3531 /** 3532 * i40e_aq_update_tag - Update an S/E-tag 3533 * @hw: pointer to the hw struct 3534 * @vsi_seid: VSI SEID using this S-tag 3535 * @old_tag: old tag value 3536 * @new_tag: new tag value 3537 * @tags_used: return value, number of tags in use by this PF 3538 * @tags_free: return value, number of unallocated tags 3539 * @cmd_details: pointer to command details structure or NULL 3540 * 3541 * This updates the value of the tag currently attached to this VSI 3542 * in the switch complex. It will return the number of tags allocated 3543 * by the PF, and the number of unallocated tags available. 3544 **/ 3545 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 3546 u16 old_tag, u16 new_tag, u16 *tags_used, 3547 u16 *tags_free, 3548 struct i40e_asq_cmd_details *cmd_details) 3549 { 3550 struct i40e_aq_desc desc; 3551 struct i40e_aqc_update_tag *cmd = 3552 (struct i40e_aqc_update_tag *)&desc.params.raw; 3553 struct i40e_aqc_update_tag_completion *resp = 3554 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 3555 enum i40e_status_code status; 3556 3557 if (vsi_seid == 0) 3558 return I40E_ERR_PARAM; 3559 3560 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 3561 3562 cmd->seid = CPU_TO_LE16(vsi_seid); 3563 cmd->old_tag = CPU_TO_LE16(old_tag); 3564 cmd->new_tag = CPU_TO_LE16(new_tag); 3565 3566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3567 3568 if (!status) { 3569 if (tags_used != NULL) 3570 *tags_used = LE16_TO_CPU(resp->tags_used); 3571 if (tags_free != NULL) 3572 *tags_free = LE16_TO_CPU(resp->tags_free); 3573 } 3574 3575 return status; 3576 } 3577 3578 /** 3579 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 3580 * @hw: pointer to the hw struct 3581 * @tcmap: TC map for request/release any ignore PFC condition 3582 * @request: request or release ignore PFC condition 3583 * @tcmap_ret: return TCs for which PFC is currently ignored 3584 * @cmd_details: pointer to command details structure or NULL 3585 * 3586 * This sends out request/release to ignore PFC condition for a TC. 3587 * It will return the TCs for which PFC is currently ignored. 3588 **/ 3589 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 3590 bool request, u8 *tcmap_ret, 3591 struct i40e_asq_cmd_details *cmd_details) 3592 { 3593 struct i40e_aq_desc desc; 3594 struct i40e_aqc_pfc_ignore *cmd_resp = 3595 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 3596 enum i40e_status_code status; 3597 3598 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 3599 3600 if (request) 3601 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 3602 3603 cmd_resp->tc_bitmap = tcmap; 3604 3605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3606 3607 if (!status) { 3608 if (tcmap_ret != NULL) 3609 *tcmap_ret = cmd_resp->tc_bitmap; 3610 } 3611 3612 return status; 3613 } 3614 3615 /** 3616 * i40e_aq_dcb_updated - DCB Updated Command 3617 * @hw: pointer to the hw struct 3618 * @cmd_details: pointer to command details structure or NULL 3619 * 3620 * When LLDP is handled in PF this command is used by the PF 3621 * to notify EMP that a DCB setting is modified. 3622 * When LLDP is handled in EMP this command is used by the PF 3623 * to notify EMP whenever one of the following parameters get 3624 * modified: 3625 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 3626 * - PCIRTT in PRTDCB_GENC.PCIRTT 3627 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 3628 * EMP will return when the shared RPB settings have been 3629 * recomputed and modified. The retval field in the descriptor 3630 * will be set to 0 when RPB is modified. 3631 **/ 3632 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 3633 struct i40e_asq_cmd_details *cmd_details) 3634 { 3635 struct i40e_aq_desc desc; 3636 enum i40e_status_code status; 3637 3638 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3639 3640 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3641 3642 return status; 3643 } 3644 3645 /** 3646 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 3647 * @hw: pointer to the hw struct 3648 * @seid: defines the SEID of the switch for which the stats are requested 3649 * @vlan_id: the VLAN ID for which the statistics are requested 3650 * @stat_index: index of the statistics counters block assigned to this VLAN 3651 * @cmd_details: pointer to command details structure or NULL 3652 * 3653 * XL710 supports 128 smonVlanStats counters.This command is used to 3654 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 3655 * switch. 3656 **/ 3657 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 3658 u16 vlan_id, u16 *stat_index, 3659 struct i40e_asq_cmd_details *cmd_details) 3660 { 3661 struct i40e_aq_desc desc; 3662 struct i40e_aqc_add_remove_statistics *cmd_resp = 3663 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 3664 enum i40e_status_code status; 3665 3666 if ((seid == 0) || (stat_index == NULL)) 3667 return I40E_ERR_PARAM; 3668 3669 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 3670 3671 cmd_resp->seid = CPU_TO_LE16(seid); 3672 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 3673 3674 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3675 3676 if (!status) 3677 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 3678 3679 return status; 3680 } 3681 3682 /** 3683 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 3684 * @hw: pointer to the hw struct 3685 * @seid: defines the SEID of the switch for which the stats are requested 3686 * @vlan_id: the VLAN ID for which the statistics are requested 3687 * @stat_index: index of the statistics counters block assigned to this VLAN 3688 * @cmd_details: pointer to command details structure or NULL 3689 * 3690 * XL710 supports 128 smonVlanStats counters.This command is used to 3691 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 3692 * switch. 3693 **/ 3694 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 3695 u16 vlan_id, u16 stat_index, 3696 struct i40e_asq_cmd_details *cmd_details) 3697 { 3698 struct i40e_aq_desc desc; 3699 struct i40e_aqc_add_remove_statistics *cmd = 3700 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 3701 enum i40e_status_code status; 3702 3703 if (seid == 0) 3704 return I40E_ERR_PARAM; 3705 3706 i40e_fill_default_direct_cmd_desc(&desc, 3707 i40e_aqc_opc_remove_statistics); 3708 3709 cmd->seid = CPU_TO_LE16(seid); 3710 cmd->vlan = CPU_TO_LE16(vlan_id); 3711 cmd->stat_index = CPU_TO_LE16(stat_index); 3712 3713 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3714 3715 return status; 3716 } 3717 3718 /** 3719 * i40e_aq_set_port_parameters - set physical port parameters. 3720 * @hw: pointer to the hw struct 3721 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 3722 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 3723 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 3724 * @double_vlan: if set double VLAN is enabled 3725 * @cmd_details: pointer to command details structure or NULL 3726 **/ 3727 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 3728 u16 bad_frame_vsi, bool save_bad_pac, 3729 bool pad_short_pac, bool double_vlan, 3730 struct i40e_asq_cmd_details *cmd_details) 3731 { 3732 struct i40e_aqc_set_port_parameters *cmd; 3733 enum i40e_status_code status; 3734 struct i40e_aq_desc desc; 3735 u16 command_flags = 0; 3736 3737 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 3738 3739 i40e_fill_default_direct_cmd_desc(&desc, 3740 i40e_aqc_opc_set_port_parameters); 3741 3742 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 3743 if (save_bad_pac) 3744 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 3745 if (pad_short_pac) 3746 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 3747 if (double_vlan) 3748 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3749 cmd->command_flags = CPU_TO_LE16(command_flags); 3750 3751 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3752 3753 return status; 3754 } 3755 3756 /** 3757 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3758 * @hw: pointer to the hw struct 3759 * @seid: seid for the physical port/switching component/vsi 3760 * @buff: Indirect buffer to hold data parameters and response 3761 * @buff_size: Indirect buffer size 3762 * @opcode: Tx scheduler AQ command opcode 3763 * @cmd_details: pointer to command details structure or NULL 3764 * 3765 * Generic command handler for Tx scheduler AQ commands 3766 **/ 3767 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3768 void *buff, u16 buff_size, 3769 enum i40e_admin_queue_opc opcode, 3770 struct i40e_asq_cmd_details *cmd_details) 3771 { 3772 struct i40e_aq_desc desc; 3773 struct i40e_aqc_tx_sched_ind *cmd = 3774 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3775 enum i40e_status_code status; 3776 bool cmd_param_flag = FALSE; 3777 3778 switch (opcode) { 3779 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3780 case i40e_aqc_opc_configure_vsi_tc_bw: 3781 case i40e_aqc_opc_enable_switching_comp_ets: 3782 case i40e_aqc_opc_modify_switching_comp_ets: 3783 case i40e_aqc_opc_disable_switching_comp_ets: 3784 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3785 case i40e_aqc_opc_configure_switching_comp_bw_config: 3786 cmd_param_flag = TRUE; 3787 break; 3788 case i40e_aqc_opc_query_vsi_bw_config: 3789 case i40e_aqc_opc_query_vsi_ets_sla_config: 3790 case i40e_aqc_opc_query_switching_comp_ets_config: 3791 case i40e_aqc_opc_query_port_ets_config: 3792 case i40e_aqc_opc_query_switching_comp_bw_config: 3793 cmd_param_flag = FALSE; 3794 break; 3795 default: 3796 return I40E_ERR_PARAM; 3797 } 3798 3799 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3800 3801 /* Indirect command */ 3802 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3803 if (cmd_param_flag) 3804 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 3805 if (buff_size > I40E_AQ_LARGE_BUF) 3806 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3807 3808 desc.datalen = CPU_TO_LE16(buff_size); 3809 3810 cmd->vsi_seid = CPU_TO_LE16(seid); 3811 3812 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3813 3814 return status; 3815 } 3816 3817 /** 3818 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3819 * @hw: pointer to the hw struct 3820 * @seid: VSI seid 3821 * @credit: BW limit credits (0 = disabled) 3822 * @max_credit: Max BW limit credits 3823 * @cmd_details: pointer to command details structure or NULL 3824 **/ 3825 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3826 u16 seid, u16 credit, u8 max_credit, 3827 struct i40e_asq_cmd_details *cmd_details) 3828 { 3829 struct i40e_aq_desc desc; 3830 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3831 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3832 enum i40e_status_code status; 3833 3834 i40e_fill_default_direct_cmd_desc(&desc, 3835 i40e_aqc_opc_configure_vsi_bw_limit); 3836 3837 cmd->vsi_seid = CPU_TO_LE16(seid); 3838 cmd->credit = CPU_TO_LE16(credit); 3839 cmd->max_credit = max_credit; 3840 3841 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3842 3843 return status; 3844 } 3845 3846 /** 3847 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 3848 * @hw: pointer to the hw struct 3849 * @seid: switching component seid 3850 * @credit: BW limit credits (0 = disabled) 3851 * @max_bw: Max BW limit credits 3852 * @cmd_details: pointer to command details structure or NULL 3853 **/ 3854 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 3855 u16 seid, u16 credit, u8 max_bw, 3856 struct i40e_asq_cmd_details *cmd_details) 3857 { 3858 struct i40e_aq_desc desc; 3859 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 3860 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 3861 enum i40e_status_code status; 3862 3863 i40e_fill_default_direct_cmd_desc(&desc, 3864 i40e_aqc_opc_configure_switching_comp_bw_limit); 3865 3866 cmd->seid = CPU_TO_LE16(seid); 3867 cmd->credit = CPU_TO_LE16(credit); 3868 cmd->max_bw = max_bw; 3869 3870 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3871 3872 return status; 3873 } 3874 3875 /** 3876 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 3877 * @hw: pointer to the hw struct 3878 * @seid: VSI seid 3879 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 3880 * @cmd_details: pointer to command details structure or NULL 3881 **/ 3882 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 3883 u16 seid, 3884 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 3885 struct i40e_asq_cmd_details *cmd_details) 3886 { 3887 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3888 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 3889 cmd_details); 3890 } 3891 3892 /** 3893 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3894 * @hw: pointer to the hw struct 3895 * @seid: VSI seid 3896 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3897 * @cmd_details: pointer to command details structure or NULL 3898 **/ 3899 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3900 u16 seid, 3901 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3902 struct i40e_asq_cmd_details *cmd_details) 3903 { 3904 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3905 i40e_aqc_opc_configure_vsi_tc_bw, 3906 cmd_details); 3907 } 3908 3909 /** 3910 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 3911 * @hw: pointer to the hw struct 3912 * @seid: seid of the switching component 3913 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 3914 * @cmd_details: pointer to command details structure or NULL 3915 **/ 3916 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 3917 struct i40e_hw *hw, u16 seid, 3918 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 3919 struct i40e_asq_cmd_details *cmd_details) 3920 { 3921 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3922 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 3923 cmd_details); 3924 } 3925 3926 /** 3927 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3928 * @hw: pointer to the hw struct 3929 * @seid: seid of the VSI 3930 * @bw_data: Buffer to hold VSI BW configuration 3931 * @cmd_details: pointer to command details structure or NULL 3932 **/ 3933 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3934 u16 seid, 3935 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3936 struct i40e_asq_cmd_details *cmd_details) 3937 { 3938 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3939 i40e_aqc_opc_query_vsi_bw_config, 3940 cmd_details); 3941 } 3942 3943 /** 3944 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3945 * @hw: pointer to the hw struct 3946 * @seid: seid of the VSI 3947 * @bw_data: Buffer to hold VSI BW configuration per TC 3948 * @cmd_details: pointer to command details structure or NULL 3949 **/ 3950 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3951 u16 seid, 3952 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3953 struct i40e_asq_cmd_details *cmd_details) 3954 { 3955 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3956 i40e_aqc_opc_query_vsi_ets_sla_config, 3957 cmd_details); 3958 } 3959 3960 /** 3961 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3962 * @hw: pointer to the hw struct 3963 * @seid: seid of the switching component 3964 * @bw_data: Buffer to hold switching component's per TC BW config 3965 * @cmd_details: pointer to command details structure or NULL 3966 **/ 3967 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3968 u16 seid, 3969 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3970 struct i40e_asq_cmd_details *cmd_details) 3971 { 3972 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3973 i40e_aqc_opc_query_switching_comp_ets_config, 3974 cmd_details); 3975 } 3976 3977 /** 3978 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3979 * @hw: pointer to the hw struct 3980 * @seid: seid of the VSI or switching component connected to Physical Port 3981 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3982 * @cmd_details: pointer to command details structure or NULL 3983 **/ 3984 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3985 u16 seid, 3986 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3987 struct i40e_asq_cmd_details *cmd_details) 3988 { 3989 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3990 i40e_aqc_opc_query_port_ets_config, 3991 cmd_details); 3992 } 3993 3994 /** 3995 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3996 * @hw: pointer to the hw struct 3997 * @seid: seid of the switching component 3998 * @bw_data: Buffer to hold switching component's BW configuration 3999 * @cmd_details: pointer to command details structure or NULL 4000 **/ 4001 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4002 u16 seid, 4003 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4004 struct i40e_asq_cmd_details *cmd_details) 4005 { 4006 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4007 i40e_aqc_opc_query_switching_comp_bw_config, 4008 cmd_details); 4009 } 4010 4011 /** 4012 * i40e_validate_filter_settings 4013 * @hw: pointer to the hardware structure 4014 * @settings: Filter control settings 4015 * 4016 * Check and validate the filter control settings passed. 4017 * The function checks for the valid filter/context sizes being 4018 * passed for FCoE and PE. 4019 * 4020 * Returns I40E_SUCCESS if the values passed are valid and within 4021 * range else returns an error. 4022 **/ 4023 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 4024 struct i40e_filter_control_settings *settings) 4025 { 4026 u32 fcoe_cntx_size, fcoe_filt_size; 4027 u32 pe_cntx_size, pe_filt_size; 4028 u32 fcoe_fmax; 4029 4030 u32 val; 4031 4032 /* Validate FCoE settings passed */ 4033 switch (settings->fcoe_filt_num) { 4034 case I40E_HASH_FILTER_SIZE_1K: 4035 case I40E_HASH_FILTER_SIZE_2K: 4036 case I40E_HASH_FILTER_SIZE_4K: 4037 case I40E_HASH_FILTER_SIZE_8K: 4038 case I40E_HASH_FILTER_SIZE_16K: 4039 case I40E_HASH_FILTER_SIZE_32K: 4040 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4041 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4042 break; 4043 default: 4044 return I40E_ERR_PARAM; 4045 } 4046 4047 switch (settings->fcoe_cntx_num) { 4048 case I40E_DMA_CNTX_SIZE_512: 4049 case I40E_DMA_CNTX_SIZE_1K: 4050 case I40E_DMA_CNTX_SIZE_2K: 4051 case I40E_DMA_CNTX_SIZE_4K: 4052 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4053 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4054 break; 4055 default: 4056 return I40E_ERR_PARAM; 4057 } 4058 4059 /* Validate PE settings passed */ 4060 switch (settings->pe_filt_num) { 4061 case I40E_HASH_FILTER_SIZE_1K: 4062 case I40E_HASH_FILTER_SIZE_2K: 4063 case I40E_HASH_FILTER_SIZE_4K: 4064 case I40E_HASH_FILTER_SIZE_8K: 4065 case I40E_HASH_FILTER_SIZE_16K: 4066 case I40E_HASH_FILTER_SIZE_32K: 4067 case I40E_HASH_FILTER_SIZE_64K: 4068 case I40E_HASH_FILTER_SIZE_128K: 4069 case I40E_HASH_FILTER_SIZE_256K: 4070 case I40E_HASH_FILTER_SIZE_512K: 4071 case I40E_HASH_FILTER_SIZE_1M: 4072 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4073 pe_filt_size <<= (u32)settings->pe_filt_num; 4074 break; 4075 default: 4076 return I40E_ERR_PARAM; 4077 } 4078 4079 switch (settings->pe_cntx_num) { 4080 case I40E_DMA_CNTX_SIZE_512: 4081 case I40E_DMA_CNTX_SIZE_1K: 4082 case I40E_DMA_CNTX_SIZE_2K: 4083 case I40E_DMA_CNTX_SIZE_4K: 4084 case I40E_DMA_CNTX_SIZE_8K: 4085 case I40E_DMA_CNTX_SIZE_16K: 4086 case I40E_DMA_CNTX_SIZE_32K: 4087 case I40E_DMA_CNTX_SIZE_64K: 4088 case I40E_DMA_CNTX_SIZE_128K: 4089 case I40E_DMA_CNTX_SIZE_256K: 4090 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4091 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4092 break; 4093 default: 4094 return I40E_ERR_PARAM; 4095 } 4096 4097 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4098 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4099 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4100 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4101 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4102 return I40E_ERR_INVALID_SIZE; 4103 4104 return I40E_SUCCESS; 4105 } 4106 4107 /** 4108 * i40e_set_filter_control 4109 * @hw: pointer to the hardware structure 4110 * @settings: Filter control settings 4111 * 4112 * Set the Queue Filters for PE/FCoE and enable filters required 4113 * for a single PF. It is expected that these settings are programmed 4114 * at the driver initialization time. 4115 **/ 4116 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 4117 struct i40e_filter_control_settings *settings) 4118 { 4119 enum i40e_status_code ret = I40E_SUCCESS; 4120 u32 hash_lut_size = 0; 4121 u32 val; 4122 4123 if (!settings) 4124 return I40E_ERR_PARAM; 4125 4126 /* Validate the input settings */ 4127 ret = i40e_validate_filter_settings(hw, settings); 4128 if (ret) 4129 return ret; 4130 4131 /* Read the PF Queue Filter control register */ 4132 val = rd32(hw, I40E_PFQF_CTL_0); 4133 4134 /* Program required PE hash buckets for the PF */ 4135 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4136 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4137 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4138 /* Program required PE contexts for the PF */ 4139 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4140 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4141 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4142 4143 /* Program required FCoE hash buckets for the PF */ 4144 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4145 val |= ((u32)settings->fcoe_filt_num << 4146 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4147 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4148 /* Program required FCoE DDP contexts for the PF */ 4149 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4150 val |= ((u32)settings->fcoe_cntx_num << 4151 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4152 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4153 4154 /* Program Hash LUT size for the PF */ 4155 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4156 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4157 hash_lut_size = 1; 4158 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4159 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4160 4161 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4162 if (settings->enable_fdir) 4163 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4164 if (settings->enable_ethtype) 4165 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4166 if (settings->enable_macvlan) 4167 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4168 4169 wr32(hw, I40E_PFQF_CTL_0, val); 4170 4171 return I40E_SUCCESS; 4172 } 4173 4174 /** 4175 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4176 * @hw: pointer to the hw struct 4177 * @mac_addr: MAC address to use in the filter 4178 * @ethtype: Ethertype to use in the filter 4179 * @flags: Flags that needs to be applied to the filter 4180 * @vsi_seid: seid of the control VSI 4181 * @queue: VSI queue number to send the packet to 4182 * @is_add: Add control packet filter if True else remove 4183 * @stats: Structure to hold information on control filter counts 4184 * @cmd_details: pointer to command details structure or NULL 4185 * 4186 * This command will Add or Remove control packet filter for a control VSI. 4187 * In return it will update the total number of perfect filter count in 4188 * the stats member. 4189 **/ 4190 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4191 u8 *mac_addr, u16 ethtype, u16 flags, 4192 u16 vsi_seid, u16 queue, bool is_add, 4193 struct i40e_control_filter_stats *stats, 4194 struct i40e_asq_cmd_details *cmd_details) 4195 { 4196 struct i40e_aq_desc desc; 4197 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4198 (struct i40e_aqc_add_remove_control_packet_filter *) 4199 &desc.params.raw; 4200 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4201 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4202 &desc.params.raw; 4203 enum i40e_status_code status; 4204 4205 if (vsi_seid == 0) 4206 return I40E_ERR_PARAM; 4207 4208 if (is_add) { 4209 i40e_fill_default_direct_cmd_desc(&desc, 4210 i40e_aqc_opc_add_control_packet_filter); 4211 cmd->queue = CPU_TO_LE16(queue); 4212 } else { 4213 i40e_fill_default_direct_cmd_desc(&desc, 4214 i40e_aqc_opc_remove_control_packet_filter); 4215 } 4216 4217 if (mac_addr) 4218 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, 4219 I40E_NONDMA_TO_NONDMA); 4220 4221 cmd->etype = CPU_TO_LE16(ethtype); 4222 cmd->flags = CPU_TO_LE16(flags); 4223 cmd->seid = CPU_TO_LE16(vsi_seid); 4224 4225 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4226 4227 if (!status && stats) { 4228 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 4229 stats->etype_used = LE16_TO_CPU(resp->etype_used); 4230 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 4231 stats->etype_free = LE16_TO_CPU(resp->etype_free); 4232 } 4233 4234 return status; 4235 } 4236 4237 /** 4238 * i40e_aq_add_cloud_filters 4239 * @hw: pointer to the hardware structure 4240 * @seid: VSI seid to add cloud filters from 4241 * @filters: Buffer which contains the filters to be added 4242 * @filter_count: number of filters contained in the buffer 4243 * 4244 * Set the cloud filters for a given VSI. The contents of the 4245 * i40e_aqc_add_remove_cloud_filters_element_data are filled 4246 * in by the caller of the function. 4247 * 4248 **/ 4249 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 4250 u16 seid, 4251 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 4252 u8 filter_count) 4253 { 4254 struct i40e_aq_desc desc; 4255 struct i40e_aqc_add_remove_cloud_filters *cmd = 4256 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 4257 u16 buff_len; 4258 enum i40e_status_code status; 4259 4260 i40e_fill_default_direct_cmd_desc(&desc, 4261 i40e_aqc_opc_add_cloud_filters); 4262 4263 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) * 4264 filter_count; 4265 desc.datalen = CPU_TO_LE16(buff_len); 4266 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4267 cmd->num_filters = filter_count; 4268 cmd->seid = CPU_TO_LE16(seid); 4269 4270 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 4271 4272 return status; 4273 } 4274 4275 /** 4276 * i40e_aq_remove_cloud_filters 4277 * @hw: pointer to the hardware structure 4278 * @seid: VSI seid to remove cloud filters from 4279 * @filters: Buffer which contains the filters to be removed 4280 * @filter_count: number of filters contained in the buffer 4281 * 4282 * Remove the cloud filters for a given VSI. The contents of the 4283 * i40e_aqc_add_remove_cloud_filters_element_data are filled 4284 * in by the caller of the function. 4285 * 4286 **/ 4287 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 4288 u16 seid, 4289 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 4290 u8 filter_count) 4291 { 4292 struct i40e_aq_desc desc; 4293 struct i40e_aqc_add_remove_cloud_filters *cmd = 4294 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 4295 enum i40e_status_code status; 4296 u16 buff_len; 4297 4298 i40e_fill_default_direct_cmd_desc(&desc, 4299 i40e_aqc_opc_remove_cloud_filters); 4300 4301 buff_len = sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data) * 4302 filter_count; 4303 desc.datalen = CPU_TO_LE16(buff_len); 4304 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4305 cmd->num_filters = filter_count; 4306 cmd->seid = CPU_TO_LE16(seid); 4307 4308 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 4309 4310 return status; 4311 } 4312 4313 /** 4314 * i40e_aq_alternate_write 4315 * @hw: pointer to the hardware structure 4316 * @reg_addr0: address of first dword to be read 4317 * @reg_val0: value to be written under 'reg_addr0' 4318 * @reg_addr1: address of second dword to be read 4319 * @reg_val1: value to be written under 'reg_addr1' 4320 * 4321 * Write one or two dwords to alternate structure. Fields are indicated 4322 * by 'reg_addr0' and 'reg_addr1' register numbers. 4323 * 4324 **/ 4325 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 4326 u32 reg_addr0, u32 reg_val0, 4327 u32 reg_addr1, u32 reg_val1) 4328 { 4329 struct i40e_aq_desc desc; 4330 struct i40e_aqc_alternate_write *cmd_resp = 4331 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4332 enum i40e_status_code status; 4333 4334 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 4335 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 4336 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 4337 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 4338 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 4339 4340 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4341 4342 return status; 4343 } 4344 4345 /** 4346 * i40e_aq_alternate_write_indirect 4347 * @hw: pointer to the hardware structure 4348 * @addr: address of a first register to be modified 4349 * @dw_count: number of alternate structure fields to write 4350 * @buffer: pointer to the command buffer 4351 * 4352 * Write 'dw_count' dwords from 'buffer' to alternate structure 4353 * starting at 'addr'. 4354 * 4355 **/ 4356 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 4357 u32 addr, u32 dw_count, void *buffer) 4358 { 4359 struct i40e_aq_desc desc; 4360 struct i40e_aqc_alternate_ind_write *cmd_resp = 4361 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 4362 enum i40e_status_code status; 4363 4364 if (buffer == NULL) 4365 return I40E_ERR_PARAM; 4366 4367 /* Indirect command */ 4368 i40e_fill_default_direct_cmd_desc(&desc, 4369 i40e_aqc_opc_alternate_write_indirect); 4370 4371 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 4372 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 4373 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 4374 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4375 4376 cmd_resp->address = CPU_TO_LE32(addr); 4377 cmd_resp->length = CPU_TO_LE32(dw_count); 4378 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)(uintptr_t)buffer)); 4379 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)(uintptr_t)buffer)); 4380 4381 status = i40e_asq_send_command(hw, &desc, buffer, 4382 I40E_LO_DWORD(4*dw_count), NULL); 4383 4384 return status; 4385 } 4386 4387 /** 4388 * i40e_aq_alternate_read 4389 * @hw: pointer to the hardware structure 4390 * @reg_addr0: address of first dword to be read 4391 * @reg_val0: pointer for data read from 'reg_addr0' 4392 * @reg_addr1: address of second dword to be read 4393 * @reg_val1: pointer for data read from 'reg_addr1' 4394 * 4395 * Read one or two dwords from alternate structure. Fields are indicated 4396 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4397 * is not passed then only register at 'reg_addr0' is read. 4398 * 4399 **/ 4400 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 4401 u32 reg_addr0, u32 *reg_val0, 4402 u32 reg_addr1, u32 *reg_val1) 4403 { 4404 struct i40e_aq_desc desc; 4405 struct i40e_aqc_alternate_write *cmd_resp = 4406 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4407 enum i40e_status_code status; 4408 4409 if (reg_val0 == NULL) 4410 return I40E_ERR_PARAM; 4411 4412 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4413 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 4414 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 4415 4416 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4417 4418 if (status == I40E_SUCCESS) { 4419 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 4420 4421 if (reg_val1 != NULL) 4422 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 4423 } 4424 4425 return status; 4426 } 4427 4428 /** 4429 * i40e_aq_alternate_read_indirect 4430 * @hw: pointer to the hardware structure 4431 * @addr: address of the alternate structure field 4432 * @dw_count: number of alternate structure fields to read 4433 * @buffer: pointer to the command buffer 4434 * 4435 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 4436 * place them in 'buffer'. The buffer should be allocated by caller. 4437 * 4438 **/ 4439 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 4440 u32 addr, u32 dw_count, void *buffer) 4441 { 4442 struct i40e_aq_desc desc; 4443 struct i40e_aqc_alternate_ind_write *cmd_resp = 4444 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 4445 enum i40e_status_code status; 4446 4447 if (buffer == NULL) 4448 return I40E_ERR_PARAM; 4449 4450 /* Indirect command */ 4451 i40e_fill_default_direct_cmd_desc(&desc, 4452 i40e_aqc_opc_alternate_read_indirect); 4453 4454 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 4455 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 4456 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 4457 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4458 4459 cmd_resp->address = CPU_TO_LE32(addr); 4460 cmd_resp->length = CPU_TO_LE32(dw_count); 4461 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)(uintptr_t)buffer)); 4462 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)(uintptr_t)buffer)); 4463 4464 status = i40e_asq_send_command(hw, &desc, buffer, 4465 I40E_LO_DWORD(4*dw_count), NULL); 4466 4467 return status; 4468 } 4469 4470 /** 4471 * i40e_aq_alternate_clear 4472 * @hw: pointer to the HW structure. 4473 * 4474 * Clear the alternate structures of the port from which the function 4475 * is called. 4476 * 4477 **/ 4478 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 4479 { 4480 struct i40e_aq_desc desc; 4481 enum i40e_status_code status; 4482 4483 i40e_fill_default_direct_cmd_desc(&desc, 4484 i40e_aqc_opc_alternate_clear_port); 4485 4486 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4487 4488 return status; 4489 } 4490 4491 /** 4492 * i40e_aq_alternate_write_done 4493 * @hw: pointer to the HW structure. 4494 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 4495 * @reset_needed: indicates the SW should trigger GLOBAL reset 4496 * 4497 * Indicates to the FW that alternate structures have been changed. 4498 * 4499 **/ 4500 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 4501 u8 bios_mode, bool *reset_needed) 4502 { 4503 struct i40e_aq_desc desc; 4504 struct i40e_aqc_alternate_write_done *cmd = 4505 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 4506 enum i40e_status_code status; 4507 4508 if (reset_needed == NULL) 4509 return I40E_ERR_PARAM; 4510 4511 i40e_fill_default_direct_cmd_desc(&desc, 4512 i40e_aqc_opc_alternate_write_done); 4513 4514 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 4515 4516 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4517 if (!status) 4518 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 4519 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 4520 4521 return status; 4522 } 4523 4524 /** 4525 * i40e_aq_set_oem_mode 4526 * @hw: pointer to the HW structure. 4527 * @oem_mode: the OEM mode to be used 4528 * 4529 * Sets the device to a specific operating mode. Currently the only supported 4530 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 4531 * 4532 **/ 4533 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 4534 u8 oem_mode) 4535 { 4536 struct i40e_aq_desc desc; 4537 struct i40e_aqc_alternate_write_done *cmd = 4538 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 4539 enum i40e_status_code status; 4540 4541 i40e_fill_default_direct_cmd_desc(&desc, 4542 i40e_aqc_opc_alternate_set_mode); 4543 4544 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 4545 4546 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4547 4548 return status; 4549 } 4550 4551 /** 4552 * i40e_aq_resume_port_tx 4553 * @hw: pointer to the hardware structure 4554 * @cmd_details: pointer to command details structure or NULL 4555 * 4556 * Resume port's Tx traffic 4557 **/ 4558 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 4559 struct i40e_asq_cmd_details *cmd_details) 4560 { 4561 struct i40e_aq_desc desc; 4562 enum i40e_status_code status; 4563 4564 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4565 4566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4567 4568 return status; 4569 } 4570 4571 /** 4572 * i40e_set_pci_config_data - store PCI bus info 4573 * @hw: pointer to hardware structure 4574 * @link_status: the link status word from PCI config space 4575 * 4576 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4577 **/ 4578 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4579 { 4580 hw->bus.type = i40e_bus_type_pci_express; 4581 4582 switch (link_status & I40E_PCI_LINK_WIDTH) { 4583 case I40E_PCI_LINK_WIDTH_1: 4584 hw->bus.width = i40e_bus_width_pcie_x1; 4585 break; 4586 case I40E_PCI_LINK_WIDTH_2: 4587 hw->bus.width = i40e_bus_width_pcie_x2; 4588 break; 4589 case I40E_PCI_LINK_WIDTH_4: 4590 hw->bus.width = i40e_bus_width_pcie_x4; 4591 break; 4592 case I40E_PCI_LINK_WIDTH_8: 4593 hw->bus.width = i40e_bus_width_pcie_x8; 4594 break; 4595 default: 4596 hw->bus.width = i40e_bus_width_unknown; 4597 break; 4598 } 4599 4600 switch (link_status & I40E_PCI_LINK_SPEED) { 4601 case I40E_PCI_LINK_SPEED_2500: 4602 hw->bus.speed = i40e_bus_speed_2500; 4603 break; 4604 case I40E_PCI_LINK_SPEED_5000: 4605 hw->bus.speed = i40e_bus_speed_5000; 4606 break; 4607 case I40E_PCI_LINK_SPEED_8000: 4608 hw->bus.speed = i40e_bus_speed_8000; 4609 break; 4610 default: 4611 hw->bus.speed = i40e_bus_speed_unknown; 4612 break; 4613 } 4614 } 4615 4616 /** 4617 * i40e_read_bw_from_alt_ram 4618 * @hw: pointer to the hardware structure 4619 * @max_bw: pointer for max_bw read 4620 * @min_bw: pointer for min_bw read 4621 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 4622 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 4623 * 4624 * Read bw from the alternate ram for the given pf 4625 **/ 4626 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4627 u32 *max_bw, u32 *min_bw, 4628 bool *min_valid, bool *max_valid) 4629 { 4630 enum i40e_status_code status; 4631 u32 max_bw_addr, min_bw_addr; 4632 4633 /* Calculate the address of the min/max bw registers */ 4634 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4635 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4636 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id); 4637 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4638 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4639 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id); 4640 4641 /* Read the bandwidths from alt ram */ 4642 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4643 min_bw_addr, min_bw); 4644 4645 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4646 *min_valid = TRUE; 4647 else 4648 *min_valid = FALSE; 4649 4650 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4651 *max_valid = TRUE; 4652 else 4653 *max_valid = FALSE; 4654 4655 return status; 4656 } 4657 4658 /** 4659 * i40e_aq_configure_partition_bw 4660 * @hw: pointer to the hardware structure 4661 * @bw_data: Buffer holding valid pfs and bw limits 4662 * @cmd_details: pointer to command details 4663 * 4664 * Configure partitions guaranteed/max bw 4665 **/ 4666 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4667 struct i40e_aqc_configure_partition_bw_data *bw_data, 4668 struct i40e_asq_cmd_details *cmd_details) 4669 { 4670 enum i40e_status_code status; 4671 struct i40e_aq_desc desc; 4672 u16 bwd_size = sizeof(struct i40e_aqc_configure_partition_bw_data); 4673 4674 i40e_fill_default_direct_cmd_desc(&desc, 4675 i40e_aqc_opc_configure_partition_bw); 4676 4677 /* Indirect command */ 4678 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4679 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 4680 4681 if (bwd_size > I40E_AQ_LARGE_BUF) 4682 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4683 4684 desc.datalen = CPU_TO_LE16(bwd_size); 4685 4686 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 4687 4688 return status; 4689 } 4690 4691 /** 4692 * i40e_aq_send_msg_to_pf 4693 * @hw: pointer to the hardware structure 4694 * @v_opcode: opcodes for VF-PF communication 4695 * @v_retval: return error code 4696 * @msg: pointer to the msg buffer 4697 * @msglen: msg length 4698 * @cmd_details: pointer to command details 4699 * 4700 * Send message to PF driver using admin queue. By default, this message 4701 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 4702 * completion before returning. 4703 **/ 4704 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 4705 enum i40e_virtchnl_ops v_opcode, 4706 enum i40e_status_code v_retval, 4707 u8 *msg, u16 msglen, 4708 struct i40e_asq_cmd_details *cmd_details) 4709 { 4710 struct i40e_aq_desc desc; 4711 struct i40e_asq_cmd_details details; 4712 enum i40e_status_code status; 4713 4714 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 4715 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 4716 desc.cookie_high = CPU_TO_LE32(v_opcode); 4717 desc.cookie_low = CPU_TO_LE32(v_retval); 4718 if (msglen) { 4719 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 4720 | I40E_AQ_FLAG_RD)); 4721 if (msglen > I40E_AQ_LARGE_BUF) 4722 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4723 desc.datalen = CPU_TO_LE16(msglen); 4724 } 4725 if (!cmd_details) { 4726 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 4727 details.async = TRUE; 4728 cmd_details = &details; 4729 } 4730 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 4731 msglen, cmd_details); 4732 return status; 4733 } 4734 4735 /** 4736 * i40e_vf_parse_hw_config 4737 * @hw: pointer to the hardware structure 4738 * @msg: pointer to the virtual channel VF resource structure 4739 * 4740 * Given a VF resource message from the PF, populate the hw struct 4741 * with appropriate information. 4742 **/ 4743 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 4744 struct i40e_virtchnl_vf_resource *msg) 4745 { 4746 struct i40e_virtchnl_vsi_resource *vsi_res; 4747 int i; 4748 4749 vsi_res = &msg->vsi_res[0]; 4750 4751 hw->dev_caps.num_vsis = msg->num_vsis; 4752 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 4753 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 4754 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 4755 hw->dev_caps.dcb = msg->vf_offload_flags & 4756 I40E_VIRTCHNL_VF_OFFLOAD_L2; 4757 hw->dev_caps.fcoe = (msg->vf_offload_flags & 4758 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0; 4759 hw->dev_caps.iwarp = (msg->vf_offload_flags & 4760 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 4761 for (i = 0; i < msg->num_vsis; i++) { 4762 if (vsi_res->vsi_type == I40E_VSI_SRIOV) { 4763 i40e_memcpy(hw->mac.perm_addr, 4764 vsi_res->default_mac_addr, 4765 I40E_ETH_LENGTH_OF_ADDRESS, 4766 I40E_NONDMA_TO_NONDMA); 4767 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 4768 I40E_ETH_LENGTH_OF_ADDRESS, 4769 I40E_NONDMA_TO_NONDMA); 4770 } 4771 vsi_res++; 4772 } 4773 } 4774 4775 /** 4776 * i40e_vf_reset 4777 * @hw: pointer to the hardware structure 4778 * 4779 * Send a VF_RESET message to the PF. Does not wait for response from PF 4780 * as none will be forthcoming. Immediately after calling this function, 4781 * the admin queue should be shut down and (optionally) reinitialized. 4782 **/ 4783 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 4784 { 4785 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF, 4786 I40E_SUCCESS, NULL, 0, NULL); 4787 } 4788