1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "i40e_virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 hw->mac.type = I40E_MAC_XL710; 68 break; 69 case I40E_DEV_ID_VF: 70 case I40E_DEV_ID_VF_HV: 71 hw->mac.type = I40E_MAC_VF; 72 break; 73 default: 74 hw->mac.type = I40E_MAC_GENERIC; 75 break; 76 } 77 } else { 78 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 79 } 80 81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 82 hw->mac.type, status); 83 return status; 84 } 85 86 /** 87 * i40e_aq_str - convert AQ err code to a string 88 * @hw: pointer to the HW structure 89 * @aq_err: the AQ error code to convert 90 **/ 91 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 92 { 93 switch (aq_err) { 94 case I40E_AQ_RC_OK: 95 return "OK"; 96 case I40E_AQ_RC_EPERM: 97 return "I40E_AQ_RC_EPERM"; 98 case I40E_AQ_RC_ENOENT: 99 return "I40E_AQ_RC_ENOENT"; 100 case I40E_AQ_RC_ESRCH: 101 return "I40E_AQ_RC_ESRCH"; 102 case I40E_AQ_RC_EINTR: 103 return "I40E_AQ_RC_EINTR"; 104 case I40E_AQ_RC_EIO: 105 return "I40E_AQ_RC_EIO"; 106 case I40E_AQ_RC_ENXIO: 107 return "I40E_AQ_RC_ENXIO"; 108 case I40E_AQ_RC_E2BIG: 109 return "I40E_AQ_RC_E2BIG"; 110 case I40E_AQ_RC_EAGAIN: 111 return "I40E_AQ_RC_EAGAIN"; 112 case I40E_AQ_RC_ENOMEM: 113 return "I40E_AQ_RC_ENOMEM"; 114 case I40E_AQ_RC_EACCES: 115 return "I40E_AQ_RC_EACCES"; 116 case I40E_AQ_RC_EFAULT: 117 return "I40E_AQ_RC_EFAULT"; 118 case I40E_AQ_RC_EBUSY: 119 return "I40E_AQ_RC_EBUSY"; 120 case I40E_AQ_RC_EEXIST: 121 return "I40E_AQ_RC_EEXIST"; 122 case I40E_AQ_RC_EINVAL: 123 return "I40E_AQ_RC_EINVAL"; 124 case I40E_AQ_RC_ENOTTY: 125 return "I40E_AQ_RC_ENOTTY"; 126 case I40E_AQ_RC_ENOSPC: 127 return "I40E_AQ_RC_ENOSPC"; 128 case I40E_AQ_RC_ENOSYS: 129 return "I40E_AQ_RC_ENOSYS"; 130 case I40E_AQ_RC_ERANGE: 131 return "I40E_AQ_RC_ERANGE"; 132 case I40E_AQ_RC_EFLUSHED: 133 return "I40E_AQ_RC_EFLUSHED"; 134 case I40E_AQ_RC_BAD_ADDR: 135 return "I40E_AQ_RC_BAD_ADDR"; 136 case I40E_AQ_RC_EMODE: 137 return "I40E_AQ_RC_EMODE"; 138 case I40E_AQ_RC_EFBIG: 139 return "I40E_AQ_RC_EFBIG"; 140 } 141 142 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 143 return hw->err_str; 144 } 145 146 /** 147 * i40e_stat_str - convert status err code to a string 148 * @hw: pointer to the HW structure 149 * @stat_err: the status error code to convert 150 **/ 151 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 152 { 153 switch (stat_err) { 154 case I40E_SUCCESS: 155 return "OK"; 156 case I40E_ERR_NVM: 157 return "I40E_ERR_NVM"; 158 case I40E_ERR_NVM_CHECKSUM: 159 return "I40E_ERR_NVM_CHECKSUM"; 160 case I40E_ERR_PHY: 161 return "I40E_ERR_PHY"; 162 case I40E_ERR_CONFIG: 163 return "I40E_ERR_CONFIG"; 164 case I40E_ERR_PARAM: 165 return "I40E_ERR_PARAM"; 166 case I40E_ERR_MAC_TYPE: 167 return "I40E_ERR_MAC_TYPE"; 168 case I40E_ERR_UNKNOWN_PHY: 169 return "I40E_ERR_UNKNOWN_PHY"; 170 case I40E_ERR_LINK_SETUP: 171 return "I40E_ERR_LINK_SETUP"; 172 case I40E_ERR_ADAPTER_STOPPED: 173 return "I40E_ERR_ADAPTER_STOPPED"; 174 case I40E_ERR_INVALID_MAC_ADDR: 175 return "I40E_ERR_INVALID_MAC_ADDR"; 176 case I40E_ERR_DEVICE_NOT_SUPPORTED: 177 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 178 case I40E_ERR_MASTER_REQUESTS_PENDING: 179 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 180 case I40E_ERR_INVALID_LINK_SETTINGS: 181 return "I40E_ERR_INVALID_LINK_SETTINGS"; 182 case I40E_ERR_AUTONEG_NOT_COMPLETE: 183 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 184 case I40E_ERR_RESET_FAILED: 185 return "I40E_ERR_RESET_FAILED"; 186 case I40E_ERR_SWFW_SYNC: 187 return "I40E_ERR_SWFW_SYNC"; 188 case I40E_ERR_NO_AVAILABLE_VSI: 189 return "I40E_ERR_NO_AVAILABLE_VSI"; 190 case I40E_ERR_NO_MEMORY: 191 return "I40E_ERR_NO_MEMORY"; 192 case I40E_ERR_BAD_PTR: 193 return "I40E_ERR_BAD_PTR"; 194 case I40E_ERR_RING_FULL: 195 return "I40E_ERR_RING_FULL"; 196 case I40E_ERR_INVALID_PD_ID: 197 return "I40E_ERR_INVALID_PD_ID"; 198 case I40E_ERR_INVALID_QP_ID: 199 return "I40E_ERR_INVALID_QP_ID"; 200 case I40E_ERR_INVALID_CQ_ID: 201 return "I40E_ERR_INVALID_CQ_ID"; 202 case I40E_ERR_INVALID_CEQ_ID: 203 return "I40E_ERR_INVALID_CEQ_ID"; 204 case I40E_ERR_INVALID_AEQ_ID: 205 return "I40E_ERR_INVALID_AEQ_ID"; 206 case I40E_ERR_INVALID_SIZE: 207 return "I40E_ERR_INVALID_SIZE"; 208 case I40E_ERR_INVALID_ARP_INDEX: 209 return "I40E_ERR_INVALID_ARP_INDEX"; 210 case I40E_ERR_INVALID_FPM_FUNC_ID: 211 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 212 case I40E_ERR_QP_INVALID_MSG_SIZE: 213 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 214 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 215 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 216 case I40E_ERR_INVALID_FRAG_COUNT: 217 return "I40E_ERR_INVALID_FRAG_COUNT"; 218 case I40E_ERR_QUEUE_EMPTY: 219 return "I40E_ERR_QUEUE_EMPTY"; 220 case I40E_ERR_INVALID_ALIGNMENT: 221 return "I40E_ERR_INVALID_ALIGNMENT"; 222 case I40E_ERR_FLUSHED_QUEUE: 223 return "I40E_ERR_FLUSHED_QUEUE"; 224 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 225 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 226 case I40E_ERR_INVALID_IMM_DATA_SIZE: 227 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 228 case I40E_ERR_TIMEOUT: 229 return "I40E_ERR_TIMEOUT"; 230 case I40E_ERR_OPCODE_MISMATCH: 231 return "I40E_ERR_OPCODE_MISMATCH"; 232 case I40E_ERR_CQP_COMPL_ERROR: 233 return "I40E_ERR_CQP_COMPL_ERROR"; 234 case I40E_ERR_INVALID_VF_ID: 235 return "I40E_ERR_INVALID_VF_ID"; 236 case I40E_ERR_INVALID_HMCFN_ID: 237 return "I40E_ERR_INVALID_HMCFN_ID"; 238 case I40E_ERR_BACKING_PAGE_ERROR: 239 return "I40E_ERR_BACKING_PAGE_ERROR"; 240 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 241 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 242 case I40E_ERR_INVALID_PBLE_INDEX: 243 return "I40E_ERR_INVALID_PBLE_INDEX"; 244 case I40E_ERR_INVALID_SD_INDEX: 245 return "I40E_ERR_INVALID_SD_INDEX"; 246 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 247 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 248 case I40E_ERR_INVALID_SD_TYPE: 249 return "I40E_ERR_INVALID_SD_TYPE"; 250 case I40E_ERR_MEMCPY_FAILED: 251 return "I40E_ERR_MEMCPY_FAILED"; 252 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 253 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 254 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 255 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 256 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 257 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 258 case I40E_ERR_SRQ_ENABLED: 259 return "I40E_ERR_SRQ_ENABLED"; 260 case I40E_ERR_ADMIN_QUEUE_ERROR: 261 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 262 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 263 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 264 case I40E_ERR_BUF_TOO_SHORT: 265 return "I40E_ERR_BUF_TOO_SHORT"; 266 case I40E_ERR_ADMIN_QUEUE_FULL: 267 return "I40E_ERR_ADMIN_QUEUE_FULL"; 268 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 269 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 270 case I40E_ERR_BAD_IWARP_CQE: 271 return "I40E_ERR_BAD_IWARP_CQE"; 272 case I40E_ERR_NVM_BLANK_MODE: 273 return "I40E_ERR_NVM_BLANK_MODE"; 274 case I40E_ERR_NOT_IMPLEMENTED: 275 return "I40E_ERR_NOT_IMPLEMENTED"; 276 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 277 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 278 case I40E_ERR_DIAG_TEST_FAILED: 279 return "I40E_ERR_DIAG_TEST_FAILED"; 280 case I40E_ERR_NOT_READY: 281 return "I40E_ERR_NOT_READY"; 282 case I40E_NOT_SUPPORTED: 283 return "I40E_NOT_SUPPORTED"; 284 case I40E_ERR_FIRMWARE_API_VERSION: 285 return "I40E_ERR_FIRMWARE_API_VERSION"; 286 } 287 288 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 289 return hw->err_str; 290 } 291 292 /** 293 * i40e_debug_aq 294 * @hw: debug mask related to admin queue 295 * @mask: debug mask 296 * @desc: pointer to admin queue descriptor 297 * @buffer: pointer to command buffer 298 * @buf_len: max length of buffer 299 * 300 * Dumps debug log about adminq command with descriptor contents. 301 **/ 302 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 303 void *buffer, u16 buf_len) 304 { 305 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 306 u16 len = LE16_TO_CPU(aq_desc->datalen); 307 u8 *buf = (u8 *)buffer; 308 u16 i = 0; 309 310 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 311 return; 312 313 i40e_debug(hw, mask, 314 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 315 LE16_TO_CPU(aq_desc->opcode), 316 LE16_TO_CPU(aq_desc->flags), 317 LE16_TO_CPU(aq_desc->datalen), 318 LE16_TO_CPU(aq_desc->retval)); 319 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 320 LE32_TO_CPU(aq_desc->cookie_high), 321 LE32_TO_CPU(aq_desc->cookie_low)); 322 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 323 LE32_TO_CPU(aq_desc->params.internal.param0), 324 LE32_TO_CPU(aq_desc->params.internal.param1)); 325 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 326 LE32_TO_CPU(aq_desc->params.external.addr_high), 327 LE32_TO_CPU(aq_desc->params.external.addr_low)); 328 329 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 330 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 331 if (buf_len < len) 332 len = buf_len; 333 /* write the full 16-byte chunks */ 334 for (i = 0; i < (len - 16); i += 16) 335 i40e_debug(hw, mask, 336 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 337 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 338 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 339 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 340 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 341 /* the most we could have left is 16 bytes, pad with zeros */ 342 if (i < len) { 343 char d_buf[16]; 344 int j; 345 346 memset(d_buf, 0, sizeof(d_buf)); 347 for (j = 0; i < len; j++, i++) 348 d_buf[j] = buf[i]; 349 i40e_debug(hw, mask, 350 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 351 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 352 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 353 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 354 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 355 } 356 } 357 } 358 359 /** 360 * i40e_check_asq_alive 361 * @hw: pointer to the hw struct 362 * 363 * Returns TRUE if Queue is enabled else FALSE. 364 **/ 365 bool i40e_check_asq_alive(struct i40e_hw *hw) 366 { 367 if (hw->aq.asq.len) 368 if (!i40e_is_vf(hw)) 369 return !!(rd32(hw, hw->aq.asq.len) & 370 I40E_PF_ATQLEN_ATQENABLE_MASK); 371 if (i40e_is_vf(hw)) 372 return !!(rd32(hw, hw->aq.asq.len) & 373 I40E_VF_ATQLEN1_ATQENABLE_MASK); 374 return FALSE; 375 } 376 377 /** 378 * i40e_aq_queue_shutdown 379 * @hw: pointer to the hw struct 380 * @unloading: is the driver unloading itself 381 * 382 * Tell the Firmware that we're shutting down the AdminQ and whether 383 * or not the driver is unloading as well. 384 **/ 385 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 386 bool unloading) 387 { 388 struct i40e_aq_desc desc; 389 struct i40e_aqc_queue_shutdown *cmd = 390 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 391 enum i40e_status_code status; 392 393 i40e_fill_default_direct_cmd_desc(&desc, 394 i40e_aqc_opc_queue_shutdown); 395 396 if (unloading) 397 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 398 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 399 400 return status; 401 } 402 403 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 404 * hardware to a bit-field that can be used by SW to more easily determine the 405 * packet type. 406 * 407 * Macros are used to shorten the table lines and make this table human 408 * readable. 409 * 410 * We store the PTYPE in the top byte of the bit field - this is just so that 411 * we can check that the table doesn't have a row missing, as the index into 412 * the table should be the PTYPE. 413 * 414 * Typical work flow: 415 * 416 * IF NOT i40e_ptype_lookup[ptype].known 417 * THEN 418 * Packet is unknown 419 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 420 * Use the rest of the fields to look at the tunnels, inner protocols, etc 421 * ELSE 422 * Use the enum i40e_rx_l2_ptype to decode the packet type 423 * ENDIF 424 */ 425 426 /* macro to make the table lines short */ 427 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 428 { PTYPE, \ 429 1, \ 430 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 431 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 432 I40E_RX_PTYPE_##OUTER_FRAG, \ 433 I40E_RX_PTYPE_TUNNEL_##T, \ 434 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 435 I40E_RX_PTYPE_##TEF, \ 436 I40E_RX_PTYPE_INNER_PROT_##I, \ 437 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 438 439 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 440 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 441 442 /* shorter macros makes the table fit but are terse */ 443 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 444 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 445 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 446 447 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 448 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 449 /* L2 Packet types */ 450 I40E_PTT_UNUSED_ENTRY(0), 451 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 452 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 453 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 454 I40E_PTT_UNUSED_ENTRY(4), 455 I40E_PTT_UNUSED_ENTRY(5), 456 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 457 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 458 I40E_PTT_UNUSED_ENTRY(8), 459 I40E_PTT_UNUSED_ENTRY(9), 460 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 461 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 462 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 463 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 464 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 465 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 466 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 467 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 468 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 469 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 470 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 471 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 472 473 /* Non Tunneled IPv4 */ 474 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 475 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 476 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 477 I40E_PTT_UNUSED_ENTRY(25), 478 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 479 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 480 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 481 482 /* IPv4 --> IPv4 */ 483 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 484 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 485 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 486 I40E_PTT_UNUSED_ENTRY(32), 487 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 488 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 489 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 490 491 /* IPv4 --> IPv6 */ 492 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 493 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 494 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 495 I40E_PTT_UNUSED_ENTRY(39), 496 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 497 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 498 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 499 500 /* IPv4 --> GRE/NAT */ 501 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 502 503 /* IPv4 --> GRE/NAT --> IPv4 */ 504 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 505 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 506 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 507 I40E_PTT_UNUSED_ENTRY(47), 508 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 509 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 510 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 511 512 /* IPv4 --> GRE/NAT --> IPv6 */ 513 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 514 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 515 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 516 I40E_PTT_UNUSED_ENTRY(54), 517 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 518 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 519 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 520 521 /* IPv4 --> GRE/NAT --> MAC */ 522 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 523 524 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 525 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 526 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 527 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 528 I40E_PTT_UNUSED_ENTRY(62), 529 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 530 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 531 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 532 533 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 534 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 535 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 536 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 537 I40E_PTT_UNUSED_ENTRY(69), 538 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 539 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 540 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 541 542 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 543 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 544 545 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 546 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 547 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 548 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 549 I40E_PTT_UNUSED_ENTRY(77), 550 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 551 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 552 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 553 554 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 555 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 556 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 557 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 558 I40E_PTT_UNUSED_ENTRY(84), 559 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 560 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 561 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 562 563 /* Non Tunneled IPv6 */ 564 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 565 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 566 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 567 I40E_PTT_UNUSED_ENTRY(91), 568 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 569 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 570 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 571 572 /* IPv6 --> IPv4 */ 573 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 574 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 575 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 576 I40E_PTT_UNUSED_ENTRY(98), 577 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 578 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 579 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 580 581 /* IPv6 --> IPv6 */ 582 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 583 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 584 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 585 I40E_PTT_UNUSED_ENTRY(105), 586 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 587 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 588 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 589 590 /* IPv6 --> GRE/NAT */ 591 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 592 593 /* IPv6 --> GRE/NAT -> IPv4 */ 594 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 595 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 596 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 597 I40E_PTT_UNUSED_ENTRY(113), 598 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 599 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 600 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 601 602 /* IPv6 --> GRE/NAT -> IPv6 */ 603 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 604 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 605 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 606 I40E_PTT_UNUSED_ENTRY(120), 607 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 608 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 609 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 610 611 /* IPv6 --> GRE/NAT -> MAC */ 612 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 613 614 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 615 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 616 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 617 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 618 I40E_PTT_UNUSED_ENTRY(128), 619 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 620 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 621 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 622 623 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 624 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 625 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 626 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 627 I40E_PTT_UNUSED_ENTRY(135), 628 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 629 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 630 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 631 632 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 633 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 634 635 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 636 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 637 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 638 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 639 I40E_PTT_UNUSED_ENTRY(143), 640 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 641 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 642 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 643 644 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 645 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 646 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 647 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(150), 649 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 650 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 651 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 652 653 /* unused entries */ 654 I40E_PTT_UNUSED_ENTRY(154), 655 I40E_PTT_UNUSED_ENTRY(155), 656 I40E_PTT_UNUSED_ENTRY(156), 657 I40E_PTT_UNUSED_ENTRY(157), 658 I40E_PTT_UNUSED_ENTRY(158), 659 I40E_PTT_UNUSED_ENTRY(159), 660 661 I40E_PTT_UNUSED_ENTRY(160), 662 I40E_PTT_UNUSED_ENTRY(161), 663 I40E_PTT_UNUSED_ENTRY(162), 664 I40E_PTT_UNUSED_ENTRY(163), 665 I40E_PTT_UNUSED_ENTRY(164), 666 I40E_PTT_UNUSED_ENTRY(165), 667 I40E_PTT_UNUSED_ENTRY(166), 668 I40E_PTT_UNUSED_ENTRY(167), 669 I40E_PTT_UNUSED_ENTRY(168), 670 I40E_PTT_UNUSED_ENTRY(169), 671 672 I40E_PTT_UNUSED_ENTRY(170), 673 I40E_PTT_UNUSED_ENTRY(171), 674 I40E_PTT_UNUSED_ENTRY(172), 675 I40E_PTT_UNUSED_ENTRY(173), 676 I40E_PTT_UNUSED_ENTRY(174), 677 I40E_PTT_UNUSED_ENTRY(175), 678 I40E_PTT_UNUSED_ENTRY(176), 679 I40E_PTT_UNUSED_ENTRY(177), 680 I40E_PTT_UNUSED_ENTRY(178), 681 I40E_PTT_UNUSED_ENTRY(179), 682 683 I40E_PTT_UNUSED_ENTRY(180), 684 I40E_PTT_UNUSED_ENTRY(181), 685 I40E_PTT_UNUSED_ENTRY(182), 686 I40E_PTT_UNUSED_ENTRY(183), 687 I40E_PTT_UNUSED_ENTRY(184), 688 I40E_PTT_UNUSED_ENTRY(185), 689 I40E_PTT_UNUSED_ENTRY(186), 690 I40E_PTT_UNUSED_ENTRY(187), 691 I40E_PTT_UNUSED_ENTRY(188), 692 I40E_PTT_UNUSED_ENTRY(189), 693 694 I40E_PTT_UNUSED_ENTRY(190), 695 I40E_PTT_UNUSED_ENTRY(191), 696 I40E_PTT_UNUSED_ENTRY(192), 697 I40E_PTT_UNUSED_ENTRY(193), 698 I40E_PTT_UNUSED_ENTRY(194), 699 I40E_PTT_UNUSED_ENTRY(195), 700 I40E_PTT_UNUSED_ENTRY(196), 701 I40E_PTT_UNUSED_ENTRY(197), 702 I40E_PTT_UNUSED_ENTRY(198), 703 I40E_PTT_UNUSED_ENTRY(199), 704 705 I40E_PTT_UNUSED_ENTRY(200), 706 I40E_PTT_UNUSED_ENTRY(201), 707 I40E_PTT_UNUSED_ENTRY(202), 708 I40E_PTT_UNUSED_ENTRY(203), 709 I40E_PTT_UNUSED_ENTRY(204), 710 I40E_PTT_UNUSED_ENTRY(205), 711 I40E_PTT_UNUSED_ENTRY(206), 712 I40E_PTT_UNUSED_ENTRY(207), 713 I40E_PTT_UNUSED_ENTRY(208), 714 I40E_PTT_UNUSED_ENTRY(209), 715 716 I40E_PTT_UNUSED_ENTRY(210), 717 I40E_PTT_UNUSED_ENTRY(211), 718 I40E_PTT_UNUSED_ENTRY(212), 719 I40E_PTT_UNUSED_ENTRY(213), 720 I40E_PTT_UNUSED_ENTRY(214), 721 I40E_PTT_UNUSED_ENTRY(215), 722 I40E_PTT_UNUSED_ENTRY(216), 723 I40E_PTT_UNUSED_ENTRY(217), 724 I40E_PTT_UNUSED_ENTRY(218), 725 I40E_PTT_UNUSED_ENTRY(219), 726 727 I40E_PTT_UNUSED_ENTRY(220), 728 I40E_PTT_UNUSED_ENTRY(221), 729 I40E_PTT_UNUSED_ENTRY(222), 730 I40E_PTT_UNUSED_ENTRY(223), 731 I40E_PTT_UNUSED_ENTRY(224), 732 I40E_PTT_UNUSED_ENTRY(225), 733 I40E_PTT_UNUSED_ENTRY(226), 734 I40E_PTT_UNUSED_ENTRY(227), 735 I40E_PTT_UNUSED_ENTRY(228), 736 I40E_PTT_UNUSED_ENTRY(229), 737 738 I40E_PTT_UNUSED_ENTRY(230), 739 I40E_PTT_UNUSED_ENTRY(231), 740 I40E_PTT_UNUSED_ENTRY(232), 741 I40E_PTT_UNUSED_ENTRY(233), 742 I40E_PTT_UNUSED_ENTRY(234), 743 I40E_PTT_UNUSED_ENTRY(235), 744 I40E_PTT_UNUSED_ENTRY(236), 745 I40E_PTT_UNUSED_ENTRY(237), 746 I40E_PTT_UNUSED_ENTRY(238), 747 I40E_PTT_UNUSED_ENTRY(239), 748 749 I40E_PTT_UNUSED_ENTRY(240), 750 I40E_PTT_UNUSED_ENTRY(241), 751 I40E_PTT_UNUSED_ENTRY(242), 752 I40E_PTT_UNUSED_ENTRY(243), 753 I40E_PTT_UNUSED_ENTRY(244), 754 I40E_PTT_UNUSED_ENTRY(245), 755 I40E_PTT_UNUSED_ENTRY(246), 756 I40E_PTT_UNUSED_ENTRY(247), 757 I40E_PTT_UNUSED_ENTRY(248), 758 I40E_PTT_UNUSED_ENTRY(249), 759 760 I40E_PTT_UNUSED_ENTRY(250), 761 I40E_PTT_UNUSED_ENTRY(251), 762 I40E_PTT_UNUSED_ENTRY(252), 763 I40E_PTT_UNUSED_ENTRY(253), 764 I40E_PTT_UNUSED_ENTRY(254), 765 I40E_PTT_UNUSED_ENTRY(255) 766 }; 767 768 769 /** 770 * i40e_validate_mac_addr - Validate unicast MAC address 771 * @mac_addr: pointer to MAC address 772 * 773 * Tests a MAC address to ensure it is a valid Individual Address 774 **/ 775 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 776 { 777 enum i40e_status_code status = I40E_SUCCESS; 778 779 DEBUGFUNC("i40e_validate_mac_addr"); 780 781 /* Broadcast addresses ARE multicast addresses 782 * Make sure it is not a multicast address 783 * Reject the zero address 784 */ 785 if (I40E_IS_MULTICAST(mac_addr) || 786 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 787 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 788 status = I40E_ERR_INVALID_MAC_ADDR; 789 790 return status; 791 } 792 793 /** 794 * i40e_init_shared_code - Initialize the shared code 795 * @hw: pointer to hardware structure 796 * 797 * This assigns the MAC type and PHY code and inits the NVM. 798 * Does not touch the hardware. This function must be called prior to any 799 * other function in the shared code. The i40e_hw structure should be 800 * memset to 0 prior to calling this function. The following fields in 801 * hw structure should be filled in prior to calling this function: 802 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 803 * subsystem_vendor_id, and revision_id 804 **/ 805 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 806 { 807 enum i40e_status_code status = I40E_SUCCESS; 808 u32 port, ari, func_rid; 809 810 DEBUGFUNC("i40e_init_shared_code"); 811 812 i40e_set_mac_type(hw); 813 814 switch (hw->mac.type) { 815 case I40E_MAC_XL710: 816 break; 817 default: 818 return I40E_ERR_DEVICE_NOT_SUPPORTED; 819 } 820 821 hw->phy.get_link_info = TRUE; 822 823 /* Determine port number and PF number*/ 824 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 825 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 826 hw->port = (u8)port; 827 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 828 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 829 func_rid = rd32(hw, I40E_PF_FUNC_RID); 830 if (ari) 831 hw->pf_id = (u8)(func_rid & 0xff); 832 else 833 hw->pf_id = (u8)(func_rid & 0x7); 834 835 status = i40e_init_nvm(hw); 836 return status; 837 } 838 839 /** 840 * i40e_aq_mac_address_read - Retrieve the MAC addresses 841 * @hw: pointer to the hw struct 842 * @flags: a return indicator of what addresses were added to the addr store 843 * @addrs: the requestor's mac addr store 844 * @cmd_details: pointer to command details structure or NULL 845 **/ 846 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 847 u16 *flags, 848 struct i40e_aqc_mac_address_read_data *addrs, 849 struct i40e_asq_cmd_details *cmd_details) 850 { 851 struct i40e_aq_desc desc; 852 struct i40e_aqc_mac_address_read *cmd_data = 853 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 854 enum i40e_status_code status; 855 856 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 857 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 858 859 status = i40e_asq_send_command(hw, &desc, addrs, 860 sizeof(*addrs), cmd_details); 861 *flags = LE16_TO_CPU(cmd_data->command_flags); 862 863 return status; 864 } 865 866 /** 867 * i40e_aq_mac_address_write - Change the MAC addresses 868 * @hw: pointer to the hw struct 869 * @flags: indicates which MAC to be written 870 * @mac_addr: address to write 871 * @cmd_details: pointer to command details structure or NULL 872 **/ 873 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 874 u16 flags, u8 *mac_addr, 875 struct i40e_asq_cmd_details *cmd_details) 876 { 877 struct i40e_aq_desc desc; 878 struct i40e_aqc_mac_address_write *cmd_data = 879 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 880 enum i40e_status_code status; 881 882 i40e_fill_default_direct_cmd_desc(&desc, 883 i40e_aqc_opc_mac_address_write); 884 cmd_data->command_flags = CPU_TO_LE16(flags); 885 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 886 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 887 ((u32)mac_addr[3] << 16) | 888 ((u32)mac_addr[4] << 8) | 889 mac_addr[5]); 890 891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 892 893 return status; 894 } 895 896 /** 897 * i40e_get_mac_addr - get MAC address 898 * @hw: pointer to the HW structure 899 * @mac_addr: pointer to MAC address 900 * 901 * Reads the adapter's MAC address from register 902 **/ 903 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 904 { 905 struct i40e_aqc_mac_address_read_data addrs; 906 enum i40e_status_code status; 907 u16 flags = 0; 908 909 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 910 911 if (flags & I40E_AQC_LAN_ADDR_VALID) 912 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 913 914 return status; 915 } 916 917 /** 918 * i40e_get_port_mac_addr - get Port MAC address 919 * @hw: pointer to the HW structure 920 * @mac_addr: pointer to Port MAC address 921 * 922 * Reads the adapter's Port MAC address 923 **/ 924 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 925 { 926 struct i40e_aqc_mac_address_read_data addrs; 927 enum i40e_status_code status; 928 u16 flags = 0; 929 930 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 931 if (status) 932 return status; 933 934 if (flags & I40E_AQC_PORT_ADDR_VALID) 935 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 936 else 937 status = I40E_ERR_INVALID_MAC_ADDR; 938 939 return status; 940 } 941 942 /** 943 * i40e_pre_tx_queue_cfg - pre tx queue configure 944 * @hw: pointer to the HW structure 945 * @queue: target pf queue index 946 * @enable: state change request 947 * 948 * Handles hw requirement to indicate intention to enable 949 * or disable target queue. 950 **/ 951 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 952 { 953 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 954 u32 reg_block = 0; 955 u32 reg_val; 956 957 if (abs_queue_idx >= 128) { 958 reg_block = abs_queue_idx / 128; 959 abs_queue_idx %= 128; 960 } 961 962 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 963 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 964 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 965 966 if (enable) 967 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 968 else 969 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 970 971 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 972 } 973 974 /** 975 * i40e_read_pba_string - Reads part number string from EEPROM 976 * @hw: pointer to hardware structure 977 * @pba_num: stores the part number string from the EEPROM 978 * @pba_num_size: part number string buffer length 979 * 980 * Reads the part number string from the EEPROM. 981 **/ 982 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 983 u32 pba_num_size) 984 { 985 enum i40e_status_code status = I40E_SUCCESS; 986 u16 pba_word = 0; 987 u16 pba_size = 0; 988 u16 pba_ptr = 0; 989 u16 i = 0; 990 991 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 992 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 993 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 994 return status; 995 } 996 997 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 998 if (status != I40E_SUCCESS) { 999 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1000 return status; 1001 } 1002 1003 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1004 if (status != I40E_SUCCESS) { 1005 DEBUGOUT("Failed to read PBA Block size.\n"); 1006 return status; 1007 } 1008 1009 /* Subtract one to get PBA word count (PBA Size word is included in 1010 * total size) 1011 */ 1012 pba_size--; 1013 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1014 DEBUGOUT("Buffer to small for PBA data.\n"); 1015 return I40E_ERR_PARAM; 1016 } 1017 1018 for (i = 0; i < pba_size; i++) { 1019 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1020 if (status != I40E_SUCCESS) { 1021 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1022 return status; 1023 } 1024 1025 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1026 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1027 } 1028 pba_num[(pba_size * 2)] = '\0'; 1029 1030 return status; 1031 } 1032 1033 /** 1034 * i40e_get_media_type - Gets media type 1035 * @hw: pointer to the hardware structure 1036 **/ 1037 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1038 { 1039 enum i40e_media_type media; 1040 1041 switch (hw->phy.link_info.phy_type) { 1042 case I40E_PHY_TYPE_10GBASE_SR: 1043 case I40E_PHY_TYPE_10GBASE_LR: 1044 case I40E_PHY_TYPE_1000BASE_SX: 1045 case I40E_PHY_TYPE_1000BASE_LX: 1046 case I40E_PHY_TYPE_40GBASE_SR4: 1047 case I40E_PHY_TYPE_40GBASE_LR4: 1048 media = I40E_MEDIA_TYPE_FIBER; 1049 break; 1050 case I40E_PHY_TYPE_100BASE_TX: 1051 case I40E_PHY_TYPE_1000BASE_T: 1052 case I40E_PHY_TYPE_10GBASE_T: 1053 media = I40E_MEDIA_TYPE_BASET; 1054 break; 1055 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1056 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1057 case I40E_PHY_TYPE_10GBASE_CR1: 1058 case I40E_PHY_TYPE_40GBASE_CR4: 1059 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1060 case I40E_PHY_TYPE_40GBASE_AOC: 1061 case I40E_PHY_TYPE_10GBASE_AOC: 1062 media = I40E_MEDIA_TYPE_DA; 1063 break; 1064 case I40E_PHY_TYPE_1000BASE_KX: 1065 case I40E_PHY_TYPE_10GBASE_KX4: 1066 case I40E_PHY_TYPE_10GBASE_KR: 1067 case I40E_PHY_TYPE_40GBASE_KR4: 1068 case I40E_PHY_TYPE_20GBASE_KR2: 1069 media = I40E_MEDIA_TYPE_BACKPLANE; 1070 break; 1071 case I40E_PHY_TYPE_SGMII: 1072 case I40E_PHY_TYPE_XAUI: 1073 case I40E_PHY_TYPE_XFI: 1074 case I40E_PHY_TYPE_XLAUI: 1075 case I40E_PHY_TYPE_XLPPI: 1076 default: 1077 media = I40E_MEDIA_TYPE_UNKNOWN; 1078 break; 1079 } 1080 1081 return media; 1082 } 1083 1084 #define I40E_PF_RESET_WAIT_COUNT 200 1085 /** 1086 * i40e_pf_reset - Reset the PF 1087 * @hw: pointer to the hardware structure 1088 * 1089 * Assuming someone else has triggered a global reset, 1090 * assure the global reset is complete and then reset the PF 1091 **/ 1092 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1093 { 1094 u32 cnt = 0; 1095 u32 cnt1 = 0; 1096 u32 reg = 0; 1097 u32 grst_del; 1098 1099 /* Poll for Global Reset steady state in case of recent GRST. 1100 * The grst delay value is in 100ms units, and we'll wait a 1101 * couple counts longer to be sure we don't just miss the end. 1102 */ 1103 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1104 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1105 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1106 1107 /* It can take upto 15 secs for GRST steady state */ 1108 grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */ 1109 1110 for (cnt = 0; cnt < grst_del; cnt++) { 1111 reg = rd32(hw, I40E_GLGEN_RSTAT); 1112 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1113 break; 1114 i40e_msec_delay(100); 1115 } 1116 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1117 DEBUGOUT("Global reset polling failed to complete.\n"); 1118 return I40E_ERR_RESET_FAILED; 1119 } 1120 1121 /* Now Wait for the FW to be ready */ 1122 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1123 reg = rd32(hw, I40E_GLNVM_ULD); 1124 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1125 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1126 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1127 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1128 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1129 break; 1130 } 1131 i40e_msec_delay(10); 1132 } 1133 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1134 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1135 DEBUGOUT("wait for FW Reset complete timedout\n"); 1136 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1137 return I40E_ERR_RESET_FAILED; 1138 } 1139 1140 /* If there was a Global Reset in progress when we got here, 1141 * we don't need to do the PF Reset 1142 */ 1143 if (!cnt) { 1144 reg = rd32(hw, I40E_PFGEN_CTRL); 1145 wr32(hw, I40E_PFGEN_CTRL, 1146 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1147 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1148 reg = rd32(hw, I40E_PFGEN_CTRL); 1149 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1150 break; 1151 i40e_msec_delay(1); 1152 } 1153 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1154 DEBUGOUT("PF reset polling failed to complete.\n"); 1155 return I40E_ERR_RESET_FAILED; 1156 } 1157 } 1158 1159 i40e_clear_pxe_mode(hw); 1160 1161 1162 return I40E_SUCCESS; 1163 } 1164 1165 /** 1166 * i40e_clear_hw - clear out any left over hw state 1167 * @hw: pointer to the hw struct 1168 * 1169 * Clear queues and interrupts, typically called at init time, 1170 * but after the capabilities have been found so we know how many 1171 * queues and msix vectors have been allocated. 1172 **/ 1173 void i40e_clear_hw(struct i40e_hw *hw) 1174 { 1175 u32 num_queues, base_queue; 1176 u32 num_pf_int; 1177 u32 num_vf_int; 1178 u32 num_vfs; 1179 u32 i, j; 1180 u32 val; 1181 u32 eol = 0x7ff; 1182 1183 /* get number of interrupts, queues, and vfs */ 1184 val = rd32(hw, I40E_GLPCI_CNF2); 1185 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1186 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1187 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1188 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1189 1190 val = rd32(hw, I40E_PFLAN_QALLOC); 1191 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1192 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1193 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1194 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1195 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1196 num_queues = (j - base_queue) + 1; 1197 else 1198 num_queues = 0; 1199 1200 val = rd32(hw, I40E_PF_VT_PFALLOC); 1201 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1202 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1203 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1204 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1205 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1206 num_vfs = (j - i) + 1; 1207 else 1208 num_vfs = 0; 1209 1210 /* stop all the interrupts */ 1211 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1212 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1213 for (i = 0; i < num_pf_int - 2; i++) 1214 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1215 1216 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1217 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1218 wr32(hw, I40E_PFINT_LNKLST0, val); 1219 for (i = 0; i < num_pf_int - 2; i++) 1220 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1221 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1222 for (i = 0; i < num_vfs; i++) 1223 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1224 for (i = 0; i < num_vf_int - 2; i++) 1225 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1226 1227 /* warn the HW of the coming Tx disables */ 1228 for (i = 0; i < num_queues; i++) { 1229 u32 abs_queue_idx = base_queue + i; 1230 u32 reg_block = 0; 1231 1232 if (abs_queue_idx >= 128) { 1233 reg_block = abs_queue_idx / 128; 1234 abs_queue_idx %= 128; 1235 } 1236 1237 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1238 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1239 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1240 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1241 1242 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1243 } 1244 i40e_usec_delay(400); 1245 1246 /* stop all the queues */ 1247 for (i = 0; i < num_queues; i++) { 1248 wr32(hw, I40E_QINT_TQCTL(i), 0); 1249 wr32(hw, I40E_QTX_ENA(i), 0); 1250 wr32(hw, I40E_QINT_RQCTL(i), 0); 1251 wr32(hw, I40E_QRX_ENA(i), 0); 1252 } 1253 1254 /* short wait for all queue disables to settle */ 1255 i40e_usec_delay(50); 1256 } 1257 1258 /** 1259 * i40e_clear_pxe_mode - clear pxe operations mode 1260 * @hw: pointer to the hw struct 1261 * 1262 * Make sure all PXE mode settings are cleared, including things 1263 * like descriptor fetch/write-back mode. 1264 **/ 1265 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1266 { 1267 if (i40e_check_asq_alive(hw)) 1268 i40e_aq_clear_pxe_mode(hw, NULL); 1269 } 1270 1271 /** 1272 * i40e_led_is_mine - helper to find matching led 1273 * @hw: pointer to the hw struct 1274 * @idx: index into GPIO registers 1275 * 1276 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1277 */ 1278 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1279 { 1280 u32 gpio_val = 0; 1281 u32 port; 1282 1283 if (!hw->func_caps.led[idx]) 1284 return 0; 1285 1286 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1287 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1288 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1289 1290 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1291 * if it is not our port then ignore 1292 */ 1293 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1294 (port != hw->port)) 1295 return 0; 1296 1297 return gpio_val; 1298 } 1299 1300 #define I40E_COMBINED_ACTIVITY 0xA 1301 #define I40E_FILTER_ACTIVITY 0xE 1302 #define I40E_LINK_ACTIVITY 0xC 1303 #define I40E_MAC_ACTIVITY 0xD 1304 #define I40E_LED0 22 1305 1306 /** 1307 * i40e_led_get - return current on/off mode 1308 * @hw: pointer to the hw struct 1309 * 1310 * The value returned is the 'mode' field as defined in the 1311 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1312 * values are variations of possible behaviors relating to 1313 * blink, link, and wire. 1314 **/ 1315 u32 i40e_led_get(struct i40e_hw *hw) 1316 { 1317 u32 current_mode = 0; 1318 u32 mode = 0; 1319 int i; 1320 1321 /* as per the documentation GPIO 22-29 are the LED 1322 * GPIO pins named LED0..LED7 1323 */ 1324 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1325 u32 gpio_val = i40e_led_is_mine(hw, i); 1326 1327 if (!gpio_val) 1328 continue; 1329 1330 /* ignore gpio LED src mode entries related to the activity 1331 * LEDs 1332 */ 1333 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1334 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1335 switch (current_mode) { 1336 case I40E_COMBINED_ACTIVITY: 1337 case I40E_FILTER_ACTIVITY: 1338 case I40E_MAC_ACTIVITY: 1339 continue; 1340 default: 1341 break; 1342 } 1343 1344 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1345 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1346 break; 1347 } 1348 1349 return mode; 1350 } 1351 1352 /** 1353 * i40e_led_set - set new on/off mode 1354 * @hw: pointer to the hw struct 1355 * @mode: 0=off, 0xf=on (else see manual for mode details) 1356 * @blink: TRUE if the LED should blink when on, FALSE if steady 1357 * 1358 * if this function is used to turn on the blink it should 1359 * be used to disable the blink when restoring the original state. 1360 **/ 1361 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1362 { 1363 u32 current_mode = 0; 1364 int i; 1365 1366 if (mode & 0xfffffff0) 1367 DEBUGOUT1("invalid mode passed in %X\n", mode); 1368 1369 /* as per the documentation GPIO 22-29 are the LED 1370 * GPIO pins named LED0..LED7 1371 */ 1372 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1373 u32 gpio_val = i40e_led_is_mine(hw, i); 1374 1375 if (!gpio_val) 1376 continue; 1377 1378 /* ignore gpio LED src mode entries related to the activity 1379 * LEDs 1380 */ 1381 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1382 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1383 switch (current_mode) { 1384 case I40E_COMBINED_ACTIVITY: 1385 case I40E_FILTER_ACTIVITY: 1386 case I40E_MAC_ACTIVITY: 1387 continue; 1388 default: 1389 break; 1390 } 1391 1392 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1393 /* this & is a bit of paranoia, but serves as a range check */ 1394 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1395 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1396 1397 if (mode == I40E_LINK_ACTIVITY) 1398 blink = FALSE; 1399 1400 if (blink) 1401 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1402 else 1403 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1404 1405 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1406 break; 1407 } 1408 } 1409 1410 /* Admin command wrappers */ 1411 1412 /** 1413 * i40e_aq_get_phy_capabilities 1414 * @hw: pointer to the hw struct 1415 * @abilities: structure for PHY capabilities to be filled 1416 * @qualified_modules: report Qualified Modules 1417 * @report_init: report init capabilities (active are default) 1418 * @cmd_details: pointer to command details structure or NULL 1419 * 1420 * Returns the various PHY abilities supported on the Port. 1421 **/ 1422 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1423 bool qualified_modules, bool report_init, 1424 struct i40e_aq_get_phy_abilities_resp *abilities, 1425 struct i40e_asq_cmd_details *cmd_details) 1426 { 1427 struct i40e_aq_desc desc; 1428 enum i40e_status_code status; 1429 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1430 1431 if (!abilities) 1432 return I40E_ERR_PARAM; 1433 1434 i40e_fill_default_direct_cmd_desc(&desc, 1435 i40e_aqc_opc_get_phy_abilities); 1436 1437 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1438 if (abilities_size > I40E_AQ_LARGE_BUF) 1439 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1440 1441 if (qualified_modules) 1442 desc.params.external.param0 |= 1443 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1444 1445 if (report_init) 1446 desc.params.external.param0 |= 1447 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1448 1449 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1450 cmd_details); 1451 1452 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1453 status = I40E_ERR_UNKNOWN_PHY; 1454 1455 if (report_init) 1456 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1457 1458 return status; 1459 } 1460 1461 /** 1462 * i40e_aq_set_phy_config 1463 * @hw: pointer to the hw struct 1464 * @config: structure with PHY configuration to be set 1465 * @cmd_details: pointer to command details structure or NULL 1466 * 1467 * Set the various PHY configuration parameters 1468 * supported on the Port.One or more of the Set PHY config parameters may be 1469 * ignored in an MFP mode as the PF may not have the privilege to set some 1470 * of the PHY Config parameters. This status will be indicated by the 1471 * command response. 1472 **/ 1473 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1474 struct i40e_aq_set_phy_config *config, 1475 struct i40e_asq_cmd_details *cmd_details) 1476 { 1477 struct i40e_aq_desc desc; 1478 struct i40e_aq_set_phy_config *cmd = 1479 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1480 enum i40e_status_code status; 1481 1482 if (!config) 1483 return I40E_ERR_PARAM; 1484 1485 i40e_fill_default_direct_cmd_desc(&desc, 1486 i40e_aqc_opc_set_phy_config); 1487 1488 *cmd = *config; 1489 1490 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1491 1492 return status; 1493 } 1494 1495 /** 1496 * i40e_set_fc 1497 * @hw: pointer to the hw struct 1498 * 1499 * Set the requested flow control mode using set_phy_config. 1500 **/ 1501 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1502 bool atomic_restart) 1503 { 1504 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1505 struct i40e_aq_get_phy_abilities_resp abilities; 1506 struct i40e_aq_set_phy_config config; 1507 enum i40e_status_code status; 1508 u8 pause_mask = 0x0; 1509 1510 *aq_failures = 0x0; 1511 1512 switch (fc_mode) { 1513 case I40E_FC_FULL: 1514 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1515 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1516 break; 1517 case I40E_FC_RX_PAUSE: 1518 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1519 break; 1520 case I40E_FC_TX_PAUSE: 1521 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 /* Get the current phy config */ 1528 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1529 NULL); 1530 if (status) { 1531 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1532 return status; 1533 } 1534 1535 memset(&config, 0, sizeof(config)); 1536 /* clear the old pause settings */ 1537 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1538 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1539 /* set the new abilities */ 1540 config.abilities |= pause_mask; 1541 /* If the abilities have changed, then set the new config */ 1542 if (config.abilities != abilities.abilities) { 1543 /* Auto restart link so settings take effect */ 1544 if (atomic_restart) 1545 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1546 /* Copy over all the old settings */ 1547 config.phy_type = abilities.phy_type; 1548 config.link_speed = abilities.link_speed; 1549 config.eee_capability = abilities.eee_capability; 1550 config.eeer = abilities.eeer_val; 1551 config.low_power_ctrl = abilities.d3_lpan; 1552 status = i40e_aq_set_phy_config(hw, &config, NULL); 1553 1554 if (status) 1555 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1556 } 1557 /* Update the link info */ 1558 status = i40e_update_link_info(hw); 1559 if (status) { 1560 /* Wait a little bit (on 40G cards it sometimes takes a really 1561 * long time for link to come back from the atomic reset) 1562 * and try once more 1563 */ 1564 i40e_msec_delay(1000); 1565 status = i40e_update_link_info(hw); 1566 } 1567 if (status) 1568 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1569 1570 return status; 1571 } 1572 1573 /** 1574 * i40e_aq_set_mac_config 1575 * @hw: pointer to the hw struct 1576 * @max_frame_size: Maximum Frame Size to be supported by the port 1577 * @crc_en: Tell HW to append a CRC to outgoing frames 1578 * @pacing: Pacing configurations 1579 * @cmd_details: pointer to command details structure or NULL 1580 * 1581 * Configure MAC settings for frame size, jumbo frame support and the 1582 * addition of a CRC by the hardware. 1583 **/ 1584 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1585 u16 max_frame_size, 1586 bool crc_en, u16 pacing, 1587 struct i40e_asq_cmd_details *cmd_details) 1588 { 1589 struct i40e_aq_desc desc; 1590 struct i40e_aq_set_mac_config *cmd = 1591 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1592 enum i40e_status_code status; 1593 1594 if (max_frame_size == 0) 1595 return I40E_ERR_PARAM; 1596 1597 i40e_fill_default_direct_cmd_desc(&desc, 1598 i40e_aqc_opc_set_mac_config); 1599 1600 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1601 cmd->params = ((u8)pacing & 0x0F) << 3; 1602 if (crc_en) 1603 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1604 1605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1606 1607 return status; 1608 } 1609 1610 /** 1611 * i40e_aq_clear_pxe_mode 1612 * @hw: pointer to the hw struct 1613 * @cmd_details: pointer to command details structure or NULL 1614 * 1615 * Tell the firmware that the driver is taking over from PXE 1616 **/ 1617 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1618 struct i40e_asq_cmd_details *cmd_details) 1619 { 1620 enum i40e_status_code status; 1621 struct i40e_aq_desc desc; 1622 struct i40e_aqc_clear_pxe *cmd = 1623 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1624 1625 i40e_fill_default_direct_cmd_desc(&desc, 1626 i40e_aqc_opc_clear_pxe_mode); 1627 1628 cmd->rx_cnt = 0x2; 1629 1630 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1631 1632 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1633 1634 return status; 1635 } 1636 1637 /** 1638 * i40e_aq_set_link_restart_an 1639 * @hw: pointer to the hw struct 1640 * @enable_link: if TRUE: enable link, if FALSE: disable link 1641 * @cmd_details: pointer to command details structure or NULL 1642 * 1643 * Sets up the link and restarts the Auto-Negotiation over the link. 1644 **/ 1645 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1646 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1647 { 1648 struct i40e_aq_desc desc; 1649 struct i40e_aqc_set_link_restart_an *cmd = 1650 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1651 enum i40e_status_code status; 1652 1653 i40e_fill_default_direct_cmd_desc(&desc, 1654 i40e_aqc_opc_set_link_restart_an); 1655 1656 cmd->command = I40E_AQ_PHY_RESTART_AN; 1657 if (enable_link) 1658 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1659 else 1660 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1661 1662 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1663 1664 return status; 1665 } 1666 1667 /** 1668 * i40e_aq_get_link_info 1669 * @hw: pointer to the hw struct 1670 * @enable_lse: enable/disable LinkStatusEvent reporting 1671 * @link: pointer to link status structure - optional 1672 * @cmd_details: pointer to command details structure or NULL 1673 * 1674 * Returns the link status of the adapter. 1675 **/ 1676 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1677 bool enable_lse, struct i40e_link_status *link, 1678 struct i40e_asq_cmd_details *cmd_details) 1679 { 1680 struct i40e_aq_desc desc; 1681 struct i40e_aqc_get_link_status *resp = 1682 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1683 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1684 enum i40e_status_code status; 1685 bool tx_pause, rx_pause; 1686 u16 command_flags; 1687 1688 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1689 1690 if (enable_lse) 1691 command_flags = I40E_AQ_LSE_ENABLE; 1692 else 1693 command_flags = I40E_AQ_LSE_DISABLE; 1694 resp->command_flags = CPU_TO_LE16(command_flags); 1695 1696 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1697 1698 if (status != I40E_SUCCESS) 1699 goto aq_get_link_info_exit; 1700 1701 /* save off old link status information */ 1702 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1703 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1704 1705 /* update link status */ 1706 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1707 hw->phy.media_type = i40e_get_media_type(hw); 1708 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1709 hw_link_info->link_info = resp->link_info; 1710 hw_link_info->an_info = resp->an_info; 1711 hw_link_info->ext_info = resp->ext_info; 1712 hw_link_info->loopback = resp->loopback; 1713 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1714 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1715 1716 /* update fc info */ 1717 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1718 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1719 if (tx_pause & rx_pause) 1720 hw->fc.current_mode = I40E_FC_FULL; 1721 else if (tx_pause) 1722 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1723 else if (rx_pause) 1724 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1725 else 1726 hw->fc.current_mode = I40E_FC_NONE; 1727 1728 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1729 hw_link_info->crc_enable = TRUE; 1730 else 1731 hw_link_info->crc_enable = FALSE; 1732 1733 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE)) 1734 hw_link_info->lse_enable = TRUE; 1735 else 1736 hw_link_info->lse_enable = FALSE; 1737 1738 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1739 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1740 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1741 1742 /* save link status information */ 1743 if (link) 1744 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1745 I40E_NONDMA_TO_NONDMA); 1746 1747 /* flag cleared so helper functions don't call AQ again */ 1748 hw->phy.get_link_info = FALSE; 1749 1750 aq_get_link_info_exit: 1751 return status; 1752 } 1753 1754 /** 1755 * i40e_aq_set_phy_int_mask 1756 * @hw: pointer to the hw struct 1757 * @mask: interrupt mask to be set 1758 * @cmd_details: pointer to command details structure or NULL 1759 * 1760 * Set link interrupt mask. 1761 **/ 1762 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1763 u16 mask, 1764 struct i40e_asq_cmd_details *cmd_details) 1765 { 1766 struct i40e_aq_desc desc; 1767 struct i40e_aqc_set_phy_int_mask *cmd = 1768 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1769 enum i40e_status_code status; 1770 1771 i40e_fill_default_direct_cmd_desc(&desc, 1772 i40e_aqc_opc_set_phy_int_mask); 1773 1774 cmd->event_mask = CPU_TO_LE16(mask); 1775 1776 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1777 1778 return status; 1779 } 1780 1781 /** 1782 * i40e_aq_get_local_advt_reg 1783 * @hw: pointer to the hw struct 1784 * @advt_reg: local AN advertisement register value 1785 * @cmd_details: pointer to command details structure or NULL 1786 * 1787 * Get the Local AN advertisement register value. 1788 **/ 1789 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1790 u64 *advt_reg, 1791 struct i40e_asq_cmd_details *cmd_details) 1792 { 1793 struct i40e_aq_desc desc; 1794 struct i40e_aqc_an_advt_reg *resp = 1795 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1796 enum i40e_status_code status; 1797 1798 i40e_fill_default_direct_cmd_desc(&desc, 1799 i40e_aqc_opc_get_local_advt_reg); 1800 1801 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1802 1803 if (status != I40E_SUCCESS) 1804 goto aq_get_local_advt_reg_exit; 1805 1806 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1807 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1808 1809 aq_get_local_advt_reg_exit: 1810 return status; 1811 } 1812 1813 /** 1814 * i40e_aq_set_local_advt_reg 1815 * @hw: pointer to the hw struct 1816 * @advt_reg: local AN advertisement register value 1817 * @cmd_details: pointer to command details structure or NULL 1818 * 1819 * Get the Local AN advertisement register value. 1820 **/ 1821 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 1822 u64 advt_reg, 1823 struct i40e_asq_cmd_details *cmd_details) 1824 { 1825 struct i40e_aq_desc desc; 1826 struct i40e_aqc_an_advt_reg *cmd = 1827 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1828 enum i40e_status_code status; 1829 1830 i40e_fill_default_direct_cmd_desc(&desc, 1831 i40e_aqc_opc_get_local_advt_reg); 1832 1833 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 1834 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 1835 1836 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1837 1838 return status; 1839 } 1840 1841 /** 1842 * i40e_aq_get_partner_advt 1843 * @hw: pointer to the hw struct 1844 * @advt_reg: AN partner advertisement register value 1845 * @cmd_details: pointer to command details structure or NULL 1846 * 1847 * Get the link partner AN advertisement register value. 1848 **/ 1849 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 1850 u64 *advt_reg, 1851 struct i40e_asq_cmd_details *cmd_details) 1852 { 1853 struct i40e_aq_desc desc; 1854 struct i40e_aqc_an_advt_reg *resp = 1855 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1856 enum i40e_status_code status; 1857 1858 i40e_fill_default_direct_cmd_desc(&desc, 1859 i40e_aqc_opc_get_partner_advt); 1860 1861 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1862 1863 if (status != I40E_SUCCESS) 1864 goto aq_get_partner_advt_exit; 1865 1866 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1867 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1868 1869 aq_get_partner_advt_exit: 1870 return status; 1871 } 1872 1873 /** 1874 * i40e_aq_set_lb_modes 1875 * @hw: pointer to the hw struct 1876 * @lb_modes: loopback mode to be set 1877 * @cmd_details: pointer to command details structure or NULL 1878 * 1879 * Sets loopback modes. 1880 **/ 1881 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 1882 u16 lb_modes, 1883 struct i40e_asq_cmd_details *cmd_details) 1884 { 1885 struct i40e_aq_desc desc; 1886 struct i40e_aqc_set_lb_mode *cmd = 1887 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 1888 enum i40e_status_code status; 1889 1890 i40e_fill_default_direct_cmd_desc(&desc, 1891 i40e_aqc_opc_set_lb_modes); 1892 1893 cmd->lb_mode = CPU_TO_LE16(lb_modes); 1894 1895 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1896 1897 return status; 1898 } 1899 1900 /** 1901 * i40e_aq_set_phy_debug 1902 * @hw: pointer to the hw struct 1903 * @cmd_flags: debug command flags 1904 * @cmd_details: pointer to command details structure or NULL 1905 * 1906 * Reset the external PHY. 1907 **/ 1908 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1909 struct i40e_asq_cmd_details *cmd_details) 1910 { 1911 struct i40e_aq_desc desc; 1912 struct i40e_aqc_set_phy_debug *cmd = 1913 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1914 enum i40e_status_code status; 1915 1916 i40e_fill_default_direct_cmd_desc(&desc, 1917 i40e_aqc_opc_set_phy_debug); 1918 1919 cmd->command_flags = cmd_flags; 1920 1921 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1922 1923 return status; 1924 } 1925 1926 /** 1927 * i40e_aq_add_vsi 1928 * @hw: pointer to the hw struct 1929 * @vsi_ctx: pointer to a vsi context struct 1930 * @cmd_details: pointer to command details structure or NULL 1931 * 1932 * Add a VSI context to the hardware. 1933 **/ 1934 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 1935 struct i40e_vsi_context *vsi_ctx, 1936 struct i40e_asq_cmd_details *cmd_details) 1937 { 1938 struct i40e_aq_desc desc; 1939 struct i40e_aqc_add_get_update_vsi *cmd = 1940 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1941 struct i40e_aqc_add_get_update_vsi_completion *resp = 1942 (struct i40e_aqc_add_get_update_vsi_completion *) 1943 &desc.params.raw; 1944 enum i40e_status_code status; 1945 1946 i40e_fill_default_direct_cmd_desc(&desc, 1947 i40e_aqc_opc_add_vsi); 1948 1949 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 1950 cmd->connection_type = vsi_ctx->connection_type; 1951 cmd->vf_id = vsi_ctx->vf_num; 1952 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 1953 1954 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1955 1956 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1957 sizeof(vsi_ctx->info), cmd_details); 1958 1959 if (status != I40E_SUCCESS) 1960 goto aq_add_vsi_exit; 1961 1962 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 1963 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 1964 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 1965 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 1966 1967 aq_add_vsi_exit: 1968 return status; 1969 } 1970 1971 /** 1972 * i40e_aq_set_default_vsi 1973 * @hw: pointer to the hw struct 1974 * @seid: vsi number 1975 * @cmd_details: pointer to command details structure or NULL 1976 **/ 1977 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 1978 u16 seid, 1979 struct i40e_asq_cmd_details *cmd_details) 1980 { 1981 struct i40e_aq_desc desc; 1982 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1983 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1984 &desc.params.raw; 1985 enum i40e_status_code status; 1986 1987 i40e_fill_default_direct_cmd_desc(&desc, 1988 i40e_aqc_opc_set_vsi_promiscuous_modes); 1989 1990 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1991 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1992 cmd->seid = CPU_TO_LE16(seid); 1993 1994 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1995 1996 return status; 1997 } 1998 1999 /** 2000 * i40e_aq_set_vsi_unicast_promiscuous 2001 * @hw: pointer to the hw struct 2002 * @seid: vsi number 2003 * @set: set unicast promiscuous enable/disable 2004 * @cmd_details: pointer to command details structure or NULL 2005 **/ 2006 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2007 u16 seid, bool set, 2008 struct i40e_asq_cmd_details *cmd_details) 2009 { 2010 struct i40e_aq_desc desc; 2011 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2012 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2013 enum i40e_status_code status; 2014 u16 flags = 0; 2015 2016 i40e_fill_default_direct_cmd_desc(&desc, 2017 i40e_aqc_opc_set_vsi_promiscuous_modes); 2018 2019 if (set) { 2020 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2021 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2022 (hw->aq.api_maj_ver > 1)) 2023 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2024 } 2025 2026 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2027 2028 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2029 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2030 (hw->aq.api_maj_ver > 1)) 2031 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2032 2033 cmd->seid = CPU_TO_LE16(seid); 2034 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2035 2036 return status; 2037 } 2038 2039 /** 2040 * i40e_aq_set_vsi_multicast_promiscuous 2041 * @hw: pointer to the hw struct 2042 * @seid: vsi number 2043 * @set: set multicast promiscuous enable/disable 2044 * @cmd_details: pointer to command details structure or NULL 2045 **/ 2046 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2047 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2048 { 2049 struct i40e_aq_desc desc; 2050 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2051 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2052 enum i40e_status_code status; 2053 u16 flags = 0; 2054 2055 i40e_fill_default_direct_cmd_desc(&desc, 2056 i40e_aqc_opc_set_vsi_promiscuous_modes); 2057 2058 if (set) 2059 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2060 2061 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2062 2063 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2064 2065 cmd->seid = CPU_TO_LE16(seid); 2066 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2067 2068 return status; 2069 } 2070 2071 /** 2072 * i40e_aq_set_vsi_mc_promisc_on_vlan 2073 * @hw: pointer to the hw struct 2074 * @seid: vsi number 2075 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2076 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2077 * @cmd_details: pointer to command details structure or NULL 2078 **/ 2079 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2080 u16 seid, bool enable, u16 vid, 2081 struct i40e_asq_cmd_details *cmd_details) 2082 { 2083 struct i40e_aq_desc desc; 2084 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2085 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2086 enum i40e_status_code status; 2087 u16 flags = 0; 2088 2089 i40e_fill_default_direct_cmd_desc(&desc, 2090 i40e_aqc_opc_set_vsi_promiscuous_modes); 2091 2092 if (enable) 2093 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2094 2095 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2096 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2097 cmd->seid = CPU_TO_LE16(seid); 2098 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2099 2100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2101 2102 return status; 2103 } 2104 2105 /** 2106 * i40e_aq_set_vsi_uc_promisc_on_vlan 2107 * @hw: pointer to the hw struct 2108 * @seid: vsi number 2109 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2110 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2111 * @cmd_details: pointer to command details structure or NULL 2112 **/ 2113 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2114 u16 seid, bool enable, u16 vid, 2115 struct i40e_asq_cmd_details *cmd_details) 2116 { 2117 struct i40e_aq_desc desc; 2118 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2119 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2120 enum i40e_status_code status; 2121 u16 flags = 0; 2122 2123 i40e_fill_default_direct_cmd_desc(&desc, 2124 i40e_aqc_opc_set_vsi_promiscuous_modes); 2125 2126 if (enable) 2127 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2128 2129 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2130 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2131 cmd->seid = CPU_TO_LE16(seid); 2132 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2133 2134 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2135 2136 return status; 2137 } 2138 2139 /** 2140 * i40e_aq_set_vsi_broadcast 2141 * @hw: pointer to the hw struct 2142 * @seid: vsi number 2143 * @set_filter: TRUE to set filter, FALSE to clear filter 2144 * @cmd_details: pointer to command details structure or NULL 2145 * 2146 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2147 **/ 2148 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2149 u16 seid, bool set_filter, 2150 struct i40e_asq_cmd_details *cmd_details) 2151 { 2152 struct i40e_aq_desc desc; 2153 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2154 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2155 enum i40e_status_code status; 2156 2157 i40e_fill_default_direct_cmd_desc(&desc, 2158 i40e_aqc_opc_set_vsi_promiscuous_modes); 2159 2160 if (set_filter) 2161 cmd->promiscuous_flags 2162 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2163 else 2164 cmd->promiscuous_flags 2165 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2166 2167 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2168 cmd->seid = CPU_TO_LE16(seid); 2169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2170 2171 return status; 2172 } 2173 2174 /** 2175 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2176 * @hw: pointer to the hw struct 2177 * @seid: vsi number 2178 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2179 * @cmd_details: pointer to command details structure or NULL 2180 **/ 2181 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2182 u16 seid, bool enable, 2183 struct i40e_asq_cmd_details *cmd_details) 2184 { 2185 struct i40e_aq_desc desc; 2186 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2187 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2188 enum i40e_status_code status; 2189 u16 flags = 0; 2190 2191 i40e_fill_default_direct_cmd_desc(&desc, 2192 i40e_aqc_opc_set_vsi_promiscuous_modes); 2193 if (enable) 2194 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2195 2196 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2197 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2198 cmd->seid = CPU_TO_LE16(seid); 2199 2200 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2201 2202 return status; 2203 } 2204 2205 /** 2206 * i40e_get_vsi_params - get VSI configuration info 2207 * @hw: pointer to the hw struct 2208 * @vsi_ctx: pointer to a vsi context struct 2209 * @cmd_details: pointer to command details structure or NULL 2210 **/ 2211 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2212 struct i40e_vsi_context *vsi_ctx, 2213 struct i40e_asq_cmd_details *cmd_details) 2214 { 2215 struct i40e_aq_desc desc; 2216 struct i40e_aqc_add_get_update_vsi *cmd = 2217 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2218 struct i40e_aqc_add_get_update_vsi_completion *resp = 2219 (struct i40e_aqc_add_get_update_vsi_completion *) 2220 &desc.params.raw; 2221 enum i40e_status_code status; 2222 2223 i40e_fill_default_direct_cmd_desc(&desc, 2224 i40e_aqc_opc_get_vsi_parameters); 2225 2226 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2227 2228 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2229 2230 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2231 sizeof(vsi_ctx->info), NULL); 2232 2233 if (status != I40E_SUCCESS) 2234 goto aq_get_vsi_params_exit; 2235 2236 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2237 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2238 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2239 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2240 2241 aq_get_vsi_params_exit: 2242 return status; 2243 } 2244 2245 /** 2246 * i40e_aq_update_vsi_params 2247 * @hw: pointer to the hw struct 2248 * @vsi_ctx: pointer to a vsi context struct 2249 * @cmd_details: pointer to command details structure or NULL 2250 * 2251 * Update a VSI context. 2252 **/ 2253 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2254 struct i40e_vsi_context *vsi_ctx, 2255 struct i40e_asq_cmd_details *cmd_details) 2256 { 2257 struct i40e_aq_desc desc; 2258 struct i40e_aqc_add_get_update_vsi *cmd = 2259 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2260 struct i40e_aqc_add_get_update_vsi_completion *resp = 2261 (struct i40e_aqc_add_get_update_vsi_completion *) 2262 &desc.params.raw; 2263 enum i40e_status_code status; 2264 2265 i40e_fill_default_direct_cmd_desc(&desc, 2266 i40e_aqc_opc_update_vsi_parameters); 2267 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2268 2269 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2270 2271 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2272 sizeof(vsi_ctx->info), cmd_details); 2273 2274 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2275 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2276 2277 return status; 2278 } 2279 2280 /** 2281 * i40e_aq_get_switch_config 2282 * @hw: pointer to the hardware structure 2283 * @buf: pointer to the result buffer 2284 * @buf_size: length of input buffer 2285 * @start_seid: seid to start for the report, 0 == beginning 2286 * @cmd_details: pointer to command details structure or NULL 2287 * 2288 * Fill the buf with switch configuration returned from AdminQ command 2289 **/ 2290 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2291 struct i40e_aqc_get_switch_config_resp *buf, 2292 u16 buf_size, u16 *start_seid, 2293 struct i40e_asq_cmd_details *cmd_details) 2294 { 2295 struct i40e_aq_desc desc; 2296 struct i40e_aqc_switch_seid *scfg = 2297 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2298 enum i40e_status_code status; 2299 2300 i40e_fill_default_direct_cmd_desc(&desc, 2301 i40e_aqc_opc_get_switch_config); 2302 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2303 if (buf_size > I40E_AQ_LARGE_BUF) 2304 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2305 scfg->seid = CPU_TO_LE16(*start_seid); 2306 2307 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2308 *start_seid = LE16_TO_CPU(scfg->seid); 2309 2310 return status; 2311 } 2312 2313 /** 2314 * i40e_aq_set_switch_config 2315 * @hw: pointer to the hardware structure 2316 * @flags: bit flag values to set 2317 * @valid_flags: which bit flags to set 2318 * @cmd_details: pointer to command details structure or NULL 2319 * 2320 * Set switch configuration bits 2321 **/ 2322 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2323 u16 flags, u16 valid_flags, 2324 struct i40e_asq_cmd_details *cmd_details) 2325 { 2326 struct i40e_aq_desc desc; 2327 struct i40e_aqc_set_switch_config *scfg = 2328 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2329 enum i40e_status_code status; 2330 2331 i40e_fill_default_direct_cmd_desc(&desc, 2332 i40e_aqc_opc_set_switch_config); 2333 scfg->flags = CPU_TO_LE16(flags); 2334 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2335 2336 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2337 2338 return status; 2339 } 2340 2341 /** 2342 * i40e_aq_get_firmware_version 2343 * @hw: pointer to the hw struct 2344 * @fw_major_version: firmware major version 2345 * @fw_minor_version: firmware minor version 2346 * @fw_build: firmware build number 2347 * @api_major_version: major queue version 2348 * @api_minor_version: minor queue version 2349 * @cmd_details: pointer to command details structure or NULL 2350 * 2351 * Get the firmware version from the admin queue commands 2352 **/ 2353 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2354 u16 *fw_major_version, u16 *fw_minor_version, 2355 u32 *fw_build, 2356 u16 *api_major_version, u16 *api_minor_version, 2357 struct i40e_asq_cmd_details *cmd_details) 2358 { 2359 struct i40e_aq_desc desc; 2360 struct i40e_aqc_get_version *resp = 2361 (struct i40e_aqc_get_version *)&desc.params.raw; 2362 enum i40e_status_code status; 2363 2364 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2365 2366 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2367 2368 if (status == I40E_SUCCESS) { 2369 if (fw_major_version != NULL) 2370 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2371 if (fw_minor_version != NULL) 2372 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2373 if (fw_build != NULL) 2374 *fw_build = LE32_TO_CPU(resp->fw_build); 2375 if (api_major_version != NULL) 2376 *api_major_version = LE16_TO_CPU(resp->api_major); 2377 if (api_minor_version != NULL) 2378 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2379 2380 /* A workaround to fix the API version in SW */ 2381 if (api_major_version && api_minor_version && 2382 fw_major_version && fw_minor_version && 2383 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2384 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2385 (*fw_major_version > 4))) 2386 *api_minor_version = 2; 2387 } 2388 2389 return status; 2390 } 2391 2392 /** 2393 * i40e_aq_send_driver_version 2394 * @hw: pointer to the hw struct 2395 * @dv: driver's major, minor version 2396 * @cmd_details: pointer to command details structure or NULL 2397 * 2398 * Send the driver version to the firmware 2399 **/ 2400 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2401 struct i40e_driver_version *dv, 2402 struct i40e_asq_cmd_details *cmd_details) 2403 { 2404 struct i40e_aq_desc desc; 2405 struct i40e_aqc_driver_version *cmd = 2406 (struct i40e_aqc_driver_version *)&desc.params.raw; 2407 enum i40e_status_code status; 2408 u16 len; 2409 2410 if (dv == NULL) 2411 return I40E_ERR_PARAM; 2412 2413 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2414 2415 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2416 cmd->driver_major_ver = dv->major_version; 2417 cmd->driver_minor_ver = dv->minor_version; 2418 cmd->driver_build_ver = dv->build_version; 2419 cmd->driver_subbuild_ver = dv->subbuild_version; 2420 2421 len = 0; 2422 while (len < sizeof(dv->driver_string) && 2423 (dv->driver_string[len] < 0x80) && 2424 dv->driver_string[len]) 2425 len++; 2426 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2427 len, cmd_details); 2428 2429 return status; 2430 } 2431 2432 /** 2433 * i40e_get_link_status - get status of the HW network link 2434 * @hw: pointer to the hw struct 2435 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2436 * 2437 * Variable link_up TRUE if link is up, FALSE if link is down. 2438 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2439 * 2440 * Side effect: LinkStatusEvent reporting becomes enabled 2441 **/ 2442 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2443 { 2444 enum i40e_status_code status = I40E_SUCCESS; 2445 2446 if (hw->phy.get_link_info) { 2447 status = i40e_update_link_info(hw); 2448 2449 if (status != I40E_SUCCESS) 2450 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2451 status); 2452 } 2453 2454 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2455 2456 return status; 2457 } 2458 2459 /** 2460 * i40e_updatelink_status - update status of the HW network link 2461 * @hw: pointer to the hw struct 2462 **/ 2463 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2464 { 2465 struct i40e_aq_get_phy_abilities_resp abilities; 2466 enum i40e_status_code status = I40E_SUCCESS; 2467 2468 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2469 if (status) 2470 return status; 2471 2472 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) { 2473 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2474 &abilities, NULL); 2475 if (status) 2476 return status; 2477 2478 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2479 sizeof(hw->phy.link_info.module_type)); 2480 } 2481 return status; 2482 } 2483 2484 2485 /** 2486 * i40e_get_link_speed 2487 * @hw: pointer to the hw struct 2488 * 2489 * Returns the link speed of the adapter. 2490 **/ 2491 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2492 { 2493 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2494 enum i40e_status_code status = I40E_SUCCESS; 2495 2496 if (hw->phy.get_link_info) { 2497 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2498 2499 if (status != I40E_SUCCESS) 2500 goto i40e_link_speed_exit; 2501 } 2502 2503 speed = hw->phy.link_info.link_speed; 2504 2505 i40e_link_speed_exit: 2506 return speed; 2507 } 2508 2509 /** 2510 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2511 * @hw: pointer to the hw struct 2512 * @uplink_seid: the MAC or other gizmo SEID 2513 * @downlink_seid: the VSI SEID 2514 * @enabled_tc: bitmap of TCs to be enabled 2515 * @default_port: TRUE for default port VSI, FALSE for control port 2516 * @veb_seid: pointer to where to put the resulting VEB SEID 2517 * @enable_stats: TRUE to turn on VEB stats 2518 * @cmd_details: pointer to command details structure or NULL 2519 * 2520 * This asks the FW to add a VEB between the uplink and downlink 2521 * elements. If the uplink SEID is 0, this will be a floating VEB. 2522 **/ 2523 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2524 u16 downlink_seid, u8 enabled_tc, 2525 bool default_port, u16 *veb_seid, 2526 bool enable_stats, 2527 struct i40e_asq_cmd_details *cmd_details) 2528 { 2529 struct i40e_aq_desc desc; 2530 struct i40e_aqc_add_veb *cmd = 2531 (struct i40e_aqc_add_veb *)&desc.params.raw; 2532 struct i40e_aqc_add_veb_completion *resp = 2533 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2534 enum i40e_status_code status; 2535 u16 veb_flags = 0; 2536 2537 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2538 if (!!uplink_seid != !!downlink_seid) 2539 return I40E_ERR_PARAM; 2540 2541 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2542 2543 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2544 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2545 cmd->enable_tcs = enabled_tc; 2546 if (!uplink_seid) 2547 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2548 if (default_port) 2549 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2550 else 2551 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2552 2553 /* reverse logic here: set the bitflag to disable the stats */ 2554 if (!enable_stats) 2555 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2556 2557 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2558 2559 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2560 2561 if (!status && veb_seid) 2562 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2563 2564 return status; 2565 } 2566 2567 /** 2568 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2569 * @hw: pointer to the hw struct 2570 * @veb_seid: the SEID of the VEB to query 2571 * @switch_id: the uplink switch id 2572 * @floating: set to TRUE if the VEB is floating 2573 * @statistic_index: index of the stats counter block for this VEB 2574 * @vebs_used: number of VEB's used by function 2575 * @vebs_free: total VEB's not reserved by any function 2576 * @cmd_details: pointer to command details structure or NULL 2577 * 2578 * This retrieves the parameters for a particular VEB, specified by 2579 * uplink_seid, and returns them to the caller. 2580 **/ 2581 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2582 u16 veb_seid, u16 *switch_id, 2583 bool *floating, u16 *statistic_index, 2584 u16 *vebs_used, u16 *vebs_free, 2585 struct i40e_asq_cmd_details *cmd_details) 2586 { 2587 struct i40e_aq_desc desc; 2588 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2589 (struct i40e_aqc_get_veb_parameters_completion *) 2590 &desc.params.raw; 2591 enum i40e_status_code status; 2592 2593 if (veb_seid == 0) 2594 return I40E_ERR_PARAM; 2595 2596 i40e_fill_default_direct_cmd_desc(&desc, 2597 i40e_aqc_opc_get_veb_parameters); 2598 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2599 2600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2601 if (status) 2602 goto get_veb_exit; 2603 2604 if (switch_id) 2605 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2606 if (statistic_index) 2607 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2608 if (vebs_used) 2609 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2610 if (vebs_free) 2611 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2612 if (floating) { 2613 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2614 2615 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2616 *floating = TRUE; 2617 else 2618 *floating = FALSE; 2619 } 2620 2621 get_veb_exit: 2622 return status; 2623 } 2624 2625 /** 2626 * i40e_aq_add_macvlan 2627 * @hw: pointer to the hw struct 2628 * @seid: VSI for the mac address 2629 * @mv_list: list of macvlans to be added 2630 * @count: length of the list 2631 * @cmd_details: pointer to command details structure or NULL 2632 * 2633 * Add MAC/VLAN addresses to the HW filtering 2634 **/ 2635 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2636 struct i40e_aqc_add_macvlan_element_data *mv_list, 2637 u16 count, struct i40e_asq_cmd_details *cmd_details) 2638 { 2639 struct i40e_aq_desc desc; 2640 struct i40e_aqc_macvlan *cmd = 2641 (struct i40e_aqc_macvlan *)&desc.params.raw; 2642 enum i40e_status_code status; 2643 u16 buf_size; 2644 int i; 2645 2646 if (count == 0 || !mv_list || !hw) 2647 return I40E_ERR_PARAM; 2648 2649 buf_size = count * sizeof(*mv_list); 2650 2651 /* prep the rest of the request */ 2652 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2653 cmd->num_addresses = CPU_TO_LE16(count); 2654 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2655 cmd->seid[1] = 0; 2656 cmd->seid[2] = 0; 2657 2658 for (i = 0; i < count; i++) 2659 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 2660 mv_list[i].flags |= 2661 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2662 2663 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2664 if (buf_size > I40E_AQ_LARGE_BUF) 2665 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2666 2667 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2668 cmd_details); 2669 2670 return status; 2671 } 2672 2673 /** 2674 * i40e_aq_remove_macvlan 2675 * @hw: pointer to the hw struct 2676 * @seid: VSI for the mac address 2677 * @mv_list: list of macvlans to be removed 2678 * @count: length of the list 2679 * @cmd_details: pointer to command details structure or NULL 2680 * 2681 * Remove MAC/VLAN addresses from the HW filtering 2682 **/ 2683 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2684 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2685 u16 count, struct i40e_asq_cmd_details *cmd_details) 2686 { 2687 struct i40e_aq_desc desc; 2688 struct i40e_aqc_macvlan *cmd = 2689 (struct i40e_aqc_macvlan *)&desc.params.raw; 2690 enum i40e_status_code status; 2691 u16 buf_size; 2692 2693 if (count == 0 || !mv_list || !hw) 2694 return I40E_ERR_PARAM; 2695 2696 buf_size = count * sizeof(*mv_list); 2697 2698 /* prep the rest of the request */ 2699 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2700 cmd->num_addresses = CPU_TO_LE16(count); 2701 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2702 cmd->seid[1] = 0; 2703 cmd->seid[2] = 0; 2704 2705 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2706 if (buf_size > I40E_AQ_LARGE_BUF) 2707 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2708 2709 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2710 cmd_details); 2711 2712 return status; 2713 } 2714 2715 /** 2716 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2717 * @hw: pointer to the hw struct 2718 * @opcode: AQ opcode for add or delete mirror rule 2719 * @sw_seid: Switch SEID (to which rule refers) 2720 * @rule_type: Rule Type (ingress/egress/VLAN) 2721 * @id: Destination VSI SEID or Rule ID 2722 * @count: length of the list 2723 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2724 * @cmd_details: pointer to command details structure or NULL 2725 * @rule_id: Rule ID returned from FW 2726 * @rule_used: Number of rules used in internal switch 2727 * @rule_free: Number of rules free in internal switch 2728 * 2729 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2730 * VEBs/VEPA elements only 2731 **/ 2732 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 2733 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2734 u16 count, __le16 *mr_list, 2735 struct i40e_asq_cmd_details *cmd_details, 2736 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2737 { 2738 struct i40e_aq_desc desc; 2739 struct i40e_aqc_add_delete_mirror_rule *cmd = 2740 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2741 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2742 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2743 enum i40e_status_code status; 2744 u16 buf_size; 2745 2746 buf_size = count * sizeof(*mr_list); 2747 2748 /* prep the rest of the request */ 2749 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2750 cmd->seid = CPU_TO_LE16(sw_seid); 2751 cmd->rule_type = CPU_TO_LE16(rule_type & 2752 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2753 cmd->num_entries = CPU_TO_LE16(count); 2754 /* Dest VSI for add, rule_id for delete */ 2755 cmd->destination = CPU_TO_LE16(id); 2756 if (mr_list) { 2757 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 2758 I40E_AQ_FLAG_RD)); 2759 if (buf_size > I40E_AQ_LARGE_BUF) 2760 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2761 } 2762 2763 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2764 cmd_details); 2765 if (status == I40E_SUCCESS || 2766 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2767 if (rule_id) 2768 *rule_id = LE16_TO_CPU(resp->rule_id); 2769 if (rules_used) 2770 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 2771 if (rules_free) 2772 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 2773 } 2774 return status; 2775 } 2776 2777 /** 2778 * i40e_aq_add_mirrorrule - add a mirror rule 2779 * @hw: pointer to the hw struct 2780 * @sw_seid: Switch SEID (to which rule refers) 2781 * @rule_type: Rule Type (ingress/egress/VLAN) 2782 * @dest_vsi: SEID of VSI to which packets will be mirrored 2783 * @count: length of the list 2784 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2785 * @cmd_details: pointer to command details structure or NULL 2786 * @rule_id: Rule ID returned from FW 2787 * @rule_used: Number of rules used in internal switch 2788 * @rule_free: Number of rules free in internal switch 2789 * 2790 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2791 **/ 2792 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2793 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2794 struct i40e_asq_cmd_details *cmd_details, 2795 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2796 { 2797 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2798 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2799 if (count == 0 || !mr_list) 2800 return I40E_ERR_PARAM; 2801 } 2802 2803 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2804 rule_type, dest_vsi, count, mr_list, 2805 cmd_details, rule_id, rules_used, rules_free); 2806 } 2807 2808 /** 2809 * i40e_aq_delete_mirrorrule - delete a mirror rule 2810 * @hw: pointer to the hw struct 2811 * @sw_seid: Switch SEID (to which rule refers) 2812 * @rule_type: Rule Type (ingress/egress/VLAN) 2813 * @count: length of the list 2814 * @rule_id: Rule ID that is returned in the receive desc as part of 2815 * add_mirrorrule. 2816 * @mr_list: list of mirrored VLAN IDs to be removed 2817 * @cmd_details: pointer to command details structure or NULL 2818 * @rule_used: Number of rules used in internal switch 2819 * @rule_free: Number of rules free in internal switch 2820 * 2821 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2822 **/ 2823 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2824 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2825 struct i40e_asq_cmd_details *cmd_details, 2826 u16 *rules_used, u16 *rules_free) 2827 { 2828 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2829 if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2830 if (!rule_id) 2831 return I40E_ERR_PARAM; 2832 } else { 2833 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2834 * mirroring. For other rule_type, count and rule_type should 2835 * not matter. 2836 */ 2837 if (count == 0 || !mr_list) 2838 return I40E_ERR_PARAM; 2839 } 2840 2841 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2842 rule_type, rule_id, count, mr_list, 2843 cmd_details, NULL, rules_used, rules_free); 2844 } 2845 2846 /** 2847 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 2848 * @hw: pointer to the hw struct 2849 * @seid: VSI for the vlan filters 2850 * @v_list: list of vlan filters to be added 2851 * @count: length of the list 2852 * @cmd_details: pointer to command details structure or NULL 2853 **/ 2854 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 2855 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2856 u8 count, struct i40e_asq_cmd_details *cmd_details) 2857 { 2858 struct i40e_aq_desc desc; 2859 struct i40e_aqc_macvlan *cmd = 2860 (struct i40e_aqc_macvlan *)&desc.params.raw; 2861 enum i40e_status_code status; 2862 u16 buf_size; 2863 2864 if (count == 0 || !v_list || !hw) 2865 return I40E_ERR_PARAM; 2866 2867 buf_size = count * sizeof(*v_list); 2868 2869 /* prep the rest of the request */ 2870 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 2871 cmd->num_addresses = CPU_TO_LE16(count); 2872 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2873 cmd->seid[1] = 0; 2874 cmd->seid[2] = 0; 2875 2876 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2877 if (buf_size > I40E_AQ_LARGE_BUF) 2878 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2879 2880 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2881 cmd_details); 2882 2883 return status; 2884 } 2885 2886 /** 2887 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 2888 * @hw: pointer to the hw struct 2889 * @seid: VSI for the vlan filters 2890 * @v_list: list of macvlans to be removed 2891 * @count: length of the list 2892 * @cmd_details: pointer to command details structure or NULL 2893 **/ 2894 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 2895 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2896 u8 count, struct i40e_asq_cmd_details *cmd_details) 2897 { 2898 struct i40e_aq_desc desc; 2899 struct i40e_aqc_macvlan *cmd = 2900 (struct i40e_aqc_macvlan *)&desc.params.raw; 2901 enum i40e_status_code status; 2902 u16 buf_size; 2903 2904 if (count == 0 || !v_list || !hw) 2905 return I40E_ERR_PARAM; 2906 2907 buf_size = count * sizeof(*v_list); 2908 2909 /* prep the rest of the request */ 2910 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 2911 cmd->num_addresses = CPU_TO_LE16(count); 2912 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2913 cmd->seid[1] = 0; 2914 cmd->seid[2] = 0; 2915 2916 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2917 if (buf_size > I40E_AQ_LARGE_BUF) 2918 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2919 2920 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2921 cmd_details); 2922 2923 return status; 2924 } 2925 2926 /** 2927 * i40e_aq_send_msg_to_vf 2928 * @hw: pointer to the hardware structure 2929 * @vfid: vf id to send msg 2930 * @v_opcode: opcodes for VF-PF communication 2931 * @v_retval: return error code 2932 * @msg: pointer to the msg buffer 2933 * @msglen: msg length 2934 * @cmd_details: pointer to command details 2935 * 2936 * send msg to vf 2937 **/ 2938 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2939 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2940 struct i40e_asq_cmd_details *cmd_details) 2941 { 2942 struct i40e_aq_desc desc; 2943 struct i40e_aqc_pf_vf_message *cmd = 2944 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2945 enum i40e_status_code status; 2946 2947 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2948 cmd->id = CPU_TO_LE32(vfid); 2949 desc.cookie_high = CPU_TO_LE32(v_opcode); 2950 desc.cookie_low = CPU_TO_LE32(v_retval); 2951 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 2952 if (msglen) { 2953 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 2954 I40E_AQ_FLAG_RD)); 2955 if (msglen > I40E_AQ_LARGE_BUF) 2956 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2957 desc.datalen = CPU_TO_LE16(msglen); 2958 } 2959 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2960 2961 return status; 2962 } 2963 2964 /** 2965 * i40e_aq_debug_read_register 2966 * @hw: pointer to the hw struct 2967 * @reg_addr: register address 2968 * @reg_val: register value 2969 * @cmd_details: pointer to command details structure or NULL 2970 * 2971 * Read the register using the admin queue commands 2972 **/ 2973 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 2974 u32 reg_addr, u64 *reg_val, 2975 struct i40e_asq_cmd_details *cmd_details) 2976 { 2977 struct i40e_aq_desc desc; 2978 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2979 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2980 enum i40e_status_code status; 2981 2982 if (reg_val == NULL) 2983 return I40E_ERR_PARAM; 2984 2985 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2986 2987 cmd_resp->address = CPU_TO_LE32(reg_addr); 2988 2989 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2990 2991 if (status == I40E_SUCCESS) { 2992 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 2993 (u64)LE32_TO_CPU(cmd_resp->value_low); 2994 } 2995 2996 return status; 2997 } 2998 2999 /** 3000 * i40e_aq_debug_write_register 3001 * @hw: pointer to the hw struct 3002 * @reg_addr: register address 3003 * @reg_val: register value 3004 * @cmd_details: pointer to command details structure or NULL 3005 * 3006 * Write to a register using the admin queue commands 3007 **/ 3008 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3009 u32 reg_addr, u64 reg_val, 3010 struct i40e_asq_cmd_details *cmd_details) 3011 { 3012 struct i40e_aq_desc desc; 3013 struct i40e_aqc_debug_reg_read_write *cmd = 3014 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3015 enum i40e_status_code status; 3016 3017 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3018 3019 cmd->address = CPU_TO_LE32(reg_addr); 3020 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3021 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3022 3023 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3024 3025 return status; 3026 } 3027 3028 /** 3029 * i40e_aq_get_hmc_resource_profile 3030 * @hw: pointer to the hw struct 3031 * @profile: type of profile the HMC is to be set as 3032 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 3033 * @cmd_details: pointer to command details structure or NULL 3034 * 3035 * query the HMC profile of the device. 3036 **/ 3037 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw, 3038 enum i40e_aq_hmc_profile *profile, 3039 u8 *pe_vf_enabled_count, 3040 struct i40e_asq_cmd_details *cmd_details) 3041 { 3042 struct i40e_aq_desc desc; 3043 struct i40e_aq_get_set_hmc_resource_profile *resp = 3044 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 3045 enum i40e_status_code status; 3046 3047 i40e_fill_default_direct_cmd_desc(&desc, 3048 i40e_aqc_opc_query_hmc_resource_profile); 3049 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3050 3051 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile & 3052 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK); 3053 *pe_vf_enabled_count = resp->pe_vf_enabled & 3054 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK; 3055 3056 return status; 3057 } 3058 3059 /** 3060 * i40e_aq_set_hmc_resource_profile 3061 * @hw: pointer to the hw struct 3062 * @profile: type of profile the HMC is to be set as 3063 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 3064 * @cmd_details: pointer to command details structure or NULL 3065 * 3066 * set the HMC profile of the device. 3067 **/ 3068 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 3069 enum i40e_aq_hmc_profile profile, 3070 u8 pe_vf_enabled_count, 3071 struct i40e_asq_cmd_details *cmd_details) 3072 { 3073 struct i40e_aq_desc desc; 3074 struct i40e_aq_get_set_hmc_resource_profile *cmd = 3075 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 3076 enum i40e_status_code status; 3077 3078 i40e_fill_default_direct_cmd_desc(&desc, 3079 i40e_aqc_opc_set_hmc_resource_profile); 3080 3081 cmd->pm_profile = (u8)profile; 3082 cmd->pe_vf_enabled = pe_vf_enabled_count; 3083 3084 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3085 3086 return status; 3087 } 3088 3089 /** 3090 * i40e_aq_request_resource 3091 * @hw: pointer to the hw struct 3092 * @resource: resource id 3093 * @access: access type 3094 * @sdp_number: resource number 3095 * @timeout: the maximum time in ms that the driver may hold the resource 3096 * @cmd_details: pointer to command details structure or NULL 3097 * 3098 * requests common resource using the admin queue commands 3099 **/ 3100 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3101 enum i40e_aq_resources_ids resource, 3102 enum i40e_aq_resource_access_type access, 3103 u8 sdp_number, u64 *timeout, 3104 struct i40e_asq_cmd_details *cmd_details) 3105 { 3106 struct i40e_aq_desc desc; 3107 struct i40e_aqc_request_resource *cmd_resp = 3108 (struct i40e_aqc_request_resource *)&desc.params.raw; 3109 enum i40e_status_code status; 3110 3111 DEBUGFUNC("i40e_aq_request_resource"); 3112 3113 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3114 3115 cmd_resp->resource_id = CPU_TO_LE16(resource); 3116 cmd_resp->access_type = CPU_TO_LE16(access); 3117 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3118 3119 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3120 /* The completion specifies the maximum time in ms that the driver 3121 * may hold the resource in the Timeout field. 3122 * If the resource is held by someone else, the command completes with 3123 * busy return value and the timeout field indicates the maximum time 3124 * the current owner of the resource has to free it. 3125 */ 3126 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3127 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3128 3129 return status; 3130 } 3131 3132 /** 3133 * i40e_aq_release_resource 3134 * @hw: pointer to the hw struct 3135 * @resource: resource id 3136 * @sdp_number: resource number 3137 * @cmd_details: pointer to command details structure or NULL 3138 * 3139 * release common resource using the admin queue commands 3140 **/ 3141 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3142 enum i40e_aq_resources_ids resource, 3143 u8 sdp_number, 3144 struct i40e_asq_cmd_details *cmd_details) 3145 { 3146 struct i40e_aq_desc desc; 3147 struct i40e_aqc_request_resource *cmd = 3148 (struct i40e_aqc_request_resource *)&desc.params.raw; 3149 enum i40e_status_code status; 3150 3151 DEBUGFUNC("i40e_aq_release_resource"); 3152 3153 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3154 3155 cmd->resource_id = CPU_TO_LE16(resource); 3156 cmd->resource_number = CPU_TO_LE32(sdp_number); 3157 3158 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3159 3160 return status; 3161 } 3162 3163 /** 3164 * i40e_aq_read_nvm 3165 * @hw: pointer to the hw struct 3166 * @module_pointer: module pointer location in words from the NVM beginning 3167 * @offset: byte offset from the module beginning 3168 * @length: length of the section to be read (in bytes from the offset) 3169 * @data: command buffer (size [bytes] = length) 3170 * @last_command: tells if this is the last command in a series 3171 * @cmd_details: pointer to command details structure or NULL 3172 * 3173 * Read the NVM using the admin queue commands 3174 **/ 3175 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3176 u32 offset, u16 length, void *data, 3177 bool last_command, 3178 struct i40e_asq_cmd_details *cmd_details) 3179 { 3180 struct i40e_aq_desc desc; 3181 struct i40e_aqc_nvm_update *cmd = 3182 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3183 enum i40e_status_code status; 3184 3185 DEBUGFUNC("i40e_aq_read_nvm"); 3186 3187 /* In offset the highest byte must be zeroed. */ 3188 if (offset & 0xFF000000) { 3189 status = I40E_ERR_PARAM; 3190 goto i40e_aq_read_nvm_exit; 3191 } 3192 3193 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3194 3195 /* If this is the last command in a series, set the proper flag. */ 3196 if (last_command) 3197 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3198 cmd->module_pointer = module_pointer; 3199 cmd->offset = CPU_TO_LE32(offset); 3200 cmd->length = CPU_TO_LE16(length); 3201 3202 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3203 if (length > I40E_AQ_LARGE_BUF) 3204 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3205 3206 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3207 3208 i40e_aq_read_nvm_exit: 3209 return status; 3210 } 3211 3212 /** 3213 * i40e_aq_read_nvm_config - read an nvm config block 3214 * @hw: pointer to the hw struct 3215 * @cmd_flags: NVM access admin command bits 3216 * @field_id: field or feature id 3217 * @data: buffer for result 3218 * @buf_size: buffer size 3219 * @element_count: pointer to count of elements read by FW 3220 * @cmd_details: pointer to command details structure or NULL 3221 **/ 3222 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3223 u8 cmd_flags, u32 field_id, void *data, 3224 u16 buf_size, u16 *element_count, 3225 struct i40e_asq_cmd_details *cmd_details) 3226 { 3227 struct i40e_aq_desc desc; 3228 struct i40e_aqc_nvm_config_read *cmd = 3229 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3230 enum i40e_status_code status; 3231 3232 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3233 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3234 if (buf_size > I40E_AQ_LARGE_BUF) 3235 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3236 3237 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3238 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3239 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3240 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3241 else 3242 cmd->element_id_msw = 0; 3243 3244 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3245 3246 if (!status && element_count) 3247 *element_count = LE16_TO_CPU(cmd->element_count); 3248 3249 return status; 3250 } 3251 3252 /** 3253 * i40e_aq_write_nvm_config - write an nvm config block 3254 * @hw: pointer to the hw struct 3255 * @cmd_flags: NVM access admin command bits 3256 * @data: buffer for result 3257 * @buf_size: buffer size 3258 * @element_count: count of elements to be written 3259 * @cmd_details: pointer to command details structure or NULL 3260 **/ 3261 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3262 u8 cmd_flags, void *data, u16 buf_size, 3263 u16 element_count, 3264 struct i40e_asq_cmd_details *cmd_details) 3265 { 3266 struct i40e_aq_desc desc; 3267 struct i40e_aqc_nvm_config_write *cmd = 3268 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3269 enum i40e_status_code status; 3270 3271 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3272 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3273 if (buf_size > I40E_AQ_LARGE_BUF) 3274 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3275 3276 cmd->element_count = CPU_TO_LE16(element_count); 3277 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3278 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3279 3280 return status; 3281 } 3282 3283 /** 3284 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3285 * @hw: pointer to the hw struct 3286 * @cmd_details: pointer to command details structure or NULL 3287 **/ 3288 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3289 void *buff, u16 buff_size, 3290 struct i40e_asq_cmd_details *cmd_details) 3291 { 3292 struct i40e_aq_desc desc; 3293 enum i40e_status_code status; 3294 3295 3296 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3297 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3298 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3299 status = I40E_ERR_NOT_IMPLEMENTED; 3300 3301 return status; 3302 } 3303 3304 /** 3305 * i40e_aq_erase_nvm 3306 * @hw: pointer to the hw struct 3307 * @module_pointer: module pointer location in words from the NVM beginning 3308 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3309 * @length: length of the section to be erased (expressed in 4 KB) 3310 * @last_command: tells if this is the last command in a series 3311 * @cmd_details: pointer to command details structure or NULL 3312 * 3313 * Erase the NVM sector using the admin queue commands 3314 **/ 3315 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3316 u32 offset, u16 length, bool last_command, 3317 struct i40e_asq_cmd_details *cmd_details) 3318 { 3319 struct i40e_aq_desc desc; 3320 struct i40e_aqc_nvm_update *cmd = 3321 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3322 enum i40e_status_code status; 3323 3324 DEBUGFUNC("i40e_aq_erase_nvm"); 3325 3326 /* In offset the highest byte must be zeroed. */ 3327 if (offset & 0xFF000000) { 3328 status = I40E_ERR_PARAM; 3329 goto i40e_aq_erase_nvm_exit; 3330 } 3331 3332 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3333 3334 /* If this is the last command in a series, set the proper flag. */ 3335 if (last_command) 3336 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3337 cmd->module_pointer = module_pointer; 3338 cmd->offset = CPU_TO_LE32(offset); 3339 cmd->length = CPU_TO_LE16(length); 3340 3341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3342 3343 i40e_aq_erase_nvm_exit: 3344 return status; 3345 } 3346 3347 /** 3348 * i40e_parse_discover_capabilities 3349 * @hw: pointer to the hw struct 3350 * @buff: pointer to a buffer containing device/function capability records 3351 * @cap_count: number of capability records in the list 3352 * @list_type_opc: type of capabilities list to parse 3353 * 3354 * Parse the device/function capabilities list. 3355 **/ 3356 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3357 u32 cap_count, 3358 enum i40e_admin_queue_opc list_type_opc) 3359 { 3360 struct i40e_aqc_list_capabilities_element_resp *cap; 3361 u32 valid_functions, num_functions; 3362 u32 number, logical_id, phys_id; 3363 struct i40e_hw_capabilities *p; 3364 u8 major_rev; 3365 u32 i = 0; 3366 u16 id; 3367 3368 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3369 3370 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3371 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3372 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3373 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3374 else 3375 return; 3376 3377 for (i = 0; i < cap_count; i++, cap++) { 3378 id = LE16_TO_CPU(cap->id); 3379 number = LE32_TO_CPU(cap->number); 3380 logical_id = LE32_TO_CPU(cap->logical_id); 3381 phys_id = LE32_TO_CPU(cap->phys_id); 3382 major_rev = cap->major_rev; 3383 3384 switch (id) { 3385 case I40E_AQ_CAP_ID_SWITCH_MODE: 3386 p->switch_mode = number; 3387 i40e_debug(hw, I40E_DEBUG_INIT, 3388 "HW Capability: Switch mode = %d\n", 3389 p->switch_mode); 3390 break; 3391 case I40E_AQ_CAP_ID_MNG_MODE: 3392 p->management_mode = number; 3393 i40e_debug(hw, I40E_DEBUG_INIT, 3394 "HW Capability: Management Mode = %d\n", 3395 p->management_mode); 3396 break; 3397 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3398 p->npar_enable = number; 3399 i40e_debug(hw, I40E_DEBUG_INIT, 3400 "HW Capability: NPAR enable = %d\n", 3401 p->npar_enable); 3402 break; 3403 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3404 p->os2bmc = number; 3405 i40e_debug(hw, I40E_DEBUG_INIT, 3406 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3407 break; 3408 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3409 p->valid_functions = number; 3410 i40e_debug(hw, I40E_DEBUG_INIT, 3411 "HW Capability: Valid Functions = %d\n", 3412 p->valid_functions); 3413 break; 3414 case I40E_AQ_CAP_ID_SRIOV: 3415 if (number == 1) 3416 p->sr_iov_1_1 = TRUE; 3417 i40e_debug(hw, I40E_DEBUG_INIT, 3418 "HW Capability: SR-IOV = %d\n", 3419 p->sr_iov_1_1); 3420 break; 3421 case I40E_AQ_CAP_ID_VF: 3422 p->num_vfs = number; 3423 p->vf_base_id = logical_id; 3424 i40e_debug(hw, I40E_DEBUG_INIT, 3425 "HW Capability: VF count = %d\n", 3426 p->num_vfs); 3427 i40e_debug(hw, I40E_DEBUG_INIT, 3428 "HW Capability: VF base_id = %d\n", 3429 p->vf_base_id); 3430 break; 3431 case I40E_AQ_CAP_ID_VMDQ: 3432 if (number == 1) 3433 p->vmdq = TRUE; 3434 i40e_debug(hw, I40E_DEBUG_INIT, 3435 "HW Capability: VMDQ = %d\n", p->vmdq); 3436 break; 3437 case I40E_AQ_CAP_ID_8021QBG: 3438 if (number == 1) 3439 p->evb_802_1_qbg = TRUE; 3440 i40e_debug(hw, I40E_DEBUG_INIT, 3441 "HW Capability: 802.1Qbg = %d\n", number); 3442 break; 3443 case I40E_AQ_CAP_ID_8021QBR: 3444 if (number == 1) 3445 p->evb_802_1_qbh = TRUE; 3446 i40e_debug(hw, I40E_DEBUG_INIT, 3447 "HW Capability: 802.1Qbh = %d\n", number); 3448 break; 3449 case I40E_AQ_CAP_ID_VSI: 3450 p->num_vsis = number; 3451 i40e_debug(hw, I40E_DEBUG_INIT, 3452 "HW Capability: VSI count = %d\n", 3453 p->num_vsis); 3454 break; 3455 case I40E_AQ_CAP_ID_DCB: 3456 if (number == 1) { 3457 p->dcb = TRUE; 3458 p->enabled_tcmap = logical_id; 3459 p->maxtc = phys_id; 3460 } 3461 i40e_debug(hw, I40E_DEBUG_INIT, 3462 "HW Capability: DCB = %d\n", p->dcb); 3463 i40e_debug(hw, I40E_DEBUG_INIT, 3464 "HW Capability: TC Mapping = %d\n", 3465 logical_id); 3466 i40e_debug(hw, I40E_DEBUG_INIT, 3467 "HW Capability: TC Max = %d\n", p->maxtc); 3468 break; 3469 case I40E_AQ_CAP_ID_FCOE: 3470 if (number == 1) 3471 p->fcoe = TRUE; 3472 i40e_debug(hw, I40E_DEBUG_INIT, 3473 "HW Capability: FCOE = %d\n", p->fcoe); 3474 break; 3475 case I40E_AQ_CAP_ID_ISCSI: 3476 if (number == 1) 3477 p->iscsi = TRUE; 3478 i40e_debug(hw, I40E_DEBUG_INIT, 3479 "HW Capability: iSCSI = %d\n", p->iscsi); 3480 break; 3481 case I40E_AQ_CAP_ID_RSS: 3482 p->rss = TRUE; 3483 p->rss_table_size = number; 3484 p->rss_table_entry_width = logical_id; 3485 i40e_debug(hw, I40E_DEBUG_INIT, 3486 "HW Capability: RSS = %d\n", p->rss); 3487 i40e_debug(hw, I40E_DEBUG_INIT, 3488 "HW Capability: RSS table size = %d\n", 3489 p->rss_table_size); 3490 i40e_debug(hw, I40E_DEBUG_INIT, 3491 "HW Capability: RSS table width = %d\n", 3492 p->rss_table_entry_width); 3493 break; 3494 case I40E_AQ_CAP_ID_RXQ: 3495 p->num_rx_qp = number; 3496 p->base_queue = phys_id; 3497 i40e_debug(hw, I40E_DEBUG_INIT, 3498 "HW Capability: Rx QP = %d\n", number); 3499 i40e_debug(hw, I40E_DEBUG_INIT, 3500 "HW Capability: base_queue = %d\n", 3501 p->base_queue); 3502 break; 3503 case I40E_AQ_CAP_ID_TXQ: 3504 p->num_tx_qp = number; 3505 p->base_queue = phys_id; 3506 i40e_debug(hw, I40E_DEBUG_INIT, 3507 "HW Capability: Tx QP = %d\n", number); 3508 i40e_debug(hw, I40E_DEBUG_INIT, 3509 "HW Capability: base_queue = %d\n", 3510 p->base_queue); 3511 break; 3512 case I40E_AQ_CAP_ID_MSIX: 3513 p->num_msix_vectors = number; 3514 i40e_debug(hw, I40E_DEBUG_INIT, 3515 "HW Capability: MSIX vector count = %d\n", 3516 p->num_msix_vectors); 3517 break; 3518 case I40E_AQ_CAP_ID_VF_MSIX: 3519 p->num_msix_vectors_vf = number; 3520 i40e_debug(hw, I40E_DEBUG_INIT, 3521 "HW Capability: MSIX VF vector count = %d\n", 3522 p->num_msix_vectors_vf); 3523 break; 3524 case I40E_AQ_CAP_ID_FLEX10: 3525 if (major_rev == 1) { 3526 if (number == 1) { 3527 p->flex10_enable = TRUE; 3528 p->flex10_capable = TRUE; 3529 } 3530 } else { 3531 /* Capability revision >= 2 */ 3532 if (number & 1) 3533 p->flex10_enable = TRUE; 3534 if (number & 2) 3535 p->flex10_capable = TRUE; 3536 } 3537 p->flex10_mode = logical_id; 3538 p->flex10_status = phys_id; 3539 i40e_debug(hw, I40E_DEBUG_INIT, 3540 "HW Capability: Flex10 mode = %d\n", 3541 p->flex10_mode); 3542 i40e_debug(hw, I40E_DEBUG_INIT, 3543 "HW Capability: Flex10 status = %d\n", 3544 p->flex10_status); 3545 break; 3546 case I40E_AQ_CAP_ID_CEM: 3547 if (number == 1) 3548 p->mgmt_cem = TRUE; 3549 i40e_debug(hw, I40E_DEBUG_INIT, 3550 "HW Capability: CEM = %d\n", p->mgmt_cem); 3551 break; 3552 case I40E_AQ_CAP_ID_IWARP: 3553 if (number == 1) 3554 p->iwarp = TRUE; 3555 i40e_debug(hw, I40E_DEBUG_INIT, 3556 "HW Capability: iWARP = %d\n", p->iwarp); 3557 break; 3558 case I40E_AQ_CAP_ID_LED: 3559 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3560 p->led[phys_id] = TRUE; 3561 i40e_debug(hw, I40E_DEBUG_INIT, 3562 "HW Capability: LED - PIN %d\n", phys_id); 3563 break; 3564 case I40E_AQ_CAP_ID_SDP: 3565 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3566 p->sdp[phys_id] = TRUE; 3567 i40e_debug(hw, I40E_DEBUG_INIT, 3568 "HW Capability: SDP - PIN %d\n", phys_id); 3569 break; 3570 case I40E_AQ_CAP_ID_MDIO: 3571 if (number == 1) { 3572 p->mdio_port_num = phys_id; 3573 p->mdio_port_mode = logical_id; 3574 } 3575 i40e_debug(hw, I40E_DEBUG_INIT, 3576 "HW Capability: MDIO port number = %d\n", 3577 p->mdio_port_num); 3578 i40e_debug(hw, I40E_DEBUG_INIT, 3579 "HW Capability: MDIO port mode = %d\n", 3580 p->mdio_port_mode); 3581 break; 3582 case I40E_AQ_CAP_ID_1588: 3583 if (number == 1) 3584 p->ieee_1588 = TRUE; 3585 i40e_debug(hw, I40E_DEBUG_INIT, 3586 "HW Capability: IEEE 1588 = %d\n", 3587 p->ieee_1588); 3588 break; 3589 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3590 p->fd = TRUE; 3591 p->fd_filters_guaranteed = number; 3592 p->fd_filters_best_effort = logical_id; 3593 i40e_debug(hw, I40E_DEBUG_INIT, 3594 "HW Capability: Flow Director = 1\n"); 3595 i40e_debug(hw, I40E_DEBUG_INIT, 3596 "HW Capability: Guaranteed FD filters = %d\n", 3597 p->fd_filters_guaranteed); 3598 break; 3599 case I40E_AQ_CAP_ID_WSR_PROT: 3600 p->wr_csr_prot = (u64)number; 3601 p->wr_csr_prot |= (u64)logical_id << 32; 3602 i40e_debug(hw, I40E_DEBUG_INIT, 3603 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3604 (p->wr_csr_prot & 0xffff)); 3605 break; 3606 default: 3607 break; 3608 } 3609 } 3610 3611 if (p->fcoe) 3612 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3613 3614 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3615 p->fcoe = FALSE; 3616 3617 /* count the enabled ports (aka the "not disabled" ports) */ 3618 hw->num_ports = 0; 3619 for (i = 0; i < 4; i++) { 3620 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3621 u64 port_cfg = 0; 3622 3623 /* use AQ read to get the physical register offset instead 3624 * of the port relative offset 3625 */ 3626 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3627 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3628 hw->num_ports++; 3629 } 3630 3631 valid_functions = p->valid_functions; 3632 num_functions = 0; 3633 while (valid_functions) { 3634 if (valid_functions & 1) 3635 num_functions++; 3636 valid_functions >>= 1; 3637 } 3638 3639 /* partition id is 1-based, and functions are evenly spread 3640 * across the ports as partitions 3641 */ 3642 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3643 hw->num_partitions = num_functions / hw->num_ports; 3644 3645 /* additional HW specific goodies that might 3646 * someday be HW version specific 3647 */ 3648 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3649 } 3650 3651 /** 3652 * i40e_aq_discover_capabilities 3653 * @hw: pointer to the hw struct 3654 * @buff: a virtual buffer to hold the capabilities 3655 * @buff_size: Size of the virtual buffer 3656 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3657 * @list_type_opc: capabilities type to discover - pass in the command opcode 3658 * @cmd_details: pointer to command details structure or NULL 3659 * 3660 * Get the device capabilities descriptions from the firmware 3661 **/ 3662 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3663 void *buff, u16 buff_size, u16 *data_size, 3664 enum i40e_admin_queue_opc list_type_opc, 3665 struct i40e_asq_cmd_details *cmd_details) 3666 { 3667 struct i40e_aqc_list_capabilites *cmd; 3668 struct i40e_aq_desc desc; 3669 enum i40e_status_code status = I40E_SUCCESS; 3670 3671 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3672 3673 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3674 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3675 status = I40E_ERR_PARAM; 3676 goto exit; 3677 } 3678 3679 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3680 3681 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3682 if (buff_size > I40E_AQ_LARGE_BUF) 3683 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3684 3685 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3686 *data_size = LE16_TO_CPU(desc.datalen); 3687 3688 if (status) 3689 goto exit; 3690 3691 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 3692 list_type_opc); 3693 3694 exit: 3695 return status; 3696 } 3697 3698 /** 3699 * i40e_aq_update_nvm 3700 * @hw: pointer to the hw struct 3701 * @module_pointer: module pointer location in words from the NVM beginning 3702 * @offset: byte offset from the module beginning 3703 * @length: length of the section to be written (in bytes from the offset) 3704 * @data: command buffer (size [bytes] = length) 3705 * @last_command: tells if this is the last command in a series 3706 * @cmd_details: pointer to command details structure or NULL 3707 * 3708 * Update the NVM using the admin queue commands 3709 **/ 3710 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3711 u32 offset, u16 length, void *data, 3712 bool last_command, 3713 struct i40e_asq_cmd_details *cmd_details) 3714 { 3715 struct i40e_aq_desc desc; 3716 struct i40e_aqc_nvm_update *cmd = 3717 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3718 enum i40e_status_code status; 3719 3720 DEBUGFUNC("i40e_aq_update_nvm"); 3721 3722 /* In offset the highest byte must be zeroed. */ 3723 if (offset & 0xFF000000) { 3724 status = I40E_ERR_PARAM; 3725 goto i40e_aq_update_nvm_exit; 3726 } 3727 3728 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3729 3730 /* If this is the last command in a series, set the proper flag. */ 3731 if (last_command) 3732 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3733 cmd->module_pointer = module_pointer; 3734 cmd->offset = CPU_TO_LE32(offset); 3735 cmd->length = CPU_TO_LE16(length); 3736 3737 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3738 if (length > I40E_AQ_LARGE_BUF) 3739 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3740 3741 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3742 3743 i40e_aq_update_nvm_exit: 3744 return status; 3745 } 3746 3747 /** 3748 * i40e_aq_get_lldp_mib 3749 * @hw: pointer to the hw struct 3750 * @bridge_type: type of bridge requested 3751 * @mib_type: Local, Remote or both Local and Remote MIBs 3752 * @buff: pointer to a user supplied buffer to store the MIB block 3753 * @buff_size: size of the buffer (in bytes) 3754 * @local_len : length of the returned Local LLDP MIB 3755 * @remote_len: length of the returned Remote LLDP MIB 3756 * @cmd_details: pointer to command details structure or NULL 3757 * 3758 * Requests the complete LLDP MIB (entire packet). 3759 **/ 3760 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3761 u8 mib_type, void *buff, u16 buff_size, 3762 u16 *local_len, u16 *remote_len, 3763 struct i40e_asq_cmd_details *cmd_details) 3764 { 3765 struct i40e_aq_desc desc; 3766 struct i40e_aqc_lldp_get_mib *cmd = 3767 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3768 struct i40e_aqc_lldp_get_mib *resp = 3769 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3770 enum i40e_status_code status; 3771 3772 if (buff_size == 0 || !buff) 3773 return I40E_ERR_PARAM; 3774 3775 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3776 /* Indirect Command */ 3777 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3778 3779 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3780 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3781 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3782 3783 desc.datalen = CPU_TO_LE16(buff_size); 3784 3785 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3786 if (buff_size > I40E_AQ_LARGE_BUF) 3787 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3788 3789 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3790 if (!status) { 3791 if (local_len != NULL) 3792 *local_len = LE16_TO_CPU(resp->local_len); 3793 if (remote_len != NULL) 3794 *remote_len = LE16_TO_CPU(resp->remote_len); 3795 } 3796 3797 return status; 3798 } 3799 3800 /** 3801 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3802 * @hw: pointer to the hw struct 3803 * @mib_type: Local, Remote or both Local and Remote MIBs 3804 * @buff: pointer to a user supplied buffer to store the MIB block 3805 * @buff_size: size of the buffer (in bytes) 3806 * @cmd_details: pointer to command details structure or NULL 3807 * 3808 * Set the LLDP MIB. 3809 **/ 3810 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3811 u8 mib_type, void *buff, u16 buff_size, 3812 struct i40e_asq_cmd_details *cmd_details) 3813 { 3814 struct i40e_aq_desc desc; 3815 struct i40e_aqc_lldp_set_local_mib *cmd = 3816 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 3817 enum i40e_status_code status; 3818 3819 if (buff_size == 0 || !buff) 3820 return I40E_ERR_PARAM; 3821 3822 i40e_fill_default_direct_cmd_desc(&desc, 3823 i40e_aqc_opc_lldp_set_local_mib); 3824 /* Indirect Command */ 3825 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3826 if (buff_size > I40E_AQ_LARGE_BUF) 3827 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3828 desc.datalen = CPU_TO_LE16(buff_size); 3829 3830 cmd->type = mib_type; 3831 cmd->length = CPU_TO_LE16(buff_size); 3832 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff)); 3833 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 3834 3835 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3836 return status; 3837 } 3838 3839 /** 3840 * i40e_aq_cfg_lldp_mib_change_event 3841 * @hw: pointer to the hw struct 3842 * @enable_update: Enable or Disable event posting 3843 * @cmd_details: pointer to command details structure or NULL 3844 * 3845 * Enable or Disable posting of an event on ARQ when LLDP MIB 3846 * associated with the interface changes 3847 **/ 3848 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3849 bool enable_update, 3850 struct i40e_asq_cmd_details *cmd_details) 3851 { 3852 struct i40e_aq_desc desc; 3853 struct i40e_aqc_lldp_update_mib *cmd = 3854 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3855 enum i40e_status_code status; 3856 3857 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3858 3859 if (!enable_update) 3860 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3861 3862 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3863 3864 return status; 3865 } 3866 3867 /** 3868 * i40e_aq_add_lldp_tlv 3869 * @hw: pointer to the hw struct 3870 * @bridge_type: type of bridge 3871 * @buff: buffer with TLV to add 3872 * @buff_size: length of the buffer 3873 * @tlv_len: length of the TLV to be added 3874 * @mib_len: length of the LLDP MIB returned in response 3875 * @cmd_details: pointer to command details structure or NULL 3876 * 3877 * Add the specified TLV to LLDP Local MIB for the given bridge type, 3878 * it is responsibility of the caller to make sure that the TLV is not 3879 * already present in the LLDPDU. 3880 * In return firmware will write the complete LLDP MIB with the newly 3881 * added TLV in the response buffer. 3882 **/ 3883 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 3884 void *buff, u16 buff_size, u16 tlv_len, 3885 u16 *mib_len, 3886 struct i40e_asq_cmd_details *cmd_details) 3887 { 3888 struct i40e_aq_desc desc; 3889 struct i40e_aqc_lldp_add_tlv *cmd = 3890 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3891 enum i40e_status_code status; 3892 3893 if (buff_size == 0 || !buff || tlv_len == 0) 3894 return I40E_ERR_PARAM; 3895 3896 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 3897 3898 /* Indirect Command */ 3899 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3900 if (buff_size > I40E_AQ_LARGE_BUF) 3901 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3902 desc.datalen = CPU_TO_LE16(buff_size); 3903 3904 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3905 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3906 cmd->len = CPU_TO_LE16(tlv_len); 3907 3908 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3909 if (!status) { 3910 if (mib_len != NULL) 3911 *mib_len = LE16_TO_CPU(desc.datalen); 3912 } 3913 3914 return status; 3915 } 3916 3917 /** 3918 * i40e_aq_update_lldp_tlv 3919 * @hw: pointer to the hw struct 3920 * @bridge_type: type of bridge 3921 * @buff: buffer with TLV to update 3922 * @buff_size: size of the buffer holding original and updated TLVs 3923 * @old_len: Length of the Original TLV 3924 * @new_len: Length of the Updated TLV 3925 * @offset: offset of the updated TLV in the buff 3926 * @mib_len: length of the returned LLDP MIB 3927 * @cmd_details: pointer to command details structure or NULL 3928 * 3929 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 3930 * Firmware will place the complete LLDP MIB in response buffer with the 3931 * updated TLV. 3932 **/ 3933 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 3934 u8 bridge_type, void *buff, u16 buff_size, 3935 u16 old_len, u16 new_len, u16 offset, 3936 u16 *mib_len, 3937 struct i40e_asq_cmd_details *cmd_details) 3938 { 3939 struct i40e_aq_desc desc; 3940 struct i40e_aqc_lldp_update_tlv *cmd = 3941 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 3942 enum i40e_status_code status; 3943 3944 if (buff_size == 0 || !buff || offset == 0 || 3945 old_len == 0 || new_len == 0) 3946 return I40E_ERR_PARAM; 3947 3948 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 3949 3950 /* Indirect Command */ 3951 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3952 if (buff_size > I40E_AQ_LARGE_BUF) 3953 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3954 desc.datalen = CPU_TO_LE16(buff_size); 3955 3956 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3957 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3958 cmd->old_len = CPU_TO_LE16(old_len); 3959 cmd->new_offset = CPU_TO_LE16(offset); 3960 cmd->new_len = CPU_TO_LE16(new_len); 3961 3962 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3963 if (!status) { 3964 if (mib_len != NULL) 3965 *mib_len = LE16_TO_CPU(desc.datalen); 3966 } 3967 3968 return status; 3969 } 3970 3971 /** 3972 * i40e_aq_delete_lldp_tlv 3973 * @hw: pointer to the hw struct 3974 * @bridge_type: type of bridge 3975 * @buff: pointer to a user supplied buffer that has the TLV 3976 * @buff_size: length of the buffer 3977 * @tlv_len: length of the TLV to be deleted 3978 * @mib_len: length of the returned LLDP MIB 3979 * @cmd_details: pointer to command details structure or NULL 3980 * 3981 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 3982 * The firmware places the entire LLDP MIB in the response buffer. 3983 **/ 3984 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 3985 u8 bridge_type, void *buff, u16 buff_size, 3986 u16 tlv_len, u16 *mib_len, 3987 struct i40e_asq_cmd_details *cmd_details) 3988 { 3989 struct i40e_aq_desc desc; 3990 struct i40e_aqc_lldp_add_tlv *cmd = 3991 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3992 enum i40e_status_code status; 3993 3994 if (buff_size == 0 || !buff) 3995 return I40E_ERR_PARAM; 3996 3997 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 3998 3999 /* Indirect Command */ 4000 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4001 if (buff_size > I40E_AQ_LARGE_BUF) 4002 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4003 desc.datalen = CPU_TO_LE16(buff_size); 4004 cmd->len = CPU_TO_LE16(tlv_len); 4005 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4006 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4007 4008 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4009 if (!status) { 4010 if (mib_len != NULL) 4011 *mib_len = LE16_TO_CPU(desc.datalen); 4012 } 4013 4014 return status; 4015 } 4016 4017 /** 4018 * i40e_aq_stop_lldp 4019 * @hw: pointer to the hw struct 4020 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4021 * @cmd_details: pointer to command details structure or NULL 4022 * 4023 * Stop or Shutdown the embedded LLDP Agent 4024 **/ 4025 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4026 struct i40e_asq_cmd_details *cmd_details) 4027 { 4028 struct i40e_aq_desc desc; 4029 struct i40e_aqc_lldp_stop *cmd = 4030 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4031 enum i40e_status_code status; 4032 4033 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4034 4035 if (shutdown_agent) 4036 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4037 4038 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4039 4040 return status; 4041 } 4042 4043 /** 4044 * i40e_aq_start_lldp 4045 * @hw: pointer to the hw struct 4046 * @cmd_details: pointer to command details structure or NULL 4047 * 4048 * Start the embedded LLDP Agent on all ports. 4049 **/ 4050 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4051 struct i40e_asq_cmd_details *cmd_details) 4052 { 4053 struct i40e_aq_desc desc; 4054 struct i40e_aqc_lldp_start *cmd = 4055 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4056 enum i40e_status_code status; 4057 4058 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4059 4060 cmd->command = I40E_AQ_LLDP_AGENT_START; 4061 4062 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4063 4064 return status; 4065 } 4066 4067 /** 4068 * i40e_aq_get_cee_dcb_config 4069 * @hw: pointer to the hw struct 4070 * @buff: response buffer that stores CEE operational configuration 4071 * @buff_size: size of the buffer passed 4072 * @cmd_details: pointer to command details structure or NULL 4073 * 4074 * Get CEE DCBX mode operational configuration from firmware 4075 **/ 4076 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4077 void *buff, u16 buff_size, 4078 struct i40e_asq_cmd_details *cmd_details) 4079 { 4080 struct i40e_aq_desc desc; 4081 enum i40e_status_code status; 4082 4083 if (buff_size == 0 || !buff) 4084 return I40E_ERR_PARAM; 4085 4086 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4087 4088 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4089 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4090 cmd_details); 4091 4092 return status; 4093 } 4094 4095 /** 4096 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4097 * @hw: pointer to the hw struct 4098 * @start_agent: True if DCBx Agent needs to be Started 4099 * False if DCBx Agent needs to be Stopped 4100 * @cmd_details: pointer to command details structure or NULL 4101 * 4102 * Start/Stop the embedded dcbx Agent 4103 **/ 4104 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4105 bool start_agent, 4106 struct i40e_asq_cmd_details *cmd_details) 4107 { 4108 struct i40e_aq_desc desc; 4109 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4110 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4111 &desc.params.raw; 4112 enum i40e_status_code status; 4113 4114 i40e_fill_default_direct_cmd_desc(&desc, 4115 i40e_aqc_opc_lldp_stop_start_spec_agent); 4116 4117 if (start_agent) 4118 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4119 4120 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4121 4122 return status; 4123 } 4124 4125 /** 4126 * i40e_aq_add_udp_tunnel 4127 * @hw: pointer to the hw struct 4128 * @udp_port: the UDP port to add 4129 * @header_len: length of the tunneling header length in DWords 4130 * @protocol_index: protocol index type 4131 * @filter_index: pointer to filter index 4132 * @cmd_details: pointer to command details structure or NULL 4133 **/ 4134 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4135 u16 udp_port, u8 protocol_index, 4136 u8 *filter_index, 4137 struct i40e_asq_cmd_details *cmd_details) 4138 { 4139 struct i40e_aq_desc desc; 4140 struct i40e_aqc_add_udp_tunnel *cmd = 4141 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4142 struct i40e_aqc_del_udp_tunnel_completion *resp = 4143 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4144 enum i40e_status_code status; 4145 4146 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4147 4148 cmd->udp_port = CPU_TO_LE16(udp_port); 4149 cmd->protocol_type = protocol_index; 4150 4151 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4152 4153 if (!status && filter_index) 4154 *filter_index = resp->index; 4155 4156 return status; 4157 } 4158 4159 /** 4160 * i40e_aq_del_udp_tunnel 4161 * @hw: pointer to the hw struct 4162 * @index: filter index 4163 * @cmd_details: pointer to command details structure or NULL 4164 **/ 4165 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4166 struct i40e_asq_cmd_details *cmd_details) 4167 { 4168 struct i40e_aq_desc desc; 4169 struct i40e_aqc_remove_udp_tunnel *cmd = 4170 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4171 enum i40e_status_code status; 4172 4173 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4174 4175 cmd->index = index; 4176 4177 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4178 4179 return status; 4180 } 4181 4182 /** 4183 * i40e_aq_get_switch_resource_alloc (0x0204) 4184 * @hw: pointer to the hw struct 4185 * @num_entries: pointer to u8 to store the number of resource entries returned 4186 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4187 * to store the resource information for all resource types. Each 4188 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4189 * @count: size, in bytes, of the buffer provided 4190 * @cmd_details: pointer to command details structure or NULL 4191 * 4192 * Query the resources allocated to a function. 4193 **/ 4194 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4195 u8 *num_entries, 4196 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4197 u16 count, 4198 struct i40e_asq_cmd_details *cmd_details) 4199 { 4200 struct i40e_aq_desc desc; 4201 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4202 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4203 enum i40e_status_code status; 4204 u16 length = count * sizeof(*buf); 4205 4206 i40e_fill_default_direct_cmd_desc(&desc, 4207 i40e_aqc_opc_get_switch_resource_alloc); 4208 4209 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4210 if (length > I40E_AQ_LARGE_BUF) 4211 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4212 4213 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4214 4215 if (!status && num_entries) 4216 *num_entries = cmd_resp->num_entries; 4217 4218 return status; 4219 } 4220 4221 /** 4222 * i40e_aq_delete_element - Delete switch element 4223 * @hw: pointer to the hw struct 4224 * @seid: the SEID to delete from the switch 4225 * @cmd_details: pointer to command details structure or NULL 4226 * 4227 * This deletes a switch element from the switch. 4228 **/ 4229 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4230 struct i40e_asq_cmd_details *cmd_details) 4231 { 4232 struct i40e_aq_desc desc; 4233 struct i40e_aqc_switch_seid *cmd = 4234 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4235 enum i40e_status_code status; 4236 4237 if (seid == 0) 4238 return I40E_ERR_PARAM; 4239 4240 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4241 4242 cmd->seid = CPU_TO_LE16(seid); 4243 4244 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4245 4246 return status; 4247 } 4248 4249 /** 4250 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4251 * @hw: pointer to the hw struct 4252 * @flags: component flags 4253 * @mac_seid: uplink seid (MAC SEID) 4254 * @vsi_seid: connected vsi seid 4255 * @ret_seid: seid of create pv component 4256 * 4257 * This instantiates an i40e port virtualizer with specified flags. 4258 * Depending on specified flags the port virtualizer can act as a 4259 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4260 */ 4261 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4262 u16 mac_seid, u16 vsi_seid, 4263 u16 *ret_seid) 4264 { 4265 struct i40e_aq_desc desc; 4266 struct i40e_aqc_add_update_pv *cmd = 4267 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4268 struct i40e_aqc_add_update_pv_completion *resp = 4269 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4270 enum i40e_status_code status; 4271 4272 if (vsi_seid == 0) 4273 return I40E_ERR_PARAM; 4274 4275 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4276 cmd->command_flags = CPU_TO_LE16(flags); 4277 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4278 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4279 4280 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4281 if (!status && ret_seid) 4282 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4283 4284 return status; 4285 } 4286 4287 /** 4288 * i40e_aq_add_tag - Add an S/E-tag 4289 * @hw: pointer to the hw struct 4290 * @direct_to_queue: should s-tag direct flow to a specific queue 4291 * @vsi_seid: VSI SEID to use this tag 4292 * @tag: value of the tag 4293 * @queue_num: queue number, only valid is direct_to_queue is TRUE 4294 * @tags_used: return value, number of tags in use by this PF 4295 * @tags_free: return value, number of unallocated tags 4296 * @cmd_details: pointer to command details structure or NULL 4297 * 4298 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4299 * the number of tags allocated by the PF, and the number of unallocated 4300 * tags available. 4301 **/ 4302 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4303 u16 vsi_seid, u16 tag, u16 queue_num, 4304 u16 *tags_used, u16 *tags_free, 4305 struct i40e_asq_cmd_details *cmd_details) 4306 { 4307 struct i40e_aq_desc desc; 4308 struct i40e_aqc_add_tag *cmd = 4309 (struct i40e_aqc_add_tag *)&desc.params.raw; 4310 struct i40e_aqc_add_remove_tag_completion *resp = 4311 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4312 enum i40e_status_code status; 4313 4314 if (vsi_seid == 0) 4315 return I40E_ERR_PARAM; 4316 4317 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4318 4319 cmd->seid = CPU_TO_LE16(vsi_seid); 4320 cmd->tag = CPU_TO_LE16(tag); 4321 if (direct_to_queue) { 4322 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4323 cmd->queue_number = CPU_TO_LE16(queue_num); 4324 } 4325 4326 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4327 4328 if (!status) { 4329 if (tags_used != NULL) 4330 *tags_used = LE16_TO_CPU(resp->tags_used); 4331 if (tags_free != NULL) 4332 *tags_free = LE16_TO_CPU(resp->tags_free); 4333 } 4334 4335 return status; 4336 } 4337 4338 /** 4339 * i40e_aq_remove_tag - Remove an S- or E-tag 4340 * @hw: pointer to the hw struct 4341 * @vsi_seid: VSI SEID this tag is associated with 4342 * @tag: value of the S-tag to delete 4343 * @tags_used: return value, number of tags in use by this PF 4344 * @tags_free: return value, number of unallocated tags 4345 * @cmd_details: pointer to command details structure or NULL 4346 * 4347 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4348 * the number of tags allocated by the PF, and the number of unallocated 4349 * tags available. 4350 **/ 4351 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4352 u16 tag, u16 *tags_used, u16 *tags_free, 4353 struct i40e_asq_cmd_details *cmd_details) 4354 { 4355 struct i40e_aq_desc desc; 4356 struct i40e_aqc_remove_tag *cmd = 4357 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4358 struct i40e_aqc_add_remove_tag_completion *resp = 4359 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4360 enum i40e_status_code status; 4361 4362 if (vsi_seid == 0) 4363 return I40E_ERR_PARAM; 4364 4365 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4366 4367 cmd->seid = CPU_TO_LE16(vsi_seid); 4368 cmd->tag = CPU_TO_LE16(tag); 4369 4370 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4371 4372 if (!status) { 4373 if (tags_used != NULL) 4374 *tags_used = LE16_TO_CPU(resp->tags_used); 4375 if (tags_free != NULL) 4376 *tags_free = LE16_TO_CPU(resp->tags_free); 4377 } 4378 4379 return status; 4380 } 4381 4382 /** 4383 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4384 * @hw: pointer to the hw struct 4385 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4386 * @etag: value of E-tag to add 4387 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4388 * @buf: address of indirect buffer 4389 * @tags_used: return value, number of E-tags in use by this port 4390 * @tags_free: return value, number of unallocated M-tags 4391 * @cmd_details: pointer to command details structure or NULL 4392 * 4393 * This associates a multicast E-tag to a port virtualizer. It will return 4394 * the number of tags allocated by the PF, and the number of unallocated 4395 * tags available. 4396 * 4397 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4398 * num_tags_in_buf long. 4399 **/ 4400 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4401 u16 etag, u8 num_tags_in_buf, void *buf, 4402 u16 *tags_used, u16 *tags_free, 4403 struct i40e_asq_cmd_details *cmd_details) 4404 { 4405 struct i40e_aq_desc desc; 4406 struct i40e_aqc_add_remove_mcast_etag *cmd = 4407 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4408 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4409 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4410 enum i40e_status_code status; 4411 u16 length = sizeof(u16) * num_tags_in_buf; 4412 4413 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4414 return I40E_ERR_PARAM; 4415 4416 i40e_fill_default_direct_cmd_desc(&desc, 4417 i40e_aqc_opc_add_multicast_etag); 4418 4419 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4420 cmd->etag = CPU_TO_LE16(etag); 4421 cmd->num_unicast_etags = num_tags_in_buf; 4422 4423 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4424 if (length > I40E_AQ_LARGE_BUF) 4425 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4426 4427 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4428 4429 if (!status) { 4430 if (tags_used != NULL) 4431 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4432 if (tags_free != NULL) 4433 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4434 } 4435 4436 return status; 4437 } 4438 4439 /** 4440 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4441 * @hw: pointer to the hw struct 4442 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4443 * @etag: value of the E-tag to remove 4444 * @tags_used: return value, number of tags in use by this port 4445 * @tags_free: return value, number of unallocated tags 4446 * @cmd_details: pointer to command details structure or NULL 4447 * 4448 * This deletes an E-tag from the port virtualizer. It will return 4449 * the number of tags allocated by the port, and the number of unallocated 4450 * tags available. 4451 **/ 4452 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4453 u16 etag, u16 *tags_used, u16 *tags_free, 4454 struct i40e_asq_cmd_details *cmd_details) 4455 { 4456 struct i40e_aq_desc desc; 4457 struct i40e_aqc_add_remove_mcast_etag *cmd = 4458 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4459 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4460 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4461 enum i40e_status_code status; 4462 4463 4464 if (pv_seid == 0) 4465 return I40E_ERR_PARAM; 4466 4467 i40e_fill_default_direct_cmd_desc(&desc, 4468 i40e_aqc_opc_remove_multicast_etag); 4469 4470 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4471 cmd->etag = CPU_TO_LE16(etag); 4472 4473 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4474 4475 if (!status) { 4476 if (tags_used != NULL) 4477 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4478 if (tags_free != NULL) 4479 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4480 } 4481 4482 return status; 4483 } 4484 4485 /** 4486 * i40e_aq_update_tag - Update an S/E-tag 4487 * @hw: pointer to the hw struct 4488 * @vsi_seid: VSI SEID using this S-tag 4489 * @old_tag: old tag value 4490 * @new_tag: new tag value 4491 * @tags_used: return value, number of tags in use by this PF 4492 * @tags_free: return value, number of unallocated tags 4493 * @cmd_details: pointer to command details structure or NULL 4494 * 4495 * This updates the value of the tag currently attached to this VSI 4496 * in the switch complex. It will return the number of tags allocated 4497 * by the PF, and the number of unallocated tags available. 4498 **/ 4499 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4500 u16 old_tag, u16 new_tag, u16 *tags_used, 4501 u16 *tags_free, 4502 struct i40e_asq_cmd_details *cmd_details) 4503 { 4504 struct i40e_aq_desc desc; 4505 struct i40e_aqc_update_tag *cmd = 4506 (struct i40e_aqc_update_tag *)&desc.params.raw; 4507 struct i40e_aqc_update_tag_completion *resp = 4508 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4509 enum i40e_status_code status; 4510 4511 if (vsi_seid == 0) 4512 return I40E_ERR_PARAM; 4513 4514 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4515 4516 cmd->seid = CPU_TO_LE16(vsi_seid); 4517 cmd->old_tag = CPU_TO_LE16(old_tag); 4518 cmd->new_tag = CPU_TO_LE16(new_tag); 4519 4520 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4521 4522 if (!status) { 4523 if (tags_used != NULL) 4524 *tags_used = LE16_TO_CPU(resp->tags_used); 4525 if (tags_free != NULL) 4526 *tags_free = LE16_TO_CPU(resp->tags_free); 4527 } 4528 4529 return status; 4530 } 4531 4532 /** 4533 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4534 * @hw: pointer to the hw struct 4535 * @tcmap: TC map for request/release any ignore PFC condition 4536 * @request: request or release ignore PFC condition 4537 * @tcmap_ret: return TCs for which PFC is currently ignored 4538 * @cmd_details: pointer to command details structure or NULL 4539 * 4540 * This sends out request/release to ignore PFC condition for a TC. 4541 * It will return the TCs for which PFC is currently ignored. 4542 **/ 4543 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4544 bool request, u8 *tcmap_ret, 4545 struct i40e_asq_cmd_details *cmd_details) 4546 { 4547 struct i40e_aq_desc desc; 4548 struct i40e_aqc_pfc_ignore *cmd_resp = 4549 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4550 enum i40e_status_code status; 4551 4552 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4553 4554 if (request) 4555 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4556 4557 cmd_resp->tc_bitmap = tcmap; 4558 4559 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4560 4561 if (!status) { 4562 if (tcmap_ret != NULL) 4563 *tcmap_ret = cmd_resp->tc_bitmap; 4564 } 4565 4566 return status; 4567 } 4568 4569 /** 4570 * i40e_aq_dcb_updated - DCB Updated Command 4571 * @hw: pointer to the hw struct 4572 * @cmd_details: pointer to command details structure or NULL 4573 * 4574 * When LLDP is handled in PF this command is used by the PF 4575 * to notify EMP that a DCB setting is modified. 4576 * When LLDP is handled in EMP this command is used by the PF 4577 * to notify EMP whenever one of the following parameters get 4578 * modified: 4579 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4580 * - PCIRTT in PRTDCB_GENC.PCIRTT 4581 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4582 * EMP will return when the shared RPB settings have been 4583 * recomputed and modified. The retval field in the descriptor 4584 * will be set to 0 when RPB is modified. 4585 **/ 4586 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4587 struct i40e_asq_cmd_details *cmd_details) 4588 { 4589 struct i40e_aq_desc desc; 4590 enum i40e_status_code status; 4591 4592 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4593 4594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4595 4596 return status; 4597 } 4598 4599 /** 4600 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4601 * @hw: pointer to the hw struct 4602 * @seid: defines the SEID of the switch for which the stats are requested 4603 * @vlan_id: the VLAN ID for which the statistics are requested 4604 * @stat_index: index of the statistics counters block assigned to this VLAN 4605 * @cmd_details: pointer to command details structure or NULL 4606 * 4607 * XL710 supports 128 smonVlanStats counters.This command is used to 4608 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4609 * switch. 4610 **/ 4611 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4612 u16 vlan_id, u16 *stat_index, 4613 struct i40e_asq_cmd_details *cmd_details) 4614 { 4615 struct i40e_aq_desc desc; 4616 struct i40e_aqc_add_remove_statistics *cmd_resp = 4617 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4618 enum i40e_status_code status; 4619 4620 if ((seid == 0) || (stat_index == NULL)) 4621 return I40E_ERR_PARAM; 4622 4623 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 4624 4625 cmd_resp->seid = CPU_TO_LE16(seid); 4626 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 4627 4628 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4629 4630 if (!status && stat_index) 4631 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 4632 4633 return status; 4634 } 4635 4636 /** 4637 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 4638 * @hw: pointer to the hw struct 4639 * @seid: defines the SEID of the switch for which the stats are requested 4640 * @vlan_id: the VLAN ID for which the statistics are requested 4641 * @stat_index: index of the statistics counters block assigned to this VLAN 4642 * @cmd_details: pointer to command details structure or NULL 4643 * 4644 * XL710 supports 128 smonVlanStats counters.This command is used to 4645 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 4646 * switch. 4647 **/ 4648 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 4649 u16 vlan_id, u16 stat_index, 4650 struct i40e_asq_cmd_details *cmd_details) 4651 { 4652 struct i40e_aq_desc desc; 4653 struct i40e_aqc_add_remove_statistics *cmd = 4654 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4655 enum i40e_status_code status; 4656 4657 if (seid == 0) 4658 return I40E_ERR_PARAM; 4659 4660 i40e_fill_default_direct_cmd_desc(&desc, 4661 i40e_aqc_opc_remove_statistics); 4662 4663 cmd->seid = CPU_TO_LE16(seid); 4664 cmd->vlan = CPU_TO_LE16(vlan_id); 4665 cmd->stat_index = CPU_TO_LE16(stat_index); 4666 4667 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4668 4669 return status; 4670 } 4671 4672 /** 4673 * i40e_aq_set_port_parameters - set physical port parameters. 4674 * @hw: pointer to the hw struct 4675 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 4676 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 4677 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 4678 * @double_vlan: if set double VLAN is enabled 4679 * @cmd_details: pointer to command details structure or NULL 4680 **/ 4681 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 4682 u16 bad_frame_vsi, bool save_bad_pac, 4683 bool pad_short_pac, bool double_vlan, 4684 struct i40e_asq_cmd_details *cmd_details) 4685 { 4686 struct i40e_aqc_set_port_parameters *cmd; 4687 enum i40e_status_code status; 4688 struct i40e_aq_desc desc; 4689 u16 command_flags = 0; 4690 4691 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 4692 4693 i40e_fill_default_direct_cmd_desc(&desc, 4694 i40e_aqc_opc_set_port_parameters); 4695 4696 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 4697 if (save_bad_pac) 4698 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 4699 if (pad_short_pac) 4700 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 4701 if (double_vlan) 4702 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 4703 cmd->command_flags = CPU_TO_LE16(command_flags); 4704 4705 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4706 4707 return status; 4708 } 4709 4710 /** 4711 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 4712 * @hw: pointer to the hw struct 4713 * @seid: seid for the physical port/switching component/vsi 4714 * @buff: Indirect buffer to hold data parameters and response 4715 * @buff_size: Indirect buffer size 4716 * @opcode: Tx scheduler AQ command opcode 4717 * @cmd_details: pointer to command details structure or NULL 4718 * 4719 * Generic command handler for Tx scheduler AQ commands 4720 **/ 4721 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 4722 void *buff, u16 buff_size, 4723 enum i40e_admin_queue_opc opcode, 4724 struct i40e_asq_cmd_details *cmd_details) 4725 { 4726 struct i40e_aq_desc desc; 4727 struct i40e_aqc_tx_sched_ind *cmd = 4728 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 4729 enum i40e_status_code status; 4730 bool cmd_param_flag = FALSE; 4731 4732 switch (opcode) { 4733 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 4734 case i40e_aqc_opc_configure_vsi_tc_bw: 4735 case i40e_aqc_opc_enable_switching_comp_ets: 4736 case i40e_aqc_opc_modify_switching_comp_ets: 4737 case i40e_aqc_opc_disable_switching_comp_ets: 4738 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 4739 case i40e_aqc_opc_configure_switching_comp_bw_config: 4740 cmd_param_flag = TRUE; 4741 break; 4742 case i40e_aqc_opc_query_vsi_bw_config: 4743 case i40e_aqc_opc_query_vsi_ets_sla_config: 4744 case i40e_aqc_opc_query_switching_comp_ets_config: 4745 case i40e_aqc_opc_query_port_ets_config: 4746 case i40e_aqc_opc_query_switching_comp_bw_config: 4747 cmd_param_flag = FALSE; 4748 break; 4749 default: 4750 return I40E_ERR_PARAM; 4751 } 4752 4753 i40e_fill_default_direct_cmd_desc(&desc, opcode); 4754 4755 /* Indirect command */ 4756 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4757 if (cmd_param_flag) 4758 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 4759 if (buff_size > I40E_AQ_LARGE_BUF) 4760 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4761 4762 desc.datalen = CPU_TO_LE16(buff_size); 4763 4764 cmd->vsi_seid = CPU_TO_LE16(seid); 4765 4766 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4767 4768 return status; 4769 } 4770 4771 /** 4772 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 4773 * @hw: pointer to the hw struct 4774 * @seid: VSI seid 4775 * @credit: BW limit credits (0 = disabled) 4776 * @max_credit: Max BW limit credits 4777 * @cmd_details: pointer to command details structure or NULL 4778 **/ 4779 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 4780 u16 seid, u16 credit, u8 max_credit, 4781 struct i40e_asq_cmd_details *cmd_details) 4782 { 4783 struct i40e_aq_desc desc; 4784 struct i40e_aqc_configure_vsi_bw_limit *cmd = 4785 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 4786 enum i40e_status_code status; 4787 4788 i40e_fill_default_direct_cmd_desc(&desc, 4789 i40e_aqc_opc_configure_vsi_bw_limit); 4790 4791 cmd->vsi_seid = CPU_TO_LE16(seid); 4792 cmd->credit = CPU_TO_LE16(credit); 4793 cmd->max_credit = max_credit; 4794 4795 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4796 4797 return status; 4798 } 4799 4800 /** 4801 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 4802 * @hw: pointer to the hw struct 4803 * @seid: switching component seid 4804 * @credit: BW limit credits (0 = disabled) 4805 * @max_bw: Max BW limit credits 4806 * @cmd_details: pointer to command details structure or NULL 4807 **/ 4808 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 4809 u16 seid, u16 credit, u8 max_bw, 4810 struct i40e_asq_cmd_details *cmd_details) 4811 { 4812 struct i40e_aq_desc desc; 4813 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 4814 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 4815 enum i40e_status_code status; 4816 4817 i40e_fill_default_direct_cmd_desc(&desc, 4818 i40e_aqc_opc_configure_switching_comp_bw_limit); 4819 4820 cmd->seid = CPU_TO_LE16(seid); 4821 cmd->credit = CPU_TO_LE16(credit); 4822 cmd->max_bw = max_bw; 4823 4824 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4825 4826 return status; 4827 } 4828 4829 /** 4830 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 4831 * @hw: pointer to the hw struct 4832 * @seid: VSI seid 4833 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 4834 * @cmd_details: pointer to command details structure or NULL 4835 **/ 4836 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 4837 u16 seid, 4838 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 4839 struct i40e_asq_cmd_details *cmd_details) 4840 { 4841 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4842 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 4843 cmd_details); 4844 } 4845 4846 /** 4847 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 4848 * @hw: pointer to the hw struct 4849 * @seid: VSI seid 4850 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 4851 * @cmd_details: pointer to command details structure or NULL 4852 **/ 4853 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 4854 u16 seid, 4855 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 4856 struct i40e_asq_cmd_details *cmd_details) 4857 { 4858 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4859 i40e_aqc_opc_configure_vsi_tc_bw, 4860 cmd_details); 4861 } 4862 4863 /** 4864 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 4865 * @hw: pointer to the hw struct 4866 * @seid: seid of the switching component 4867 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 4868 * @cmd_details: pointer to command details structure or NULL 4869 **/ 4870 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 4871 struct i40e_hw *hw, u16 seid, 4872 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 4873 struct i40e_asq_cmd_details *cmd_details) 4874 { 4875 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4876 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 4877 cmd_details); 4878 } 4879 4880 /** 4881 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 4882 * @hw: pointer to the hw struct 4883 * @seid: seid of the VSI 4884 * @bw_data: Buffer to hold VSI BW configuration 4885 * @cmd_details: pointer to command details structure or NULL 4886 **/ 4887 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 4888 u16 seid, 4889 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 4890 struct i40e_asq_cmd_details *cmd_details) 4891 { 4892 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4893 i40e_aqc_opc_query_vsi_bw_config, 4894 cmd_details); 4895 } 4896 4897 /** 4898 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 4899 * @hw: pointer to the hw struct 4900 * @seid: seid of the VSI 4901 * @bw_data: Buffer to hold VSI BW configuration per TC 4902 * @cmd_details: pointer to command details structure or NULL 4903 **/ 4904 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 4905 u16 seid, 4906 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 4907 struct i40e_asq_cmd_details *cmd_details) 4908 { 4909 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4910 i40e_aqc_opc_query_vsi_ets_sla_config, 4911 cmd_details); 4912 } 4913 4914 /** 4915 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 4916 * @hw: pointer to the hw struct 4917 * @seid: seid of the switching component 4918 * @bw_data: Buffer to hold switching component's per TC BW config 4919 * @cmd_details: pointer to command details structure or NULL 4920 **/ 4921 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 4922 u16 seid, 4923 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 4924 struct i40e_asq_cmd_details *cmd_details) 4925 { 4926 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4927 i40e_aqc_opc_query_switching_comp_ets_config, 4928 cmd_details); 4929 } 4930 4931 /** 4932 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 4933 * @hw: pointer to the hw struct 4934 * @seid: seid of the VSI or switching component connected to Physical Port 4935 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 4936 * @cmd_details: pointer to command details structure or NULL 4937 **/ 4938 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 4939 u16 seid, 4940 struct i40e_aqc_query_port_ets_config_resp *bw_data, 4941 struct i40e_asq_cmd_details *cmd_details) 4942 { 4943 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4944 i40e_aqc_opc_query_port_ets_config, 4945 cmd_details); 4946 } 4947 4948 /** 4949 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 4950 * @hw: pointer to the hw struct 4951 * @seid: seid of the switching component 4952 * @bw_data: Buffer to hold switching component's BW configuration 4953 * @cmd_details: pointer to command details structure or NULL 4954 **/ 4955 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4956 u16 seid, 4957 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4958 struct i40e_asq_cmd_details *cmd_details) 4959 { 4960 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4961 i40e_aqc_opc_query_switching_comp_bw_config, 4962 cmd_details); 4963 } 4964 4965 /** 4966 * i40e_validate_filter_settings 4967 * @hw: pointer to the hardware structure 4968 * @settings: Filter control settings 4969 * 4970 * Check and validate the filter control settings passed. 4971 * The function checks for the valid filter/context sizes being 4972 * passed for FCoE and PE. 4973 * 4974 * Returns I40E_SUCCESS if the values passed are valid and within 4975 * range else returns an error. 4976 **/ 4977 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 4978 struct i40e_filter_control_settings *settings) 4979 { 4980 u32 fcoe_cntx_size, fcoe_filt_size; 4981 u32 pe_cntx_size, pe_filt_size; 4982 u32 fcoe_fmax; 4983 4984 u32 val; 4985 4986 /* Validate FCoE settings passed */ 4987 switch (settings->fcoe_filt_num) { 4988 case I40E_HASH_FILTER_SIZE_1K: 4989 case I40E_HASH_FILTER_SIZE_2K: 4990 case I40E_HASH_FILTER_SIZE_4K: 4991 case I40E_HASH_FILTER_SIZE_8K: 4992 case I40E_HASH_FILTER_SIZE_16K: 4993 case I40E_HASH_FILTER_SIZE_32K: 4994 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4995 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4996 break; 4997 default: 4998 return I40E_ERR_PARAM; 4999 } 5000 5001 switch (settings->fcoe_cntx_num) { 5002 case I40E_DMA_CNTX_SIZE_512: 5003 case I40E_DMA_CNTX_SIZE_1K: 5004 case I40E_DMA_CNTX_SIZE_2K: 5005 case I40E_DMA_CNTX_SIZE_4K: 5006 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5007 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5008 break; 5009 default: 5010 return I40E_ERR_PARAM; 5011 } 5012 5013 /* Validate PE settings passed */ 5014 switch (settings->pe_filt_num) { 5015 case I40E_HASH_FILTER_SIZE_1K: 5016 case I40E_HASH_FILTER_SIZE_2K: 5017 case I40E_HASH_FILTER_SIZE_4K: 5018 case I40E_HASH_FILTER_SIZE_8K: 5019 case I40E_HASH_FILTER_SIZE_16K: 5020 case I40E_HASH_FILTER_SIZE_32K: 5021 case I40E_HASH_FILTER_SIZE_64K: 5022 case I40E_HASH_FILTER_SIZE_128K: 5023 case I40E_HASH_FILTER_SIZE_256K: 5024 case I40E_HASH_FILTER_SIZE_512K: 5025 case I40E_HASH_FILTER_SIZE_1M: 5026 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5027 pe_filt_size <<= (u32)settings->pe_filt_num; 5028 break; 5029 default: 5030 return I40E_ERR_PARAM; 5031 } 5032 5033 switch (settings->pe_cntx_num) { 5034 case I40E_DMA_CNTX_SIZE_512: 5035 case I40E_DMA_CNTX_SIZE_1K: 5036 case I40E_DMA_CNTX_SIZE_2K: 5037 case I40E_DMA_CNTX_SIZE_4K: 5038 case I40E_DMA_CNTX_SIZE_8K: 5039 case I40E_DMA_CNTX_SIZE_16K: 5040 case I40E_DMA_CNTX_SIZE_32K: 5041 case I40E_DMA_CNTX_SIZE_64K: 5042 case I40E_DMA_CNTX_SIZE_128K: 5043 case I40E_DMA_CNTX_SIZE_256K: 5044 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5045 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5046 break; 5047 default: 5048 return I40E_ERR_PARAM; 5049 } 5050 5051 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5052 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5053 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5054 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5055 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5056 return I40E_ERR_INVALID_SIZE; 5057 5058 return I40E_SUCCESS; 5059 } 5060 5061 /** 5062 * i40e_set_filter_control 5063 * @hw: pointer to the hardware structure 5064 * @settings: Filter control settings 5065 * 5066 * Set the Queue Filters for PE/FCoE and enable filters required 5067 * for a single PF. It is expected that these settings are programmed 5068 * at the driver initialization time. 5069 **/ 5070 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5071 struct i40e_filter_control_settings *settings) 5072 { 5073 enum i40e_status_code ret = I40E_SUCCESS; 5074 u32 hash_lut_size = 0; 5075 u32 val; 5076 5077 if (!settings) 5078 return I40E_ERR_PARAM; 5079 5080 /* Validate the input settings */ 5081 ret = i40e_validate_filter_settings(hw, settings); 5082 if (ret) 5083 return ret; 5084 5085 /* Read the PF Queue Filter control register */ 5086 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5087 5088 /* Program required PE hash buckets for the PF */ 5089 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5090 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5091 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5092 /* Program required PE contexts for the PF */ 5093 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5094 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5095 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5096 5097 /* Program required FCoE hash buckets for the PF */ 5098 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5099 val |= ((u32)settings->fcoe_filt_num << 5100 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5101 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5102 /* Program required FCoE DDP contexts for the PF */ 5103 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5104 val |= ((u32)settings->fcoe_cntx_num << 5105 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5106 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5107 5108 /* Program Hash LUT size for the PF */ 5109 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5110 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5111 hash_lut_size = 1; 5112 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5113 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5114 5115 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5116 if (settings->enable_fdir) 5117 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5118 if (settings->enable_ethtype) 5119 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5120 if (settings->enable_macvlan) 5121 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5122 5123 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5124 5125 return I40E_SUCCESS; 5126 } 5127 5128 /** 5129 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5130 * @hw: pointer to the hw struct 5131 * @mac_addr: MAC address to use in the filter 5132 * @ethtype: Ethertype to use in the filter 5133 * @flags: Flags that needs to be applied to the filter 5134 * @vsi_seid: seid of the control VSI 5135 * @queue: VSI queue number to send the packet to 5136 * @is_add: Add control packet filter if True else remove 5137 * @stats: Structure to hold information on control filter counts 5138 * @cmd_details: pointer to command details structure or NULL 5139 * 5140 * This command will Add or Remove control packet filter for a control VSI. 5141 * In return it will update the total number of perfect filter count in 5142 * the stats member. 5143 **/ 5144 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5145 u8 *mac_addr, u16 ethtype, u16 flags, 5146 u16 vsi_seid, u16 queue, bool is_add, 5147 struct i40e_control_filter_stats *stats, 5148 struct i40e_asq_cmd_details *cmd_details) 5149 { 5150 struct i40e_aq_desc desc; 5151 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5152 (struct i40e_aqc_add_remove_control_packet_filter *) 5153 &desc.params.raw; 5154 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5155 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5156 &desc.params.raw; 5157 enum i40e_status_code status; 5158 5159 if (vsi_seid == 0) 5160 return I40E_ERR_PARAM; 5161 5162 if (is_add) { 5163 i40e_fill_default_direct_cmd_desc(&desc, 5164 i40e_aqc_opc_add_control_packet_filter); 5165 cmd->queue = CPU_TO_LE16(queue); 5166 } else { 5167 i40e_fill_default_direct_cmd_desc(&desc, 5168 i40e_aqc_opc_remove_control_packet_filter); 5169 } 5170 5171 if (mac_addr) 5172 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, 5173 I40E_NONDMA_TO_NONDMA); 5174 5175 cmd->etype = CPU_TO_LE16(ethtype); 5176 cmd->flags = CPU_TO_LE16(flags); 5177 cmd->seid = CPU_TO_LE16(vsi_seid); 5178 5179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5180 5181 if (!status && stats) { 5182 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5183 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5184 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5185 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5186 } 5187 5188 return status; 5189 } 5190 5191 /** 5192 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5193 * @hw: pointer to the hw struct 5194 * @seid: VSI seid to add ethertype filter from 5195 **/ 5196 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5197 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5198 u16 seid) 5199 { 5200 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5201 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5202 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5203 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5204 enum i40e_status_code status; 5205 5206 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5207 seid, 0, TRUE, NULL, 5208 NULL); 5209 if (status) 5210 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5211 } 5212 5213 /** 5214 * i40e_aq_add_cloud_filters 5215 * @hw: pointer to the hardware structure 5216 * @seid: VSI seid to add cloud filters from 5217 * @filters: Buffer which contains the filters to be added 5218 * @filter_count: number of filters contained in the buffer 5219 * 5220 * Set the cloud filters for a given VSI. The contents of the 5221 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5222 * in by the caller of the function. 5223 * 5224 **/ 5225 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5226 u16 seid, 5227 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5228 u8 filter_count) 5229 { 5230 struct i40e_aq_desc desc; 5231 struct i40e_aqc_add_remove_cloud_filters *cmd = 5232 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5233 u16 buff_len; 5234 enum i40e_status_code status; 5235 5236 i40e_fill_default_direct_cmd_desc(&desc, 5237 i40e_aqc_opc_add_cloud_filters); 5238 5239 buff_len = filter_count * sizeof(*filters); 5240 desc.datalen = CPU_TO_LE16(buff_len); 5241 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5242 cmd->num_filters = filter_count; 5243 cmd->seid = CPU_TO_LE16(seid); 5244 5245 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5246 5247 return status; 5248 } 5249 5250 /** 5251 * i40e_aq_remove_cloud_filters 5252 * @hw: pointer to the hardware structure 5253 * @seid: VSI seid to remove cloud filters from 5254 * @filters: Buffer which contains the filters to be removed 5255 * @filter_count: number of filters contained in the buffer 5256 * 5257 * Remove the cloud filters for a given VSI. The contents of the 5258 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5259 * in by the caller of the function. 5260 * 5261 **/ 5262 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5263 u16 seid, 5264 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5265 u8 filter_count) 5266 { 5267 struct i40e_aq_desc desc; 5268 struct i40e_aqc_add_remove_cloud_filters *cmd = 5269 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5270 enum i40e_status_code status; 5271 u16 buff_len; 5272 5273 i40e_fill_default_direct_cmd_desc(&desc, 5274 i40e_aqc_opc_remove_cloud_filters); 5275 5276 buff_len = filter_count * sizeof(*filters); 5277 desc.datalen = CPU_TO_LE16(buff_len); 5278 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5279 cmd->num_filters = filter_count; 5280 cmd->seid = CPU_TO_LE16(seid); 5281 5282 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5283 5284 return status; 5285 } 5286 5287 /** 5288 * i40e_aq_alternate_write 5289 * @hw: pointer to the hardware structure 5290 * @reg_addr0: address of first dword to be read 5291 * @reg_val0: value to be written under 'reg_addr0' 5292 * @reg_addr1: address of second dword to be read 5293 * @reg_val1: value to be written under 'reg_addr1' 5294 * 5295 * Write one or two dwords to alternate structure. Fields are indicated 5296 * by 'reg_addr0' and 'reg_addr1' register numbers. 5297 * 5298 **/ 5299 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5300 u32 reg_addr0, u32 reg_val0, 5301 u32 reg_addr1, u32 reg_val1) 5302 { 5303 struct i40e_aq_desc desc; 5304 struct i40e_aqc_alternate_write *cmd_resp = 5305 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5306 enum i40e_status_code status; 5307 5308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5309 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5310 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5311 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5312 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5313 5314 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5315 5316 return status; 5317 } 5318 5319 /** 5320 * i40e_aq_alternate_write_indirect 5321 * @hw: pointer to the hardware structure 5322 * @addr: address of a first register to be modified 5323 * @dw_count: number of alternate structure fields to write 5324 * @buffer: pointer to the command buffer 5325 * 5326 * Write 'dw_count' dwords from 'buffer' to alternate structure 5327 * starting at 'addr'. 5328 * 5329 **/ 5330 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5331 u32 addr, u32 dw_count, void *buffer) 5332 { 5333 struct i40e_aq_desc desc; 5334 struct i40e_aqc_alternate_ind_write *cmd_resp = 5335 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5336 enum i40e_status_code status; 5337 5338 if (buffer == NULL) 5339 return I40E_ERR_PARAM; 5340 5341 /* Indirect command */ 5342 i40e_fill_default_direct_cmd_desc(&desc, 5343 i40e_aqc_opc_alternate_write_indirect); 5344 5345 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5346 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5347 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5348 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5349 5350 cmd_resp->address = CPU_TO_LE32(addr); 5351 cmd_resp->length = CPU_TO_LE32(dw_count); 5352 5353 status = i40e_asq_send_command(hw, &desc, buffer, 5354 I40E_LO_DWORD(4*dw_count), NULL); 5355 5356 return status; 5357 } 5358 5359 /** 5360 * i40e_aq_alternate_read 5361 * @hw: pointer to the hardware structure 5362 * @reg_addr0: address of first dword to be read 5363 * @reg_val0: pointer for data read from 'reg_addr0' 5364 * @reg_addr1: address of second dword to be read 5365 * @reg_val1: pointer for data read from 'reg_addr1' 5366 * 5367 * Read one or two dwords from alternate structure. Fields are indicated 5368 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5369 * is not passed then only register at 'reg_addr0' is read. 5370 * 5371 **/ 5372 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5373 u32 reg_addr0, u32 *reg_val0, 5374 u32 reg_addr1, u32 *reg_val1) 5375 { 5376 struct i40e_aq_desc desc; 5377 struct i40e_aqc_alternate_write *cmd_resp = 5378 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5379 enum i40e_status_code status; 5380 5381 if (reg_val0 == NULL) 5382 return I40E_ERR_PARAM; 5383 5384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5385 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5386 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5387 5388 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5389 5390 if (status == I40E_SUCCESS) { 5391 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5392 5393 if (reg_val1 != NULL) 5394 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5395 } 5396 5397 return status; 5398 } 5399 5400 /** 5401 * i40e_aq_alternate_read_indirect 5402 * @hw: pointer to the hardware structure 5403 * @addr: address of the alternate structure field 5404 * @dw_count: number of alternate structure fields to read 5405 * @buffer: pointer to the command buffer 5406 * 5407 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5408 * place them in 'buffer'. The buffer should be allocated by caller. 5409 * 5410 **/ 5411 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5412 u32 addr, u32 dw_count, void *buffer) 5413 { 5414 struct i40e_aq_desc desc; 5415 struct i40e_aqc_alternate_ind_write *cmd_resp = 5416 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5417 enum i40e_status_code status; 5418 5419 if (buffer == NULL) 5420 return I40E_ERR_PARAM; 5421 5422 /* Indirect command */ 5423 i40e_fill_default_direct_cmd_desc(&desc, 5424 i40e_aqc_opc_alternate_read_indirect); 5425 5426 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5427 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5428 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5429 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5430 5431 cmd_resp->address = CPU_TO_LE32(addr); 5432 cmd_resp->length = CPU_TO_LE32(dw_count); 5433 5434 status = i40e_asq_send_command(hw, &desc, buffer, 5435 I40E_LO_DWORD(4*dw_count), NULL); 5436 5437 return status; 5438 } 5439 5440 /** 5441 * i40e_aq_alternate_clear 5442 * @hw: pointer to the HW structure. 5443 * 5444 * Clear the alternate structures of the port from which the function 5445 * is called. 5446 * 5447 **/ 5448 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5449 { 5450 struct i40e_aq_desc desc; 5451 enum i40e_status_code status; 5452 5453 i40e_fill_default_direct_cmd_desc(&desc, 5454 i40e_aqc_opc_alternate_clear_port); 5455 5456 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5457 5458 return status; 5459 } 5460 5461 /** 5462 * i40e_aq_alternate_write_done 5463 * @hw: pointer to the HW structure. 5464 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5465 * @reset_needed: indicates the SW should trigger GLOBAL reset 5466 * 5467 * Indicates to the FW that alternate structures have been changed. 5468 * 5469 **/ 5470 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5471 u8 bios_mode, bool *reset_needed) 5472 { 5473 struct i40e_aq_desc desc; 5474 struct i40e_aqc_alternate_write_done *cmd = 5475 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5476 enum i40e_status_code status; 5477 5478 if (reset_needed == NULL) 5479 return I40E_ERR_PARAM; 5480 5481 i40e_fill_default_direct_cmd_desc(&desc, 5482 i40e_aqc_opc_alternate_write_done); 5483 5484 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5485 5486 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5487 if (!status && reset_needed) 5488 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5489 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5490 5491 return status; 5492 } 5493 5494 /** 5495 * i40e_aq_set_oem_mode 5496 * @hw: pointer to the HW structure. 5497 * @oem_mode: the OEM mode to be used 5498 * 5499 * Sets the device to a specific operating mode. Currently the only supported 5500 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5501 * 5502 **/ 5503 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5504 u8 oem_mode) 5505 { 5506 struct i40e_aq_desc desc; 5507 struct i40e_aqc_alternate_write_done *cmd = 5508 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5509 enum i40e_status_code status; 5510 5511 i40e_fill_default_direct_cmd_desc(&desc, 5512 i40e_aqc_opc_alternate_set_mode); 5513 5514 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5515 5516 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5517 5518 return status; 5519 } 5520 5521 /** 5522 * i40e_aq_resume_port_tx 5523 * @hw: pointer to the hardware structure 5524 * @cmd_details: pointer to command details structure or NULL 5525 * 5526 * Resume port's Tx traffic 5527 **/ 5528 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5529 struct i40e_asq_cmd_details *cmd_details) 5530 { 5531 struct i40e_aq_desc desc; 5532 enum i40e_status_code status; 5533 5534 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5535 5536 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5537 5538 return status; 5539 } 5540 5541 /** 5542 * i40e_set_pci_config_data - store PCI bus info 5543 * @hw: pointer to hardware structure 5544 * @link_status: the link status word from PCI config space 5545 * 5546 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5547 **/ 5548 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5549 { 5550 hw->bus.type = i40e_bus_type_pci_express; 5551 5552 switch (link_status & I40E_PCI_LINK_WIDTH) { 5553 case I40E_PCI_LINK_WIDTH_1: 5554 hw->bus.width = i40e_bus_width_pcie_x1; 5555 break; 5556 case I40E_PCI_LINK_WIDTH_2: 5557 hw->bus.width = i40e_bus_width_pcie_x2; 5558 break; 5559 case I40E_PCI_LINK_WIDTH_4: 5560 hw->bus.width = i40e_bus_width_pcie_x4; 5561 break; 5562 case I40E_PCI_LINK_WIDTH_8: 5563 hw->bus.width = i40e_bus_width_pcie_x8; 5564 break; 5565 default: 5566 hw->bus.width = i40e_bus_width_unknown; 5567 break; 5568 } 5569 5570 switch (link_status & I40E_PCI_LINK_SPEED) { 5571 case I40E_PCI_LINK_SPEED_2500: 5572 hw->bus.speed = i40e_bus_speed_2500; 5573 break; 5574 case I40E_PCI_LINK_SPEED_5000: 5575 hw->bus.speed = i40e_bus_speed_5000; 5576 break; 5577 case I40E_PCI_LINK_SPEED_8000: 5578 hw->bus.speed = i40e_bus_speed_8000; 5579 break; 5580 default: 5581 hw->bus.speed = i40e_bus_speed_unknown; 5582 break; 5583 } 5584 } 5585 5586 /** 5587 * i40e_aq_debug_dump 5588 * @hw: pointer to the hardware structure 5589 * @cluster_id: specific cluster to dump 5590 * @table_id: table id within cluster 5591 * @start_index: index of line in the block to read 5592 * @buff_size: dump buffer size 5593 * @buff: dump buffer 5594 * @ret_buff_size: actual buffer size returned 5595 * @ret_next_table: next block to read 5596 * @ret_next_index: next index to read 5597 * 5598 * Dump internal FW/HW data for debug purposes. 5599 * 5600 **/ 5601 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 5602 u8 table_id, u32 start_index, u16 buff_size, 5603 void *buff, u16 *ret_buff_size, 5604 u8 *ret_next_table, u32 *ret_next_index, 5605 struct i40e_asq_cmd_details *cmd_details) 5606 { 5607 struct i40e_aq_desc desc; 5608 struct i40e_aqc_debug_dump_internals *cmd = 5609 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5610 struct i40e_aqc_debug_dump_internals *resp = 5611 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5612 enum i40e_status_code status; 5613 5614 if (buff_size == 0 || !buff) 5615 return I40E_ERR_PARAM; 5616 5617 i40e_fill_default_direct_cmd_desc(&desc, 5618 i40e_aqc_opc_debug_dump_internals); 5619 /* Indirect Command */ 5620 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5621 if (buff_size > I40E_AQ_LARGE_BUF) 5622 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5623 5624 cmd->cluster_id = cluster_id; 5625 cmd->table_id = table_id; 5626 cmd->idx = CPU_TO_LE32(start_index); 5627 5628 desc.datalen = CPU_TO_LE16(buff_size); 5629 5630 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5631 if (!status) { 5632 if (ret_buff_size != NULL) 5633 *ret_buff_size = LE16_TO_CPU(desc.datalen); 5634 if (ret_next_table != NULL) 5635 *ret_next_table = resp->table_id; 5636 if (ret_next_index != NULL) 5637 *ret_next_index = LE32_TO_CPU(resp->idx); 5638 } 5639 5640 return status; 5641 } 5642 5643 /** 5644 * i40e_read_bw_from_alt_ram 5645 * @hw: pointer to the hardware structure 5646 * @max_bw: pointer for max_bw read 5647 * @min_bw: pointer for min_bw read 5648 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 5649 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 5650 * 5651 * Read bw from the alternate ram for the given pf 5652 **/ 5653 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 5654 u32 *max_bw, u32 *min_bw, 5655 bool *min_valid, bool *max_valid) 5656 { 5657 enum i40e_status_code status; 5658 u32 max_bw_addr, min_bw_addr; 5659 5660 /* Calculate the address of the min/max bw registers */ 5661 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5662 I40E_ALT_STRUCT_MAX_BW_OFFSET + 5663 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5664 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5665 I40E_ALT_STRUCT_MIN_BW_OFFSET + 5666 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5667 5668 /* Read the bandwidths from alt ram */ 5669 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 5670 min_bw_addr, min_bw); 5671 5672 if (*min_bw & I40E_ALT_BW_VALID_MASK) 5673 *min_valid = TRUE; 5674 else 5675 *min_valid = FALSE; 5676 5677 if (*max_bw & I40E_ALT_BW_VALID_MASK) 5678 *max_valid = TRUE; 5679 else 5680 *max_valid = FALSE; 5681 5682 return status; 5683 } 5684 5685 /** 5686 * i40e_aq_configure_partition_bw 5687 * @hw: pointer to the hardware structure 5688 * @bw_data: Buffer holding valid pfs and bw limits 5689 * @cmd_details: pointer to command details 5690 * 5691 * Configure partitions guaranteed/max bw 5692 **/ 5693 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 5694 struct i40e_aqc_configure_partition_bw_data *bw_data, 5695 struct i40e_asq_cmd_details *cmd_details) 5696 { 5697 enum i40e_status_code status; 5698 struct i40e_aq_desc desc; 5699 u16 bwd_size = sizeof(*bw_data); 5700 5701 i40e_fill_default_direct_cmd_desc(&desc, 5702 i40e_aqc_opc_configure_partition_bw); 5703 5704 /* Indirect command */ 5705 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5706 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5707 5708 if (bwd_size > I40E_AQ_LARGE_BUF) 5709 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5710 5711 desc.datalen = CPU_TO_LE16(bwd_size); 5712 5713 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 5714 5715 return status; 5716 } 5717 5718 /** 5719 * i40e_read_phy_register 5720 * @hw: pointer to the HW structure 5721 * @page: registers page number 5722 * @reg: register address in the page 5723 * @phy_adr: PHY address on MDIO interface 5724 * @value: PHY register value 5725 * 5726 * Reads specified PHY register value 5727 **/ 5728 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 5729 u8 page, u16 reg, u8 phy_addr, 5730 u16 *value) 5731 { 5732 enum i40e_status_code status = I40E_ERR_TIMEOUT; 5733 u32 command = 0; 5734 u16 retry = 1000; 5735 u8 port_num = (u8)hw->func_caps.mdio_port_num; 5736 5737 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 5738 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 5739 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 5740 (I40E_MDIO_OPCODE_ADDRESS) | 5741 (I40E_MDIO_STCODE) | 5742 (I40E_GLGEN_MSCA_MDICMD_MASK) | 5743 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 5744 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 5745 do { 5746 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 5747 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 5748 status = I40E_SUCCESS; 5749 break; 5750 } 5751 i40e_usec_delay(10); 5752 retry--; 5753 } while (retry); 5754 5755 if (status) { 5756 i40e_debug(hw, I40E_DEBUG_PHY, 5757 "PHY: Can't write command to external PHY.\n"); 5758 goto phy_read_end; 5759 } 5760 5761 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 5762 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 5763 (I40E_MDIO_OPCODE_READ) | 5764 (I40E_MDIO_STCODE) | 5765 (I40E_GLGEN_MSCA_MDICMD_MASK) | 5766 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 5767 status = I40E_ERR_TIMEOUT; 5768 retry = 1000; 5769 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 5770 do { 5771 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 5772 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 5773 status = I40E_SUCCESS; 5774 break; 5775 } 5776 i40e_usec_delay(10); 5777 retry--; 5778 } while (retry); 5779 5780 if (!status) { 5781 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 5782 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 5783 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 5784 } else { 5785 i40e_debug(hw, I40E_DEBUG_PHY, 5786 "PHY: Can't read register value from external PHY.\n"); 5787 } 5788 5789 phy_read_end: 5790 return status; 5791 } 5792 5793 /** 5794 * i40e_write_phy_register 5795 * @hw: pointer to the HW structure 5796 * @page: registers page number 5797 * @reg: register address in the page 5798 * @phy_adr: PHY address on MDIO interface 5799 * @value: PHY register value 5800 * 5801 * Writes value to specified PHY register 5802 **/ 5803 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 5804 u8 page, u16 reg, u8 phy_addr, 5805 u16 value) 5806 { 5807 enum i40e_status_code status = I40E_ERR_TIMEOUT; 5808 u32 command = 0; 5809 u16 retry = 1000; 5810 u8 port_num = (u8)hw->func_caps.mdio_port_num; 5811 5812 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 5813 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 5814 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 5815 (I40E_MDIO_OPCODE_ADDRESS) | 5816 (I40E_MDIO_STCODE) | 5817 (I40E_GLGEN_MSCA_MDICMD_MASK) | 5818 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 5819 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 5820 do { 5821 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 5822 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 5823 status = I40E_SUCCESS; 5824 break; 5825 } 5826 i40e_usec_delay(10); 5827 retry--; 5828 } while (retry); 5829 if (status) { 5830 i40e_debug(hw, I40E_DEBUG_PHY, 5831 "PHY: Can't write command to external PHY.\n"); 5832 goto phy_write_end; 5833 } 5834 5835 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 5836 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 5837 5838 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 5839 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 5840 (I40E_MDIO_OPCODE_WRITE) | 5841 (I40E_MDIO_STCODE) | 5842 (I40E_GLGEN_MSCA_MDICMD_MASK) | 5843 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 5844 status = I40E_ERR_TIMEOUT; 5845 retry = 1000; 5846 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 5847 do { 5848 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 5849 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 5850 status = I40E_SUCCESS; 5851 break; 5852 } 5853 i40e_usec_delay(10); 5854 retry--; 5855 } while (retry); 5856 5857 phy_write_end: 5858 return status; 5859 } 5860 5861 /** 5862 * i40e_get_phy_address 5863 * @hw: pointer to the HW structure 5864 * @dev_num: PHY port num that address we want 5865 * @phy_addr: Returned PHY address 5866 * 5867 * Gets PHY address for current port 5868 **/ 5869 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 5870 { 5871 u8 port_num = (u8)hw->func_caps.mdio_port_num; 5872 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 5873 5874 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 5875 } 5876 5877 /** 5878 * i40e_blink_phy_led 5879 * @hw: pointer to the HW structure 5880 * @time: time how long led will blinks in secs 5881 * @interval: gap between LED on and off in msecs 5882 * 5883 * Blinks PHY link LED 5884 **/ 5885 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 5886 u32 time, u32 interval) 5887 { 5888 enum i40e_status_code status = I40E_SUCCESS; 5889 u32 i; 5890 u16 led_ctl = 0; 5891 u16 gpio_led_port; 5892 u16 led_reg; 5893 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 5894 u8 phy_addr = 0; 5895 u8 port_num; 5896 5897 i = rd32(hw, I40E_PFGEN_PORTNUM); 5898 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5899 phy_addr = i40e_get_phy_address(hw, port_num); 5900 5901 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 5902 led_addr++) { 5903 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, 5904 led_addr, phy_addr, &led_reg); 5905 if (status) 5906 goto phy_blinking_end; 5907 led_ctl = led_reg; 5908 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5909 led_reg = 0; 5910 status = i40e_write_phy_register(hw, 5911 I40E_PHY_COM_REG_PAGE, 5912 led_addr, phy_addr, 5913 led_reg); 5914 if (status) 5915 goto phy_blinking_end; 5916 break; 5917 } 5918 } 5919 5920 if (time > 0 && interval > 0) { 5921 for (i = 0; i < time * 1000; i += interval) { 5922 status = i40e_read_phy_register(hw, 5923 I40E_PHY_COM_REG_PAGE, 5924 led_addr, phy_addr, 5925 &led_reg); 5926 if (status) 5927 goto restore_config; 5928 if (led_reg & I40E_PHY_LED_MANUAL_ON) 5929 led_reg = 0; 5930 else 5931 led_reg = I40E_PHY_LED_MANUAL_ON; 5932 status = i40e_write_phy_register(hw, 5933 I40E_PHY_COM_REG_PAGE, 5934 led_addr, phy_addr, 5935 led_reg); 5936 if (status) 5937 goto restore_config; 5938 i40e_msec_delay(interval); 5939 } 5940 } 5941 5942 restore_config: 5943 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr, 5944 phy_addr, led_ctl); 5945 5946 phy_blinking_end: 5947 return status; 5948 } 5949 5950 /** 5951 * i40e_led_get_phy - return current on/off mode 5952 * @hw: pointer to the hw struct 5953 * @led_addr: address of led register to use 5954 * @val: original value of register to use 5955 * 5956 **/ 5957 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 5958 u16 *val) 5959 { 5960 enum i40e_status_code status = I40E_SUCCESS; 5961 u16 gpio_led_port; 5962 u8 phy_addr = 0; 5963 u16 reg_val; 5964 u16 temp_addr; 5965 u8 port_num; 5966 u32 i; 5967 5968 temp_addr = I40E_PHY_LED_PROV_REG_1; 5969 i = rd32(hw, I40E_PFGEN_PORTNUM); 5970 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5971 phy_addr = i40e_get_phy_address(hw, port_num); 5972 5973 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 5974 temp_addr++) { 5975 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, 5976 temp_addr, phy_addr, ®_val); 5977 if (status) 5978 return status; 5979 *val = reg_val; 5980 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 5981 *led_addr = temp_addr; 5982 break; 5983 } 5984 } 5985 return status; 5986 } 5987 5988 /** 5989 * i40e_led_set_phy 5990 * @hw: pointer to the HW structure 5991 * @on: TRUE or FALSE 5992 * @mode: original val plus bit for set or ignore 5993 * Set led's on or off when controlled by the PHY 5994 * 5995 **/ 5996 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 5997 u16 led_addr, u32 mode) 5998 { 5999 enum i40e_status_code status = I40E_SUCCESS; 6000 u16 led_ctl = 0; 6001 u16 led_reg = 0; 6002 u8 phy_addr = 0; 6003 u8 port_num; 6004 u32 i; 6005 6006 i = rd32(hw, I40E_PFGEN_PORTNUM); 6007 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6008 phy_addr = i40e_get_phy_address(hw, port_num); 6009 6010 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr, 6011 phy_addr, &led_reg); 6012 if (status) 6013 return status; 6014 led_ctl = led_reg; 6015 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6016 led_reg = 0; 6017 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, 6018 led_addr, phy_addr, led_reg); 6019 if (status) 6020 return status; 6021 } 6022 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, 6023 led_addr, phy_addr, &led_reg); 6024 if (status) 6025 goto restore_config; 6026 if (on) 6027 led_reg = I40E_PHY_LED_MANUAL_ON; 6028 else 6029 led_reg = 0; 6030 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, 6031 led_addr, phy_addr, led_reg); 6032 if (status) 6033 goto restore_config; 6034 if (mode & I40E_PHY_LED_MODE_ORIG) { 6035 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6036 status = i40e_write_phy_register(hw, 6037 I40E_PHY_COM_REG_PAGE, 6038 led_addr, phy_addr, led_ctl); 6039 } 6040 return status; 6041 restore_config: 6042 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr, 6043 phy_addr, led_ctl); 6044 return status; 6045 } 6046 6047 /** 6048 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 6049 * @hw: pointer to the hw struct 6050 * @reg_addr: register address 6051 * @reg_val: ptr to register value 6052 * @cmd_details: pointer to command details structure or NULL 6053 * 6054 * Use the firmware to read the Rx control register, 6055 * especially useful if the Rx unit is under heavy pressure 6056 **/ 6057 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 6058 u32 reg_addr, u32 *reg_val, 6059 struct i40e_asq_cmd_details *cmd_details) 6060 { 6061 struct i40e_aq_desc desc; 6062 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 6063 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6064 enum i40e_status_code status; 6065 6066 if (reg_val == NULL) 6067 return I40E_ERR_PARAM; 6068 6069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 6070 6071 cmd_resp->address = CPU_TO_LE32(reg_addr); 6072 6073 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6074 6075 if (status == I40E_SUCCESS) 6076 *reg_val = LE32_TO_CPU(cmd_resp->value); 6077 6078 return status; 6079 } 6080 6081 /** 6082 * i40e_read_rx_ctl - read from an Rx control register 6083 * @hw: pointer to the hw struct 6084 * @reg_addr: register address 6085 **/ 6086 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 6087 { 6088 enum i40e_status_code status = I40E_SUCCESS; 6089 bool use_register; 6090 int retry = 5; 6091 u32 val = 0; 6092 6093 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 6094 if (!use_register) { 6095 do_retry: 6096 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 6097 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6098 i40e_msec_delay(1); 6099 retry--; 6100 goto do_retry; 6101 } 6102 } 6103 6104 /* if the AQ access failed, try the old-fashioned way */ 6105 if (status || use_register) 6106 val = rd32(hw, reg_addr); 6107 6108 return val; 6109 } 6110 6111 /** 6112 * i40e_aq_rx_ctl_write_register 6113 * @hw: pointer to the hw struct 6114 * @reg_addr: register address 6115 * @reg_val: register value 6116 * @cmd_details: pointer to command details structure or NULL 6117 * 6118 * Use the firmware to write to an Rx control register, 6119 * especially useful if the Rx unit is under heavy pressure 6120 **/ 6121 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 6122 u32 reg_addr, u32 reg_val, 6123 struct i40e_asq_cmd_details *cmd_details) 6124 { 6125 struct i40e_aq_desc desc; 6126 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 6127 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6128 enum i40e_status_code status; 6129 6130 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 6131 6132 cmd->address = CPU_TO_LE32(reg_addr); 6133 cmd->value = CPU_TO_LE32(reg_val); 6134 6135 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6136 6137 return status; 6138 } 6139 6140 /** 6141 * i40e_write_rx_ctl - write to an Rx control register 6142 * @hw: pointer to the hw struct 6143 * @reg_addr: register address 6144 * @reg_val: register value 6145 **/ 6146 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 6147 { 6148 enum i40e_status_code status = I40E_SUCCESS; 6149 bool use_register; 6150 int retry = 5; 6151 6152 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 6153 if (!use_register) { 6154 do_retry: 6155 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 6156 reg_val, NULL); 6157 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6158 i40e_msec_delay(1); 6159 retry--; 6160 goto do_retry; 6161 } 6162 } 6163 6164 /* if the AQ access failed, try the old-fashioned way */ 6165 if (status || use_register) 6166 wr32(hw, reg_addr, reg_val); 6167 } 6168 6169 /** 6170 * i40e_aq_send_msg_to_pf 6171 * @hw: pointer to the hardware structure 6172 * @v_opcode: opcodes for VF-PF communication 6173 * @v_retval: return error code 6174 * @msg: pointer to the msg buffer 6175 * @msglen: msg length 6176 * @cmd_details: pointer to command details 6177 * 6178 * Send message to PF driver using admin queue. By default, this message 6179 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 6180 * completion before returning. 6181 **/ 6182 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 6183 enum i40e_virtchnl_ops v_opcode, 6184 enum i40e_status_code v_retval, 6185 u8 *msg, u16 msglen, 6186 struct i40e_asq_cmd_details *cmd_details) 6187 { 6188 struct i40e_aq_desc desc; 6189 struct i40e_asq_cmd_details details; 6190 enum i40e_status_code status; 6191 6192 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 6193 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 6194 desc.cookie_high = CPU_TO_LE32(v_opcode); 6195 desc.cookie_low = CPU_TO_LE32(v_retval); 6196 if (msglen) { 6197 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 6198 | I40E_AQ_FLAG_RD)); 6199 if (msglen > I40E_AQ_LARGE_BUF) 6200 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6201 desc.datalen = CPU_TO_LE16(msglen); 6202 } 6203 if (!cmd_details) { 6204 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 6205 details.async = TRUE; 6206 cmd_details = &details; 6207 } 6208 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 6209 msglen, cmd_details); 6210 return status; 6211 } 6212 6213 /** 6214 * i40e_vf_parse_hw_config 6215 * @hw: pointer to the hardware structure 6216 * @msg: pointer to the virtual channel VF resource structure 6217 * 6218 * Given a VF resource message from the PF, populate the hw struct 6219 * with appropriate information. 6220 **/ 6221 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 6222 struct i40e_virtchnl_vf_resource *msg) 6223 { 6224 struct i40e_virtchnl_vsi_resource *vsi_res; 6225 int i; 6226 6227 vsi_res = &msg->vsi_res[0]; 6228 6229 hw->dev_caps.num_vsis = msg->num_vsis; 6230 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 6231 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 6232 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 6233 hw->dev_caps.dcb = msg->vf_offload_flags & 6234 I40E_VIRTCHNL_VF_OFFLOAD_L2; 6235 hw->dev_caps.fcoe = (msg->vf_offload_flags & 6236 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0; 6237 hw->dev_caps.iwarp = (msg->vf_offload_flags & 6238 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 6239 for (i = 0; i < msg->num_vsis; i++) { 6240 if (vsi_res->vsi_type == I40E_VSI_SRIOV) { 6241 i40e_memcpy(hw->mac.perm_addr, 6242 vsi_res->default_mac_addr, 6243 I40E_ETH_LENGTH_OF_ADDRESS, 6244 I40E_NONDMA_TO_NONDMA); 6245 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 6246 I40E_ETH_LENGTH_OF_ADDRESS, 6247 I40E_NONDMA_TO_NONDMA); 6248 } 6249 vsi_res++; 6250 } 6251 } 6252 6253 /** 6254 * i40e_vf_reset 6255 * @hw: pointer to the hardware structure 6256 * 6257 * Send a VF_RESET message to the PF. Does not wait for response from PF 6258 * as none will be forthcoming. Immediately after calling this function, 6259 * the admin queue should be shut down and (optionally) reinitialized. 6260 **/ 6261 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 6262 { 6263 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF, 6264 I40E_SUCCESS, NULL, 0, NULL); 6265 } 6266