1 /****************************************************************************** 2 3 Copyright (c) 2013-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "i40e_virtchnl.h" 39 40 /** 41 * i40e_set_mac_type - Sets MAC type 42 * @hw: pointer to the HW structure 43 * 44 * This function sets the mac type of the adapter based on the 45 * vendor ID and device ID stored in the hw structure. 46 **/ 47 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 48 { 49 enum i40e_status_code status = I40E_SUCCESS; 50 51 DEBUGFUNC("i40e_set_mac_type\n"); 52 53 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 54 switch (hw->device_id) { 55 case I40E_DEV_ID_SFP_XL710: 56 case I40E_DEV_ID_QEMU: 57 case I40E_DEV_ID_KX_A: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 hw->mac.type = I40E_MAC_XL710; 65 break; 66 case I40E_DEV_ID_VF: 67 case I40E_DEV_ID_VF_HV: 68 hw->mac.type = I40E_MAC_VF; 69 break; 70 default: 71 hw->mac.type = I40E_MAC_GENERIC; 72 break; 73 } 74 } else { 75 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 76 } 77 78 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 79 hw->mac.type, status); 80 return status; 81 } 82 83 /** 84 * i40e_debug_aq 85 * @hw: debug mask related to admin queue 86 * @mask: debug mask 87 * @desc: pointer to admin queue descriptor 88 * @buffer: pointer to command buffer 89 * @buf_len: max length of buffer 90 * 91 * Dumps debug log about adminq command with descriptor contents. 92 **/ 93 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 94 void *buffer, u16 buf_len) 95 { 96 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 97 u16 len = LE16_TO_CPU(aq_desc->datalen); 98 u8 *buf = (u8 *)buffer; 99 u16 i = 0; 100 101 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 102 return; 103 104 i40e_debug(hw, mask, 105 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 106 LE16_TO_CPU(aq_desc->opcode), 107 LE16_TO_CPU(aq_desc->flags), 108 LE16_TO_CPU(aq_desc->datalen), 109 LE16_TO_CPU(aq_desc->retval)); 110 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 111 LE32_TO_CPU(aq_desc->cookie_high), 112 LE32_TO_CPU(aq_desc->cookie_low)); 113 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 114 LE32_TO_CPU(aq_desc->params.internal.param0), 115 LE32_TO_CPU(aq_desc->params.internal.param1)); 116 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 117 LE32_TO_CPU(aq_desc->params.external.addr_high), 118 LE32_TO_CPU(aq_desc->params.external.addr_low)); 119 120 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 121 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 122 if (buf_len < len) 123 len = buf_len; 124 /* write the full 16-byte chunks */ 125 for (i = 0; i < (len - 16); i += 16) 126 i40e_debug(hw, mask, 127 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 128 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 129 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 130 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 131 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 132 /* write whatever's left over without overrunning the buffer */ 133 if (i < len) { 134 char d_buf[80]; 135 int j = 0; 136 137 memset(d_buf, 0, sizeof(d_buf)); 138 j += sprintf(d_buf, "\t0x%04X ", i); 139 while (i < len) 140 j += sprintf(&d_buf[j], " %02X", buf[i++]); 141 i40e_debug(hw, mask, "%s\n", d_buf); 142 } 143 } 144 } 145 146 /** 147 * i40e_check_asq_alive 148 * @hw: pointer to the hw struct 149 * 150 * Returns TRUE if Queue is enabled else FALSE. 151 **/ 152 bool i40e_check_asq_alive(struct i40e_hw *hw) 153 { 154 if (hw->aq.asq.len) 155 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK); 156 else 157 return FALSE; 158 } 159 160 /** 161 * i40e_aq_queue_shutdown 162 * @hw: pointer to the hw struct 163 * @unloading: is the driver unloading itself 164 * 165 * Tell the Firmware that we're shutting down the AdminQ and whether 166 * or not the driver is unloading as well. 167 **/ 168 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 169 bool unloading) 170 { 171 struct i40e_aq_desc desc; 172 struct i40e_aqc_queue_shutdown *cmd = 173 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 174 enum i40e_status_code status; 175 176 i40e_fill_default_direct_cmd_desc(&desc, 177 i40e_aqc_opc_queue_shutdown); 178 179 if (unloading) 180 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 181 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 182 183 return status; 184 } 185 186 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 187 * hardware to a bit-field that can be used by SW to more easily determine the 188 * packet type. 189 * 190 * Macros are used to shorten the table lines and make this table human 191 * readable. 192 * 193 * We store the PTYPE in the top byte of the bit field - this is just so that 194 * we can check that the table doesn't have a row missing, as the index into 195 * the table should be the PTYPE. 196 * 197 * Typical work flow: 198 * 199 * IF NOT i40e_ptype_lookup[ptype].known 200 * THEN 201 * Packet is unknown 202 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 203 * Use the rest of the fields to look at the tunnels, inner protocols, etc 204 * ELSE 205 * Use the enum i40e_rx_l2_ptype to decode the packet type 206 * ENDIF 207 */ 208 209 /* macro to make the table lines short */ 210 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 211 { PTYPE, \ 212 1, \ 213 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 214 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 215 I40E_RX_PTYPE_##OUTER_FRAG, \ 216 I40E_RX_PTYPE_TUNNEL_##T, \ 217 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 218 I40E_RX_PTYPE_##TEF, \ 219 I40E_RX_PTYPE_INNER_PROT_##I, \ 220 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 221 222 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 223 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 224 225 /* shorter macros makes the table fit but are terse */ 226 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 227 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 228 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 229 230 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 231 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 232 /* L2 Packet types */ 233 I40E_PTT_UNUSED_ENTRY(0), 234 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 235 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 236 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 237 I40E_PTT_UNUSED_ENTRY(4), 238 I40E_PTT_UNUSED_ENTRY(5), 239 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 240 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 241 I40E_PTT_UNUSED_ENTRY(8), 242 I40E_PTT_UNUSED_ENTRY(9), 243 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 244 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 245 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 246 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 247 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 248 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 249 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 250 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 251 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 252 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 253 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 254 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 255 256 /* Non Tunneled IPv4 */ 257 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 258 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 259 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 260 I40E_PTT_UNUSED_ENTRY(25), 261 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 262 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 263 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 264 265 /* IPv4 --> IPv4 */ 266 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 267 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 268 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 269 I40E_PTT_UNUSED_ENTRY(32), 270 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 271 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 272 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 273 274 /* IPv4 --> IPv6 */ 275 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 276 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 277 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 278 I40E_PTT_UNUSED_ENTRY(39), 279 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 280 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 281 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 282 283 /* IPv4 --> GRE/NAT */ 284 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 285 286 /* IPv4 --> GRE/NAT --> IPv4 */ 287 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 288 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 289 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 290 I40E_PTT_UNUSED_ENTRY(47), 291 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 292 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 293 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 294 295 /* IPv4 --> GRE/NAT --> IPv6 */ 296 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 297 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 298 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 299 I40E_PTT_UNUSED_ENTRY(54), 300 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 301 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 302 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 303 304 /* IPv4 --> GRE/NAT --> MAC */ 305 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 306 307 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 308 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 309 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 310 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 311 I40E_PTT_UNUSED_ENTRY(62), 312 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 313 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 314 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 315 316 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 317 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 318 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 319 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 320 I40E_PTT_UNUSED_ENTRY(69), 321 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 322 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 323 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 324 325 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 326 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 327 328 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 329 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 330 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 331 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 332 I40E_PTT_UNUSED_ENTRY(77), 333 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 334 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 335 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 336 337 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 338 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 339 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 340 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 341 I40E_PTT_UNUSED_ENTRY(84), 342 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 343 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 344 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 345 346 /* Non Tunneled IPv6 */ 347 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 348 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 349 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 350 I40E_PTT_UNUSED_ENTRY(91), 351 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 352 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 353 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 354 355 /* IPv6 --> IPv4 */ 356 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 357 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 358 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 359 I40E_PTT_UNUSED_ENTRY(98), 360 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 361 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 362 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 363 364 /* IPv6 --> IPv6 */ 365 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 366 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 367 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 368 I40E_PTT_UNUSED_ENTRY(105), 369 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 370 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 371 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 372 373 /* IPv6 --> GRE/NAT */ 374 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 375 376 /* IPv6 --> GRE/NAT -> IPv4 */ 377 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 378 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 379 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 380 I40E_PTT_UNUSED_ENTRY(113), 381 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 382 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 383 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 384 385 /* IPv6 --> GRE/NAT -> IPv6 */ 386 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 387 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 388 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 389 I40E_PTT_UNUSED_ENTRY(120), 390 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 391 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 392 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 393 394 /* IPv6 --> GRE/NAT -> MAC */ 395 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 396 397 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 398 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 399 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 400 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 401 I40E_PTT_UNUSED_ENTRY(128), 402 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 403 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 404 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 405 406 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 407 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 408 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 409 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 410 I40E_PTT_UNUSED_ENTRY(135), 411 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 412 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 413 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 414 415 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 416 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 417 418 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 419 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 420 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 421 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 422 I40E_PTT_UNUSED_ENTRY(143), 423 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 424 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 425 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 426 427 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 428 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 429 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 430 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 431 I40E_PTT_UNUSED_ENTRY(150), 432 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 433 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 434 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 435 436 /* unused entries */ 437 I40E_PTT_UNUSED_ENTRY(154), 438 I40E_PTT_UNUSED_ENTRY(155), 439 I40E_PTT_UNUSED_ENTRY(156), 440 I40E_PTT_UNUSED_ENTRY(157), 441 I40E_PTT_UNUSED_ENTRY(158), 442 I40E_PTT_UNUSED_ENTRY(159), 443 444 I40E_PTT_UNUSED_ENTRY(160), 445 I40E_PTT_UNUSED_ENTRY(161), 446 I40E_PTT_UNUSED_ENTRY(162), 447 I40E_PTT_UNUSED_ENTRY(163), 448 I40E_PTT_UNUSED_ENTRY(164), 449 I40E_PTT_UNUSED_ENTRY(165), 450 I40E_PTT_UNUSED_ENTRY(166), 451 I40E_PTT_UNUSED_ENTRY(167), 452 I40E_PTT_UNUSED_ENTRY(168), 453 I40E_PTT_UNUSED_ENTRY(169), 454 455 I40E_PTT_UNUSED_ENTRY(170), 456 I40E_PTT_UNUSED_ENTRY(171), 457 I40E_PTT_UNUSED_ENTRY(172), 458 I40E_PTT_UNUSED_ENTRY(173), 459 I40E_PTT_UNUSED_ENTRY(174), 460 I40E_PTT_UNUSED_ENTRY(175), 461 I40E_PTT_UNUSED_ENTRY(176), 462 I40E_PTT_UNUSED_ENTRY(177), 463 I40E_PTT_UNUSED_ENTRY(178), 464 I40E_PTT_UNUSED_ENTRY(179), 465 466 I40E_PTT_UNUSED_ENTRY(180), 467 I40E_PTT_UNUSED_ENTRY(181), 468 I40E_PTT_UNUSED_ENTRY(182), 469 I40E_PTT_UNUSED_ENTRY(183), 470 I40E_PTT_UNUSED_ENTRY(184), 471 I40E_PTT_UNUSED_ENTRY(185), 472 I40E_PTT_UNUSED_ENTRY(186), 473 I40E_PTT_UNUSED_ENTRY(187), 474 I40E_PTT_UNUSED_ENTRY(188), 475 I40E_PTT_UNUSED_ENTRY(189), 476 477 I40E_PTT_UNUSED_ENTRY(190), 478 I40E_PTT_UNUSED_ENTRY(191), 479 I40E_PTT_UNUSED_ENTRY(192), 480 I40E_PTT_UNUSED_ENTRY(193), 481 I40E_PTT_UNUSED_ENTRY(194), 482 I40E_PTT_UNUSED_ENTRY(195), 483 I40E_PTT_UNUSED_ENTRY(196), 484 I40E_PTT_UNUSED_ENTRY(197), 485 I40E_PTT_UNUSED_ENTRY(198), 486 I40E_PTT_UNUSED_ENTRY(199), 487 488 I40E_PTT_UNUSED_ENTRY(200), 489 I40E_PTT_UNUSED_ENTRY(201), 490 I40E_PTT_UNUSED_ENTRY(202), 491 I40E_PTT_UNUSED_ENTRY(203), 492 I40E_PTT_UNUSED_ENTRY(204), 493 I40E_PTT_UNUSED_ENTRY(205), 494 I40E_PTT_UNUSED_ENTRY(206), 495 I40E_PTT_UNUSED_ENTRY(207), 496 I40E_PTT_UNUSED_ENTRY(208), 497 I40E_PTT_UNUSED_ENTRY(209), 498 499 I40E_PTT_UNUSED_ENTRY(210), 500 I40E_PTT_UNUSED_ENTRY(211), 501 I40E_PTT_UNUSED_ENTRY(212), 502 I40E_PTT_UNUSED_ENTRY(213), 503 I40E_PTT_UNUSED_ENTRY(214), 504 I40E_PTT_UNUSED_ENTRY(215), 505 I40E_PTT_UNUSED_ENTRY(216), 506 I40E_PTT_UNUSED_ENTRY(217), 507 I40E_PTT_UNUSED_ENTRY(218), 508 I40E_PTT_UNUSED_ENTRY(219), 509 510 I40E_PTT_UNUSED_ENTRY(220), 511 I40E_PTT_UNUSED_ENTRY(221), 512 I40E_PTT_UNUSED_ENTRY(222), 513 I40E_PTT_UNUSED_ENTRY(223), 514 I40E_PTT_UNUSED_ENTRY(224), 515 I40E_PTT_UNUSED_ENTRY(225), 516 I40E_PTT_UNUSED_ENTRY(226), 517 I40E_PTT_UNUSED_ENTRY(227), 518 I40E_PTT_UNUSED_ENTRY(228), 519 I40E_PTT_UNUSED_ENTRY(229), 520 521 I40E_PTT_UNUSED_ENTRY(230), 522 I40E_PTT_UNUSED_ENTRY(231), 523 I40E_PTT_UNUSED_ENTRY(232), 524 I40E_PTT_UNUSED_ENTRY(233), 525 I40E_PTT_UNUSED_ENTRY(234), 526 I40E_PTT_UNUSED_ENTRY(235), 527 I40E_PTT_UNUSED_ENTRY(236), 528 I40E_PTT_UNUSED_ENTRY(237), 529 I40E_PTT_UNUSED_ENTRY(238), 530 I40E_PTT_UNUSED_ENTRY(239), 531 532 I40E_PTT_UNUSED_ENTRY(240), 533 I40E_PTT_UNUSED_ENTRY(241), 534 I40E_PTT_UNUSED_ENTRY(242), 535 I40E_PTT_UNUSED_ENTRY(243), 536 I40E_PTT_UNUSED_ENTRY(244), 537 I40E_PTT_UNUSED_ENTRY(245), 538 I40E_PTT_UNUSED_ENTRY(246), 539 I40E_PTT_UNUSED_ENTRY(247), 540 I40E_PTT_UNUSED_ENTRY(248), 541 I40E_PTT_UNUSED_ENTRY(249), 542 543 I40E_PTT_UNUSED_ENTRY(250), 544 I40E_PTT_UNUSED_ENTRY(251), 545 I40E_PTT_UNUSED_ENTRY(252), 546 I40E_PTT_UNUSED_ENTRY(253), 547 I40E_PTT_UNUSED_ENTRY(254), 548 I40E_PTT_UNUSED_ENTRY(255) 549 }; 550 551 552 /** 553 * i40e_validate_mac_addr - Validate unicast MAC address 554 * @mac_addr: pointer to MAC address 555 * 556 * Tests a MAC address to ensure it is a valid Individual Address 557 **/ 558 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 559 { 560 enum i40e_status_code status = I40E_SUCCESS; 561 562 DEBUGFUNC("i40e_validate_mac_addr"); 563 564 /* Broadcast addresses ARE multicast addresses 565 * Make sure it is not a multicast address 566 * Reject the zero address 567 */ 568 if (I40E_IS_MULTICAST(mac_addr) || 569 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 570 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 571 status = I40E_ERR_INVALID_MAC_ADDR; 572 573 return status; 574 } 575 576 /** 577 * i40e_init_shared_code - Initialize the shared code 578 * @hw: pointer to hardware structure 579 * 580 * This assigns the MAC type and PHY code and inits the NVM. 581 * Does not touch the hardware. This function must be called prior to any 582 * other function in the shared code. The i40e_hw structure should be 583 * memset to 0 prior to calling this function. The following fields in 584 * hw structure should be filled in prior to calling this function: 585 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 586 * subsystem_vendor_id, and revision_id 587 **/ 588 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 589 { 590 enum i40e_status_code status = I40E_SUCCESS; 591 u32 port, ari, func_rid; 592 593 DEBUGFUNC("i40e_init_shared_code"); 594 595 i40e_set_mac_type(hw); 596 597 switch (hw->mac.type) { 598 case I40E_MAC_XL710: 599 break; 600 default: 601 return I40E_ERR_DEVICE_NOT_SUPPORTED; 602 } 603 604 hw->phy.get_link_info = TRUE; 605 606 /* Determine port number and PF number*/ 607 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 608 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 609 hw->port = (u8)port; 610 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 611 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 612 func_rid = rd32(hw, I40E_PF_FUNC_RID); 613 if (ari) 614 hw->pf_id = (u8)(func_rid & 0xff); 615 else 616 hw->pf_id = (u8)(func_rid & 0x7); 617 618 status = i40e_init_nvm(hw); 619 return status; 620 } 621 622 /** 623 * i40e_aq_mac_address_read - Retrieve the MAC addresses 624 * @hw: pointer to the hw struct 625 * @flags: a return indicator of what addresses were added to the addr store 626 * @addrs: the requestor's mac addr store 627 * @cmd_details: pointer to command details structure or NULL 628 **/ 629 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 630 u16 *flags, 631 struct i40e_aqc_mac_address_read_data *addrs, 632 struct i40e_asq_cmd_details *cmd_details) 633 { 634 struct i40e_aq_desc desc; 635 struct i40e_aqc_mac_address_read *cmd_data = 636 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 637 enum i40e_status_code status; 638 639 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 640 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 641 642 status = i40e_asq_send_command(hw, &desc, addrs, 643 sizeof(*addrs), cmd_details); 644 *flags = LE16_TO_CPU(cmd_data->command_flags); 645 646 return status; 647 } 648 649 /** 650 * i40e_aq_mac_address_write - Change the MAC addresses 651 * @hw: pointer to the hw struct 652 * @flags: indicates which MAC to be written 653 * @mac_addr: address to write 654 * @cmd_details: pointer to command details structure or NULL 655 **/ 656 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 657 u16 flags, u8 *mac_addr, 658 struct i40e_asq_cmd_details *cmd_details) 659 { 660 struct i40e_aq_desc desc; 661 struct i40e_aqc_mac_address_write *cmd_data = 662 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 663 enum i40e_status_code status; 664 665 i40e_fill_default_direct_cmd_desc(&desc, 666 i40e_aqc_opc_mac_address_write); 667 cmd_data->command_flags = CPU_TO_LE16(flags); 668 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 669 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 670 ((u32)mac_addr[3] << 16) | 671 ((u32)mac_addr[4] << 8) | 672 mac_addr[5]); 673 674 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 675 676 return status; 677 } 678 679 /** 680 * i40e_get_mac_addr - get MAC address 681 * @hw: pointer to the HW structure 682 * @mac_addr: pointer to MAC address 683 * 684 * Reads the adapter's MAC address from register 685 **/ 686 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 687 { 688 struct i40e_aqc_mac_address_read_data addrs; 689 enum i40e_status_code status; 690 u16 flags = 0; 691 692 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 693 694 if (flags & I40E_AQC_LAN_ADDR_VALID) 695 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 696 697 return status; 698 } 699 700 /** 701 * i40e_get_port_mac_addr - get Port MAC address 702 * @hw: pointer to the HW structure 703 * @mac_addr: pointer to Port MAC address 704 * 705 * Reads the adapter's Port MAC address 706 **/ 707 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 708 { 709 struct i40e_aqc_mac_address_read_data addrs; 710 enum i40e_status_code status; 711 u16 flags = 0; 712 713 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 714 if (status) 715 return status; 716 717 if (flags & I40E_AQC_PORT_ADDR_VALID) 718 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 719 else 720 status = I40E_ERR_INVALID_MAC_ADDR; 721 722 return status; 723 } 724 725 /** 726 * i40e_pre_tx_queue_cfg - pre tx queue configure 727 * @hw: pointer to the HW structure 728 * @queue: target pf queue index 729 * @enable: state change request 730 * 731 * Handles hw requirement to indicate intention to enable 732 * or disable target queue. 733 **/ 734 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 735 { 736 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 737 u32 reg_block = 0; 738 u32 reg_val; 739 740 if (abs_queue_idx >= 128) { 741 reg_block = abs_queue_idx / 128; 742 abs_queue_idx %= 128; 743 } 744 745 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 746 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 747 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 748 749 if (enable) 750 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 751 else 752 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 753 754 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 755 } 756 757 /** 758 * i40e_read_pba_string - Reads part number string from EEPROM 759 * @hw: pointer to hardware structure 760 * @pba_num: stores the part number string from the EEPROM 761 * @pba_num_size: part number string buffer length 762 * 763 * Reads the part number string from the EEPROM. 764 **/ 765 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 766 u32 pba_num_size) 767 { 768 enum i40e_status_code status = I40E_SUCCESS; 769 u16 pba_word = 0; 770 u16 pba_size = 0; 771 u16 pba_ptr = 0; 772 u16 i = 0; 773 774 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 775 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 776 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 777 return status; 778 } 779 780 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 781 if (status != I40E_SUCCESS) { 782 DEBUGOUT("Failed to read PBA Block pointer.\n"); 783 return status; 784 } 785 786 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 787 if (status != I40E_SUCCESS) { 788 DEBUGOUT("Failed to read PBA Block size.\n"); 789 return status; 790 } 791 792 /* Subtract one to get PBA word count (PBA Size word is included in 793 * total size) 794 */ 795 pba_size--; 796 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 797 DEBUGOUT("Buffer to small for PBA data.\n"); 798 return I40E_ERR_PARAM; 799 } 800 801 for (i = 0; i < pba_size; i++) { 802 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 803 if (status != I40E_SUCCESS) { 804 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 805 return status; 806 } 807 808 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 809 pba_num[(i * 2) + 1] = pba_word & 0xFF; 810 } 811 pba_num[(pba_size * 2)] = '\0'; 812 813 return status; 814 } 815 816 /** 817 * i40e_get_media_type - Gets media type 818 * @hw: pointer to the hardware structure 819 **/ 820 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 821 { 822 enum i40e_media_type media; 823 824 switch (hw->phy.link_info.phy_type) { 825 case I40E_PHY_TYPE_10GBASE_SR: 826 case I40E_PHY_TYPE_10GBASE_LR: 827 case I40E_PHY_TYPE_1000BASE_SX: 828 case I40E_PHY_TYPE_1000BASE_LX: 829 case I40E_PHY_TYPE_40GBASE_SR4: 830 case I40E_PHY_TYPE_40GBASE_LR4: 831 media = I40E_MEDIA_TYPE_FIBER; 832 break; 833 case I40E_PHY_TYPE_100BASE_TX: 834 case I40E_PHY_TYPE_1000BASE_T: 835 case I40E_PHY_TYPE_10GBASE_T: 836 media = I40E_MEDIA_TYPE_BASET; 837 break; 838 case I40E_PHY_TYPE_10GBASE_CR1_CU: 839 case I40E_PHY_TYPE_40GBASE_CR4_CU: 840 case I40E_PHY_TYPE_10GBASE_CR1: 841 case I40E_PHY_TYPE_40GBASE_CR4: 842 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 843 media = I40E_MEDIA_TYPE_DA; 844 break; 845 case I40E_PHY_TYPE_1000BASE_KX: 846 case I40E_PHY_TYPE_10GBASE_KX4: 847 case I40E_PHY_TYPE_10GBASE_KR: 848 case I40E_PHY_TYPE_40GBASE_KR4: 849 media = I40E_MEDIA_TYPE_BACKPLANE; 850 break; 851 case I40E_PHY_TYPE_SGMII: 852 case I40E_PHY_TYPE_XAUI: 853 case I40E_PHY_TYPE_XFI: 854 case I40E_PHY_TYPE_XLAUI: 855 case I40E_PHY_TYPE_XLPPI: 856 default: 857 media = I40E_MEDIA_TYPE_UNKNOWN; 858 break; 859 } 860 861 return media; 862 } 863 864 #define I40E_PF_RESET_WAIT_COUNT 110 865 /** 866 * i40e_pf_reset - Reset the PF 867 * @hw: pointer to the hardware structure 868 * 869 * Assuming someone else has triggered a global reset, 870 * assure the global reset is complete and then reset the PF 871 **/ 872 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 873 { 874 u32 cnt = 0; 875 u32 cnt1 = 0; 876 u32 reg = 0; 877 u32 grst_del; 878 879 /* Poll for Global Reset steady state in case of recent GRST. 880 * The grst delay value is in 100ms units, and we'll wait a 881 * couple counts longer to be sure we don't just miss the end. 882 */ 883 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 884 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 885 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 886 for (cnt = 0; cnt < grst_del + 2; cnt++) { 887 reg = rd32(hw, I40E_GLGEN_RSTAT); 888 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 889 break; 890 i40e_msec_delay(100); 891 } 892 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 893 DEBUGOUT("Global reset polling failed to complete.\n"); 894 return I40E_ERR_RESET_FAILED; 895 } 896 897 /* Now Wait for the FW to be ready */ 898 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 899 reg = rd32(hw, I40E_GLNVM_ULD); 900 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 901 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 902 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 903 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 904 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 905 break; 906 } 907 i40e_msec_delay(10); 908 } 909 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 910 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 911 DEBUGOUT("wait for FW Reset complete timedout\n"); 912 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 913 return I40E_ERR_RESET_FAILED; 914 } 915 916 /* If there was a Global Reset in progress when we got here, 917 * we don't need to do the PF Reset 918 */ 919 if (!cnt) { 920 reg = rd32(hw, I40E_PFGEN_CTRL); 921 wr32(hw, I40E_PFGEN_CTRL, 922 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 923 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 924 reg = rd32(hw, I40E_PFGEN_CTRL); 925 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 926 break; 927 i40e_msec_delay(1); 928 } 929 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 930 DEBUGOUT("PF reset polling failed to complete.\n"); 931 return I40E_ERR_RESET_FAILED; 932 } 933 } 934 935 i40e_clear_pxe_mode(hw); 936 937 938 return I40E_SUCCESS; 939 } 940 941 /** 942 * i40e_clear_hw - clear out any left over hw state 943 * @hw: pointer to the hw struct 944 * 945 * Clear queues and interrupts, typically called at init time, 946 * but after the capabilities have been found so we know how many 947 * queues and msix vectors have been allocated. 948 **/ 949 void i40e_clear_hw(struct i40e_hw *hw) 950 { 951 u32 num_queues, base_queue; 952 u32 num_pf_int; 953 u32 num_vf_int; 954 u32 num_vfs; 955 u32 i, j; 956 u32 val; 957 u32 eol = 0x7ff; 958 959 /* get number of interrupts, queues, and vfs */ 960 val = rd32(hw, I40E_GLPCI_CNF2); 961 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 962 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 963 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 964 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 965 966 val = rd32(hw, I40E_PFLAN_QALLOC); 967 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 968 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 969 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 970 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 971 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 972 num_queues = (j - base_queue) + 1; 973 else 974 num_queues = 0; 975 976 val = rd32(hw, I40E_PF_VT_PFALLOC); 977 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 978 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 979 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 980 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 981 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 982 num_vfs = (j - i) + 1; 983 else 984 num_vfs = 0; 985 986 /* stop all the interrupts */ 987 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 988 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 989 for (i = 0; i < num_pf_int - 2; i++) 990 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 991 992 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 993 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 994 wr32(hw, I40E_PFINT_LNKLST0, val); 995 for (i = 0; i < num_pf_int - 2; i++) 996 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 997 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 998 for (i = 0; i < num_vfs; i++) 999 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1000 for (i = 0; i < num_vf_int - 2; i++) 1001 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1002 1003 /* warn the HW of the coming Tx disables */ 1004 for (i = 0; i < num_queues; i++) { 1005 u32 abs_queue_idx = base_queue + i; 1006 u32 reg_block = 0; 1007 1008 if (abs_queue_idx >= 128) { 1009 reg_block = abs_queue_idx / 128; 1010 abs_queue_idx %= 128; 1011 } 1012 1013 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1014 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1015 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1016 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1017 1018 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1019 } 1020 i40e_usec_delay(400); 1021 1022 /* stop all the queues */ 1023 for (i = 0; i < num_queues; i++) { 1024 wr32(hw, I40E_QINT_TQCTL(i), 0); 1025 wr32(hw, I40E_QTX_ENA(i), 0); 1026 wr32(hw, I40E_QINT_RQCTL(i), 0); 1027 wr32(hw, I40E_QRX_ENA(i), 0); 1028 } 1029 1030 /* short wait for all queue disables to settle */ 1031 i40e_usec_delay(50); 1032 } 1033 1034 /** 1035 * i40e_clear_pxe_mode - clear pxe operations mode 1036 * @hw: pointer to the hw struct 1037 * 1038 * Make sure all PXE mode settings are cleared, including things 1039 * like descriptor fetch/write-back mode. 1040 **/ 1041 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1042 { 1043 if (i40e_check_asq_alive(hw)) 1044 i40e_aq_clear_pxe_mode(hw, NULL); 1045 } 1046 1047 /** 1048 * i40e_led_is_mine - helper to find matching led 1049 * @hw: pointer to the hw struct 1050 * @idx: index into GPIO registers 1051 * 1052 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1053 */ 1054 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1055 { 1056 u32 gpio_val = 0; 1057 u32 port; 1058 1059 if (!hw->func_caps.led[idx]) 1060 return 0; 1061 1062 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1063 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1064 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1065 1066 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1067 * if it is not our port then ignore 1068 */ 1069 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1070 (port != hw->port)) 1071 return 0; 1072 1073 return gpio_val; 1074 } 1075 1076 #define I40E_COMBINED_ACTIVITY 0xA 1077 #define I40E_FILTER_ACTIVITY 0xE 1078 #define I40E_LINK_ACTIVITY 0xC 1079 #define I40E_MAC_ACTIVITY 0xD 1080 #define I40E_LED0 22 1081 1082 /** 1083 * i40e_led_get - return current on/off mode 1084 * @hw: pointer to the hw struct 1085 * 1086 * The value returned is the 'mode' field as defined in the 1087 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1088 * values are variations of possible behaviors relating to 1089 * blink, link, and wire. 1090 **/ 1091 u32 i40e_led_get(struct i40e_hw *hw) 1092 { 1093 u32 current_mode = 0; 1094 u32 mode = 0; 1095 int i; 1096 1097 /* as per the documentation GPIO 22-29 are the LED 1098 * GPIO pins named LED0..LED7 1099 */ 1100 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1101 u32 gpio_val = i40e_led_is_mine(hw, i); 1102 1103 if (!gpio_val) 1104 continue; 1105 1106 /* ignore gpio LED src mode entries related to the activity 1107 * LEDs 1108 */ 1109 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1110 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1111 switch (current_mode) { 1112 case I40E_COMBINED_ACTIVITY: 1113 case I40E_FILTER_ACTIVITY: 1114 case I40E_MAC_ACTIVITY: 1115 continue; 1116 default: 1117 break; 1118 } 1119 1120 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1121 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1122 break; 1123 } 1124 1125 return mode; 1126 } 1127 1128 /** 1129 * i40e_led_set - set new on/off mode 1130 * @hw: pointer to the hw struct 1131 * @mode: 0=off, 0xf=on (else see manual for mode details) 1132 * @blink: TRUE if the LED should blink when on, FALSE if steady 1133 * 1134 * if this function is used to turn on the blink it should 1135 * be used to disable the blink when restoring the original state. 1136 **/ 1137 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1138 { 1139 u32 current_mode = 0; 1140 int i; 1141 1142 if (mode & 0xfffffff0) 1143 DEBUGOUT1("invalid mode passed in %X\n", mode); 1144 1145 /* as per the documentation GPIO 22-29 are the LED 1146 * GPIO pins named LED0..LED7 1147 */ 1148 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1149 u32 gpio_val = i40e_led_is_mine(hw, i); 1150 1151 if (!gpio_val) 1152 continue; 1153 1154 /* ignore gpio LED src mode entries related to the activity 1155 * LEDs 1156 */ 1157 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1158 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1159 switch (current_mode) { 1160 case I40E_COMBINED_ACTIVITY: 1161 case I40E_FILTER_ACTIVITY: 1162 case I40E_MAC_ACTIVITY: 1163 continue; 1164 default: 1165 break; 1166 } 1167 1168 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1169 /* this & is a bit of paranoia, but serves as a range check */ 1170 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1171 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1172 1173 if (mode == I40E_LINK_ACTIVITY) 1174 blink = FALSE; 1175 1176 if (blink) 1177 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1178 else 1179 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1180 1181 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1182 break; 1183 } 1184 } 1185 1186 /* Admin command wrappers */ 1187 1188 /** 1189 * i40e_aq_get_phy_capabilities 1190 * @hw: pointer to the hw struct 1191 * @abilities: structure for PHY capabilities to be filled 1192 * @qualified_modules: report Qualified Modules 1193 * @report_init: report init capabilities (active are default) 1194 * @cmd_details: pointer to command details structure or NULL 1195 * 1196 * Returns the various PHY abilities supported on the Port. 1197 **/ 1198 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1199 bool qualified_modules, bool report_init, 1200 struct i40e_aq_get_phy_abilities_resp *abilities, 1201 struct i40e_asq_cmd_details *cmd_details) 1202 { 1203 struct i40e_aq_desc desc; 1204 enum i40e_status_code status; 1205 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1206 1207 if (!abilities) 1208 return I40E_ERR_PARAM; 1209 1210 i40e_fill_default_direct_cmd_desc(&desc, 1211 i40e_aqc_opc_get_phy_abilities); 1212 1213 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1214 if (abilities_size > I40E_AQ_LARGE_BUF) 1215 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1216 1217 if (qualified_modules) 1218 desc.params.external.param0 |= 1219 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1220 1221 if (report_init) 1222 desc.params.external.param0 |= 1223 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1224 1225 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1226 cmd_details); 1227 1228 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1229 status = I40E_ERR_UNKNOWN_PHY; 1230 1231 return status; 1232 } 1233 1234 /** 1235 * i40e_aq_set_phy_config 1236 * @hw: pointer to the hw struct 1237 * @config: structure with PHY configuration to be set 1238 * @cmd_details: pointer to command details structure or NULL 1239 * 1240 * Set the various PHY configuration parameters 1241 * supported on the Port.One or more of the Set PHY config parameters may be 1242 * ignored in an MFP mode as the PF may not have the privilege to set some 1243 * of the PHY Config parameters. This status will be indicated by the 1244 * command response. 1245 **/ 1246 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1247 struct i40e_aq_set_phy_config *config, 1248 struct i40e_asq_cmd_details *cmd_details) 1249 { 1250 struct i40e_aq_desc desc; 1251 struct i40e_aq_set_phy_config *cmd = 1252 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1253 enum i40e_status_code status; 1254 1255 if (!config) 1256 return I40E_ERR_PARAM; 1257 1258 i40e_fill_default_direct_cmd_desc(&desc, 1259 i40e_aqc_opc_set_phy_config); 1260 1261 *cmd = *config; 1262 1263 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1264 1265 return status; 1266 } 1267 1268 /** 1269 * i40e_set_fc 1270 * @hw: pointer to the hw struct 1271 * 1272 * Set the requested flow control mode using set_phy_config. 1273 **/ 1274 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1275 bool atomic_restart) 1276 { 1277 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1278 struct i40e_aq_get_phy_abilities_resp abilities; 1279 struct i40e_aq_set_phy_config config; 1280 enum i40e_status_code status; 1281 u8 pause_mask = 0x0; 1282 1283 *aq_failures = 0x0; 1284 1285 switch (fc_mode) { 1286 case I40E_FC_FULL: 1287 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1288 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1289 break; 1290 case I40E_FC_RX_PAUSE: 1291 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1292 break; 1293 case I40E_FC_TX_PAUSE: 1294 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1295 break; 1296 default: 1297 break; 1298 } 1299 1300 /* Get the current phy config */ 1301 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1302 NULL); 1303 if (status) { 1304 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1305 return status; 1306 } 1307 1308 memset(&config, 0, sizeof(config)); 1309 /* clear the old pause settings */ 1310 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1311 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1312 /* set the new abilities */ 1313 config.abilities |= pause_mask; 1314 /* If the abilities have changed, then set the new config */ 1315 if (config.abilities != abilities.abilities) { 1316 /* Auto restart link so settings take effect */ 1317 if (atomic_restart) 1318 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1319 /* Copy over all the old settings */ 1320 config.phy_type = abilities.phy_type; 1321 config.link_speed = abilities.link_speed; 1322 config.eee_capability = abilities.eee_capability; 1323 config.eeer = abilities.eeer_val; 1324 config.low_power_ctrl = abilities.d3_lpan; 1325 status = i40e_aq_set_phy_config(hw, &config, NULL); 1326 1327 if (status) 1328 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1329 } 1330 /* Update the link info */ 1331 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 1332 if (status) { 1333 /* Wait a little bit (on 40G cards it sometimes takes a really 1334 * long time for link to come back from the atomic reset) 1335 * and try once more 1336 */ 1337 i40e_msec_delay(1000); 1338 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 1339 } 1340 if (status) 1341 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1342 1343 return status; 1344 } 1345 1346 /** 1347 * i40e_aq_set_mac_config 1348 * @hw: pointer to the hw struct 1349 * @max_frame_size: Maximum Frame Size to be supported by the port 1350 * @crc_en: Tell HW to append a CRC to outgoing frames 1351 * @pacing: Pacing configurations 1352 * @cmd_details: pointer to command details structure or NULL 1353 * 1354 * Configure MAC settings for frame size, jumbo frame support and the 1355 * addition of a CRC by the hardware. 1356 **/ 1357 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1358 u16 max_frame_size, 1359 bool crc_en, u16 pacing, 1360 struct i40e_asq_cmd_details *cmd_details) 1361 { 1362 struct i40e_aq_desc desc; 1363 struct i40e_aq_set_mac_config *cmd = 1364 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1365 enum i40e_status_code status; 1366 1367 if (max_frame_size == 0) 1368 return I40E_ERR_PARAM; 1369 1370 i40e_fill_default_direct_cmd_desc(&desc, 1371 i40e_aqc_opc_set_mac_config); 1372 1373 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1374 cmd->params = ((u8)pacing & 0x0F) << 3; 1375 if (crc_en) 1376 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1377 1378 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1379 1380 return status; 1381 } 1382 1383 /** 1384 * i40e_aq_clear_pxe_mode 1385 * @hw: pointer to the hw struct 1386 * @cmd_details: pointer to command details structure or NULL 1387 * 1388 * Tell the firmware that the driver is taking over from PXE 1389 **/ 1390 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1391 struct i40e_asq_cmd_details *cmd_details) 1392 { 1393 enum i40e_status_code status; 1394 struct i40e_aq_desc desc; 1395 struct i40e_aqc_clear_pxe *cmd = 1396 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1397 1398 i40e_fill_default_direct_cmd_desc(&desc, 1399 i40e_aqc_opc_clear_pxe_mode); 1400 1401 cmd->rx_cnt = 0x2; 1402 1403 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1404 1405 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1406 1407 return status; 1408 } 1409 1410 /** 1411 * i40e_aq_set_link_restart_an 1412 * @hw: pointer to the hw struct 1413 * @enable_link: if TRUE: enable link, if FALSE: disable link 1414 * @cmd_details: pointer to command details structure or NULL 1415 * 1416 * Sets up the link and restarts the Auto-Negotiation over the link. 1417 **/ 1418 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1419 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1420 { 1421 struct i40e_aq_desc desc; 1422 struct i40e_aqc_set_link_restart_an *cmd = 1423 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1424 enum i40e_status_code status; 1425 1426 i40e_fill_default_direct_cmd_desc(&desc, 1427 i40e_aqc_opc_set_link_restart_an); 1428 1429 cmd->command = I40E_AQ_PHY_RESTART_AN; 1430 if (enable_link) 1431 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1432 else 1433 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1434 1435 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1436 1437 return status; 1438 } 1439 1440 /** 1441 * i40e_aq_get_link_info 1442 * @hw: pointer to the hw struct 1443 * @enable_lse: enable/disable LinkStatusEvent reporting 1444 * @link: pointer to link status structure - optional 1445 * @cmd_details: pointer to command details structure or NULL 1446 * 1447 * Returns the link status of the adapter. 1448 **/ 1449 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1450 bool enable_lse, struct i40e_link_status *link, 1451 struct i40e_asq_cmd_details *cmd_details) 1452 { 1453 struct i40e_aq_desc desc; 1454 struct i40e_aqc_get_link_status *resp = 1455 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1456 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1457 enum i40e_status_code status; 1458 bool tx_pause, rx_pause; 1459 u16 command_flags; 1460 1461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1462 1463 if (enable_lse) 1464 command_flags = I40E_AQ_LSE_ENABLE; 1465 else 1466 command_flags = I40E_AQ_LSE_DISABLE; 1467 resp->command_flags = CPU_TO_LE16(command_flags); 1468 1469 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1470 1471 if (status != I40E_SUCCESS) 1472 goto aq_get_link_info_exit; 1473 1474 /* save off old link status information */ 1475 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1476 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1477 1478 /* update link status */ 1479 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1480 hw->phy.media_type = i40e_get_media_type(hw); 1481 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1482 hw_link_info->link_info = resp->link_info; 1483 hw_link_info->an_info = resp->an_info; 1484 hw_link_info->ext_info = resp->ext_info; 1485 hw_link_info->loopback = resp->loopback; 1486 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1487 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1488 1489 /* update fc info */ 1490 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1491 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1492 if (tx_pause & rx_pause) 1493 hw->fc.current_mode = I40E_FC_FULL; 1494 else if (tx_pause) 1495 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1496 else if (rx_pause) 1497 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1498 else 1499 hw->fc.current_mode = I40E_FC_NONE; 1500 1501 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1502 hw_link_info->crc_enable = TRUE; 1503 else 1504 hw_link_info->crc_enable = FALSE; 1505 1506 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE)) 1507 hw_link_info->lse_enable = TRUE; 1508 else 1509 hw_link_info->lse_enable = FALSE; 1510 1511 /* save link status information */ 1512 if (link) 1513 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1514 I40E_NONDMA_TO_NONDMA); 1515 1516 /* flag cleared so helper functions don't call AQ again */ 1517 hw->phy.get_link_info = FALSE; 1518 1519 aq_get_link_info_exit: 1520 return status; 1521 } 1522 1523 /** 1524 * i40e_aq_set_phy_int_mask 1525 * @hw: pointer to the hw struct 1526 * @mask: interrupt mask to be set 1527 * @cmd_details: pointer to command details structure or NULL 1528 * 1529 * Set link interrupt mask. 1530 **/ 1531 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1532 u16 mask, 1533 struct i40e_asq_cmd_details *cmd_details) 1534 { 1535 struct i40e_aq_desc desc; 1536 struct i40e_aqc_set_phy_int_mask *cmd = 1537 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1538 enum i40e_status_code status; 1539 1540 i40e_fill_default_direct_cmd_desc(&desc, 1541 i40e_aqc_opc_set_phy_int_mask); 1542 1543 cmd->event_mask = CPU_TO_LE16(mask); 1544 1545 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1546 1547 return status; 1548 } 1549 1550 /** 1551 * i40e_aq_get_local_advt_reg 1552 * @hw: pointer to the hw struct 1553 * @advt_reg: local AN advertisement register value 1554 * @cmd_details: pointer to command details structure or NULL 1555 * 1556 * Get the Local AN advertisement register value. 1557 **/ 1558 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1559 u64 *advt_reg, 1560 struct i40e_asq_cmd_details *cmd_details) 1561 { 1562 struct i40e_aq_desc desc; 1563 struct i40e_aqc_an_advt_reg *resp = 1564 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1565 enum i40e_status_code status; 1566 1567 i40e_fill_default_direct_cmd_desc(&desc, 1568 i40e_aqc_opc_get_local_advt_reg); 1569 1570 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1571 1572 if (status != I40E_SUCCESS) 1573 goto aq_get_local_advt_reg_exit; 1574 1575 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1576 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1577 1578 aq_get_local_advt_reg_exit: 1579 return status; 1580 } 1581 1582 /** 1583 * i40e_aq_set_local_advt_reg 1584 * @hw: pointer to the hw struct 1585 * @advt_reg: local AN advertisement register value 1586 * @cmd_details: pointer to command details structure or NULL 1587 * 1588 * Get the Local AN advertisement register value. 1589 **/ 1590 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 1591 u64 advt_reg, 1592 struct i40e_asq_cmd_details *cmd_details) 1593 { 1594 struct i40e_aq_desc desc; 1595 struct i40e_aqc_an_advt_reg *cmd = 1596 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1597 enum i40e_status_code status; 1598 1599 i40e_fill_default_direct_cmd_desc(&desc, 1600 i40e_aqc_opc_get_local_advt_reg); 1601 1602 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 1603 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 1604 1605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1606 1607 return status; 1608 } 1609 1610 /** 1611 * i40e_aq_get_partner_advt 1612 * @hw: pointer to the hw struct 1613 * @advt_reg: AN partner advertisement register value 1614 * @cmd_details: pointer to command details structure or NULL 1615 * 1616 * Get the link partner AN advertisement register value. 1617 **/ 1618 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 1619 u64 *advt_reg, 1620 struct i40e_asq_cmd_details *cmd_details) 1621 { 1622 struct i40e_aq_desc desc; 1623 struct i40e_aqc_an_advt_reg *resp = 1624 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1625 enum i40e_status_code status; 1626 1627 i40e_fill_default_direct_cmd_desc(&desc, 1628 i40e_aqc_opc_get_partner_advt); 1629 1630 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1631 1632 if (status != I40E_SUCCESS) 1633 goto aq_get_partner_advt_exit; 1634 1635 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1636 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1637 1638 aq_get_partner_advt_exit: 1639 return status; 1640 } 1641 1642 /** 1643 * i40e_aq_set_lb_modes 1644 * @hw: pointer to the hw struct 1645 * @lb_modes: loopback mode to be set 1646 * @cmd_details: pointer to command details structure or NULL 1647 * 1648 * Sets loopback modes. 1649 **/ 1650 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 1651 u16 lb_modes, 1652 struct i40e_asq_cmd_details *cmd_details) 1653 { 1654 struct i40e_aq_desc desc; 1655 struct i40e_aqc_set_lb_mode *cmd = 1656 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 1657 enum i40e_status_code status; 1658 1659 i40e_fill_default_direct_cmd_desc(&desc, 1660 i40e_aqc_opc_set_lb_modes); 1661 1662 cmd->lb_mode = CPU_TO_LE16(lb_modes); 1663 1664 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1665 1666 return status; 1667 } 1668 1669 /** 1670 * i40e_aq_set_phy_debug 1671 * @hw: pointer to the hw struct 1672 * @cmd_flags: debug command flags 1673 * @cmd_details: pointer to command details structure or NULL 1674 * 1675 * Reset the external PHY. 1676 **/ 1677 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1678 struct i40e_asq_cmd_details *cmd_details) 1679 { 1680 struct i40e_aq_desc desc; 1681 struct i40e_aqc_set_phy_debug *cmd = 1682 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1683 enum i40e_status_code status; 1684 1685 i40e_fill_default_direct_cmd_desc(&desc, 1686 i40e_aqc_opc_set_phy_debug); 1687 1688 cmd->command_flags = cmd_flags; 1689 1690 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1691 1692 return status; 1693 } 1694 1695 /** 1696 * i40e_aq_add_vsi 1697 * @hw: pointer to the hw struct 1698 * @vsi_ctx: pointer to a vsi context struct 1699 * @cmd_details: pointer to command details structure or NULL 1700 * 1701 * Add a VSI context to the hardware. 1702 **/ 1703 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 1704 struct i40e_vsi_context *vsi_ctx, 1705 struct i40e_asq_cmd_details *cmd_details) 1706 { 1707 struct i40e_aq_desc desc; 1708 struct i40e_aqc_add_get_update_vsi *cmd = 1709 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1710 struct i40e_aqc_add_get_update_vsi_completion *resp = 1711 (struct i40e_aqc_add_get_update_vsi_completion *) 1712 &desc.params.raw; 1713 enum i40e_status_code status; 1714 1715 i40e_fill_default_direct_cmd_desc(&desc, 1716 i40e_aqc_opc_add_vsi); 1717 1718 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 1719 cmd->connection_type = vsi_ctx->connection_type; 1720 cmd->vf_id = vsi_ctx->vf_num; 1721 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 1722 1723 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1724 1725 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1726 sizeof(vsi_ctx->info), cmd_details); 1727 1728 if (status != I40E_SUCCESS) 1729 goto aq_add_vsi_exit; 1730 1731 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 1732 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 1733 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 1734 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 1735 1736 aq_add_vsi_exit: 1737 return status; 1738 } 1739 1740 /** 1741 * i40e_aq_set_default_vsi 1742 * @hw: pointer to the hw struct 1743 * @seid: vsi number 1744 * @cmd_details: pointer to command details structure or NULL 1745 **/ 1746 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 1747 u16 seid, 1748 struct i40e_asq_cmd_details *cmd_details) 1749 { 1750 struct i40e_aq_desc desc; 1751 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1752 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1753 &desc.params.raw; 1754 enum i40e_status_code status; 1755 1756 i40e_fill_default_direct_cmd_desc(&desc, 1757 i40e_aqc_opc_set_vsi_promiscuous_modes); 1758 1759 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1760 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1761 cmd->seid = CPU_TO_LE16(seid); 1762 1763 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1764 1765 return status; 1766 } 1767 1768 /** 1769 * i40e_aq_set_vsi_unicast_promiscuous 1770 * @hw: pointer to the hw struct 1771 * @seid: vsi number 1772 * @set: set unicast promiscuous enable/disable 1773 * @cmd_details: pointer to command details structure or NULL 1774 **/ 1775 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1776 u16 seid, bool set, 1777 struct i40e_asq_cmd_details *cmd_details) 1778 { 1779 struct i40e_aq_desc desc; 1780 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1781 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1782 enum i40e_status_code status; 1783 u16 flags = 0; 1784 1785 i40e_fill_default_direct_cmd_desc(&desc, 1786 i40e_aqc_opc_set_vsi_promiscuous_modes); 1787 1788 if (set) 1789 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1790 1791 cmd->promiscuous_flags = CPU_TO_LE16(flags); 1792 1793 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1794 1795 cmd->seid = CPU_TO_LE16(seid); 1796 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1797 1798 return status; 1799 } 1800 1801 /** 1802 * i40e_aq_set_vsi_multicast_promiscuous 1803 * @hw: pointer to the hw struct 1804 * @seid: vsi number 1805 * @set: set multicast promiscuous enable/disable 1806 * @cmd_details: pointer to command details structure or NULL 1807 **/ 1808 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1809 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 1810 { 1811 struct i40e_aq_desc desc; 1812 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1813 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1814 enum i40e_status_code status; 1815 u16 flags = 0; 1816 1817 i40e_fill_default_direct_cmd_desc(&desc, 1818 i40e_aqc_opc_set_vsi_promiscuous_modes); 1819 1820 if (set) 1821 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1822 1823 cmd->promiscuous_flags = CPU_TO_LE16(flags); 1824 1825 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1826 1827 cmd->seid = CPU_TO_LE16(seid); 1828 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1829 1830 return status; 1831 } 1832 1833 /** 1834 * i40e_aq_set_vsi_broadcast 1835 * @hw: pointer to the hw struct 1836 * @seid: vsi number 1837 * @set_filter: TRUE to set filter, FALSE to clear filter 1838 * @cmd_details: pointer to command details structure or NULL 1839 * 1840 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1841 **/ 1842 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1843 u16 seid, bool set_filter, 1844 struct i40e_asq_cmd_details *cmd_details) 1845 { 1846 struct i40e_aq_desc desc; 1847 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1848 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1849 enum i40e_status_code status; 1850 1851 i40e_fill_default_direct_cmd_desc(&desc, 1852 i40e_aqc_opc_set_vsi_promiscuous_modes); 1853 1854 if (set_filter) 1855 cmd->promiscuous_flags 1856 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1857 else 1858 cmd->promiscuous_flags 1859 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1860 1861 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1862 cmd->seid = CPU_TO_LE16(seid); 1863 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1864 1865 return status; 1866 } 1867 1868 /** 1869 * i40e_get_vsi_params - get VSI configuration info 1870 * @hw: pointer to the hw struct 1871 * @vsi_ctx: pointer to a vsi context struct 1872 * @cmd_details: pointer to command details structure or NULL 1873 **/ 1874 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 1875 struct i40e_vsi_context *vsi_ctx, 1876 struct i40e_asq_cmd_details *cmd_details) 1877 { 1878 struct i40e_aq_desc desc; 1879 struct i40e_aqc_add_get_update_vsi *cmd = 1880 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1881 struct i40e_aqc_add_get_update_vsi_completion *resp = 1882 (struct i40e_aqc_add_get_update_vsi_completion *) 1883 &desc.params.raw; 1884 enum i40e_status_code status; 1885 1886 i40e_fill_default_direct_cmd_desc(&desc, 1887 i40e_aqc_opc_get_vsi_parameters); 1888 1889 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 1890 1891 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1892 1893 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1894 sizeof(vsi_ctx->info), NULL); 1895 1896 if (status != I40E_SUCCESS) 1897 goto aq_get_vsi_params_exit; 1898 1899 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 1900 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 1901 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 1902 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 1903 1904 aq_get_vsi_params_exit: 1905 return status; 1906 } 1907 1908 /** 1909 * i40e_aq_update_vsi_params 1910 * @hw: pointer to the hw struct 1911 * @vsi_ctx: pointer to a vsi context struct 1912 * @cmd_details: pointer to command details structure or NULL 1913 * 1914 * Update a VSI context. 1915 **/ 1916 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 1917 struct i40e_vsi_context *vsi_ctx, 1918 struct i40e_asq_cmd_details *cmd_details) 1919 { 1920 struct i40e_aq_desc desc; 1921 struct i40e_aqc_add_get_update_vsi *cmd = 1922 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1923 enum i40e_status_code status; 1924 1925 i40e_fill_default_direct_cmd_desc(&desc, 1926 i40e_aqc_opc_update_vsi_parameters); 1927 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 1928 1929 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1930 1931 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1932 sizeof(vsi_ctx->info), cmd_details); 1933 1934 return status; 1935 } 1936 1937 /** 1938 * i40e_aq_get_switch_config 1939 * @hw: pointer to the hardware structure 1940 * @buf: pointer to the result buffer 1941 * @buf_size: length of input buffer 1942 * @start_seid: seid to start for the report, 0 == beginning 1943 * @cmd_details: pointer to command details structure or NULL 1944 * 1945 * Fill the buf with switch configuration returned from AdminQ command 1946 **/ 1947 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 1948 struct i40e_aqc_get_switch_config_resp *buf, 1949 u16 buf_size, u16 *start_seid, 1950 struct i40e_asq_cmd_details *cmd_details) 1951 { 1952 struct i40e_aq_desc desc; 1953 struct i40e_aqc_switch_seid *scfg = 1954 (struct i40e_aqc_switch_seid *)&desc.params.raw; 1955 enum i40e_status_code status; 1956 1957 i40e_fill_default_direct_cmd_desc(&desc, 1958 i40e_aqc_opc_get_switch_config); 1959 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1960 if (buf_size > I40E_AQ_LARGE_BUF) 1961 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1962 scfg->seid = CPU_TO_LE16(*start_seid); 1963 1964 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1965 *start_seid = LE16_TO_CPU(scfg->seid); 1966 1967 return status; 1968 } 1969 1970 /** 1971 * i40e_aq_get_firmware_version 1972 * @hw: pointer to the hw struct 1973 * @fw_major_version: firmware major version 1974 * @fw_minor_version: firmware minor version 1975 * @fw_build: firmware build number 1976 * @api_major_version: major queue version 1977 * @api_minor_version: minor queue version 1978 * @cmd_details: pointer to command details structure or NULL 1979 * 1980 * Get the firmware version from the admin queue commands 1981 **/ 1982 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 1983 u16 *fw_major_version, u16 *fw_minor_version, 1984 u32 *fw_build, 1985 u16 *api_major_version, u16 *api_minor_version, 1986 struct i40e_asq_cmd_details *cmd_details) 1987 { 1988 struct i40e_aq_desc desc; 1989 struct i40e_aqc_get_version *resp = 1990 (struct i40e_aqc_get_version *)&desc.params.raw; 1991 enum i40e_status_code status; 1992 1993 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1994 1995 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1996 1997 if (status == I40E_SUCCESS) { 1998 if (fw_major_version != NULL) 1999 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2000 if (fw_minor_version != NULL) 2001 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2002 if (fw_build != NULL) 2003 *fw_build = LE32_TO_CPU(resp->fw_build); 2004 if (api_major_version != NULL) 2005 *api_major_version = LE16_TO_CPU(resp->api_major); 2006 if (api_minor_version != NULL) 2007 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2008 2009 /* A workaround to fix the API version in SW */ 2010 if (api_major_version && api_minor_version && 2011 fw_major_version && fw_minor_version && 2012 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2013 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2014 (*fw_major_version > 4))) 2015 *api_minor_version = 2; 2016 } 2017 2018 return status; 2019 } 2020 2021 /** 2022 * i40e_aq_send_driver_version 2023 * @hw: pointer to the hw struct 2024 * @dv: driver's major, minor version 2025 * @cmd_details: pointer to command details structure or NULL 2026 * 2027 * Send the driver version to the firmware 2028 **/ 2029 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2030 struct i40e_driver_version *dv, 2031 struct i40e_asq_cmd_details *cmd_details) 2032 { 2033 struct i40e_aq_desc desc; 2034 struct i40e_aqc_driver_version *cmd = 2035 (struct i40e_aqc_driver_version *)&desc.params.raw; 2036 enum i40e_status_code status; 2037 u16 len; 2038 2039 if (dv == NULL) 2040 return I40E_ERR_PARAM; 2041 2042 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2043 2044 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2045 cmd->driver_major_ver = dv->major_version; 2046 cmd->driver_minor_ver = dv->minor_version; 2047 cmd->driver_build_ver = dv->build_version; 2048 cmd->driver_subbuild_ver = dv->subbuild_version; 2049 2050 len = 0; 2051 while (len < sizeof(dv->driver_string) && 2052 (dv->driver_string[len] < 0x80) && 2053 dv->driver_string[len]) 2054 len++; 2055 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2056 len, cmd_details); 2057 2058 return status; 2059 } 2060 2061 /** 2062 * i40e_get_link_status - get status of the HW network link 2063 * @hw: pointer to the hw struct 2064 * 2065 * Returns TRUE if link is up, FALSE if link is down. 2066 * 2067 * Side effect: LinkStatusEvent reporting becomes enabled 2068 **/ 2069 bool i40e_get_link_status(struct i40e_hw *hw) 2070 { 2071 enum i40e_status_code status = I40E_SUCCESS; 2072 bool link_status = FALSE; 2073 2074 if (hw->phy.get_link_info) { 2075 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2076 2077 if (status != I40E_SUCCESS) 2078 goto i40e_get_link_status_exit; 2079 } 2080 2081 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2082 2083 i40e_get_link_status_exit: 2084 return link_status; 2085 } 2086 2087 /** 2088 * i40e_get_link_speed 2089 * @hw: pointer to the hw struct 2090 * 2091 * Returns the link speed of the adapter. 2092 **/ 2093 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2094 { 2095 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2096 enum i40e_status_code status = I40E_SUCCESS; 2097 2098 if (hw->phy.get_link_info) { 2099 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2100 2101 if (status != I40E_SUCCESS) 2102 goto i40e_link_speed_exit; 2103 } 2104 2105 speed = hw->phy.link_info.link_speed; 2106 2107 i40e_link_speed_exit: 2108 return speed; 2109 } 2110 2111 /** 2112 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2113 * @hw: pointer to the hw struct 2114 * @uplink_seid: the MAC or other gizmo SEID 2115 * @downlink_seid: the VSI SEID 2116 * @enabled_tc: bitmap of TCs to be enabled 2117 * @default_port: TRUE for default port VSI, FALSE for control port 2118 * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support 2119 * @veb_seid: pointer to where to put the resulting VEB SEID 2120 * @cmd_details: pointer to command details structure or NULL 2121 * 2122 * This asks the FW to add a VEB between the uplink and downlink 2123 * elements. If the uplink SEID is 0, this will be a floating VEB. 2124 **/ 2125 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2126 u16 downlink_seid, u8 enabled_tc, 2127 bool default_port, bool enable_l2_filtering, 2128 u16 *veb_seid, 2129 struct i40e_asq_cmd_details *cmd_details) 2130 { 2131 struct i40e_aq_desc desc; 2132 struct i40e_aqc_add_veb *cmd = 2133 (struct i40e_aqc_add_veb *)&desc.params.raw; 2134 struct i40e_aqc_add_veb_completion *resp = 2135 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2136 enum i40e_status_code status; 2137 u16 veb_flags = 0; 2138 2139 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2140 if (!!uplink_seid != !!downlink_seid) 2141 return I40E_ERR_PARAM; 2142 2143 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2144 2145 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2146 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2147 cmd->enable_tcs = enabled_tc; 2148 if (!uplink_seid) 2149 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2150 if (default_port) 2151 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2152 else 2153 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2154 2155 if (enable_l2_filtering) 2156 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 2157 2158 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2159 2160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2161 2162 if (!status && veb_seid) 2163 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2164 2165 return status; 2166 } 2167 2168 /** 2169 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2170 * @hw: pointer to the hw struct 2171 * @veb_seid: the SEID of the VEB to query 2172 * @switch_id: the uplink switch id 2173 * @floating: set to TRUE if the VEB is floating 2174 * @statistic_index: index of the stats counter block for this VEB 2175 * @vebs_used: number of VEB's used by function 2176 * @vebs_free: total VEB's not reserved by any function 2177 * @cmd_details: pointer to command details structure or NULL 2178 * 2179 * This retrieves the parameters for a particular VEB, specified by 2180 * uplink_seid, and returns them to the caller. 2181 **/ 2182 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2183 u16 veb_seid, u16 *switch_id, 2184 bool *floating, u16 *statistic_index, 2185 u16 *vebs_used, u16 *vebs_free, 2186 struct i40e_asq_cmd_details *cmd_details) 2187 { 2188 struct i40e_aq_desc desc; 2189 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2190 (struct i40e_aqc_get_veb_parameters_completion *) 2191 &desc.params.raw; 2192 enum i40e_status_code status; 2193 2194 if (veb_seid == 0) 2195 return I40E_ERR_PARAM; 2196 2197 i40e_fill_default_direct_cmd_desc(&desc, 2198 i40e_aqc_opc_get_veb_parameters); 2199 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2200 2201 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2202 if (status) 2203 goto get_veb_exit; 2204 2205 if (switch_id) 2206 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2207 if (statistic_index) 2208 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2209 if (vebs_used) 2210 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2211 if (vebs_free) 2212 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2213 if (floating) { 2214 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2215 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2216 *floating = TRUE; 2217 else 2218 *floating = FALSE; 2219 } 2220 2221 get_veb_exit: 2222 return status; 2223 } 2224 2225 /** 2226 * i40e_aq_add_macvlan 2227 * @hw: pointer to the hw struct 2228 * @seid: VSI for the mac address 2229 * @mv_list: list of macvlans to be added 2230 * @count: length of the list 2231 * @cmd_details: pointer to command details structure or NULL 2232 * 2233 * Add MAC/VLAN addresses to the HW filtering 2234 **/ 2235 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2236 struct i40e_aqc_add_macvlan_element_data *mv_list, 2237 u16 count, struct i40e_asq_cmd_details *cmd_details) 2238 { 2239 struct i40e_aq_desc desc; 2240 struct i40e_aqc_macvlan *cmd = 2241 (struct i40e_aqc_macvlan *)&desc.params.raw; 2242 enum i40e_status_code status; 2243 u16 buf_size; 2244 2245 if (count == 0 || !mv_list || !hw) 2246 return I40E_ERR_PARAM; 2247 2248 buf_size = count * sizeof(*mv_list); 2249 2250 /* prep the rest of the request */ 2251 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2252 cmd->num_addresses = CPU_TO_LE16(count); 2253 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2254 cmd->seid[1] = 0; 2255 cmd->seid[2] = 0; 2256 2257 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2258 if (buf_size > I40E_AQ_LARGE_BUF) 2259 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2260 2261 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2262 cmd_details); 2263 2264 return status; 2265 } 2266 2267 /** 2268 * i40e_aq_remove_macvlan 2269 * @hw: pointer to the hw struct 2270 * @seid: VSI for the mac address 2271 * @mv_list: list of macvlans to be removed 2272 * @count: length of the list 2273 * @cmd_details: pointer to command details structure or NULL 2274 * 2275 * Remove MAC/VLAN addresses from the HW filtering 2276 **/ 2277 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2278 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2279 u16 count, struct i40e_asq_cmd_details *cmd_details) 2280 { 2281 struct i40e_aq_desc desc; 2282 struct i40e_aqc_macvlan *cmd = 2283 (struct i40e_aqc_macvlan *)&desc.params.raw; 2284 enum i40e_status_code status; 2285 u16 buf_size; 2286 2287 if (count == 0 || !mv_list || !hw) 2288 return I40E_ERR_PARAM; 2289 2290 buf_size = count * sizeof(*mv_list); 2291 2292 /* prep the rest of the request */ 2293 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2294 cmd->num_addresses = CPU_TO_LE16(count); 2295 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2296 cmd->seid[1] = 0; 2297 cmd->seid[2] = 0; 2298 2299 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2300 if (buf_size > I40E_AQ_LARGE_BUF) 2301 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2302 2303 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2304 cmd_details); 2305 2306 return status; 2307 } 2308 2309 /** 2310 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 2311 * @hw: pointer to the hw struct 2312 * @seid: VSI for the vlan filters 2313 * @v_list: list of vlan filters to be added 2314 * @count: length of the list 2315 * @cmd_details: pointer to command details structure or NULL 2316 **/ 2317 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 2318 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2319 u8 count, struct i40e_asq_cmd_details *cmd_details) 2320 { 2321 struct i40e_aq_desc desc; 2322 struct i40e_aqc_macvlan *cmd = 2323 (struct i40e_aqc_macvlan *)&desc.params.raw; 2324 enum i40e_status_code status; 2325 u16 buf_size; 2326 2327 if (count == 0 || !v_list || !hw) 2328 return I40E_ERR_PARAM; 2329 2330 buf_size = count * sizeof(*v_list); 2331 2332 /* prep the rest of the request */ 2333 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 2334 cmd->num_addresses = CPU_TO_LE16(count); 2335 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2336 cmd->seid[1] = 0; 2337 cmd->seid[2] = 0; 2338 2339 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2340 if (buf_size > I40E_AQ_LARGE_BUF) 2341 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2342 2343 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2344 cmd_details); 2345 2346 return status; 2347 } 2348 2349 /** 2350 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 2351 * @hw: pointer to the hw struct 2352 * @seid: VSI for the vlan filters 2353 * @v_list: list of macvlans to be removed 2354 * @count: length of the list 2355 * @cmd_details: pointer to command details structure or NULL 2356 **/ 2357 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 2358 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2359 u8 count, struct i40e_asq_cmd_details *cmd_details) 2360 { 2361 struct i40e_aq_desc desc; 2362 struct i40e_aqc_macvlan *cmd = 2363 (struct i40e_aqc_macvlan *)&desc.params.raw; 2364 enum i40e_status_code status; 2365 u16 buf_size; 2366 2367 if (count == 0 || !v_list || !hw) 2368 return I40E_ERR_PARAM; 2369 2370 buf_size = count * sizeof(*v_list); 2371 2372 /* prep the rest of the request */ 2373 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 2374 cmd->num_addresses = CPU_TO_LE16(count); 2375 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2376 cmd->seid[1] = 0; 2377 cmd->seid[2] = 0; 2378 2379 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2380 if (buf_size > I40E_AQ_LARGE_BUF) 2381 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2382 2383 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2384 cmd_details); 2385 2386 return status; 2387 } 2388 2389 /** 2390 * i40e_aq_send_msg_to_vf 2391 * @hw: pointer to the hardware structure 2392 * @vfid: vf id to send msg 2393 * @v_opcode: opcodes for VF-PF communication 2394 * @v_retval: return error code 2395 * @msg: pointer to the msg buffer 2396 * @msglen: msg length 2397 * @cmd_details: pointer to command details 2398 * 2399 * send msg to vf 2400 **/ 2401 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2402 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2403 struct i40e_asq_cmd_details *cmd_details) 2404 { 2405 struct i40e_aq_desc desc; 2406 struct i40e_aqc_pf_vf_message *cmd = 2407 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2408 enum i40e_status_code status; 2409 2410 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2411 cmd->id = CPU_TO_LE32(vfid); 2412 desc.cookie_high = CPU_TO_LE32(v_opcode); 2413 desc.cookie_low = CPU_TO_LE32(v_retval); 2414 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 2415 if (msglen) { 2416 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 2417 I40E_AQ_FLAG_RD)); 2418 if (msglen > I40E_AQ_LARGE_BUF) 2419 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2420 desc.datalen = CPU_TO_LE16(msglen); 2421 } 2422 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2423 2424 return status; 2425 } 2426 2427 /** 2428 * i40e_aq_debug_read_register 2429 * @hw: pointer to the hw struct 2430 * @reg_addr: register address 2431 * @reg_val: register value 2432 * @cmd_details: pointer to command details structure or NULL 2433 * 2434 * Read the register using the admin queue commands 2435 **/ 2436 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 2437 u32 reg_addr, u64 *reg_val, 2438 struct i40e_asq_cmd_details *cmd_details) 2439 { 2440 struct i40e_aq_desc desc; 2441 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2442 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2443 enum i40e_status_code status; 2444 2445 if (reg_val == NULL) 2446 return I40E_ERR_PARAM; 2447 2448 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2449 2450 cmd_resp->address = CPU_TO_LE32(reg_addr); 2451 2452 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2453 2454 if (status == I40E_SUCCESS) { 2455 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 2456 (u64)LE32_TO_CPU(cmd_resp->value_low); 2457 } 2458 2459 return status; 2460 } 2461 2462 /** 2463 * i40e_aq_debug_write_register 2464 * @hw: pointer to the hw struct 2465 * @reg_addr: register address 2466 * @reg_val: register value 2467 * @cmd_details: pointer to command details structure or NULL 2468 * 2469 * Write to a register using the admin queue commands 2470 **/ 2471 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 2472 u32 reg_addr, u64 reg_val, 2473 struct i40e_asq_cmd_details *cmd_details) 2474 { 2475 struct i40e_aq_desc desc; 2476 struct i40e_aqc_debug_reg_read_write *cmd = 2477 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2478 enum i40e_status_code status; 2479 2480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2481 2482 cmd->address = CPU_TO_LE32(reg_addr); 2483 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 2484 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 2485 2486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2487 2488 return status; 2489 } 2490 2491 /** 2492 * i40e_aq_get_hmc_resource_profile 2493 * @hw: pointer to the hw struct 2494 * @profile: type of profile the HMC is to be set as 2495 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2496 * @cmd_details: pointer to command details structure or NULL 2497 * 2498 * query the HMC profile of the device. 2499 **/ 2500 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw, 2501 enum i40e_aq_hmc_profile *profile, 2502 u8 *pe_vf_enabled_count, 2503 struct i40e_asq_cmd_details *cmd_details) 2504 { 2505 struct i40e_aq_desc desc; 2506 struct i40e_aq_get_set_hmc_resource_profile *resp = 2507 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2508 enum i40e_status_code status; 2509 2510 i40e_fill_default_direct_cmd_desc(&desc, 2511 i40e_aqc_opc_query_hmc_resource_profile); 2512 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2513 2514 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile & 2515 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK); 2516 *pe_vf_enabled_count = resp->pe_vf_enabled & 2517 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK; 2518 2519 return status; 2520 } 2521 2522 /** 2523 * i40e_aq_set_hmc_resource_profile 2524 * @hw: pointer to the hw struct 2525 * @profile: type of profile the HMC is to be set as 2526 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2527 * @cmd_details: pointer to command details structure or NULL 2528 * 2529 * set the HMC profile of the device. 2530 **/ 2531 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2532 enum i40e_aq_hmc_profile profile, 2533 u8 pe_vf_enabled_count, 2534 struct i40e_asq_cmd_details *cmd_details) 2535 { 2536 struct i40e_aq_desc desc; 2537 struct i40e_aq_get_set_hmc_resource_profile *cmd = 2538 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2539 enum i40e_status_code status; 2540 2541 i40e_fill_default_direct_cmd_desc(&desc, 2542 i40e_aqc_opc_set_hmc_resource_profile); 2543 2544 cmd->pm_profile = (u8)profile; 2545 cmd->pe_vf_enabled = pe_vf_enabled_count; 2546 2547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2548 2549 return status; 2550 } 2551 2552 /** 2553 * i40e_aq_request_resource 2554 * @hw: pointer to the hw struct 2555 * @resource: resource id 2556 * @access: access type 2557 * @sdp_number: resource number 2558 * @timeout: the maximum time in ms that the driver may hold the resource 2559 * @cmd_details: pointer to command details structure or NULL 2560 * 2561 * requests common resource using the admin queue commands 2562 **/ 2563 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 2564 enum i40e_aq_resources_ids resource, 2565 enum i40e_aq_resource_access_type access, 2566 u8 sdp_number, u64 *timeout, 2567 struct i40e_asq_cmd_details *cmd_details) 2568 { 2569 struct i40e_aq_desc desc; 2570 struct i40e_aqc_request_resource *cmd_resp = 2571 (struct i40e_aqc_request_resource *)&desc.params.raw; 2572 enum i40e_status_code status; 2573 2574 DEBUGFUNC("i40e_aq_request_resource"); 2575 2576 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2577 2578 cmd_resp->resource_id = CPU_TO_LE16(resource); 2579 cmd_resp->access_type = CPU_TO_LE16(access); 2580 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 2581 2582 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2583 /* The completion specifies the maximum time in ms that the driver 2584 * may hold the resource in the Timeout field. 2585 * If the resource is held by someone else, the command completes with 2586 * busy return value and the timeout field indicates the maximum time 2587 * the current owner of the resource has to free it. 2588 */ 2589 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2590 *timeout = LE32_TO_CPU(cmd_resp->timeout); 2591 2592 return status; 2593 } 2594 2595 /** 2596 * i40e_aq_release_resource 2597 * @hw: pointer to the hw struct 2598 * @resource: resource id 2599 * @sdp_number: resource number 2600 * @cmd_details: pointer to command details structure or NULL 2601 * 2602 * release common resource using the admin queue commands 2603 **/ 2604 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 2605 enum i40e_aq_resources_ids resource, 2606 u8 sdp_number, 2607 struct i40e_asq_cmd_details *cmd_details) 2608 { 2609 struct i40e_aq_desc desc; 2610 struct i40e_aqc_request_resource *cmd = 2611 (struct i40e_aqc_request_resource *)&desc.params.raw; 2612 enum i40e_status_code status; 2613 2614 DEBUGFUNC("i40e_aq_release_resource"); 2615 2616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2617 2618 cmd->resource_id = CPU_TO_LE16(resource); 2619 cmd->resource_number = CPU_TO_LE32(sdp_number); 2620 2621 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2622 2623 return status; 2624 } 2625 2626 /** 2627 * i40e_aq_read_nvm 2628 * @hw: pointer to the hw struct 2629 * @module_pointer: module pointer location in words from the NVM beginning 2630 * @offset: byte offset from the module beginning 2631 * @length: length of the section to be read (in bytes from the offset) 2632 * @data: command buffer (size [bytes] = length) 2633 * @last_command: tells if this is the last command in a series 2634 * @cmd_details: pointer to command details structure or NULL 2635 * 2636 * Read the NVM using the admin queue commands 2637 **/ 2638 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2639 u32 offset, u16 length, void *data, 2640 bool last_command, 2641 struct i40e_asq_cmd_details *cmd_details) 2642 { 2643 struct i40e_aq_desc desc; 2644 struct i40e_aqc_nvm_update *cmd = 2645 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2646 enum i40e_status_code status; 2647 2648 DEBUGFUNC("i40e_aq_read_nvm"); 2649 2650 /* In offset the highest byte must be zeroed. */ 2651 if (offset & 0xFF000000) { 2652 status = I40E_ERR_PARAM; 2653 goto i40e_aq_read_nvm_exit; 2654 } 2655 2656 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2657 2658 /* If this is the last command in a series, set the proper flag. */ 2659 if (last_command) 2660 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2661 cmd->module_pointer = module_pointer; 2662 cmd->offset = CPU_TO_LE32(offset); 2663 cmd->length = CPU_TO_LE16(length); 2664 2665 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2666 if (length > I40E_AQ_LARGE_BUF) 2667 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2668 2669 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2670 2671 i40e_aq_read_nvm_exit: 2672 return status; 2673 } 2674 2675 /** 2676 * i40e_aq_read_nvm_config - read an nvm config block 2677 * @hw: pointer to the hw struct 2678 * @cmd_flags: NVM access admin command bits 2679 * @field_id: field or feature id 2680 * @data: buffer for result 2681 * @buf_size: buffer size 2682 * @element_count: pointer to count of elements read by FW 2683 * @cmd_details: pointer to command details structure or NULL 2684 **/ 2685 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 2686 u8 cmd_flags, u32 field_id, void *data, 2687 u16 buf_size, u16 *element_count, 2688 struct i40e_asq_cmd_details *cmd_details) 2689 { 2690 struct i40e_aq_desc desc; 2691 struct i40e_aqc_nvm_config_read *cmd = 2692 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 2693 enum i40e_status_code status; 2694 2695 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 2696 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 2697 if (buf_size > I40E_AQ_LARGE_BUF) 2698 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2699 2700 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 2701 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 2702 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 2703 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 2704 else 2705 cmd->element_id_msw = 0; 2706 2707 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 2708 2709 if (!status && element_count) 2710 *element_count = LE16_TO_CPU(cmd->element_count); 2711 2712 return status; 2713 } 2714 2715 /** 2716 * i40e_aq_write_nvm_config - write an nvm config block 2717 * @hw: pointer to the hw struct 2718 * @cmd_flags: NVM access admin command bits 2719 * @data: buffer for result 2720 * @buf_size: buffer size 2721 * @element_count: count of elements to be written 2722 * @cmd_details: pointer to command details structure or NULL 2723 **/ 2724 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 2725 u8 cmd_flags, void *data, u16 buf_size, 2726 u16 element_count, 2727 struct i40e_asq_cmd_details *cmd_details) 2728 { 2729 struct i40e_aq_desc desc; 2730 struct i40e_aqc_nvm_config_write *cmd = 2731 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 2732 enum i40e_status_code status; 2733 2734 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 2735 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2736 if (buf_size > I40E_AQ_LARGE_BUF) 2737 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2738 2739 cmd->element_count = CPU_TO_LE16(element_count); 2740 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 2741 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 2742 2743 return status; 2744 } 2745 2746 /** 2747 * i40e_aq_erase_nvm 2748 * @hw: pointer to the hw struct 2749 * @module_pointer: module pointer location in words from the NVM beginning 2750 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2751 * @length: length of the section to be erased (expressed in 4 KB) 2752 * @last_command: tells if this is the last command in a series 2753 * @cmd_details: pointer to command details structure or NULL 2754 * 2755 * Erase the NVM sector using the admin queue commands 2756 **/ 2757 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2758 u32 offset, u16 length, bool last_command, 2759 struct i40e_asq_cmd_details *cmd_details) 2760 { 2761 struct i40e_aq_desc desc; 2762 struct i40e_aqc_nvm_update *cmd = 2763 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2764 enum i40e_status_code status; 2765 2766 DEBUGFUNC("i40e_aq_erase_nvm"); 2767 2768 /* In offset the highest byte must be zeroed. */ 2769 if (offset & 0xFF000000) { 2770 status = I40E_ERR_PARAM; 2771 goto i40e_aq_erase_nvm_exit; 2772 } 2773 2774 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2775 2776 /* If this is the last command in a series, set the proper flag. */ 2777 if (last_command) 2778 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2779 cmd->module_pointer = module_pointer; 2780 cmd->offset = CPU_TO_LE32(offset); 2781 cmd->length = CPU_TO_LE16(length); 2782 2783 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2784 2785 i40e_aq_erase_nvm_exit: 2786 return status; 2787 } 2788 2789 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 2790 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 2791 #define I40E_DEV_FUNC_CAP_NPAR 0x03 2792 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04 2793 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 2794 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 2795 #define I40E_DEV_FUNC_CAP_VF 0x13 2796 #define I40E_DEV_FUNC_CAP_VMDQ 0x14 2797 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 2798 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 2799 #define I40E_DEV_FUNC_CAP_VSI 0x17 2800 #define I40E_DEV_FUNC_CAP_DCB 0x18 2801 #define I40E_DEV_FUNC_CAP_FCOE 0x21 2802 #define I40E_DEV_FUNC_CAP_ISCSI 0x22 2803 #define I40E_DEV_FUNC_CAP_RSS 0x40 2804 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 2805 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 2806 #define I40E_DEV_FUNC_CAP_MSIX 0x43 2807 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 2808 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 2809 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 2810 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1 2811 #define I40E_DEV_FUNC_CAP_CEM 0xF2 2812 #define I40E_DEV_FUNC_CAP_IWARP 0x51 2813 #define I40E_DEV_FUNC_CAP_LED 0x61 2814 #define I40E_DEV_FUNC_CAP_SDP 0x62 2815 #define I40E_DEV_FUNC_CAP_MDIO 0x63 2816 2817 /** 2818 * i40e_parse_discover_capabilities 2819 * @hw: pointer to the hw struct 2820 * @buff: pointer to a buffer containing device/function capability records 2821 * @cap_count: number of capability records in the list 2822 * @list_type_opc: type of capabilities list to parse 2823 * 2824 * Parse the device/function capabilities list. 2825 **/ 2826 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2827 u32 cap_count, 2828 enum i40e_admin_queue_opc list_type_opc) 2829 { 2830 struct i40e_aqc_list_capabilities_element_resp *cap; 2831 u32 valid_functions, num_functions; 2832 u32 number, logical_id, phys_id; 2833 struct i40e_hw_capabilities *p; 2834 u32 i = 0; 2835 u16 id; 2836 2837 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2838 2839 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2840 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 2841 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2842 p = (struct i40e_hw_capabilities *)&hw->func_caps; 2843 else 2844 return; 2845 2846 for (i = 0; i < cap_count; i++, cap++) { 2847 id = LE16_TO_CPU(cap->id); 2848 number = LE32_TO_CPU(cap->number); 2849 logical_id = LE32_TO_CPU(cap->logical_id); 2850 phys_id = LE32_TO_CPU(cap->phys_id); 2851 2852 switch (id) { 2853 case I40E_DEV_FUNC_CAP_SWITCH_MODE: 2854 p->switch_mode = number; 2855 break; 2856 case I40E_DEV_FUNC_CAP_MGMT_MODE: 2857 p->management_mode = number; 2858 break; 2859 case I40E_DEV_FUNC_CAP_NPAR: 2860 p->npar_enable = number; 2861 break; 2862 case I40E_DEV_FUNC_CAP_OS2BMC: 2863 p->os2bmc = number; 2864 break; 2865 case I40E_DEV_FUNC_CAP_VALID_FUNC: 2866 p->valid_functions = number; 2867 break; 2868 case I40E_DEV_FUNC_CAP_SRIOV_1_1: 2869 if (number == 1) 2870 p->sr_iov_1_1 = TRUE; 2871 break; 2872 case I40E_DEV_FUNC_CAP_VF: 2873 p->num_vfs = number; 2874 p->vf_base_id = logical_id; 2875 break; 2876 case I40E_DEV_FUNC_CAP_VMDQ: 2877 if (number == 1) 2878 p->vmdq = TRUE; 2879 break; 2880 case I40E_DEV_FUNC_CAP_802_1_QBG: 2881 if (number == 1) 2882 p->evb_802_1_qbg = TRUE; 2883 break; 2884 case I40E_DEV_FUNC_CAP_802_1_QBH: 2885 if (number == 1) 2886 p->evb_802_1_qbh = TRUE; 2887 break; 2888 case I40E_DEV_FUNC_CAP_VSI: 2889 p->num_vsis = number; 2890 break; 2891 case I40E_DEV_FUNC_CAP_DCB: 2892 if (number == 1) { 2893 p->dcb = TRUE; 2894 p->enabled_tcmap = logical_id; 2895 p->maxtc = phys_id; 2896 } 2897 break; 2898 case I40E_DEV_FUNC_CAP_FCOE: 2899 if (number == 1) 2900 p->fcoe = TRUE; 2901 break; 2902 case I40E_DEV_FUNC_CAP_ISCSI: 2903 if (number == 1) 2904 p->iscsi = TRUE; 2905 break; 2906 case I40E_DEV_FUNC_CAP_RSS: 2907 p->rss = TRUE; 2908 p->rss_table_size = number; 2909 p->rss_table_entry_width = logical_id; 2910 break; 2911 case I40E_DEV_FUNC_CAP_RX_QUEUES: 2912 p->num_rx_qp = number; 2913 p->base_queue = phys_id; 2914 break; 2915 case I40E_DEV_FUNC_CAP_TX_QUEUES: 2916 p->num_tx_qp = number; 2917 p->base_queue = phys_id; 2918 break; 2919 case I40E_DEV_FUNC_CAP_MSIX: 2920 p->num_msix_vectors = number; 2921 break; 2922 case I40E_DEV_FUNC_CAP_MSIX_VF: 2923 p->num_msix_vectors_vf = number; 2924 break; 2925 case I40E_DEV_FUNC_CAP_MFP_MODE_1: 2926 if (number == 1) 2927 p->mfp_mode_1 = TRUE; 2928 break; 2929 case I40E_DEV_FUNC_CAP_CEM: 2930 if (number == 1) 2931 p->mgmt_cem = TRUE; 2932 break; 2933 case I40E_DEV_FUNC_CAP_IWARP: 2934 if (number == 1) 2935 p->iwarp = TRUE; 2936 break; 2937 case I40E_DEV_FUNC_CAP_LED: 2938 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2939 p->led[phys_id] = TRUE; 2940 break; 2941 case I40E_DEV_FUNC_CAP_SDP: 2942 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2943 p->sdp[phys_id] = TRUE; 2944 break; 2945 case I40E_DEV_FUNC_CAP_MDIO: 2946 if (number == 1) { 2947 p->mdio_port_num = phys_id; 2948 p->mdio_port_mode = logical_id; 2949 } 2950 break; 2951 case I40E_DEV_FUNC_CAP_IEEE_1588: 2952 if (number == 1) 2953 p->ieee_1588 = TRUE; 2954 break; 2955 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 2956 p->fd = TRUE; 2957 p->fd_filters_guaranteed = number; 2958 p->fd_filters_best_effort = logical_id; 2959 break; 2960 default: 2961 break; 2962 } 2963 } 2964 2965 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 2966 p->fcoe = FALSE; 2967 2968 /* count the enabled ports (aka the "not disabled" ports) */ 2969 hw->num_ports = 0; 2970 for (i = 0; i < 4; i++) { 2971 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 2972 u64 port_cfg = 0; 2973 2974 /* use AQ read to get the physical register offset instead 2975 * of the port relative offset 2976 */ 2977 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 2978 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 2979 hw->num_ports++; 2980 } 2981 2982 valid_functions = p->valid_functions; 2983 num_functions = 0; 2984 while (valid_functions) { 2985 if (valid_functions & 1) 2986 num_functions++; 2987 valid_functions >>= 1; 2988 } 2989 2990 /* partition id is 1-based, and functions are evenly spread 2991 * across the ports as partitions 2992 */ 2993 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 2994 hw->num_partitions = num_functions / hw->num_ports; 2995 2996 /* additional HW specific goodies that might 2997 * someday be HW version specific 2998 */ 2999 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3000 } 3001 3002 /** 3003 * i40e_aq_discover_capabilities 3004 * @hw: pointer to the hw struct 3005 * @buff: a virtual buffer to hold the capabilities 3006 * @buff_size: Size of the virtual buffer 3007 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3008 * @list_type_opc: capabilities type to discover - pass in the command opcode 3009 * @cmd_details: pointer to command details structure or NULL 3010 * 3011 * Get the device capabilities descriptions from the firmware 3012 **/ 3013 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3014 void *buff, u16 buff_size, u16 *data_size, 3015 enum i40e_admin_queue_opc list_type_opc, 3016 struct i40e_asq_cmd_details *cmd_details) 3017 { 3018 struct i40e_aqc_list_capabilites *cmd; 3019 struct i40e_aq_desc desc; 3020 enum i40e_status_code status = I40E_SUCCESS; 3021 3022 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3023 3024 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3025 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3026 status = I40E_ERR_PARAM; 3027 goto exit; 3028 } 3029 3030 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3031 3032 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3033 if (buff_size > I40E_AQ_LARGE_BUF) 3034 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3035 3036 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3037 *data_size = LE16_TO_CPU(desc.datalen); 3038 3039 if (status) 3040 goto exit; 3041 3042 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 3043 list_type_opc); 3044 3045 exit: 3046 return status; 3047 } 3048 3049 /** 3050 * i40e_aq_update_nvm 3051 * @hw: pointer to the hw struct 3052 * @module_pointer: module pointer location in words from the NVM beginning 3053 * @offset: byte offset from the module beginning 3054 * @length: length of the section to be written (in bytes from the offset) 3055 * @data: command buffer (size [bytes] = length) 3056 * @last_command: tells if this is the last command in a series 3057 * @cmd_details: pointer to command details structure or NULL 3058 * 3059 * Update the NVM using the admin queue commands 3060 **/ 3061 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3062 u32 offset, u16 length, void *data, 3063 bool last_command, 3064 struct i40e_asq_cmd_details *cmd_details) 3065 { 3066 struct i40e_aq_desc desc; 3067 struct i40e_aqc_nvm_update *cmd = 3068 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3069 enum i40e_status_code status; 3070 3071 DEBUGFUNC("i40e_aq_update_nvm"); 3072 3073 /* In offset the highest byte must be zeroed. */ 3074 if (offset & 0xFF000000) { 3075 status = I40E_ERR_PARAM; 3076 goto i40e_aq_update_nvm_exit; 3077 } 3078 3079 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3080 3081 /* If this is the last command in a series, set the proper flag. */ 3082 if (last_command) 3083 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3084 cmd->module_pointer = module_pointer; 3085 cmd->offset = CPU_TO_LE32(offset); 3086 cmd->length = CPU_TO_LE16(length); 3087 3088 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3089 if (length > I40E_AQ_LARGE_BUF) 3090 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3091 3092 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3093 3094 i40e_aq_update_nvm_exit: 3095 return status; 3096 } 3097 3098 /** 3099 * i40e_aq_get_lldp_mib 3100 * @hw: pointer to the hw struct 3101 * @bridge_type: type of bridge requested 3102 * @mib_type: Local, Remote or both Local and Remote MIBs 3103 * @buff: pointer to a user supplied buffer to store the MIB block 3104 * @buff_size: size of the buffer (in bytes) 3105 * @local_len : length of the returned Local LLDP MIB 3106 * @remote_len: length of the returned Remote LLDP MIB 3107 * @cmd_details: pointer to command details structure or NULL 3108 * 3109 * Requests the complete LLDP MIB (entire packet). 3110 **/ 3111 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3112 u8 mib_type, void *buff, u16 buff_size, 3113 u16 *local_len, u16 *remote_len, 3114 struct i40e_asq_cmd_details *cmd_details) 3115 { 3116 struct i40e_aq_desc desc; 3117 struct i40e_aqc_lldp_get_mib *cmd = 3118 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3119 struct i40e_aqc_lldp_get_mib *resp = 3120 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3121 enum i40e_status_code status; 3122 3123 if (buff_size == 0 || !buff) 3124 return I40E_ERR_PARAM; 3125 3126 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3127 /* Indirect Command */ 3128 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3129 3130 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3131 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3132 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3133 3134 desc.datalen = CPU_TO_LE16(buff_size); 3135 3136 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3137 if (buff_size > I40E_AQ_LARGE_BUF) 3138 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3139 3140 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3141 if (!status) { 3142 if (local_len != NULL) 3143 *local_len = LE16_TO_CPU(resp->local_len); 3144 if (remote_len != NULL) 3145 *remote_len = LE16_TO_CPU(resp->remote_len); 3146 } 3147 3148 return status; 3149 } 3150 3151 /** 3152 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3153 * @hw: pointer to the hw struct 3154 * @mib_type: Local, Remote or both Local and Remote MIBs 3155 * @buff: pointer to a user supplied buffer to store the MIB block 3156 * @buff_size: size of the buffer (in bytes) 3157 * @cmd_details: pointer to command details structure or NULL 3158 * 3159 * Set the LLDP MIB. 3160 **/ 3161 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3162 u8 mib_type, void *buff, u16 buff_size, 3163 struct i40e_asq_cmd_details *cmd_details) 3164 { 3165 struct i40e_aq_desc desc; 3166 struct i40e_aqc_lldp_set_local_mib *cmd = 3167 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 3168 enum i40e_status_code status; 3169 3170 if (buff_size == 0 || !buff) 3171 return I40E_ERR_PARAM; 3172 3173 i40e_fill_default_direct_cmd_desc(&desc, 3174 i40e_aqc_opc_lldp_set_local_mib); 3175 /* Indirect Command */ 3176 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3177 if (buff_size > I40E_AQ_LARGE_BUF) 3178 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3179 desc.datalen = CPU_TO_LE16(buff_size); 3180 3181 cmd->type = mib_type; 3182 cmd->length = CPU_TO_LE16(buff_size); 3183 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff)); 3184 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 3185 3186 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3187 return status; 3188 } 3189 3190 /** 3191 * i40e_aq_cfg_lldp_mib_change_event 3192 * @hw: pointer to the hw struct 3193 * @enable_update: Enable or Disable event posting 3194 * @cmd_details: pointer to command details structure or NULL 3195 * 3196 * Enable or Disable posting of an event on ARQ when LLDP MIB 3197 * associated with the interface changes 3198 **/ 3199 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3200 bool enable_update, 3201 struct i40e_asq_cmd_details *cmd_details) 3202 { 3203 struct i40e_aq_desc desc; 3204 struct i40e_aqc_lldp_update_mib *cmd = 3205 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3206 enum i40e_status_code status; 3207 3208 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3209 3210 if (!enable_update) 3211 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3212 3213 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3214 3215 return status; 3216 } 3217 3218 /** 3219 * i40e_aq_add_lldp_tlv 3220 * @hw: pointer to the hw struct 3221 * @bridge_type: type of bridge 3222 * @buff: buffer with TLV to add 3223 * @buff_size: length of the buffer 3224 * @tlv_len: length of the TLV to be added 3225 * @mib_len: length of the LLDP MIB returned in response 3226 * @cmd_details: pointer to command details structure or NULL 3227 * 3228 * Add the specified TLV to LLDP Local MIB for the given bridge type, 3229 * it is responsibility of the caller to make sure that the TLV is not 3230 * already present in the LLDPDU. 3231 * In return firmware will write the complete LLDP MIB with the newly 3232 * added TLV in the response buffer. 3233 **/ 3234 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 3235 void *buff, u16 buff_size, u16 tlv_len, 3236 u16 *mib_len, 3237 struct i40e_asq_cmd_details *cmd_details) 3238 { 3239 struct i40e_aq_desc desc; 3240 struct i40e_aqc_lldp_add_tlv *cmd = 3241 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3242 enum i40e_status_code status; 3243 3244 if (buff_size == 0 || !buff || tlv_len == 0) 3245 return I40E_ERR_PARAM; 3246 3247 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 3248 3249 /* Indirect Command */ 3250 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3251 if (buff_size > I40E_AQ_LARGE_BUF) 3252 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3253 desc.datalen = CPU_TO_LE16(buff_size); 3254 3255 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3256 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3257 cmd->len = CPU_TO_LE16(tlv_len); 3258 3259 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3260 if (!status) { 3261 if (mib_len != NULL) 3262 *mib_len = LE16_TO_CPU(desc.datalen); 3263 } 3264 3265 return status; 3266 } 3267 3268 /** 3269 * i40e_aq_update_lldp_tlv 3270 * @hw: pointer to the hw struct 3271 * @bridge_type: type of bridge 3272 * @buff: buffer with TLV to update 3273 * @buff_size: size of the buffer holding original and updated TLVs 3274 * @old_len: Length of the Original TLV 3275 * @new_len: Length of the Updated TLV 3276 * @offset: offset of the updated TLV in the buff 3277 * @mib_len: length of the returned LLDP MIB 3278 * @cmd_details: pointer to command details structure or NULL 3279 * 3280 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 3281 * Firmware will place the complete LLDP MIB in response buffer with the 3282 * updated TLV. 3283 **/ 3284 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 3285 u8 bridge_type, void *buff, u16 buff_size, 3286 u16 old_len, u16 new_len, u16 offset, 3287 u16 *mib_len, 3288 struct i40e_asq_cmd_details *cmd_details) 3289 { 3290 struct i40e_aq_desc desc; 3291 struct i40e_aqc_lldp_update_tlv *cmd = 3292 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 3293 enum i40e_status_code status; 3294 3295 if (buff_size == 0 || !buff || offset == 0 || 3296 old_len == 0 || new_len == 0) 3297 return I40E_ERR_PARAM; 3298 3299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 3300 3301 /* Indirect Command */ 3302 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3303 if (buff_size > I40E_AQ_LARGE_BUF) 3304 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3305 desc.datalen = CPU_TO_LE16(buff_size); 3306 3307 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3308 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3309 cmd->old_len = CPU_TO_LE16(old_len); 3310 cmd->new_offset = CPU_TO_LE16(offset); 3311 cmd->new_len = CPU_TO_LE16(new_len); 3312 3313 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3314 if (!status) { 3315 if (mib_len != NULL) 3316 *mib_len = LE16_TO_CPU(desc.datalen); 3317 } 3318 3319 return status; 3320 } 3321 3322 /** 3323 * i40e_aq_delete_lldp_tlv 3324 * @hw: pointer to the hw struct 3325 * @bridge_type: type of bridge 3326 * @buff: pointer to a user supplied buffer that has the TLV 3327 * @buff_size: length of the buffer 3328 * @tlv_len: length of the TLV to be deleted 3329 * @mib_len: length of the returned LLDP MIB 3330 * @cmd_details: pointer to command details structure or NULL 3331 * 3332 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 3333 * The firmware places the entire LLDP MIB in the response buffer. 3334 **/ 3335 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 3336 u8 bridge_type, void *buff, u16 buff_size, 3337 u16 tlv_len, u16 *mib_len, 3338 struct i40e_asq_cmd_details *cmd_details) 3339 { 3340 struct i40e_aq_desc desc; 3341 struct i40e_aqc_lldp_add_tlv *cmd = 3342 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3343 enum i40e_status_code status; 3344 3345 if (buff_size == 0 || !buff) 3346 return I40E_ERR_PARAM; 3347 3348 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 3349 3350 /* Indirect Command */ 3351 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3352 if (buff_size > I40E_AQ_LARGE_BUF) 3353 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3354 desc.datalen = CPU_TO_LE16(buff_size); 3355 cmd->len = CPU_TO_LE16(tlv_len); 3356 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3357 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3358 3359 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3360 if (!status) { 3361 if (mib_len != NULL) 3362 *mib_len = LE16_TO_CPU(desc.datalen); 3363 } 3364 3365 return status; 3366 } 3367 3368 /** 3369 * i40e_aq_stop_lldp 3370 * @hw: pointer to the hw struct 3371 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3372 * @cmd_details: pointer to command details structure or NULL 3373 * 3374 * Stop or Shutdown the embedded LLDP Agent 3375 **/ 3376 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3377 struct i40e_asq_cmd_details *cmd_details) 3378 { 3379 struct i40e_aq_desc desc; 3380 struct i40e_aqc_lldp_stop *cmd = 3381 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3382 enum i40e_status_code status; 3383 3384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3385 3386 if (shutdown_agent) 3387 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3388 3389 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3390 3391 return status; 3392 } 3393 3394 /** 3395 * i40e_aq_start_lldp 3396 * @hw: pointer to the hw struct 3397 * @cmd_details: pointer to command details structure or NULL 3398 * 3399 * Start the embedded LLDP Agent on all ports. 3400 **/ 3401 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 3402 struct i40e_asq_cmd_details *cmd_details) 3403 { 3404 struct i40e_aq_desc desc; 3405 struct i40e_aqc_lldp_start *cmd = 3406 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3407 enum i40e_status_code status; 3408 3409 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3410 3411 cmd->command = I40E_AQ_LLDP_AGENT_START; 3412 3413 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3414 3415 return status; 3416 } 3417 3418 /** 3419 * i40e_aq_get_cee_dcb_config 3420 * @hw: pointer to the hw struct 3421 * @buff: response buffer that stores CEE operational configuration 3422 * @buff_size: size of the buffer passed 3423 * @cmd_details: pointer to command details structure or NULL 3424 * 3425 * Get CEE DCBX mode operational configuration from firmware 3426 **/ 3427 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3428 void *buff, u16 buff_size, 3429 struct i40e_asq_cmd_details *cmd_details) 3430 { 3431 struct i40e_aq_desc desc; 3432 enum i40e_status_code status; 3433 3434 if (buff_size == 0 || !buff) 3435 return I40E_ERR_PARAM; 3436 3437 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3438 3439 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3440 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3441 cmd_details); 3442 3443 return status; 3444 } 3445 3446 /** 3447 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 3448 * @hw: pointer to the hw struct 3449 * @start_agent: True if DCBx Agent needs to be Started 3450 * False if DCBx Agent needs to be Stopped 3451 * @cmd_details: pointer to command details structure or NULL 3452 * 3453 * Start/Stop the embedded dcbx Agent 3454 **/ 3455 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 3456 bool start_agent, 3457 struct i40e_asq_cmd_details *cmd_details) 3458 { 3459 struct i40e_aq_desc desc; 3460 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 3461 (struct i40e_aqc_lldp_stop_start_specific_agent *) 3462 &desc.params.raw; 3463 enum i40e_status_code status; 3464 3465 i40e_fill_default_direct_cmd_desc(&desc, 3466 i40e_aqc_opc_lldp_stop_start_spec_agent); 3467 3468 if (start_agent) 3469 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 3470 3471 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3472 3473 return status; 3474 } 3475 3476 /** 3477 * i40e_aq_add_udp_tunnel 3478 * @hw: pointer to the hw struct 3479 * @udp_port: the UDP port to add 3480 * @header_len: length of the tunneling header length in DWords 3481 * @protocol_index: protocol index type 3482 * @filter_index: pointer to filter index 3483 * @cmd_details: pointer to command details structure or NULL 3484 **/ 3485 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3486 u16 udp_port, u8 protocol_index, 3487 u8 *filter_index, 3488 struct i40e_asq_cmd_details *cmd_details) 3489 { 3490 struct i40e_aq_desc desc; 3491 struct i40e_aqc_add_udp_tunnel *cmd = 3492 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3493 struct i40e_aqc_del_udp_tunnel_completion *resp = 3494 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3495 enum i40e_status_code status; 3496 3497 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3498 3499 cmd->udp_port = CPU_TO_LE16(udp_port); 3500 cmd->protocol_type = protocol_index; 3501 3502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3503 3504 if (!status && filter_index) 3505 *filter_index = resp->index; 3506 3507 return status; 3508 } 3509 3510 /** 3511 * i40e_aq_del_udp_tunnel 3512 * @hw: pointer to the hw struct 3513 * @index: filter index 3514 * @cmd_details: pointer to command details structure or NULL 3515 **/ 3516 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3517 struct i40e_asq_cmd_details *cmd_details) 3518 { 3519 struct i40e_aq_desc desc; 3520 struct i40e_aqc_remove_udp_tunnel *cmd = 3521 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3522 enum i40e_status_code status; 3523 3524 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3525 3526 cmd->index = index; 3527 3528 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3529 3530 return status; 3531 } 3532 3533 /** 3534 * i40e_aq_get_switch_resource_alloc (0x0204) 3535 * @hw: pointer to the hw struct 3536 * @num_entries: pointer to u8 to store the number of resource entries returned 3537 * @buf: pointer to a user supplied buffer. This buffer must be large enough 3538 * to store the resource information for all resource types. Each 3539 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 3540 * @count: size, in bytes, of the buffer provided 3541 * @cmd_details: pointer to command details structure or NULL 3542 * 3543 * Query the resources allocated to a function. 3544 **/ 3545 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 3546 u8 *num_entries, 3547 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 3548 u16 count, 3549 struct i40e_asq_cmd_details *cmd_details) 3550 { 3551 struct i40e_aq_desc desc; 3552 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 3553 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 3554 enum i40e_status_code status; 3555 u16 length = count * sizeof(*buf); 3556 3557 i40e_fill_default_direct_cmd_desc(&desc, 3558 i40e_aqc_opc_get_switch_resource_alloc); 3559 3560 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3561 if (length > I40E_AQ_LARGE_BUF) 3562 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3563 3564 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 3565 3566 if (!status && num_entries) 3567 *num_entries = cmd_resp->num_entries; 3568 3569 return status; 3570 } 3571 3572 /** 3573 * i40e_aq_delete_element - Delete switch element 3574 * @hw: pointer to the hw struct 3575 * @seid: the SEID to delete from the switch 3576 * @cmd_details: pointer to command details structure or NULL 3577 * 3578 * This deletes a switch element from the switch. 3579 **/ 3580 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3581 struct i40e_asq_cmd_details *cmd_details) 3582 { 3583 struct i40e_aq_desc desc; 3584 struct i40e_aqc_switch_seid *cmd = 3585 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3586 enum i40e_status_code status; 3587 3588 if (seid == 0) 3589 return I40E_ERR_PARAM; 3590 3591 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3592 3593 cmd->seid = CPU_TO_LE16(seid); 3594 3595 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3596 3597 return status; 3598 } 3599 3600 /** 3601 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port 3602 * @hw: pointer to the hw struct 3603 * @flags: component flags 3604 * @mac_seid: uplink seid (MAC SEID) 3605 * @vsi_seid: connected vsi seid 3606 * @ret_seid: seid of create pv component 3607 * 3608 * This instantiates an i40e port virtualizer with specified flags. 3609 * Depending on specified flags the port virtualizer can act as a 3610 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 3611 */ 3612 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 3613 u16 mac_seid, u16 vsi_seid, 3614 u16 *ret_seid) 3615 { 3616 struct i40e_aq_desc desc; 3617 struct i40e_aqc_add_update_pv *cmd = 3618 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 3619 struct i40e_aqc_add_update_pv_completion *resp = 3620 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 3621 enum i40e_status_code status; 3622 3623 if (vsi_seid == 0) 3624 return I40E_ERR_PARAM; 3625 3626 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 3627 cmd->command_flags = CPU_TO_LE16(flags); 3628 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 3629 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 3630 3631 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3632 if (!status && ret_seid) 3633 *ret_seid = LE16_TO_CPU(resp->pv_seid); 3634 3635 return status; 3636 } 3637 3638 /** 3639 * i40e_aq_add_tag - Add an S/E-tag 3640 * @hw: pointer to the hw struct 3641 * @direct_to_queue: should s-tag direct flow to a specific queue 3642 * @vsi_seid: VSI SEID to use this tag 3643 * @tag: value of the tag 3644 * @queue_num: queue number, only valid is direct_to_queue is TRUE 3645 * @tags_used: return value, number of tags in use by this PF 3646 * @tags_free: return value, number of unallocated tags 3647 * @cmd_details: pointer to command details structure or NULL 3648 * 3649 * This associates an S- or E-tag to a VSI in the switch complex. It returns 3650 * the number of tags allocated by the PF, and the number of unallocated 3651 * tags available. 3652 **/ 3653 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 3654 u16 vsi_seid, u16 tag, u16 queue_num, 3655 u16 *tags_used, u16 *tags_free, 3656 struct i40e_asq_cmd_details *cmd_details) 3657 { 3658 struct i40e_aq_desc desc; 3659 struct i40e_aqc_add_tag *cmd = 3660 (struct i40e_aqc_add_tag *)&desc.params.raw; 3661 struct i40e_aqc_add_remove_tag_completion *resp = 3662 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 3663 enum i40e_status_code status; 3664 3665 if (vsi_seid == 0) 3666 return I40E_ERR_PARAM; 3667 3668 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 3669 3670 cmd->seid = CPU_TO_LE16(vsi_seid); 3671 cmd->tag = CPU_TO_LE16(tag); 3672 if (direct_to_queue) { 3673 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 3674 cmd->queue_number = CPU_TO_LE16(queue_num); 3675 } 3676 3677 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3678 3679 if (!status) { 3680 if (tags_used != NULL) 3681 *tags_used = LE16_TO_CPU(resp->tags_used); 3682 if (tags_free != NULL) 3683 *tags_free = LE16_TO_CPU(resp->tags_free); 3684 } 3685 3686 return status; 3687 } 3688 3689 /** 3690 * i40e_aq_remove_tag - Remove an S- or E-tag 3691 * @hw: pointer to the hw struct 3692 * @vsi_seid: VSI SEID this tag is associated with 3693 * @tag: value of the S-tag to delete 3694 * @tags_used: return value, number of tags in use by this PF 3695 * @tags_free: return value, number of unallocated tags 3696 * @cmd_details: pointer to command details structure or NULL 3697 * 3698 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 3699 * the number of tags allocated by the PF, and the number of unallocated 3700 * tags available. 3701 **/ 3702 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 3703 u16 tag, u16 *tags_used, u16 *tags_free, 3704 struct i40e_asq_cmd_details *cmd_details) 3705 { 3706 struct i40e_aq_desc desc; 3707 struct i40e_aqc_remove_tag *cmd = 3708 (struct i40e_aqc_remove_tag *)&desc.params.raw; 3709 struct i40e_aqc_add_remove_tag_completion *resp = 3710 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 3711 enum i40e_status_code status; 3712 3713 if (vsi_seid == 0) 3714 return I40E_ERR_PARAM; 3715 3716 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 3717 3718 cmd->seid = CPU_TO_LE16(vsi_seid); 3719 cmd->tag = CPU_TO_LE16(tag); 3720 3721 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3722 3723 if (!status) { 3724 if (tags_used != NULL) 3725 *tags_used = LE16_TO_CPU(resp->tags_used); 3726 if (tags_free != NULL) 3727 *tags_free = LE16_TO_CPU(resp->tags_free); 3728 } 3729 3730 return status; 3731 } 3732 3733 /** 3734 * i40e_aq_add_mcast_etag - Add a multicast E-tag 3735 * @hw: pointer to the hw struct 3736 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 3737 * @etag: value of E-tag to add 3738 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 3739 * @buf: address of indirect buffer 3740 * @tags_used: return value, number of E-tags in use by this port 3741 * @tags_free: return value, number of unallocated M-tags 3742 * @cmd_details: pointer to command details structure or NULL 3743 * 3744 * This associates a multicast E-tag to a port virtualizer. It will return 3745 * the number of tags allocated by the PF, and the number of unallocated 3746 * tags available. 3747 * 3748 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 3749 * num_tags_in_buf long. 3750 **/ 3751 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 3752 u16 etag, u8 num_tags_in_buf, void *buf, 3753 u16 *tags_used, u16 *tags_free, 3754 struct i40e_asq_cmd_details *cmd_details) 3755 { 3756 struct i40e_aq_desc desc; 3757 struct i40e_aqc_add_remove_mcast_etag *cmd = 3758 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 3759 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 3760 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 3761 enum i40e_status_code status; 3762 u16 length = sizeof(u16) * num_tags_in_buf; 3763 3764 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 3765 return I40E_ERR_PARAM; 3766 3767 i40e_fill_default_direct_cmd_desc(&desc, 3768 i40e_aqc_opc_add_multicast_etag); 3769 3770 cmd->pv_seid = CPU_TO_LE16(pv_seid); 3771 cmd->etag = CPU_TO_LE16(etag); 3772 cmd->num_unicast_etags = num_tags_in_buf; 3773 3774 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3775 if (length > I40E_AQ_LARGE_BUF) 3776 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3777 3778 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 3779 3780 if (!status) { 3781 if (tags_used != NULL) 3782 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 3783 if (tags_free != NULL) 3784 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 3785 } 3786 3787 return status; 3788 } 3789 3790 /** 3791 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 3792 * @hw: pointer to the hw struct 3793 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 3794 * @etag: value of the E-tag to remove 3795 * @tags_used: return value, number of tags in use by this port 3796 * @tags_free: return value, number of unallocated tags 3797 * @cmd_details: pointer to command details structure or NULL 3798 * 3799 * This deletes an E-tag from the port virtualizer. It will return 3800 * the number of tags allocated by the port, and the number of unallocated 3801 * tags available. 3802 **/ 3803 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 3804 u16 etag, u16 *tags_used, u16 *tags_free, 3805 struct i40e_asq_cmd_details *cmd_details) 3806 { 3807 struct i40e_aq_desc desc; 3808 struct i40e_aqc_add_remove_mcast_etag *cmd = 3809 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 3810 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 3811 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 3812 enum i40e_status_code status; 3813 3814 3815 if (pv_seid == 0) 3816 return I40E_ERR_PARAM; 3817 3818 i40e_fill_default_direct_cmd_desc(&desc, 3819 i40e_aqc_opc_remove_multicast_etag); 3820 3821 cmd->pv_seid = CPU_TO_LE16(pv_seid); 3822 cmd->etag = CPU_TO_LE16(etag); 3823 3824 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3825 3826 if (!status) { 3827 if (tags_used != NULL) 3828 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 3829 if (tags_free != NULL) 3830 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 3831 } 3832 3833 return status; 3834 } 3835 3836 /** 3837 * i40e_aq_update_tag - Update an S/E-tag 3838 * @hw: pointer to the hw struct 3839 * @vsi_seid: VSI SEID using this S-tag 3840 * @old_tag: old tag value 3841 * @new_tag: new tag value 3842 * @tags_used: return value, number of tags in use by this PF 3843 * @tags_free: return value, number of unallocated tags 3844 * @cmd_details: pointer to command details structure or NULL 3845 * 3846 * This updates the value of the tag currently attached to this VSI 3847 * in the switch complex. It will return the number of tags allocated 3848 * by the PF, and the number of unallocated tags available. 3849 **/ 3850 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 3851 u16 old_tag, u16 new_tag, u16 *tags_used, 3852 u16 *tags_free, 3853 struct i40e_asq_cmd_details *cmd_details) 3854 { 3855 struct i40e_aq_desc desc; 3856 struct i40e_aqc_update_tag *cmd = 3857 (struct i40e_aqc_update_tag *)&desc.params.raw; 3858 struct i40e_aqc_update_tag_completion *resp = 3859 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 3860 enum i40e_status_code status; 3861 3862 if (vsi_seid == 0) 3863 return I40E_ERR_PARAM; 3864 3865 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 3866 3867 cmd->seid = CPU_TO_LE16(vsi_seid); 3868 cmd->old_tag = CPU_TO_LE16(old_tag); 3869 cmd->new_tag = CPU_TO_LE16(new_tag); 3870 3871 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3872 3873 if (!status) { 3874 if (tags_used != NULL) 3875 *tags_used = LE16_TO_CPU(resp->tags_used); 3876 if (tags_free != NULL) 3877 *tags_free = LE16_TO_CPU(resp->tags_free); 3878 } 3879 3880 return status; 3881 } 3882 3883 /** 3884 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 3885 * @hw: pointer to the hw struct 3886 * @tcmap: TC map for request/release any ignore PFC condition 3887 * @request: request or release ignore PFC condition 3888 * @tcmap_ret: return TCs for which PFC is currently ignored 3889 * @cmd_details: pointer to command details structure or NULL 3890 * 3891 * This sends out request/release to ignore PFC condition for a TC. 3892 * It will return the TCs for which PFC is currently ignored. 3893 **/ 3894 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 3895 bool request, u8 *tcmap_ret, 3896 struct i40e_asq_cmd_details *cmd_details) 3897 { 3898 struct i40e_aq_desc desc; 3899 struct i40e_aqc_pfc_ignore *cmd_resp = 3900 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 3901 enum i40e_status_code status; 3902 3903 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 3904 3905 if (request) 3906 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 3907 3908 cmd_resp->tc_bitmap = tcmap; 3909 3910 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3911 3912 if (!status) { 3913 if (tcmap_ret != NULL) 3914 *tcmap_ret = cmd_resp->tc_bitmap; 3915 } 3916 3917 return status; 3918 } 3919 3920 /** 3921 * i40e_aq_dcb_updated - DCB Updated Command 3922 * @hw: pointer to the hw struct 3923 * @cmd_details: pointer to command details structure or NULL 3924 * 3925 * When LLDP is handled in PF this command is used by the PF 3926 * to notify EMP that a DCB setting is modified. 3927 * When LLDP is handled in EMP this command is used by the PF 3928 * to notify EMP whenever one of the following parameters get 3929 * modified: 3930 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 3931 * - PCIRTT in PRTDCB_GENC.PCIRTT 3932 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 3933 * EMP will return when the shared RPB settings have been 3934 * recomputed and modified. The retval field in the descriptor 3935 * will be set to 0 when RPB is modified. 3936 **/ 3937 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 3938 struct i40e_asq_cmd_details *cmd_details) 3939 { 3940 struct i40e_aq_desc desc; 3941 enum i40e_status_code status; 3942 3943 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3944 3945 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3946 3947 return status; 3948 } 3949 3950 /** 3951 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 3952 * @hw: pointer to the hw struct 3953 * @seid: defines the SEID of the switch for which the stats are requested 3954 * @vlan_id: the VLAN ID for which the statistics are requested 3955 * @stat_index: index of the statistics counters block assigned to this VLAN 3956 * @cmd_details: pointer to command details structure or NULL 3957 * 3958 * XL710 supports 128 smonVlanStats counters.This command is used to 3959 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 3960 * switch. 3961 **/ 3962 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 3963 u16 vlan_id, u16 *stat_index, 3964 struct i40e_asq_cmd_details *cmd_details) 3965 { 3966 struct i40e_aq_desc desc; 3967 struct i40e_aqc_add_remove_statistics *cmd_resp = 3968 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 3969 enum i40e_status_code status; 3970 3971 if ((seid == 0) || (stat_index == NULL)) 3972 return I40E_ERR_PARAM; 3973 3974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 3975 3976 cmd_resp->seid = CPU_TO_LE16(seid); 3977 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 3978 3979 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3980 3981 if (!status && stat_index) 3982 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 3983 3984 return status; 3985 } 3986 3987 /** 3988 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 3989 * @hw: pointer to the hw struct 3990 * @seid: defines the SEID of the switch for which the stats are requested 3991 * @vlan_id: the VLAN ID for which the statistics are requested 3992 * @stat_index: index of the statistics counters block assigned to this VLAN 3993 * @cmd_details: pointer to command details structure or NULL 3994 * 3995 * XL710 supports 128 smonVlanStats counters.This command is used to 3996 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 3997 * switch. 3998 **/ 3999 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 4000 u16 vlan_id, u16 stat_index, 4001 struct i40e_asq_cmd_details *cmd_details) 4002 { 4003 struct i40e_aq_desc desc; 4004 struct i40e_aqc_add_remove_statistics *cmd = 4005 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4006 enum i40e_status_code status; 4007 4008 if (seid == 0) 4009 return I40E_ERR_PARAM; 4010 4011 i40e_fill_default_direct_cmd_desc(&desc, 4012 i40e_aqc_opc_remove_statistics); 4013 4014 cmd->seid = CPU_TO_LE16(seid); 4015 cmd->vlan = CPU_TO_LE16(vlan_id); 4016 cmd->stat_index = CPU_TO_LE16(stat_index); 4017 4018 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4019 4020 return status; 4021 } 4022 4023 /** 4024 * i40e_aq_set_port_parameters - set physical port parameters. 4025 * @hw: pointer to the hw struct 4026 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 4027 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 4028 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 4029 * @double_vlan: if set double VLAN is enabled 4030 * @cmd_details: pointer to command details structure or NULL 4031 **/ 4032 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 4033 u16 bad_frame_vsi, bool save_bad_pac, 4034 bool pad_short_pac, bool double_vlan, 4035 struct i40e_asq_cmd_details *cmd_details) 4036 { 4037 struct i40e_aqc_set_port_parameters *cmd; 4038 enum i40e_status_code status; 4039 struct i40e_aq_desc desc; 4040 u16 command_flags = 0; 4041 4042 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 4043 4044 i40e_fill_default_direct_cmd_desc(&desc, 4045 i40e_aqc_opc_set_port_parameters); 4046 4047 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 4048 if (save_bad_pac) 4049 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 4050 if (pad_short_pac) 4051 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 4052 if (double_vlan) 4053 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 4054 cmd->command_flags = CPU_TO_LE16(command_flags); 4055 4056 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4057 4058 return status; 4059 } 4060 4061 /** 4062 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 4063 * @hw: pointer to the hw struct 4064 * @seid: seid for the physical port/switching component/vsi 4065 * @buff: Indirect buffer to hold data parameters and response 4066 * @buff_size: Indirect buffer size 4067 * @opcode: Tx scheduler AQ command opcode 4068 * @cmd_details: pointer to command details structure or NULL 4069 * 4070 * Generic command handler for Tx scheduler AQ commands 4071 **/ 4072 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 4073 void *buff, u16 buff_size, 4074 enum i40e_admin_queue_opc opcode, 4075 struct i40e_asq_cmd_details *cmd_details) 4076 { 4077 struct i40e_aq_desc desc; 4078 struct i40e_aqc_tx_sched_ind *cmd = 4079 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 4080 enum i40e_status_code status; 4081 bool cmd_param_flag = FALSE; 4082 4083 switch (opcode) { 4084 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 4085 case i40e_aqc_opc_configure_vsi_tc_bw: 4086 case i40e_aqc_opc_enable_switching_comp_ets: 4087 case i40e_aqc_opc_modify_switching_comp_ets: 4088 case i40e_aqc_opc_disable_switching_comp_ets: 4089 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 4090 case i40e_aqc_opc_configure_switching_comp_bw_config: 4091 cmd_param_flag = TRUE; 4092 break; 4093 case i40e_aqc_opc_query_vsi_bw_config: 4094 case i40e_aqc_opc_query_vsi_ets_sla_config: 4095 case i40e_aqc_opc_query_switching_comp_ets_config: 4096 case i40e_aqc_opc_query_port_ets_config: 4097 case i40e_aqc_opc_query_switching_comp_bw_config: 4098 cmd_param_flag = FALSE; 4099 break; 4100 default: 4101 return I40E_ERR_PARAM; 4102 } 4103 4104 i40e_fill_default_direct_cmd_desc(&desc, opcode); 4105 4106 /* Indirect command */ 4107 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4108 if (cmd_param_flag) 4109 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 4110 if (buff_size > I40E_AQ_LARGE_BUF) 4111 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4112 4113 desc.datalen = CPU_TO_LE16(buff_size); 4114 4115 cmd->vsi_seid = CPU_TO_LE16(seid); 4116 4117 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4118 4119 return status; 4120 } 4121 4122 /** 4123 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 4124 * @hw: pointer to the hw struct 4125 * @seid: VSI seid 4126 * @credit: BW limit credits (0 = disabled) 4127 * @max_credit: Max BW limit credits 4128 * @cmd_details: pointer to command details structure or NULL 4129 **/ 4130 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 4131 u16 seid, u16 credit, u8 max_credit, 4132 struct i40e_asq_cmd_details *cmd_details) 4133 { 4134 struct i40e_aq_desc desc; 4135 struct i40e_aqc_configure_vsi_bw_limit *cmd = 4136 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 4137 enum i40e_status_code status; 4138 4139 i40e_fill_default_direct_cmd_desc(&desc, 4140 i40e_aqc_opc_configure_vsi_bw_limit); 4141 4142 cmd->vsi_seid = CPU_TO_LE16(seid); 4143 cmd->credit = CPU_TO_LE16(credit); 4144 cmd->max_credit = max_credit; 4145 4146 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4147 4148 return status; 4149 } 4150 4151 /** 4152 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 4153 * @hw: pointer to the hw struct 4154 * @seid: switching component seid 4155 * @credit: BW limit credits (0 = disabled) 4156 * @max_bw: Max BW limit credits 4157 * @cmd_details: pointer to command details structure or NULL 4158 **/ 4159 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 4160 u16 seid, u16 credit, u8 max_bw, 4161 struct i40e_asq_cmd_details *cmd_details) 4162 { 4163 struct i40e_aq_desc desc; 4164 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 4165 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 4166 enum i40e_status_code status; 4167 4168 i40e_fill_default_direct_cmd_desc(&desc, 4169 i40e_aqc_opc_configure_switching_comp_bw_limit); 4170 4171 cmd->seid = CPU_TO_LE16(seid); 4172 cmd->credit = CPU_TO_LE16(credit); 4173 cmd->max_bw = max_bw; 4174 4175 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4176 4177 return status; 4178 } 4179 4180 /** 4181 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 4182 * @hw: pointer to the hw struct 4183 * @seid: VSI seid 4184 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 4185 * @cmd_details: pointer to command details structure or NULL 4186 **/ 4187 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 4188 u16 seid, 4189 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 4190 struct i40e_asq_cmd_details *cmd_details) 4191 { 4192 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4193 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 4194 cmd_details); 4195 } 4196 4197 /** 4198 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 4199 * @hw: pointer to the hw struct 4200 * @seid: VSI seid 4201 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 4202 * @cmd_details: pointer to command details structure or NULL 4203 **/ 4204 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 4205 u16 seid, 4206 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 4207 struct i40e_asq_cmd_details *cmd_details) 4208 { 4209 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4210 i40e_aqc_opc_configure_vsi_tc_bw, 4211 cmd_details); 4212 } 4213 4214 /** 4215 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 4216 * @hw: pointer to the hw struct 4217 * @seid: seid of the switching component 4218 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 4219 * @cmd_details: pointer to command details structure or NULL 4220 **/ 4221 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 4222 struct i40e_hw *hw, u16 seid, 4223 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 4224 struct i40e_asq_cmd_details *cmd_details) 4225 { 4226 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4227 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 4228 cmd_details); 4229 } 4230 4231 /** 4232 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 4233 * @hw: pointer to the hw struct 4234 * @seid: seid of the VSI 4235 * @bw_data: Buffer to hold VSI BW configuration 4236 * @cmd_details: pointer to command details structure or NULL 4237 **/ 4238 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 4239 u16 seid, 4240 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 4241 struct i40e_asq_cmd_details *cmd_details) 4242 { 4243 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4244 i40e_aqc_opc_query_vsi_bw_config, 4245 cmd_details); 4246 } 4247 4248 /** 4249 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 4250 * @hw: pointer to the hw struct 4251 * @seid: seid of the VSI 4252 * @bw_data: Buffer to hold VSI BW configuration per TC 4253 * @cmd_details: pointer to command details structure or NULL 4254 **/ 4255 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 4256 u16 seid, 4257 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 4258 struct i40e_asq_cmd_details *cmd_details) 4259 { 4260 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4261 i40e_aqc_opc_query_vsi_ets_sla_config, 4262 cmd_details); 4263 } 4264 4265 /** 4266 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 4267 * @hw: pointer to the hw struct 4268 * @seid: seid of the switching component 4269 * @bw_data: Buffer to hold switching component's per TC BW config 4270 * @cmd_details: pointer to command details structure or NULL 4271 **/ 4272 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 4273 u16 seid, 4274 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 4275 struct i40e_asq_cmd_details *cmd_details) 4276 { 4277 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4278 i40e_aqc_opc_query_switching_comp_ets_config, 4279 cmd_details); 4280 } 4281 4282 /** 4283 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 4284 * @hw: pointer to the hw struct 4285 * @seid: seid of the VSI or switching component connected to Physical Port 4286 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 4287 * @cmd_details: pointer to command details structure or NULL 4288 **/ 4289 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 4290 u16 seid, 4291 struct i40e_aqc_query_port_ets_config_resp *bw_data, 4292 struct i40e_asq_cmd_details *cmd_details) 4293 { 4294 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4295 i40e_aqc_opc_query_port_ets_config, 4296 cmd_details); 4297 } 4298 4299 /** 4300 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 4301 * @hw: pointer to the hw struct 4302 * @seid: seid of the switching component 4303 * @bw_data: Buffer to hold switching component's BW configuration 4304 * @cmd_details: pointer to command details structure or NULL 4305 **/ 4306 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4307 u16 seid, 4308 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4309 struct i40e_asq_cmd_details *cmd_details) 4310 { 4311 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4312 i40e_aqc_opc_query_switching_comp_bw_config, 4313 cmd_details); 4314 } 4315 4316 /** 4317 * i40e_validate_filter_settings 4318 * @hw: pointer to the hardware structure 4319 * @settings: Filter control settings 4320 * 4321 * Check and validate the filter control settings passed. 4322 * The function checks for the valid filter/context sizes being 4323 * passed for FCoE and PE. 4324 * 4325 * Returns I40E_SUCCESS if the values passed are valid and within 4326 * range else returns an error. 4327 **/ 4328 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 4329 struct i40e_filter_control_settings *settings) 4330 { 4331 u32 fcoe_cntx_size, fcoe_filt_size; 4332 u32 pe_cntx_size, pe_filt_size; 4333 u32 fcoe_fmax; 4334 4335 u32 val; 4336 4337 /* Validate FCoE settings passed */ 4338 switch (settings->fcoe_filt_num) { 4339 case I40E_HASH_FILTER_SIZE_1K: 4340 case I40E_HASH_FILTER_SIZE_2K: 4341 case I40E_HASH_FILTER_SIZE_4K: 4342 case I40E_HASH_FILTER_SIZE_8K: 4343 case I40E_HASH_FILTER_SIZE_16K: 4344 case I40E_HASH_FILTER_SIZE_32K: 4345 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4346 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4347 break; 4348 default: 4349 return I40E_ERR_PARAM; 4350 } 4351 4352 switch (settings->fcoe_cntx_num) { 4353 case I40E_DMA_CNTX_SIZE_512: 4354 case I40E_DMA_CNTX_SIZE_1K: 4355 case I40E_DMA_CNTX_SIZE_2K: 4356 case I40E_DMA_CNTX_SIZE_4K: 4357 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4358 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4359 break; 4360 default: 4361 return I40E_ERR_PARAM; 4362 } 4363 4364 /* Validate PE settings passed */ 4365 switch (settings->pe_filt_num) { 4366 case I40E_HASH_FILTER_SIZE_1K: 4367 case I40E_HASH_FILTER_SIZE_2K: 4368 case I40E_HASH_FILTER_SIZE_4K: 4369 case I40E_HASH_FILTER_SIZE_8K: 4370 case I40E_HASH_FILTER_SIZE_16K: 4371 case I40E_HASH_FILTER_SIZE_32K: 4372 case I40E_HASH_FILTER_SIZE_64K: 4373 case I40E_HASH_FILTER_SIZE_128K: 4374 case I40E_HASH_FILTER_SIZE_256K: 4375 case I40E_HASH_FILTER_SIZE_512K: 4376 case I40E_HASH_FILTER_SIZE_1M: 4377 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4378 pe_filt_size <<= (u32)settings->pe_filt_num; 4379 break; 4380 default: 4381 return I40E_ERR_PARAM; 4382 } 4383 4384 switch (settings->pe_cntx_num) { 4385 case I40E_DMA_CNTX_SIZE_512: 4386 case I40E_DMA_CNTX_SIZE_1K: 4387 case I40E_DMA_CNTX_SIZE_2K: 4388 case I40E_DMA_CNTX_SIZE_4K: 4389 case I40E_DMA_CNTX_SIZE_8K: 4390 case I40E_DMA_CNTX_SIZE_16K: 4391 case I40E_DMA_CNTX_SIZE_32K: 4392 case I40E_DMA_CNTX_SIZE_64K: 4393 case I40E_DMA_CNTX_SIZE_128K: 4394 case I40E_DMA_CNTX_SIZE_256K: 4395 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4396 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4397 break; 4398 default: 4399 return I40E_ERR_PARAM; 4400 } 4401 4402 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4403 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4404 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4405 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4406 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4407 return I40E_ERR_INVALID_SIZE; 4408 4409 return I40E_SUCCESS; 4410 } 4411 4412 /** 4413 * i40e_set_filter_control 4414 * @hw: pointer to the hardware structure 4415 * @settings: Filter control settings 4416 * 4417 * Set the Queue Filters for PE/FCoE and enable filters required 4418 * for a single PF. It is expected that these settings are programmed 4419 * at the driver initialization time. 4420 **/ 4421 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 4422 struct i40e_filter_control_settings *settings) 4423 { 4424 enum i40e_status_code ret = I40E_SUCCESS; 4425 u32 hash_lut_size = 0; 4426 u32 val; 4427 4428 if (!settings) 4429 return I40E_ERR_PARAM; 4430 4431 /* Validate the input settings */ 4432 ret = i40e_validate_filter_settings(hw, settings); 4433 if (ret) 4434 return ret; 4435 4436 /* Read the PF Queue Filter control register */ 4437 val = rd32(hw, I40E_PFQF_CTL_0); 4438 4439 /* Program required PE hash buckets for the PF */ 4440 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4441 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4442 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4443 /* Program required PE contexts for the PF */ 4444 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4445 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4446 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4447 4448 /* Program required FCoE hash buckets for the PF */ 4449 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4450 val |= ((u32)settings->fcoe_filt_num << 4451 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4452 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4453 /* Program required FCoE DDP contexts for the PF */ 4454 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4455 val |= ((u32)settings->fcoe_cntx_num << 4456 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4457 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4458 4459 /* Program Hash LUT size for the PF */ 4460 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4461 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4462 hash_lut_size = 1; 4463 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4464 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4465 4466 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4467 if (settings->enable_fdir) 4468 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4469 if (settings->enable_ethtype) 4470 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4471 if (settings->enable_macvlan) 4472 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4473 4474 wr32(hw, I40E_PFQF_CTL_0, val); 4475 4476 return I40E_SUCCESS; 4477 } 4478 4479 /** 4480 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4481 * @hw: pointer to the hw struct 4482 * @mac_addr: MAC address to use in the filter 4483 * @ethtype: Ethertype to use in the filter 4484 * @flags: Flags that needs to be applied to the filter 4485 * @vsi_seid: seid of the control VSI 4486 * @queue: VSI queue number to send the packet to 4487 * @is_add: Add control packet filter if True else remove 4488 * @stats: Structure to hold information on control filter counts 4489 * @cmd_details: pointer to command details structure or NULL 4490 * 4491 * This command will Add or Remove control packet filter for a control VSI. 4492 * In return it will update the total number of perfect filter count in 4493 * the stats member. 4494 **/ 4495 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4496 u8 *mac_addr, u16 ethtype, u16 flags, 4497 u16 vsi_seid, u16 queue, bool is_add, 4498 struct i40e_control_filter_stats *stats, 4499 struct i40e_asq_cmd_details *cmd_details) 4500 { 4501 struct i40e_aq_desc desc; 4502 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4503 (struct i40e_aqc_add_remove_control_packet_filter *) 4504 &desc.params.raw; 4505 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4506 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4507 &desc.params.raw; 4508 enum i40e_status_code status; 4509 4510 if (vsi_seid == 0) 4511 return I40E_ERR_PARAM; 4512 4513 if (is_add) { 4514 i40e_fill_default_direct_cmd_desc(&desc, 4515 i40e_aqc_opc_add_control_packet_filter); 4516 cmd->queue = CPU_TO_LE16(queue); 4517 } else { 4518 i40e_fill_default_direct_cmd_desc(&desc, 4519 i40e_aqc_opc_remove_control_packet_filter); 4520 } 4521 4522 if (mac_addr) 4523 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, 4524 I40E_NONDMA_TO_NONDMA); 4525 4526 cmd->etype = CPU_TO_LE16(ethtype); 4527 cmd->flags = CPU_TO_LE16(flags); 4528 cmd->seid = CPU_TO_LE16(vsi_seid); 4529 4530 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4531 4532 if (!status && stats) { 4533 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 4534 stats->etype_used = LE16_TO_CPU(resp->etype_used); 4535 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 4536 stats->etype_free = LE16_TO_CPU(resp->etype_free); 4537 } 4538 4539 return status; 4540 } 4541 4542 /** 4543 * i40e_aq_add_cloud_filters 4544 * @hw: pointer to the hardware structure 4545 * @seid: VSI seid to add cloud filters from 4546 * @filters: Buffer which contains the filters to be added 4547 * @filter_count: number of filters contained in the buffer 4548 * 4549 * Set the cloud filters for a given VSI. The contents of the 4550 * i40e_aqc_add_remove_cloud_filters_element_data are filled 4551 * in by the caller of the function. 4552 * 4553 **/ 4554 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 4555 u16 seid, 4556 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 4557 u8 filter_count) 4558 { 4559 struct i40e_aq_desc desc; 4560 struct i40e_aqc_add_remove_cloud_filters *cmd = 4561 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 4562 u16 buff_len; 4563 enum i40e_status_code status; 4564 4565 i40e_fill_default_direct_cmd_desc(&desc, 4566 i40e_aqc_opc_add_cloud_filters); 4567 4568 buff_len = filter_count * sizeof(*filters); 4569 desc.datalen = CPU_TO_LE16(buff_len); 4570 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4571 cmd->num_filters = filter_count; 4572 cmd->seid = CPU_TO_LE16(seid); 4573 4574 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 4575 4576 return status; 4577 } 4578 4579 /** 4580 * i40e_aq_remove_cloud_filters 4581 * @hw: pointer to the hardware structure 4582 * @seid: VSI seid to remove cloud filters from 4583 * @filters: Buffer which contains the filters to be removed 4584 * @filter_count: number of filters contained in the buffer 4585 * 4586 * Remove the cloud filters for a given VSI. The contents of the 4587 * i40e_aqc_add_remove_cloud_filters_element_data are filled 4588 * in by the caller of the function. 4589 * 4590 **/ 4591 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 4592 u16 seid, 4593 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 4594 u8 filter_count) 4595 { 4596 struct i40e_aq_desc desc; 4597 struct i40e_aqc_add_remove_cloud_filters *cmd = 4598 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 4599 enum i40e_status_code status; 4600 u16 buff_len; 4601 4602 i40e_fill_default_direct_cmd_desc(&desc, 4603 i40e_aqc_opc_remove_cloud_filters); 4604 4605 buff_len = filter_count * sizeof(*filters); 4606 desc.datalen = CPU_TO_LE16(buff_len); 4607 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4608 cmd->num_filters = filter_count; 4609 cmd->seid = CPU_TO_LE16(seid); 4610 4611 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 4612 4613 return status; 4614 } 4615 4616 /** 4617 * i40e_aq_alternate_write 4618 * @hw: pointer to the hardware structure 4619 * @reg_addr0: address of first dword to be read 4620 * @reg_val0: value to be written under 'reg_addr0' 4621 * @reg_addr1: address of second dword to be read 4622 * @reg_val1: value to be written under 'reg_addr1' 4623 * 4624 * Write one or two dwords to alternate structure. Fields are indicated 4625 * by 'reg_addr0' and 'reg_addr1' register numbers. 4626 * 4627 **/ 4628 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 4629 u32 reg_addr0, u32 reg_val0, 4630 u32 reg_addr1, u32 reg_val1) 4631 { 4632 struct i40e_aq_desc desc; 4633 struct i40e_aqc_alternate_write *cmd_resp = 4634 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4635 enum i40e_status_code status; 4636 4637 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 4638 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 4639 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 4640 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 4641 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 4642 4643 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4644 4645 return status; 4646 } 4647 4648 /** 4649 * i40e_aq_alternate_write_indirect 4650 * @hw: pointer to the hardware structure 4651 * @addr: address of a first register to be modified 4652 * @dw_count: number of alternate structure fields to write 4653 * @buffer: pointer to the command buffer 4654 * 4655 * Write 'dw_count' dwords from 'buffer' to alternate structure 4656 * starting at 'addr'. 4657 * 4658 **/ 4659 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 4660 u32 addr, u32 dw_count, void *buffer) 4661 { 4662 struct i40e_aq_desc desc; 4663 struct i40e_aqc_alternate_ind_write *cmd_resp = 4664 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 4665 enum i40e_status_code status; 4666 4667 if (buffer == NULL) 4668 return I40E_ERR_PARAM; 4669 4670 /* Indirect command */ 4671 i40e_fill_default_direct_cmd_desc(&desc, 4672 i40e_aqc_opc_alternate_write_indirect); 4673 4674 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 4675 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 4676 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 4677 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4678 4679 cmd_resp->address = CPU_TO_LE32(addr); 4680 cmd_resp->length = CPU_TO_LE32(dw_count); 4681 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer)); 4682 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer)); 4683 4684 status = i40e_asq_send_command(hw, &desc, buffer, 4685 I40E_LO_DWORD(4*dw_count), NULL); 4686 4687 return status; 4688 } 4689 4690 /** 4691 * i40e_aq_alternate_read 4692 * @hw: pointer to the hardware structure 4693 * @reg_addr0: address of first dword to be read 4694 * @reg_val0: pointer for data read from 'reg_addr0' 4695 * @reg_addr1: address of second dword to be read 4696 * @reg_val1: pointer for data read from 'reg_addr1' 4697 * 4698 * Read one or two dwords from alternate structure. Fields are indicated 4699 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4700 * is not passed then only register at 'reg_addr0' is read. 4701 * 4702 **/ 4703 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 4704 u32 reg_addr0, u32 *reg_val0, 4705 u32 reg_addr1, u32 *reg_val1) 4706 { 4707 struct i40e_aq_desc desc; 4708 struct i40e_aqc_alternate_write *cmd_resp = 4709 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4710 enum i40e_status_code status; 4711 4712 if (reg_val0 == NULL) 4713 return I40E_ERR_PARAM; 4714 4715 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4716 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 4717 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 4718 4719 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4720 4721 if (status == I40E_SUCCESS) { 4722 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 4723 4724 if (reg_val1 != NULL) 4725 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 4726 } 4727 4728 return status; 4729 } 4730 4731 /** 4732 * i40e_aq_alternate_read_indirect 4733 * @hw: pointer to the hardware structure 4734 * @addr: address of the alternate structure field 4735 * @dw_count: number of alternate structure fields to read 4736 * @buffer: pointer to the command buffer 4737 * 4738 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 4739 * place them in 'buffer'. The buffer should be allocated by caller. 4740 * 4741 **/ 4742 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 4743 u32 addr, u32 dw_count, void *buffer) 4744 { 4745 struct i40e_aq_desc desc; 4746 struct i40e_aqc_alternate_ind_write *cmd_resp = 4747 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 4748 enum i40e_status_code status; 4749 4750 if (buffer == NULL) 4751 return I40E_ERR_PARAM; 4752 4753 /* Indirect command */ 4754 i40e_fill_default_direct_cmd_desc(&desc, 4755 i40e_aqc_opc_alternate_read_indirect); 4756 4757 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 4758 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 4759 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 4760 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4761 4762 cmd_resp->address = CPU_TO_LE32(addr); 4763 cmd_resp->length = CPU_TO_LE32(dw_count); 4764 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer)); 4765 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer)); 4766 4767 status = i40e_asq_send_command(hw, &desc, buffer, 4768 I40E_LO_DWORD(4*dw_count), NULL); 4769 4770 return status; 4771 } 4772 4773 /** 4774 * i40e_aq_alternate_clear 4775 * @hw: pointer to the HW structure. 4776 * 4777 * Clear the alternate structures of the port from which the function 4778 * is called. 4779 * 4780 **/ 4781 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 4782 { 4783 struct i40e_aq_desc desc; 4784 enum i40e_status_code status; 4785 4786 i40e_fill_default_direct_cmd_desc(&desc, 4787 i40e_aqc_opc_alternate_clear_port); 4788 4789 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4790 4791 return status; 4792 } 4793 4794 /** 4795 * i40e_aq_alternate_write_done 4796 * @hw: pointer to the HW structure. 4797 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 4798 * @reset_needed: indicates the SW should trigger GLOBAL reset 4799 * 4800 * Indicates to the FW that alternate structures have been changed. 4801 * 4802 **/ 4803 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 4804 u8 bios_mode, bool *reset_needed) 4805 { 4806 struct i40e_aq_desc desc; 4807 struct i40e_aqc_alternate_write_done *cmd = 4808 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 4809 enum i40e_status_code status; 4810 4811 if (reset_needed == NULL) 4812 return I40E_ERR_PARAM; 4813 4814 i40e_fill_default_direct_cmd_desc(&desc, 4815 i40e_aqc_opc_alternate_write_done); 4816 4817 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 4818 4819 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4820 if (!status && reset_needed) 4821 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 4822 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 4823 4824 return status; 4825 } 4826 4827 /** 4828 * i40e_aq_set_oem_mode 4829 * @hw: pointer to the HW structure. 4830 * @oem_mode: the OEM mode to be used 4831 * 4832 * Sets the device to a specific operating mode. Currently the only supported 4833 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 4834 * 4835 **/ 4836 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 4837 u8 oem_mode) 4838 { 4839 struct i40e_aq_desc desc; 4840 struct i40e_aqc_alternate_write_done *cmd = 4841 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 4842 enum i40e_status_code status; 4843 4844 i40e_fill_default_direct_cmd_desc(&desc, 4845 i40e_aqc_opc_alternate_set_mode); 4846 4847 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 4848 4849 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4850 4851 return status; 4852 } 4853 4854 /** 4855 * i40e_aq_resume_port_tx 4856 * @hw: pointer to the hardware structure 4857 * @cmd_details: pointer to command details structure or NULL 4858 * 4859 * Resume port's Tx traffic 4860 **/ 4861 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 4862 struct i40e_asq_cmd_details *cmd_details) 4863 { 4864 struct i40e_aq_desc desc; 4865 enum i40e_status_code status; 4866 4867 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4868 4869 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4870 4871 return status; 4872 } 4873 4874 /** 4875 * i40e_set_pci_config_data - store PCI bus info 4876 * @hw: pointer to hardware structure 4877 * @link_status: the link status word from PCI config space 4878 * 4879 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4880 **/ 4881 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4882 { 4883 hw->bus.type = i40e_bus_type_pci_express; 4884 4885 switch (link_status & I40E_PCI_LINK_WIDTH) { 4886 case I40E_PCI_LINK_WIDTH_1: 4887 hw->bus.width = i40e_bus_width_pcie_x1; 4888 break; 4889 case I40E_PCI_LINK_WIDTH_2: 4890 hw->bus.width = i40e_bus_width_pcie_x2; 4891 break; 4892 case I40E_PCI_LINK_WIDTH_4: 4893 hw->bus.width = i40e_bus_width_pcie_x4; 4894 break; 4895 case I40E_PCI_LINK_WIDTH_8: 4896 hw->bus.width = i40e_bus_width_pcie_x8; 4897 break; 4898 default: 4899 hw->bus.width = i40e_bus_width_unknown; 4900 break; 4901 } 4902 4903 switch (link_status & I40E_PCI_LINK_SPEED) { 4904 case I40E_PCI_LINK_SPEED_2500: 4905 hw->bus.speed = i40e_bus_speed_2500; 4906 break; 4907 case I40E_PCI_LINK_SPEED_5000: 4908 hw->bus.speed = i40e_bus_speed_5000; 4909 break; 4910 case I40E_PCI_LINK_SPEED_8000: 4911 hw->bus.speed = i40e_bus_speed_8000; 4912 break; 4913 default: 4914 hw->bus.speed = i40e_bus_speed_unknown; 4915 break; 4916 } 4917 } 4918 4919 /** 4920 * i40e_read_bw_from_alt_ram 4921 * @hw: pointer to the hardware structure 4922 * @max_bw: pointer for max_bw read 4923 * @min_bw: pointer for min_bw read 4924 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 4925 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 4926 * 4927 * Read bw from the alternate ram for the given pf 4928 **/ 4929 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4930 u32 *max_bw, u32 *min_bw, 4931 bool *min_valid, bool *max_valid) 4932 { 4933 enum i40e_status_code status; 4934 u32 max_bw_addr, min_bw_addr; 4935 4936 /* Calculate the address of the min/max bw registers */ 4937 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4938 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4939 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id); 4940 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4941 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4942 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id); 4943 4944 /* Read the bandwidths from alt ram */ 4945 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4946 min_bw_addr, min_bw); 4947 4948 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4949 *min_valid = TRUE; 4950 else 4951 *min_valid = FALSE; 4952 4953 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4954 *max_valid = TRUE; 4955 else 4956 *max_valid = FALSE; 4957 4958 return status; 4959 } 4960 4961 /** 4962 * i40e_aq_configure_partition_bw 4963 * @hw: pointer to the hardware structure 4964 * @bw_data: Buffer holding valid pfs and bw limits 4965 * @cmd_details: pointer to command details 4966 * 4967 * Configure partitions guaranteed/max bw 4968 **/ 4969 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4970 struct i40e_aqc_configure_partition_bw_data *bw_data, 4971 struct i40e_asq_cmd_details *cmd_details) 4972 { 4973 enum i40e_status_code status; 4974 struct i40e_aq_desc desc; 4975 u16 bwd_size = sizeof(*bw_data); 4976 4977 i40e_fill_default_direct_cmd_desc(&desc, 4978 i40e_aqc_opc_configure_partition_bw); 4979 4980 /* Indirect command */ 4981 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4982 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 4983 4984 if (bwd_size > I40E_AQ_LARGE_BUF) 4985 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4986 4987 desc.datalen = CPU_TO_LE16(bwd_size); 4988 4989 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 4990 4991 return status; 4992 } 4993 4994 /** 4995 * i40e_aq_send_msg_to_pf 4996 * @hw: pointer to the hardware structure 4997 * @v_opcode: opcodes for VF-PF communication 4998 * @v_retval: return error code 4999 * @msg: pointer to the msg buffer 5000 * @msglen: msg length 5001 * @cmd_details: pointer to command details 5002 * 5003 * Send message to PF driver using admin queue. By default, this message 5004 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 5005 * completion before returning. 5006 **/ 5007 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 5008 enum i40e_virtchnl_ops v_opcode, 5009 enum i40e_status_code v_retval, 5010 u8 *msg, u16 msglen, 5011 struct i40e_asq_cmd_details *cmd_details) 5012 { 5013 struct i40e_aq_desc desc; 5014 struct i40e_asq_cmd_details details; 5015 enum i40e_status_code status; 5016 5017 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 5018 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 5019 desc.cookie_high = CPU_TO_LE32(v_opcode); 5020 desc.cookie_low = CPU_TO_LE32(v_retval); 5021 if (msglen) { 5022 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 5023 | I40E_AQ_FLAG_RD)); 5024 if (msglen > I40E_AQ_LARGE_BUF) 5025 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5026 desc.datalen = CPU_TO_LE16(msglen); 5027 } 5028 if (!cmd_details) { 5029 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 5030 details.async = TRUE; 5031 cmd_details = &details; 5032 } 5033 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 5034 msglen, cmd_details); 5035 return status; 5036 } 5037 5038 /** 5039 * i40e_vf_parse_hw_config 5040 * @hw: pointer to the hardware structure 5041 * @msg: pointer to the virtual channel VF resource structure 5042 * 5043 * Given a VF resource message from the PF, populate the hw struct 5044 * with appropriate information. 5045 **/ 5046 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 5047 struct i40e_virtchnl_vf_resource *msg) 5048 { 5049 struct i40e_virtchnl_vsi_resource *vsi_res; 5050 int i; 5051 5052 vsi_res = &msg->vsi_res[0]; 5053 5054 hw->dev_caps.num_vsis = msg->num_vsis; 5055 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 5056 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 5057 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 5058 hw->dev_caps.dcb = msg->vf_offload_flags & 5059 I40E_VIRTCHNL_VF_OFFLOAD_L2; 5060 hw->dev_caps.fcoe = (msg->vf_offload_flags & 5061 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0; 5062 hw->dev_caps.iwarp = (msg->vf_offload_flags & 5063 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 5064 for (i = 0; i < msg->num_vsis; i++) { 5065 if (vsi_res->vsi_type == I40E_VSI_SRIOV) { 5066 i40e_memcpy(hw->mac.perm_addr, 5067 vsi_res->default_mac_addr, 5068 I40E_ETH_LENGTH_OF_ADDRESS, 5069 I40E_NONDMA_TO_NONDMA); 5070 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 5071 I40E_ETH_LENGTH_OF_ADDRESS, 5072 I40E_NONDMA_TO_NONDMA); 5073 } 5074 vsi_res++; 5075 } 5076 } 5077 5078 /** 5079 * i40e_vf_reset 5080 * @hw: pointer to the hardware structure 5081 * 5082 * Send a VF_RESET message to the PF. Does not wait for response from PF 5083 * as none will be forthcoming. Immediately after calling this function, 5084 * the admin queue should be shut down and (optionally) reinitialized. 5085 **/ 5086 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 5087 { 5088 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF, 5089 I40E_SUCCESS, NULL, 0, NULL); 5090 } 5091