1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/rman.h> 39 #include <sys/module.h> 40 #include <sys/proc.h> 41 #include <sys/queue.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <machine/bus.h> 69 #include <machine/in_cksum.h> 70 71 #include <dev/jme/if_jmereg.h> 72 #include <dev/jme/if_jmevar.h> 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 /* Define the following to disable printing Rx errors. */ 78 #undef JME_SHOW_ERRORS 79 80 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(jme, pci, 1, 1, 1); 83 MODULE_DEPEND(jme, ether, 1, 1, 1); 84 MODULE_DEPEND(jme, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.jme.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.jme.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static struct jme_dev { 96 uint16_t jme_vendorid; 97 uint16_t jme_deviceid; 98 const char *jme_name; 99 } jme_devs[] = { 100 { VENDORID_JMICRON, DEVICEID_JMC250, 101 "JMicron Inc, JMC25x Gigabit Ethernet" }, 102 { VENDORID_JMICRON, DEVICEID_JMC260, 103 "JMicron Inc, JMC26x Fast Ethernet" }, 104 }; 105 106 static int jme_miibus_readreg(device_t, int, int); 107 static int jme_miibus_writereg(device_t, int, int, int); 108 static void jme_miibus_statchg(device_t); 109 static void jme_mediastatus(if_t, struct ifmediareq *); 110 static int jme_mediachange(if_t); 111 static int jme_probe(device_t); 112 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 113 static int jme_eeprom_macaddr(struct jme_softc *); 114 static int jme_efuse_macaddr(struct jme_softc *); 115 static void jme_reg_macaddr(struct jme_softc *); 116 static void jme_set_macaddr(struct jme_softc *, uint8_t *); 117 static void jme_map_intr_vector(struct jme_softc *); 118 static int jme_attach(device_t); 119 static int jme_detach(device_t); 120 static void jme_sysctl_node(struct jme_softc *); 121 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 122 static int jme_dma_alloc(struct jme_softc *); 123 static void jme_dma_free(struct jme_softc *); 124 static int jme_shutdown(device_t); 125 static void jme_setlinkspeed(struct jme_softc *); 126 static void jme_setwol(struct jme_softc *); 127 static int jme_suspend(device_t); 128 static int jme_resume(device_t); 129 static int jme_encap(struct jme_softc *, struct mbuf **); 130 static void jme_start(if_t); 131 static void jme_start_locked(if_t); 132 static void jme_watchdog(struct jme_softc *); 133 static int jme_ioctl(if_t, u_long, caddr_t); 134 static void jme_mac_config(struct jme_softc *); 135 static void jme_link_task(void *, int); 136 static int jme_intr(void *); 137 static void jme_int_task(void *, int); 138 static void jme_txeof(struct jme_softc *); 139 static __inline void jme_discard_rxbuf(struct jme_softc *, int); 140 static void jme_rxeof(struct jme_softc *); 141 static int jme_rxintr(struct jme_softc *, int); 142 static void jme_tick(void *); 143 static void jme_reset(struct jme_softc *); 144 static void jme_init(void *); 145 static void jme_init_locked(struct jme_softc *); 146 static void jme_stop(struct jme_softc *); 147 static void jme_stop_tx(struct jme_softc *); 148 static void jme_stop_rx(struct jme_softc *); 149 static int jme_init_rx_ring(struct jme_softc *); 150 static void jme_init_tx_ring(struct jme_softc *); 151 static void jme_init_ssb(struct jme_softc *); 152 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 153 static void jme_set_vlan(struct jme_softc *); 154 static void jme_set_filter(struct jme_softc *); 155 static void jme_stats_clear(struct jme_softc *); 156 static void jme_stats_save(struct jme_softc *); 157 static void jme_stats_update(struct jme_softc *); 158 static void jme_phy_down(struct jme_softc *); 159 static void jme_phy_up(struct jme_softc *); 160 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 161 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 162 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 163 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 164 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 165 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 166 167 168 static device_method_t jme_methods[] = { 169 /* Device interface. */ 170 DEVMETHOD(device_probe, jme_probe), 171 DEVMETHOD(device_attach, jme_attach), 172 DEVMETHOD(device_detach, jme_detach), 173 DEVMETHOD(device_shutdown, jme_shutdown), 174 DEVMETHOD(device_suspend, jme_suspend), 175 DEVMETHOD(device_resume, jme_resume), 176 177 /* MII interface. */ 178 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 179 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 180 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 181 182 { NULL, NULL } 183 }; 184 185 static driver_t jme_driver = { 186 "jme", 187 jme_methods, 188 sizeof(struct jme_softc) 189 }; 190 191 DRIVER_MODULE(jme, pci, jme_driver, 0, 0); 192 DRIVER_MODULE(miibus, jme, miibus_driver, 0, 0); 193 194 static struct resource_spec jme_res_spec_mem[] = { 195 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 196 { -1, 0, 0 } 197 }; 198 199 static struct resource_spec jme_irq_spec_legacy[] = { 200 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 201 { -1, 0, 0 } 202 }; 203 204 static struct resource_spec jme_irq_spec_msi[] = { 205 { SYS_RES_IRQ, 1, RF_ACTIVE }, 206 { -1, 0, 0 } 207 }; 208 209 /* 210 * Read a PHY register on the MII of the JMC250. 211 */ 212 static int 213 jme_miibus_readreg(device_t dev, int phy, int reg) 214 { 215 struct jme_softc *sc; 216 uint32_t val; 217 int i; 218 219 sc = device_get_softc(dev); 220 221 /* For FPGA version, PHY address 0 should be ignored. */ 222 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 223 return (0); 224 225 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 226 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 227 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 228 DELAY(1); 229 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 230 break; 231 } 232 233 if (i == 0) { 234 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 235 return (0); 236 } 237 238 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 239 } 240 241 /* 242 * Write a PHY register on the MII of the JMC250. 243 */ 244 static int 245 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 246 { 247 struct jme_softc *sc; 248 int i; 249 250 sc = device_get_softc(dev); 251 252 /* For FPGA version, PHY address 0 should be ignored. */ 253 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 254 return (0); 255 256 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 257 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 258 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 259 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 260 DELAY(1); 261 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 262 break; 263 } 264 265 if (i == 0) 266 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 267 268 return (0); 269 } 270 271 /* 272 * Callback from MII layer when media changes. 273 */ 274 static void 275 jme_miibus_statchg(device_t dev) 276 { 277 struct jme_softc *sc; 278 279 sc = device_get_softc(dev); 280 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 281 } 282 283 /* 284 * Get the current interface media status. 285 */ 286 static void 287 jme_mediastatus(if_t ifp, struct ifmediareq *ifmr) 288 { 289 struct jme_softc *sc; 290 struct mii_data *mii; 291 292 sc = if_getsoftc(ifp); 293 JME_LOCK(sc); 294 if ((if_getflags(ifp) & IFF_UP) == 0) { 295 JME_UNLOCK(sc); 296 return; 297 } 298 mii = device_get_softc(sc->jme_miibus); 299 300 mii_pollstat(mii); 301 ifmr->ifm_status = mii->mii_media_status; 302 ifmr->ifm_active = mii->mii_media_active; 303 JME_UNLOCK(sc); 304 } 305 306 /* 307 * Set hardware to newly-selected media. 308 */ 309 static int 310 jme_mediachange(if_t ifp) 311 { 312 struct jme_softc *sc; 313 struct mii_data *mii; 314 struct mii_softc *miisc; 315 int error; 316 317 sc = if_getsoftc(ifp); 318 JME_LOCK(sc); 319 mii = device_get_softc(sc->jme_miibus); 320 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 321 PHY_RESET(miisc); 322 error = mii_mediachg(mii); 323 JME_UNLOCK(sc); 324 325 return (error); 326 } 327 328 static int 329 jme_probe(device_t dev) 330 { 331 struct jme_dev *sp; 332 int i; 333 uint16_t vendor, devid; 334 335 vendor = pci_get_vendor(dev); 336 devid = pci_get_device(dev); 337 sp = jme_devs; 338 for (i = 0; i < nitems(jme_devs); i++, sp++) { 339 if (vendor == sp->jme_vendorid && 340 devid == sp->jme_deviceid) { 341 device_set_desc(dev, sp->jme_name); 342 return (BUS_PROBE_DEFAULT); 343 } 344 } 345 346 return (ENXIO); 347 } 348 349 static int 350 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 351 { 352 uint32_t reg; 353 int i; 354 355 *val = 0; 356 for (i = JME_TIMEOUT; i > 0; i--) { 357 reg = CSR_READ_4(sc, JME_SMBCSR); 358 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 359 break; 360 DELAY(1); 361 } 362 363 if (i == 0) { 364 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 365 return (ETIMEDOUT); 366 } 367 368 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 369 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 370 for (i = JME_TIMEOUT; i > 0; i--) { 371 DELAY(1); 372 reg = CSR_READ_4(sc, JME_SMBINTF); 373 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 374 break; 375 } 376 377 if (i == 0) { 378 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 379 return (ETIMEDOUT); 380 } 381 382 reg = CSR_READ_4(sc, JME_SMBINTF); 383 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 384 385 return (0); 386 } 387 388 static int 389 jme_eeprom_macaddr(struct jme_softc *sc) 390 { 391 uint8_t eaddr[ETHER_ADDR_LEN]; 392 uint8_t fup, reg, val; 393 uint32_t offset; 394 int match; 395 396 offset = 0; 397 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 398 fup != JME_EEPROM_SIG0) 399 return (ENOENT); 400 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 401 fup != JME_EEPROM_SIG1) 402 return (ENOENT); 403 match = 0; 404 do { 405 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 406 break; 407 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 408 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 409 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 410 break; 411 if (reg >= JME_PAR0 && 412 reg < JME_PAR0 + ETHER_ADDR_LEN) { 413 if (jme_eeprom_read_byte(sc, offset + 2, 414 &val) != 0) 415 break; 416 eaddr[reg - JME_PAR0] = val; 417 match++; 418 } 419 } 420 /* Check for the end of EEPROM descriptor. */ 421 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 422 break; 423 /* Try next eeprom descriptor. */ 424 offset += JME_EEPROM_DESC_BYTES; 425 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 426 427 if (match == ETHER_ADDR_LEN) { 428 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 429 return (0); 430 } 431 432 return (ENOENT); 433 } 434 435 static int 436 jme_efuse_macaddr(struct jme_softc *sc) 437 { 438 uint32_t reg; 439 int i; 440 441 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 442 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) != 443 EFUSE_CTL1_AUTOLAOD_DONE) 444 return (ENOENT); 445 /* Reset eFuse controller. */ 446 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 447 reg |= EFUSE_CTL2_RESET; 448 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 449 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 450 reg &= ~EFUSE_CTL2_RESET; 451 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 452 453 /* Have eFuse reload station address to MAC controller. */ 454 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 455 reg &= ~EFUSE_CTL1_CMD_MASK; 456 reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE; 457 pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4); 458 459 /* 460 * Verify completion of eFuse autload command. It should be 461 * completed within 108us. 462 */ 463 DELAY(110); 464 for (i = 10; i > 0; i--) { 465 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 466 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | 467 EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) { 468 DELAY(20); 469 continue; 470 } 471 if ((reg & EFUSE_CTL1_EXECUTE) == 0) 472 break; 473 /* Station address loading is still in progress. */ 474 DELAY(20); 475 } 476 if (i == 0) { 477 device_printf(sc->jme_dev, "eFuse autoload timed out.\n"); 478 return (ETIMEDOUT); 479 } 480 481 return (0); 482 } 483 484 static void 485 jme_reg_macaddr(struct jme_softc *sc) 486 { 487 uint32_t par0, par1; 488 489 /* Read station address. */ 490 par0 = CSR_READ_4(sc, JME_PAR0); 491 par1 = CSR_READ_4(sc, JME_PAR1); 492 par1 &= 0xFFFF; 493 if ((par0 == 0 && par1 == 0) || 494 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 495 device_printf(sc->jme_dev, 496 "Failed to retrieve Ethernet address.\n"); 497 } else { 498 /* 499 * For controllers that use eFuse, the station address 500 * could also be extracted from JME_PCI_PAR0 and 501 * JME_PCI_PAR1 registers in PCI configuration space. 502 * Each register holds exactly half of station address(24bits) 503 * so use JME_PAR0, JME_PAR1 registers instead. 504 */ 505 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 506 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 507 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 508 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 509 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 510 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 511 } 512 } 513 514 static void 515 jme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr) 516 { 517 uint32_t val; 518 int i; 519 520 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 521 /* 522 * Avoid reprogramming station address if the address 523 * is the same as previous one. Note, reprogrammed 524 * station address is permanent as if it was written 525 * to EEPROM. So if station address was changed by 526 * admistrator it's possible to lose factory configured 527 * address when driver fails to restore its address. 528 * (e.g. reboot or system crash) 529 */ 530 if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) { 531 for (i = 0; i < ETHER_ADDR_LEN; i++) { 532 val = JME_EFUSE_EEPROM_FUNC0 << 533 JME_EFUSE_EEPROM_FUNC_SHIFT; 534 val |= JME_EFUSE_EEPROM_PAGE_BAR1 << 535 JME_EFUSE_EEPROM_PAGE_SHIFT; 536 val |= (JME_PAR0 + i) << 537 JME_EFUSE_EEPROM_ADDR_SHIFT; 538 val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT; 539 pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM, 540 val | JME_EFUSE_EEPROM_WRITE, 4); 541 } 542 } 543 } else { 544 CSR_WRITE_4(sc, JME_PAR0, 545 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 546 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 547 } 548 } 549 550 static void 551 jme_map_intr_vector(struct jme_softc *sc) 552 { 553 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 554 555 bzero(map, sizeof(map)); 556 557 /* Map Tx interrupts source to MSI/MSIX vector 2. */ 558 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 559 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 560 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 561 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 562 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 563 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 564 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 565 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 566 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 567 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 568 map[MSINUM_REG_INDEX(N_INTR_TXQ5_COMP)] |= 569 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 570 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 571 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 572 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 573 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 574 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 575 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 576 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 577 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 578 579 /* Map Rx interrupts source to MSI/MSIX vector 1. */ 580 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 581 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 582 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 583 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 584 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 585 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 586 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 587 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 588 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 589 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 590 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 591 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 592 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 593 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 594 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 595 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 596 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 597 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 598 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 599 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 600 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 601 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 602 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 603 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 604 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 605 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 606 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 607 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 608 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 609 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 610 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 611 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 612 613 /* Map all other interrupts source to MSI/MSIX vector 0. */ 614 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 615 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 616 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 617 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 618 } 619 620 static int 621 jme_attach(device_t dev) 622 { 623 struct jme_softc *sc; 624 if_t ifp; 625 struct mii_softc *miisc; 626 struct mii_data *mii; 627 uint32_t reg; 628 uint16_t burst; 629 int error, i, mii_flags, msic, msixc, pmc; 630 631 error = 0; 632 sc = device_get_softc(dev); 633 sc->jme_dev = dev; 634 635 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 636 MTX_DEF); 637 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 638 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 639 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 640 641 /* 642 * Map the device. JMC250 supports both memory mapped and I/O 643 * register space access. Because I/O register access should 644 * use different BARs to access registers it's waste of time 645 * to use I/O register spce access. JMC250 uses 16K to map 646 * entire memory space. 647 */ 648 pci_enable_busmaster(dev); 649 sc->jme_res_spec = jme_res_spec_mem; 650 sc->jme_irq_spec = jme_irq_spec_legacy; 651 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 652 if (error != 0) { 653 device_printf(dev, "cannot allocate memory resources.\n"); 654 goto fail; 655 } 656 657 /* Allocate IRQ resources. */ 658 msixc = pci_msix_count(dev); 659 msic = pci_msi_count(dev); 660 if (bootverbose) { 661 device_printf(dev, "MSIX count : %d\n", msixc); 662 device_printf(dev, "MSI count : %d\n", msic); 663 } 664 665 /* Use 1 MSI/MSI-X. */ 666 if (msixc > 1) 667 msixc = 1; 668 if (msic > 1) 669 msic = 1; 670 /* Prefer MSIX over MSI. */ 671 if (msix_disable == 0 || msi_disable == 0) { 672 if (msix_disable == 0 && msixc > 0 && 673 pci_alloc_msix(dev, &msixc) == 0) { 674 if (msixc == 1) { 675 device_printf(dev, "Using %d MSIX messages.\n", 676 msixc); 677 sc->jme_flags |= JME_FLAG_MSIX; 678 sc->jme_irq_spec = jme_irq_spec_msi; 679 } else 680 pci_release_msi(dev); 681 } 682 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 683 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 684 if (msic == 1) { 685 device_printf(dev, "Using %d MSI messages.\n", 686 msic); 687 sc->jme_flags |= JME_FLAG_MSI; 688 sc->jme_irq_spec = jme_irq_spec_msi; 689 } else 690 pci_release_msi(dev); 691 } 692 /* Map interrupt vector 0, 1 and 2. */ 693 if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 694 (sc->jme_flags & JME_FLAG_MSIX) != 0) 695 jme_map_intr_vector(sc); 696 } 697 698 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 699 if (error != 0) { 700 device_printf(dev, "cannot allocate IRQ resources.\n"); 701 goto fail; 702 } 703 704 sc->jme_rev = pci_get_device(dev); 705 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 706 sc->jme_flags |= JME_FLAG_FASTETH; 707 sc->jme_flags |= JME_FLAG_NOJUMBO; 708 } 709 reg = CSR_READ_4(sc, JME_CHIPMODE); 710 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 711 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 712 CHIPMODE_NOT_FPGA) 713 sc->jme_flags |= JME_FLAG_FPGA; 714 if (bootverbose) { 715 device_printf(dev, "PCI device revision : 0x%04x\n", 716 sc->jme_rev); 717 device_printf(dev, "Chip revision : 0x%02x\n", 718 sc->jme_chip_rev); 719 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 720 device_printf(dev, "FPGA revision : 0x%04x\n", 721 (reg & CHIPMODE_FPGA_REV_MASK) >> 722 CHIPMODE_FPGA_REV_SHIFT); 723 } 724 if (sc->jme_chip_rev == 0xFF) { 725 device_printf(dev, "Unknown chip revision : 0x%02x\n", 726 sc->jme_rev); 727 error = ENXIO; 728 goto fail; 729 } 730 731 /* Identify controller features and bugs. */ 732 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 733 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 734 CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 735 sc->jme_flags |= JME_FLAG_DMA32BIT; 736 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 737 sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD; 738 sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK; 739 sc->jme_flags |= JME_FLAG_HWMIB; 740 } 741 742 /* Reset the ethernet controller. */ 743 jme_reset(sc); 744 745 /* Get station address. */ 746 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 747 error = jme_efuse_macaddr(sc); 748 if (error == 0) 749 jme_reg_macaddr(sc); 750 } else { 751 error = ENOENT; 752 reg = CSR_READ_4(sc, JME_SMBCSR); 753 if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 754 error = jme_eeprom_macaddr(sc); 755 if (error != 0 && bootverbose) 756 device_printf(sc->jme_dev, 757 "ethernet hardware address not found in EEPROM.\n"); 758 if (error != 0) 759 jme_reg_macaddr(sc); 760 } 761 762 /* 763 * Save PHY address. 764 * Integrated JR0211 has fixed PHY address whereas FPGA version 765 * requires PHY probing to get correct PHY address. 766 */ 767 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 768 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 769 GPREG0_PHY_ADDR_MASK; 770 if (bootverbose) 771 device_printf(dev, "PHY is at address %d.\n", 772 sc->jme_phyaddr); 773 } else 774 sc->jme_phyaddr = 0; 775 776 /* Set max allowable DMA size. */ 777 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 778 sc->jme_flags |= JME_FLAG_PCIE; 779 burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 780 if (bootverbose) { 781 device_printf(dev, "Read request size : %d bytes.\n", 782 128 << ((burst >> 12) & 0x07)); 783 device_printf(dev, "TLP payload size : %d bytes.\n", 784 128 << ((burst >> 5) & 0x07)); 785 } 786 switch ((burst >> 12) & 0x07) { 787 case 0: 788 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 789 break; 790 case 1: 791 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 792 break; 793 default: 794 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 795 break; 796 } 797 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 798 } else { 799 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 800 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 801 } 802 /* Create coalescing sysctl node. */ 803 jme_sysctl_node(sc); 804 if ((error = jme_dma_alloc(sc)) != 0) 805 goto fail; 806 807 ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 808 if (ifp == NULL) { 809 device_printf(dev, "cannot allocate ifnet structure.\n"); 810 error = ENXIO; 811 goto fail; 812 } 813 814 if_setsoftc(ifp, sc); 815 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 816 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 817 if_setioctlfn(ifp, jme_ioctl); 818 if_setstartfn(ifp, jme_start); 819 if_setinitfn(ifp, jme_init); 820 if_setsendqlen(ifp, JME_TX_RING_CNT - 1); 821 if_setsendqready(ifp); 822 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 823 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 824 if_sethwassist(ifp, JME_CSUM_FEATURES | CSUM_TSO); 825 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 826 sc->jme_flags |= JME_FLAG_PMCAP; 827 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 828 } 829 if_setcapenable(ifp, if_getcapabilities(ifp)); 830 831 /* Wakeup PHY. */ 832 jme_phy_up(sc); 833 mii_flags = MIIF_DOPAUSE; 834 /* Ask PHY calibration to PHY driver. */ 835 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 836 mii_flags |= MIIF_MACPRIV0; 837 /* Set up MII bus. */ 838 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange, 839 jme_mediastatus, BMSR_DEFCAPMASK, 840 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr, 841 MII_OFFSET_ANY, mii_flags); 842 if (error != 0) { 843 device_printf(dev, "attaching PHYs failed\n"); 844 goto fail; 845 } 846 847 /* 848 * Force PHY to FPGA mode. 849 */ 850 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 851 mii = device_get_softc(sc->jme_miibus); 852 if (mii->mii_instance != 0) { 853 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 854 if (miisc->mii_phy != 0) { 855 sc->jme_phyaddr = miisc->mii_phy; 856 break; 857 } 858 } 859 if (sc->jme_phyaddr != 0) { 860 device_printf(sc->jme_dev, 861 "FPGA PHY is at %d\n", sc->jme_phyaddr); 862 /* vendor magic. */ 863 jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 864 0x0004); 865 } 866 } 867 } 868 869 ether_ifattach(ifp, sc->jme_eaddr); 870 871 /* VLAN capability setup */ 872 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 873 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 874 if_setcapenable(ifp, if_getcapabilities(ifp)); 875 876 /* Tell the upper layer(s) we support long frames. */ 877 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 878 879 /* Create local taskq. */ 880 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 881 taskqueue_thread_enqueue, &sc->jme_tq); 882 if (sc->jme_tq == NULL) { 883 device_printf(dev, "could not create taskqueue.\n"); 884 ether_ifdetach(ifp); 885 error = ENXIO; 886 goto fail; 887 } 888 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 889 device_get_nameunit(sc->jme_dev)); 890 891 for (i = 0; i < 1; i++) { 892 error = bus_setup_intr(dev, sc->jme_irq[i], 893 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 894 &sc->jme_intrhand[i]); 895 if (error != 0) 896 break; 897 } 898 899 if (error != 0) { 900 device_printf(dev, "could not set up interrupt handler.\n"); 901 taskqueue_free(sc->jme_tq); 902 sc->jme_tq = NULL; 903 ether_ifdetach(ifp); 904 goto fail; 905 } 906 907 fail: 908 if (error != 0) 909 jme_detach(dev); 910 911 return (error); 912 } 913 914 static int 915 jme_detach(device_t dev) 916 { 917 struct jme_softc *sc; 918 if_t ifp; 919 int i; 920 921 sc = device_get_softc(dev); 922 923 ifp = sc->jme_ifp; 924 if (device_is_attached(dev)) { 925 JME_LOCK(sc); 926 sc->jme_flags |= JME_FLAG_DETACH; 927 jme_stop(sc); 928 JME_UNLOCK(sc); 929 callout_drain(&sc->jme_tick_ch); 930 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 931 taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 932 /* Restore possibly modified station address. */ 933 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) 934 jme_set_macaddr(sc, sc->jme_eaddr); 935 ether_ifdetach(ifp); 936 } 937 938 if (sc->jme_tq != NULL) { 939 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 940 taskqueue_free(sc->jme_tq); 941 sc->jme_tq = NULL; 942 } 943 944 if (sc->jme_miibus != NULL) { 945 device_delete_child(dev, sc->jme_miibus); 946 sc->jme_miibus = NULL; 947 } 948 bus_generic_detach(dev); 949 jme_dma_free(sc); 950 951 if (ifp != NULL) { 952 if_free(ifp); 953 sc->jme_ifp = NULL; 954 } 955 956 for (i = 0; i < 1; i++) { 957 if (sc->jme_intrhand[i] != NULL) { 958 bus_teardown_intr(dev, sc->jme_irq[i], 959 sc->jme_intrhand[i]); 960 sc->jme_intrhand[i] = NULL; 961 } 962 } 963 964 if (sc->jme_irq[0] != NULL) 965 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 966 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 967 pci_release_msi(dev); 968 if (sc->jme_res[0] != NULL) 969 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 970 mtx_destroy(&sc->jme_mtx); 971 972 return (0); 973 } 974 975 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 976 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 977 978 static void 979 jme_sysctl_node(struct jme_softc *sc) 980 { 981 struct sysctl_ctx_list *ctx; 982 struct sysctl_oid_list *child, *parent; 983 struct sysctl_oid *tree; 984 struct jme_hw_stats *stats; 985 int error; 986 987 stats = &sc->jme_stats; 988 ctx = device_get_sysctl_ctx(sc->jme_dev); 989 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)); 990 991 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to", 992 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_tx_coal_to, 993 0, sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 994 995 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", 996 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_tx_coal_pkt, 997 0, sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 998 999 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to", 1000 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_rx_coal_to, 1001 0, sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 1002 1003 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", 1004 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_rx_coal_pkt, 1005 0, sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 1006 1007 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1008 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1009 &sc->jme_process_limit, 0, sysctl_hw_jme_proc_limit, "I", 1010 "max number of Rx events to process"); 1011 1012 /* Pull in device tunables. */ 1013 sc->jme_process_limit = JME_PROC_DEFAULT; 1014 error = resource_int_value(device_get_name(sc->jme_dev), 1015 device_get_unit(sc->jme_dev), "process_limit", 1016 &sc->jme_process_limit); 1017 if (error == 0) { 1018 if (sc->jme_process_limit < JME_PROC_MIN || 1019 sc->jme_process_limit > JME_PROC_MAX) { 1020 device_printf(sc->jme_dev, 1021 "process_limit value out of range; " 1022 "using default: %d\n", JME_PROC_DEFAULT); 1023 sc->jme_process_limit = JME_PROC_DEFAULT; 1024 } 1025 } 1026 1027 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1028 error = resource_int_value(device_get_name(sc->jme_dev), 1029 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 1030 if (error == 0) { 1031 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 1032 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 1033 device_printf(sc->jme_dev, 1034 "tx_coal_to value out of range; " 1035 "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 1036 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1037 } 1038 } 1039 1040 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1041 error = resource_int_value(device_get_name(sc->jme_dev), 1042 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 1043 if (error == 0) { 1044 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 1045 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 1046 device_printf(sc->jme_dev, 1047 "tx_coal_pkt value out of range; " 1048 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 1049 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1050 } 1051 } 1052 1053 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1054 error = resource_int_value(device_get_name(sc->jme_dev), 1055 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 1056 if (error == 0) { 1057 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 1058 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 1059 device_printf(sc->jme_dev, 1060 "rx_coal_to value out of range; " 1061 "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 1062 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1063 } 1064 } 1065 1066 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1067 error = resource_int_value(device_get_name(sc->jme_dev), 1068 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 1069 if (error == 0) { 1070 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 1071 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 1072 device_printf(sc->jme_dev, 1073 "tx_coal_pkt value out of range; " 1074 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 1075 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1076 } 1077 } 1078 1079 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 1080 return; 1081 1082 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1083 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "JME statistics"); 1084 parent = SYSCTL_CHILDREN(tree); 1085 1086 /* Rx statistics. */ 1087 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1088 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1089 child = SYSCTL_CHILDREN(tree); 1090 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1091 &stats->rx_good_frames, "Good frames"); 1092 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1093 &stats->rx_crc_errs, "CRC errors"); 1094 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs", 1095 &stats->rx_mii_errs, "MII errors"); 1096 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1097 &stats->rx_fifo_oflows, "FIFO overflows"); 1098 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty", 1099 &stats->rx_desc_empty, "Descriptor empty"); 1100 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1101 &stats->rx_bad_frames, "Bad frames"); 1102 1103 /* Tx statistics. */ 1104 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1105 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1106 child = SYSCTL_CHILDREN(tree); 1107 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1108 &stats->tx_good_frames, "Good frames"); 1109 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1110 &stats->tx_bad_frames, "Bad frames"); 1111 } 1112 1113 #undef JME_SYSCTL_STAT_ADD32 1114 1115 struct jme_dmamap_arg { 1116 bus_addr_t jme_busaddr; 1117 }; 1118 1119 static void 1120 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1121 { 1122 struct jme_dmamap_arg *ctx; 1123 1124 if (error != 0) 1125 return; 1126 1127 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1128 1129 ctx = (struct jme_dmamap_arg *)arg; 1130 ctx->jme_busaddr = segs[0].ds_addr; 1131 } 1132 1133 static int 1134 jme_dma_alloc(struct jme_softc *sc) 1135 { 1136 struct jme_dmamap_arg ctx; 1137 struct jme_txdesc *txd; 1138 struct jme_rxdesc *rxd; 1139 bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1140 int error, i; 1141 1142 lowaddr = BUS_SPACE_MAXADDR; 1143 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1144 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1145 1146 again: 1147 /* Create parent ring tag. */ 1148 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1149 1, 0, /* algnmnt, boundary */ 1150 lowaddr, /* lowaddr */ 1151 BUS_SPACE_MAXADDR, /* highaddr */ 1152 NULL, NULL, /* filter, filterarg */ 1153 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1154 0, /* nsegments */ 1155 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1156 0, /* flags */ 1157 NULL, NULL, /* lockfunc, lockarg */ 1158 &sc->jme_cdata.jme_ring_tag); 1159 if (error != 0) { 1160 device_printf(sc->jme_dev, 1161 "could not create parent ring DMA tag.\n"); 1162 goto fail; 1163 } 1164 /* Create tag for Tx ring. */ 1165 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1166 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1167 BUS_SPACE_MAXADDR, /* lowaddr */ 1168 BUS_SPACE_MAXADDR, /* highaddr */ 1169 NULL, NULL, /* filter, filterarg */ 1170 JME_TX_RING_SIZE, /* maxsize */ 1171 1, /* nsegments */ 1172 JME_TX_RING_SIZE, /* maxsegsize */ 1173 0, /* flags */ 1174 NULL, NULL, /* lockfunc, lockarg */ 1175 &sc->jme_cdata.jme_tx_ring_tag); 1176 if (error != 0) { 1177 device_printf(sc->jme_dev, 1178 "could not allocate Tx ring DMA tag.\n"); 1179 goto fail; 1180 } 1181 1182 /* Create tag for Rx ring. */ 1183 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1184 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1185 lowaddr, /* lowaddr */ 1186 BUS_SPACE_MAXADDR, /* highaddr */ 1187 NULL, NULL, /* filter, filterarg */ 1188 JME_RX_RING_SIZE, /* maxsize */ 1189 1, /* nsegments */ 1190 JME_RX_RING_SIZE, /* maxsegsize */ 1191 0, /* flags */ 1192 NULL, NULL, /* lockfunc, lockarg */ 1193 &sc->jme_cdata.jme_rx_ring_tag); 1194 if (error != 0) { 1195 device_printf(sc->jme_dev, 1196 "could not allocate Rx ring DMA tag.\n"); 1197 goto fail; 1198 } 1199 1200 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1201 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1202 (void **)&sc->jme_rdata.jme_tx_ring, 1203 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1204 &sc->jme_cdata.jme_tx_ring_map); 1205 if (error != 0) { 1206 device_printf(sc->jme_dev, 1207 "could not allocate DMA'able memory for Tx ring.\n"); 1208 goto fail; 1209 } 1210 1211 ctx.jme_busaddr = 0; 1212 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1213 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1214 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1215 if (error != 0 || ctx.jme_busaddr == 0) { 1216 device_printf(sc->jme_dev, 1217 "could not load DMA'able memory for Tx ring.\n"); 1218 goto fail; 1219 } 1220 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1221 1222 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1223 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1224 (void **)&sc->jme_rdata.jme_rx_ring, 1225 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1226 &sc->jme_cdata.jme_rx_ring_map); 1227 if (error != 0) { 1228 device_printf(sc->jme_dev, 1229 "could not allocate DMA'able memory for Rx ring.\n"); 1230 goto fail; 1231 } 1232 1233 ctx.jme_busaddr = 0; 1234 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1235 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1236 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1237 if (error != 0 || ctx.jme_busaddr == 0) { 1238 device_printf(sc->jme_dev, 1239 "could not load DMA'able memory for Rx ring.\n"); 1240 goto fail; 1241 } 1242 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1243 1244 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1245 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1246 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1247 JME_TX_RING_SIZE; 1248 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1249 JME_RX_RING_SIZE; 1250 if ((JME_ADDR_HI(tx_ring_end) != 1251 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1252 (JME_ADDR_HI(rx_ring_end) != 1253 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1254 device_printf(sc->jme_dev, "4GB boundary crossed, " 1255 "switching to 32bit DMA address mode.\n"); 1256 jme_dma_free(sc); 1257 /* Limit DMA address space to 32bit and try again. */ 1258 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1259 goto again; 1260 } 1261 } 1262 1263 lowaddr = BUS_SPACE_MAXADDR; 1264 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1265 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1266 /* Create parent buffer tag. */ 1267 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1268 1, 0, /* algnmnt, boundary */ 1269 lowaddr, /* lowaddr */ 1270 BUS_SPACE_MAXADDR, /* highaddr */ 1271 NULL, NULL, /* filter, filterarg */ 1272 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1273 0, /* nsegments */ 1274 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1275 0, /* flags */ 1276 NULL, NULL, /* lockfunc, lockarg */ 1277 &sc->jme_cdata.jme_buffer_tag); 1278 if (error != 0) { 1279 device_printf(sc->jme_dev, 1280 "could not create parent buffer DMA tag.\n"); 1281 goto fail; 1282 } 1283 1284 /* Create shadow status block tag. */ 1285 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1286 JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1287 BUS_SPACE_MAXADDR, /* lowaddr */ 1288 BUS_SPACE_MAXADDR, /* highaddr */ 1289 NULL, NULL, /* filter, filterarg */ 1290 JME_SSB_SIZE, /* maxsize */ 1291 1, /* nsegments */ 1292 JME_SSB_SIZE, /* maxsegsize */ 1293 0, /* flags */ 1294 NULL, NULL, /* lockfunc, lockarg */ 1295 &sc->jme_cdata.jme_ssb_tag); 1296 if (error != 0) { 1297 device_printf(sc->jme_dev, 1298 "could not create shared status block DMA tag.\n"); 1299 goto fail; 1300 } 1301 1302 /* Create tag for Tx buffers. */ 1303 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1304 1, 0, /* algnmnt, boundary */ 1305 BUS_SPACE_MAXADDR, /* lowaddr */ 1306 BUS_SPACE_MAXADDR, /* highaddr */ 1307 NULL, NULL, /* filter, filterarg */ 1308 JME_TSO_MAXSIZE, /* maxsize */ 1309 JME_MAXTXSEGS, /* nsegments */ 1310 JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1311 0, /* flags */ 1312 NULL, NULL, /* lockfunc, lockarg */ 1313 &sc->jme_cdata.jme_tx_tag); 1314 if (error != 0) { 1315 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1316 goto fail; 1317 } 1318 1319 /* Create tag for Rx buffers. */ 1320 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1321 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1322 BUS_SPACE_MAXADDR, /* lowaddr */ 1323 BUS_SPACE_MAXADDR, /* highaddr */ 1324 NULL, NULL, /* filter, filterarg */ 1325 MCLBYTES, /* maxsize */ 1326 1, /* nsegments */ 1327 MCLBYTES, /* maxsegsize */ 1328 0, /* flags */ 1329 NULL, NULL, /* lockfunc, lockarg */ 1330 &sc->jme_cdata.jme_rx_tag); 1331 if (error != 0) { 1332 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1333 goto fail; 1334 } 1335 1336 /* 1337 * Allocate DMA'able memory and load the DMA map for shared 1338 * status block. 1339 */ 1340 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1341 (void **)&sc->jme_rdata.jme_ssb_block, 1342 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1343 &sc->jme_cdata.jme_ssb_map); 1344 if (error != 0) { 1345 device_printf(sc->jme_dev, "could not allocate DMA'able " 1346 "memory for shared status block.\n"); 1347 goto fail; 1348 } 1349 1350 ctx.jme_busaddr = 0; 1351 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1352 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1353 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1354 if (error != 0 || ctx.jme_busaddr == 0) { 1355 device_printf(sc->jme_dev, "could not load DMA'able memory " 1356 "for shared status block.\n"); 1357 goto fail; 1358 } 1359 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1360 1361 /* Create DMA maps for Tx buffers. */ 1362 for (i = 0; i < JME_TX_RING_CNT; i++) { 1363 txd = &sc->jme_cdata.jme_txdesc[i]; 1364 txd->tx_m = NULL; 1365 txd->tx_dmamap = NULL; 1366 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1367 &txd->tx_dmamap); 1368 if (error != 0) { 1369 device_printf(sc->jme_dev, 1370 "could not create Tx dmamap.\n"); 1371 goto fail; 1372 } 1373 } 1374 /* Create DMA maps for Rx buffers. */ 1375 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1376 &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1377 device_printf(sc->jme_dev, 1378 "could not create spare Rx dmamap.\n"); 1379 goto fail; 1380 } 1381 for (i = 0; i < JME_RX_RING_CNT; i++) { 1382 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1383 rxd->rx_m = NULL; 1384 rxd->rx_dmamap = NULL; 1385 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1386 &rxd->rx_dmamap); 1387 if (error != 0) { 1388 device_printf(sc->jme_dev, 1389 "could not create Rx dmamap.\n"); 1390 goto fail; 1391 } 1392 } 1393 1394 fail: 1395 return (error); 1396 } 1397 1398 static void 1399 jme_dma_free(struct jme_softc *sc) 1400 { 1401 struct jme_txdesc *txd; 1402 struct jme_rxdesc *rxd; 1403 int i; 1404 1405 /* Tx ring */ 1406 if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1407 if (sc->jme_rdata.jme_tx_ring_paddr) 1408 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1409 sc->jme_cdata.jme_tx_ring_map); 1410 if (sc->jme_rdata.jme_tx_ring) 1411 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1412 sc->jme_rdata.jme_tx_ring, 1413 sc->jme_cdata.jme_tx_ring_map); 1414 sc->jme_rdata.jme_tx_ring = NULL; 1415 sc->jme_rdata.jme_tx_ring_paddr = 0; 1416 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1417 sc->jme_cdata.jme_tx_ring_tag = NULL; 1418 } 1419 /* Rx ring */ 1420 if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1421 if (sc->jme_rdata.jme_rx_ring_paddr) 1422 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1423 sc->jme_cdata.jme_rx_ring_map); 1424 if (sc->jme_rdata.jme_rx_ring) 1425 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1426 sc->jme_rdata.jme_rx_ring, 1427 sc->jme_cdata.jme_rx_ring_map); 1428 sc->jme_rdata.jme_rx_ring = NULL; 1429 sc->jme_rdata.jme_rx_ring_paddr = 0; 1430 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1431 sc->jme_cdata.jme_rx_ring_tag = NULL; 1432 } 1433 /* Tx buffers */ 1434 if (sc->jme_cdata.jme_tx_tag != NULL) { 1435 for (i = 0; i < JME_TX_RING_CNT; i++) { 1436 txd = &sc->jme_cdata.jme_txdesc[i]; 1437 if (txd->tx_dmamap != NULL) { 1438 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1439 txd->tx_dmamap); 1440 txd->tx_dmamap = NULL; 1441 } 1442 } 1443 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1444 sc->jme_cdata.jme_tx_tag = NULL; 1445 } 1446 /* Rx buffers */ 1447 if (sc->jme_cdata.jme_rx_tag != NULL) { 1448 for (i = 0; i < JME_RX_RING_CNT; i++) { 1449 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1450 if (rxd->rx_dmamap != NULL) { 1451 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1452 rxd->rx_dmamap); 1453 rxd->rx_dmamap = NULL; 1454 } 1455 } 1456 if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1457 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1458 sc->jme_cdata.jme_rx_sparemap); 1459 sc->jme_cdata.jme_rx_sparemap = NULL; 1460 } 1461 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1462 sc->jme_cdata.jme_rx_tag = NULL; 1463 } 1464 1465 /* Shared status block. */ 1466 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1467 if (sc->jme_rdata.jme_ssb_block_paddr) 1468 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1469 sc->jme_cdata.jme_ssb_map); 1470 if (sc->jme_rdata.jme_ssb_block) 1471 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1472 sc->jme_rdata.jme_ssb_block, 1473 sc->jme_cdata.jme_ssb_map); 1474 sc->jme_rdata.jme_ssb_block = NULL; 1475 sc->jme_rdata.jme_ssb_block_paddr = 0; 1476 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1477 sc->jme_cdata.jme_ssb_tag = NULL; 1478 } 1479 1480 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1481 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1482 sc->jme_cdata.jme_buffer_tag = NULL; 1483 } 1484 if (sc->jme_cdata.jme_ring_tag != NULL) { 1485 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1486 sc->jme_cdata.jme_ring_tag = NULL; 1487 } 1488 } 1489 1490 /* 1491 * Make sure the interface is stopped at reboot time. 1492 */ 1493 static int 1494 jme_shutdown(device_t dev) 1495 { 1496 1497 return (jme_suspend(dev)); 1498 } 1499 1500 /* 1501 * Unlike other ethernet controllers, JMC250 requires 1502 * explicit resetting link speed to 10/100Mbps as gigabit 1503 * link will cunsume more power than 375mA. 1504 * Note, we reset the link speed to 10/100Mbps with 1505 * auto-negotiation but we don't know whether that operation 1506 * would succeed or not as we have no control after powering 1507 * off. If the renegotiation fail WOL may not work. Running 1508 * at 1Gbps draws more power than 375mA at 3.3V which is 1509 * specified in PCI specification and that would result in 1510 * complete shutdowning power to ethernet controller. 1511 * 1512 * TODO 1513 * Save current negotiated media speed/duplex/flow-control 1514 * to softc and restore the same link again after resuming. 1515 * PHY handling such as power down/resetting to 100Mbps 1516 * may be better handled in suspend method in phy driver. 1517 */ 1518 static void 1519 jme_setlinkspeed(struct jme_softc *sc) 1520 { 1521 struct mii_data *mii; 1522 int aneg, i; 1523 1524 JME_LOCK_ASSERT(sc); 1525 1526 mii = device_get_softc(sc->jme_miibus); 1527 mii_pollstat(mii); 1528 aneg = 0; 1529 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1530 switch IFM_SUBTYPE(mii->mii_media_active) { 1531 case IFM_10_T: 1532 case IFM_100_TX: 1533 return; 1534 case IFM_1000_T: 1535 aneg++; 1536 default: 1537 break; 1538 } 1539 } 1540 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1541 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1542 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1543 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1544 BMCR_AUTOEN | BMCR_STARTNEG); 1545 DELAY(1000); 1546 if (aneg != 0) { 1547 /* Poll link state until jme(4) get a 10/100 link. */ 1548 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1549 mii_pollstat(mii); 1550 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1551 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1552 case IFM_10_T: 1553 case IFM_100_TX: 1554 jme_mac_config(sc); 1555 return; 1556 default: 1557 break; 1558 } 1559 } 1560 JME_UNLOCK(sc); 1561 pause("jmelnk", hz); 1562 JME_LOCK(sc); 1563 } 1564 if (i == MII_ANEGTICKS_GIGE) 1565 device_printf(sc->jme_dev, "establishing link failed, " 1566 "WOL may not work!"); 1567 } 1568 /* 1569 * No link, force MAC to have 100Mbps, full-duplex link. 1570 * This is the last resort and may/may not work. 1571 */ 1572 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1573 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1574 jme_mac_config(sc); 1575 } 1576 1577 static void 1578 jme_setwol(struct jme_softc *sc) 1579 { 1580 if_t ifp; 1581 uint32_t gpr, pmcs; 1582 uint16_t pmstat; 1583 int pmc; 1584 1585 JME_LOCK_ASSERT(sc); 1586 1587 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1588 /* Remove Tx MAC/offload clock to save more power. */ 1589 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1590 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1591 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1592 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1593 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 1594 CSR_WRITE_4(sc, JME_GPREG1, 1595 CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS); 1596 /* No PME capability, PHY power down. */ 1597 jme_phy_down(sc); 1598 return; 1599 } 1600 1601 ifp = sc->jme_ifp; 1602 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1603 pmcs = CSR_READ_4(sc, JME_PMCS); 1604 pmcs &= ~PMCS_WOL_ENB_MASK; 1605 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 1606 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1607 /* Enable PME message. */ 1608 gpr |= GPREG0_PME_ENB; 1609 /* For gigabit controllers, reset link speed to 10/100. */ 1610 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1611 jme_setlinkspeed(sc); 1612 } 1613 1614 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1615 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1616 /* Remove Tx MAC/offload clock to save more power. */ 1617 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1618 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1619 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1620 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1621 /* Request PME. */ 1622 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1623 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1624 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1625 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1626 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1627 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1628 /* No WOL, PHY power down. */ 1629 jme_phy_down(sc); 1630 } 1631 } 1632 1633 static int 1634 jme_suspend(device_t dev) 1635 { 1636 struct jme_softc *sc; 1637 1638 sc = device_get_softc(dev); 1639 1640 JME_LOCK(sc); 1641 jme_stop(sc); 1642 jme_setwol(sc); 1643 JME_UNLOCK(sc); 1644 1645 return (0); 1646 } 1647 1648 static int 1649 jme_resume(device_t dev) 1650 { 1651 struct jme_softc *sc; 1652 if_t ifp; 1653 uint16_t pmstat; 1654 int pmc; 1655 1656 sc = device_get_softc(dev); 1657 1658 JME_LOCK(sc); 1659 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) == 0) { 1660 pmstat = pci_read_config(sc->jme_dev, 1661 pmc + PCIR_POWER_STATUS, 2); 1662 /* Disable PME clear PME status. */ 1663 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1664 pci_write_config(sc->jme_dev, 1665 pmc + PCIR_POWER_STATUS, pmstat, 2); 1666 } 1667 /* Wakeup PHY. */ 1668 jme_phy_up(sc); 1669 ifp = sc->jme_ifp; 1670 if ((if_getflags(ifp) & IFF_UP) != 0) { 1671 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1672 jme_init_locked(sc); 1673 } 1674 1675 JME_UNLOCK(sc); 1676 1677 return (0); 1678 } 1679 1680 static int 1681 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1682 { 1683 struct jme_txdesc *txd; 1684 struct jme_desc *desc; 1685 struct mbuf *m; 1686 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1687 int error, i, nsegs, prod; 1688 uint32_t cflags, tsosegsz; 1689 1690 JME_LOCK_ASSERT(sc); 1691 1692 M_ASSERTPKTHDR((*m_head)); 1693 1694 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1695 /* 1696 * Due to the adherence to NDIS specification JMC250 1697 * assumes upper stack computed TCP pseudo checksum 1698 * without including payload length. This breaks 1699 * checksum offload for TSO case so recompute TCP 1700 * pseudo checksum for JMC250. Hopefully this wouldn't 1701 * be much burden on modern CPUs. 1702 */ 1703 struct ether_header *eh; 1704 struct ip *ip; 1705 struct tcphdr *tcp; 1706 uint32_t ip_off, poff; 1707 1708 if (M_WRITABLE(*m_head) == 0) { 1709 /* Get a writable copy. */ 1710 m = m_dup(*m_head, M_NOWAIT); 1711 m_freem(*m_head); 1712 if (m == NULL) { 1713 *m_head = NULL; 1714 return (ENOBUFS); 1715 } 1716 *m_head = m; 1717 } 1718 ip_off = sizeof(struct ether_header); 1719 m = m_pullup(*m_head, ip_off); 1720 if (m == NULL) { 1721 *m_head = NULL; 1722 return (ENOBUFS); 1723 } 1724 eh = mtod(m, struct ether_header *); 1725 /* Check the existence of VLAN tag. */ 1726 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1727 ip_off = sizeof(struct ether_vlan_header); 1728 m = m_pullup(m, ip_off); 1729 if (m == NULL) { 1730 *m_head = NULL; 1731 return (ENOBUFS); 1732 } 1733 } 1734 m = m_pullup(m, ip_off + sizeof(struct ip)); 1735 if (m == NULL) { 1736 *m_head = NULL; 1737 return (ENOBUFS); 1738 } 1739 ip = (struct ip *)(mtod(m, char *) + ip_off); 1740 poff = ip_off + (ip->ip_hl << 2); 1741 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1742 if (m == NULL) { 1743 *m_head = NULL; 1744 return (ENOBUFS); 1745 } 1746 /* 1747 * Reset IP checksum and recompute TCP pseudo 1748 * checksum that NDIS specification requires. 1749 */ 1750 ip = (struct ip *)(mtod(m, char *) + ip_off); 1751 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1752 ip->ip_sum = 0; 1753 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1754 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1755 ip->ip_dst.s_addr, 1756 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1757 /* No need to TSO, force IP checksum offload. */ 1758 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1759 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1760 } else 1761 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1762 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1763 *m_head = m; 1764 } 1765 1766 prod = sc->jme_cdata.jme_tx_prod; 1767 txd = &sc->jme_cdata.jme_txdesc[prod]; 1768 1769 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1770 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1771 if (error == EFBIG) { 1772 m = m_collapse(*m_head, M_NOWAIT, JME_MAXTXSEGS); 1773 if (m == NULL) { 1774 m_freem(*m_head); 1775 *m_head = NULL; 1776 return (ENOMEM); 1777 } 1778 *m_head = m; 1779 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1780 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1781 if (error != 0) { 1782 m_freem(*m_head); 1783 *m_head = NULL; 1784 return (error); 1785 } 1786 } else if (error != 0) 1787 return (error); 1788 if (nsegs == 0) { 1789 m_freem(*m_head); 1790 *m_head = NULL; 1791 return (EIO); 1792 } 1793 1794 /* 1795 * Check descriptor overrun. Leave one free descriptor. 1796 * Since we always use 64bit address mode for transmitting, 1797 * each Tx request requires one more dummy descriptor. 1798 */ 1799 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1800 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1801 return (ENOBUFS); 1802 } 1803 1804 m = *m_head; 1805 cflags = 0; 1806 tsosegsz = 0; 1807 /* Configure checksum offload and TSO. */ 1808 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1809 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 1810 JME_TD_MSS_SHIFT; 1811 cflags |= JME_TD_TSO; 1812 } else { 1813 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1814 cflags |= JME_TD_IPCSUM; 1815 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1816 cflags |= JME_TD_TCPCSUM; 1817 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1818 cflags |= JME_TD_UDPCSUM; 1819 } 1820 /* Configure VLAN. */ 1821 if ((m->m_flags & M_VLANTAG) != 0) { 1822 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1823 cflags |= JME_TD_VLAN_TAG; 1824 } 1825 1826 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1827 desc->flags = htole32(cflags); 1828 desc->buflen = htole32(tsosegsz); 1829 desc->addr_hi = htole32(m->m_pkthdr.len); 1830 desc->addr_lo = 0; 1831 sc->jme_cdata.jme_tx_cnt++; 1832 JME_DESC_INC(prod, JME_TX_RING_CNT); 1833 for (i = 0; i < nsegs; i++) { 1834 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1835 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1836 desc->buflen = htole32(txsegs[i].ds_len); 1837 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1838 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1839 sc->jme_cdata.jme_tx_cnt++; 1840 JME_DESC_INC(prod, JME_TX_RING_CNT); 1841 } 1842 1843 /* Update producer index. */ 1844 sc->jme_cdata.jme_tx_prod = prod; 1845 /* 1846 * Finally request interrupt and give the first descriptor 1847 * owenership to hardware. 1848 */ 1849 desc = txd->tx_desc; 1850 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1851 1852 txd->tx_m = m; 1853 txd->tx_ndesc = nsegs + 1; 1854 1855 /* Sync descriptors. */ 1856 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1857 BUS_DMASYNC_PREWRITE); 1858 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1859 sc->jme_cdata.jme_tx_ring_map, 1860 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1861 1862 return (0); 1863 } 1864 1865 static void 1866 jme_start(if_t ifp) 1867 { 1868 struct jme_softc *sc; 1869 1870 sc = if_getsoftc(ifp); 1871 JME_LOCK(sc); 1872 jme_start_locked(ifp); 1873 JME_UNLOCK(sc); 1874 } 1875 1876 static void 1877 jme_start_locked(if_t ifp) 1878 { 1879 struct jme_softc *sc; 1880 struct mbuf *m_head; 1881 int enq; 1882 1883 sc = if_getsoftc(ifp); 1884 1885 JME_LOCK_ASSERT(sc); 1886 1887 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1888 jme_txeof(sc); 1889 1890 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1891 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) 1892 return; 1893 1894 for (enq = 0; !if_sendq_empty(ifp); ) { 1895 m_head = if_dequeue(ifp); 1896 if (m_head == NULL) 1897 break; 1898 /* 1899 * Pack the data into the transmit ring. If we 1900 * don't have room, set the OACTIVE flag and wait 1901 * for the NIC to drain the ring. 1902 */ 1903 if (jme_encap(sc, &m_head)) { 1904 if (m_head == NULL) 1905 break; 1906 if_sendq_prepend(ifp, m_head); 1907 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1908 break; 1909 } 1910 1911 enq++; 1912 /* 1913 * If there's a BPF listener, bounce a copy of this frame 1914 * to him. 1915 */ 1916 ETHER_BPF_MTAP(ifp, m_head); 1917 } 1918 1919 if (enq > 0) { 1920 /* 1921 * Reading TXCSR takes very long time under heavy load 1922 * so cache TXCSR value and writes the ORed value with 1923 * the kick command to the TXCSR. This saves one register 1924 * access cycle. 1925 */ 1926 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1927 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1928 /* Set a timeout in case the chip goes out to lunch. */ 1929 sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1930 } 1931 } 1932 1933 static void 1934 jme_watchdog(struct jme_softc *sc) 1935 { 1936 if_t ifp; 1937 1938 JME_LOCK_ASSERT(sc); 1939 1940 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1941 return; 1942 1943 ifp = sc->jme_ifp; 1944 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1945 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1946 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1947 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1948 jme_init_locked(sc); 1949 return; 1950 } 1951 jme_txeof(sc); 1952 if (sc->jme_cdata.jme_tx_cnt == 0) { 1953 if_printf(sc->jme_ifp, 1954 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1955 if (!if_sendq_empty(ifp)) 1956 jme_start_locked(ifp); 1957 return; 1958 } 1959 1960 if_printf(sc->jme_ifp, "watchdog timeout\n"); 1961 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1962 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1963 jme_init_locked(sc); 1964 if (!if_sendq_empty(ifp)) 1965 jme_start_locked(ifp); 1966 } 1967 1968 static int 1969 jme_ioctl(if_t ifp, u_long cmd, caddr_t data) 1970 { 1971 struct jme_softc *sc; 1972 struct ifreq *ifr; 1973 struct mii_data *mii; 1974 uint32_t reg; 1975 int error, mask; 1976 1977 sc = if_getsoftc(ifp); 1978 ifr = (struct ifreq *)data; 1979 error = 0; 1980 switch (cmd) { 1981 case SIOCSIFMTU: 1982 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1983 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1984 ifr->ifr_mtu > JME_MAX_MTU)) { 1985 error = EINVAL; 1986 break; 1987 } 1988 1989 if (if_getmtu(ifp) != ifr->ifr_mtu) { 1990 /* 1991 * No special configuration is required when interface 1992 * MTU is changed but availability of TSO/Tx checksum 1993 * offload should be chcked against new MTU size as 1994 * FIFO size is just 2K. 1995 */ 1996 JME_LOCK(sc); 1997 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1998 if_setcapenablebit(ifp, 0, 1999 IFCAP_TXCSUM | IFCAP_TSO4); 2000 if_sethwassistbits(ifp, 0, 2001 JME_CSUM_FEATURES | CSUM_TSO); 2002 VLAN_CAPABILITIES(ifp); 2003 } 2004 if_setmtu(ifp, ifr->ifr_mtu); 2005 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2006 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2007 jme_init_locked(sc); 2008 } 2009 JME_UNLOCK(sc); 2010 } 2011 break; 2012 case SIOCSIFFLAGS: 2013 JME_LOCK(sc); 2014 if ((if_getflags(ifp) & IFF_UP) != 0) { 2015 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2016 if (((if_getflags(ifp) ^ sc->jme_if_flags) 2017 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2018 jme_set_filter(sc); 2019 } else { 2020 if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 2021 jme_init_locked(sc); 2022 } 2023 } else { 2024 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2025 jme_stop(sc); 2026 } 2027 sc->jme_if_flags = if_getflags(ifp); 2028 JME_UNLOCK(sc); 2029 break; 2030 case SIOCADDMULTI: 2031 case SIOCDELMULTI: 2032 JME_LOCK(sc); 2033 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2034 jme_set_filter(sc); 2035 JME_UNLOCK(sc); 2036 break; 2037 case SIOCSIFMEDIA: 2038 case SIOCGIFMEDIA: 2039 mii = device_get_softc(sc->jme_miibus); 2040 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2041 break; 2042 case SIOCSIFCAP: 2043 JME_LOCK(sc); 2044 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2045 if ((mask & IFCAP_TXCSUM) != 0 && 2046 if_getmtu(ifp) < JME_TX_FIFO_SIZE) { 2047 if ((IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 2048 if_togglecapenable(ifp, IFCAP_TXCSUM); 2049 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 2050 if_sethwassistbits(ifp, JME_CSUM_FEATURES, 0); 2051 else 2052 if_sethwassistbits(ifp, 0, JME_CSUM_FEATURES); 2053 } 2054 } 2055 if ((mask & IFCAP_RXCSUM) != 0 && 2056 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) { 2057 if_togglecapenable(ifp, IFCAP_RXCSUM); 2058 reg = CSR_READ_4(sc, JME_RXMAC); 2059 reg &= ~RXMAC_CSUM_ENB; 2060 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2061 reg |= RXMAC_CSUM_ENB; 2062 CSR_WRITE_4(sc, JME_RXMAC, reg); 2063 } 2064 if ((mask & IFCAP_TSO4) != 0 && 2065 if_getmtu(ifp) < JME_TX_FIFO_SIZE) { 2066 if ((IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) { 2067 if_togglecapenable(ifp, IFCAP_TSO4); 2068 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 2069 if_sethwassistbits(ifp, CSUM_TSO, 0); 2070 else 2071 if_sethwassistbits(ifp, 0, CSUM_TSO); 2072 } 2073 } 2074 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2075 (IFCAP_WOL_MAGIC & if_getcapabilities(ifp)) != 0) 2076 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2077 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2078 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2079 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2080 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2081 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2082 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2083 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2084 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 2085 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2086 jme_set_vlan(sc); 2087 } 2088 JME_UNLOCK(sc); 2089 VLAN_CAPABILITIES(ifp); 2090 break; 2091 default: 2092 error = ether_ioctl(ifp, cmd, data); 2093 break; 2094 } 2095 2096 return (error); 2097 } 2098 2099 static void 2100 jme_mac_config(struct jme_softc *sc) 2101 { 2102 struct mii_data *mii; 2103 uint32_t ghc, gpreg, rxmac, txmac, txpause; 2104 uint32_t txclk; 2105 2106 JME_LOCK_ASSERT(sc); 2107 2108 mii = device_get_softc(sc->jme_miibus); 2109 2110 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2111 DELAY(10); 2112 CSR_WRITE_4(sc, JME_GHC, 0); 2113 ghc = 0; 2114 txclk = 0; 2115 rxmac = CSR_READ_4(sc, JME_RXMAC); 2116 rxmac &= ~RXMAC_FC_ENB; 2117 txmac = CSR_READ_4(sc, JME_TXMAC); 2118 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2119 txpause = CSR_READ_4(sc, JME_TXPFC); 2120 txpause &= ~TXPFC_PAUSE_ENB; 2121 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2122 ghc |= GHC_FULL_DUPLEX; 2123 rxmac &= ~RXMAC_COLL_DET_ENB; 2124 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2125 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2126 TXMAC_FRAME_BURST); 2127 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2128 txpause |= TXPFC_PAUSE_ENB; 2129 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2130 rxmac |= RXMAC_FC_ENB; 2131 /* Disable retry transmit timer/retry limit. */ 2132 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2133 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2134 } else { 2135 rxmac |= RXMAC_COLL_DET_ENB; 2136 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2137 /* Enable retry transmit timer/retry limit. */ 2138 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2139 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2140 } 2141 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2142 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2143 case IFM_10_T: 2144 ghc |= GHC_SPEED_10; 2145 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2146 break; 2147 case IFM_100_TX: 2148 ghc |= GHC_SPEED_100; 2149 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2150 break; 2151 case IFM_1000_T: 2152 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2153 break; 2154 ghc |= GHC_SPEED_1000; 2155 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2156 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2157 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2158 break; 2159 default: 2160 break; 2161 } 2162 if (sc->jme_rev == DEVICEID_JMC250 && 2163 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2164 /* 2165 * Workaround occasional packet loss issue of JMC250 A2 2166 * when it runs on half-duplex media. 2167 */ 2168 gpreg = CSR_READ_4(sc, JME_GPREG1); 2169 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2170 gpreg &= ~GPREG1_HDPX_FIX; 2171 else 2172 gpreg |= GPREG1_HDPX_FIX; 2173 CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2174 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 2175 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2176 /* Extend interface FIFO depth. */ 2177 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2178 0x1B, 0x0000); 2179 } else { 2180 /* Select default interface FIFO depth. */ 2181 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2182 0x1B, 0x0004); 2183 } 2184 } 2185 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2186 ghc |= txclk; 2187 CSR_WRITE_4(sc, JME_GHC, ghc); 2188 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2189 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2190 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2191 } 2192 2193 static void 2194 jme_link_task(void *arg, int pending) 2195 { 2196 struct jme_softc *sc; 2197 struct mii_data *mii; 2198 if_t ifp; 2199 struct jme_txdesc *txd; 2200 bus_addr_t paddr; 2201 int i; 2202 2203 sc = (struct jme_softc *)arg; 2204 2205 JME_LOCK(sc); 2206 mii = device_get_softc(sc->jme_miibus); 2207 ifp = sc->jme_ifp; 2208 if (mii == NULL || ifp == NULL || 2209 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2210 JME_UNLOCK(sc); 2211 return; 2212 } 2213 2214 sc->jme_flags &= ~JME_FLAG_LINK; 2215 if ((mii->mii_media_status & IFM_AVALID) != 0) { 2216 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2217 case IFM_10_T: 2218 case IFM_100_TX: 2219 sc->jme_flags |= JME_FLAG_LINK; 2220 break; 2221 case IFM_1000_T: 2222 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2223 break; 2224 sc->jme_flags |= JME_FLAG_LINK; 2225 break; 2226 default: 2227 break; 2228 } 2229 } 2230 2231 /* 2232 * Disabling Rx/Tx MACs have a side-effect of resetting 2233 * JME_TXNDA/JME_RXNDA register to the first address of 2234 * Tx/Rx descriptor address. So driver should reset its 2235 * internal procucer/consumer pointer and reclaim any 2236 * allocated resources. Note, just saving the value of 2237 * JME_TXNDA and JME_RXNDA registers before stopping MAC 2238 * and restoring JME_TXNDA/JME_RXNDA register is not 2239 * sufficient to make sure correct MAC state because 2240 * stopping MAC operation can take a while and hardware 2241 * might have updated JME_TXNDA/JME_RXNDA registers 2242 * during the stop operation. 2243 */ 2244 /* Block execution of task. */ 2245 taskqueue_block(sc->jme_tq); 2246 /* Disable interrupts and stop driver. */ 2247 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2248 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2249 callout_stop(&sc->jme_tick_ch); 2250 sc->jme_watchdog_timer = 0; 2251 2252 /* Stop receiver/transmitter. */ 2253 jme_stop_rx(sc); 2254 jme_stop_tx(sc); 2255 2256 /* XXX Drain all queued tasks. */ 2257 JME_UNLOCK(sc); 2258 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2259 JME_LOCK(sc); 2260 2261 if (sc->jme_cdata.jme_rxhead != NULL) 2262 m_freem(sc->jme_cdata.jme_rxhead); 2263 JME_RXCHAIN_RESET(sc); 2264 jme_txeof(sc); 2265 if (sc->jme_cdata.jme_tx_cnt != 0) { 2266 /* Remove queued packets for transmit. */ 2267 for (i = 0; i < JME_TX_RING_CNT; i++) { 2268 txd = &sc->jme_cdata.jme_txdesc[i]; 2269 if (txd->tx_m != NULL) { 2270 bus_dmamap_sync( 2271 sc->jme_cdata.jme_tx_tag, 2272 txd->tx_dmamap, 2273 BUS_DMASYNC_POSTWRITE); 2274 bus_dmamap_unload( 2275 sc->jme_cdata.jme_tx_tag, 2276 txd->tx_dmamap); 2277 m_freem(txd->tx_m); 2278 txd->tx_m = NULL; 2279 txd->tx_ndesc = 0; 2280 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2281 } 2282 } 2283 } 2284 2285 /* 2286 * Reuse configured Rx descriptors and reset 2287 * producer/consumer index. 2288 */ 2289 sc->jme_cdata.jme_rx_cons = 0; 2290 sc->jme_morework = 0; 2291 jme_init_tx_ring(sc); 2292 /* Initialize shadow status block. */ 2293 jme_init_ssb(sc); 2294 2295 /* Program MAC with resolved speed/duplex/flow-control. */ 2296 if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2297 jme_mac_config(sc); 2298 jme_stats_clear(sc); 2299 2300 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2301 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2302 2303 /* Set Tx ring address to the hardware. */ 2304 paddr = JME_TX_RING_ADDR(sc, 0); 2305 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2306 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2307 2308 /* Set Rx ring address to the hardware. */ 2309 paddr = JME_RX_RING_ADDR(sc, 0); 2310 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2311 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2312 2313 /* Restart receiver/transmitter. */ 2314 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2315 RXCSR_RXQ_START); 2316 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2317 /* Lastly enable TX/RX clock. */ 2318 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2319 CSR_WRITE_4(sc, JME_GHC, 2320 CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS); 2321 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 2322 CSR_WRITE_4(sc, JME_GPREG1, 2323 CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS); 2324 } 2325 2326 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2327 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2328 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2329 /* Unblock execution of task. */ 2330 taskqueue_unblock(sc->jme_tq); 2331 /* Reenable interrupts. */ 2332 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2333 2334 JME_UNLOCK(sc); 2335 } 2336 2337 static int 2338 jme_intr(void *arg) 2339 { 2340 struct jme_softc *sc; 2341 uint32_t status; 2342 2343 sc = (struct jme_softc *)arg; 2344 2345 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2346 if (status == 0 || status == 0xFFFFFFFF) 2347 return (FILTER_STRAY); 2348 /* Disable interrupts. */ 2349 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2350 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2351 2352 return (FILTER_HANDLED); 2353 } 2354 2355 static void 2356 jme_int_task(void *arg, int pending) 2357 { 2358 struct jme_softc *sc; 2359 if_t ifp; 2360 uint32_t status; 2361 int more; 2362 2363 sc = (struct jme_softc *)arg; 2364 ifp = sc->jme_ifp; 2365 2366 JME_LOCK(sc); 2367 status = CSR_READ_4(sc, JME_INTR_STATUS); 2368 if (sc->jme_morework != 0) { 2369 sc->jme_morework = 0; 2370 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2371 } 2372 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2373 goto done; 2374 /* Reset PCC counter/timer and Ack interrupts. */ 2375 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2376 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2377 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2378 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2379 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2380 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2381 more = 0; 2382 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2383 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2384 more = jme_rxintr(sc, sc->jme_process_limit); 2385 if (more != 0) 2386 sc->jme_morework = 1; 2387 } 2388 if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2389 /* 2390 * Notify hardware availability of new Rx 2391 * buffers. 2392 * Reading RXCSR takes very long time under 2393 * heavy load so cache RXCSR value and writes 2394 * the ORed value with the kick command to 2395 * the RXCSR. This saves one register access 2396 * cycle. 2397 */ 2398 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2399 RXCSR_RX_ENB | RXCSR_RXQ_START); 2400 } 2401 if (!if_sendq_empty(ifp)) 2402 jme_start_locked(ifp); 2403 } 2404 2405 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2406 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2407 JME_UNLOCK(sc); 2408 return; 2409 } 2410 done: 2411 JME_UNLOCK(sc); 2412 2413 /* Reenable interrupts. */ 2414 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2415 } 2416 2417 static void 2418 jme_txeof(struct jme_softc *sc) 2419 { 2420 if_t ifp; 2421 struct jme_txdesc *txd; 2422 uint32_t status; 2423 int cons, nsegs; 2424 2425 JME_LOCK_ASSERT(sc); 2426 2427 ifp = sc->jme_ifp; 2428 2429 cons = sc->jme_cdata.jme_tx_cons; 2430 if (cons == sc->jme_cdata.jme_tx_prod) 2431 return; 2432 2433 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2434 sc->jme_cdata.jme_tx_ring_map, 2435 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2436 2437 /* 2438 * Go through our Tx list and free mbufs for those 2439 * frames which have been transmitted. 2440 */ 2441 for (; cons != sc->jme_cdata.jme_tx_prod;) { 2442 txd = &sc->jme_cdata.jme_txdesc[cons]; 2443 status = le32toh(txd->tx_desc->flags); 2444 if ((status & JME_TD_OWN) == JME_TD_OWN) 2445 break; 2446 2447 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2448 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2449 else { 2450 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2451 if ((status & JME_TD_COLLISION) != 0) 2452 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2453 le32toh(txd->tx_desc->buflen) & 2454 JME_TD_BUF_LEN_MASK); 2455 } 2456 /* 2457 * Only the first descriptor of multi-descriptor 2458 * transmission is updated so driver have to skip entire 2459 * chained buffers for the transmiited frame. In other 2460 * words, JME_TD_OWN bit is valid only at the first 2461 * descriptor of a multi-descriptor transmission. 2462 */ 2463 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2464 sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2465 JME_DESC_INC(cons, JME_TX_RING_CNT); 2466 } 2467 2468 /* Reclaim transferred mbufs. */ 2469 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2470 BUS_DMASYNC_POSTWRITE); 2471 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2472 2473 KASSERT(txd->tx_m != NULL, 2474 ("%s: freeing NULL mbuf!\n", __func__)); 2475 m_freem(txd->tx_m); 2476 txd->tx_m = NULL; 2477 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2478 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2479 ("%s: Active Tx desc counter was garbled\n", __func__)); 2480 txd->tx_ndesc = 0; 2481 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2482 } 2483 sc->jme_cdata.jme_tx_cons = cons; 2484 /* Unarm watchdog timer when there is no pending descriptors in queue. */ 2485 if (sc->jme_cdata.jme_tx_cnt == 0) 2486 sc->jme_watchdog_timer = 0; 2487 2488 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2489 sc->jme_cdata.jme_tx_ring_map, 2490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2491 } 2492 2493 static __inline void 2494 jme_discard_rxbuf(struct jme_softc *sc, int cons) 2495 { 2496 struct jme_desc *desc; 2497 2498 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2499 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2500 desc->buflen = htole32(MCLBYTES); 2501 } 2502 2503 /* Receive a frame. */ 2504 static void 2505 jme_rxeof(struct jme_softc *sc) 2506 { 2507 if_t ifp; 2508 struct jme_desc *desc; 2509 struct jme_rxdesc *rxd; 2510 struct mbuf *mp, *m; 2511 uint32_t flags, status; 2512 int cons, count, nsegs; 2513 2514 JME_LOCK_ASSERT(sc); 2515 2516 ifp = sc->jme_ifp; 2517 2518 cons = sc->jme_cdata.jme_rx_cons; 2519 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2520 flags = le32toh(desc->flags); 2521 status = le32toh(desc->buflen); 2522 nsegs = JME_RX_NSEGS(status); 2523 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2524 if ((status & JME_RX_ERR_STAT) != 0) { 2525 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2526 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2527 #ifdef JME_SHOW_ERRORS 2528 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2529 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2530 #endif 2531 sc->jme_cdata.jme_rx_cons += nsegs; 2532 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2533 return; 2534 } 2535 2536 for (count = 0; count < nsegs; count++, 2537 JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2538 rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2539 mp = rxd->rx_m; 2540 /* Add a new receive buffer to the ring. */ 2541 if (jme_newbuf(sc, rxd) != 0) { 2542 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2543 /* Reuse buffer. */ 2544 for (; count < nsegs; count++) { 2545 jme_discard_rxbuf(sc, cons); 2546 JME_DESC_INC(cons, JME_RX_RING_CNT); 2547 } 2548 if (sc->jme_cdata.jme_rxhead != NULL) { 2549 m_freem(sc->jme_cdata.jme_rxhead); 2550 JME_RXCHAIN_RESET(sc); 2551 } 2552 break; 2553 } 2554 2555 /* 2556 * Assume we've received a full sized frame. 2557 * Actual size is fixed when we encounter the end of 2558 * multi-segmented frame. 2559 */ 2560 mp->m_len = MCLBYTES; 2561 2562 /* Chain received mbufs. */ 2563 if (sc->jme_cdata.jme_rxhead == NULL) { 2564 sc->jme_cdata.jme_rxhead = mp; 2565 sc->jme_cdata.jme_rxtail = mp; 2566 } else { 2567 /* 2568 * Receive processor can receive a maximum frame 2569 * size of 65535 bytes. 2570 */ 2571 mp->m_flags &= ~M_PKTHDR; 2572 sc->jme_cdata.jme_rxtail->m_next = mp; 2573 sc->jme_cdata.jme_rxtail = mp; 2574 } 2575 2576 if (count == nsegs - 1) { 2577 /* Last desc. for this frame. */ 2578 m = sc->jme_cdata.jme_rxhead; 2579 m->m_flags |= M_PKTHDR; 2580 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2581 if (nsegs > 1) { 2582 /* Set first mbuf size. */ 2583 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2584 /* Set last mbuf size. */ 2585 mp->m_len = sc->jme_cdata.jme_rxlen - 2586 ((MCLBYTES - JME_RX_PAD_BYTES) + 2587 (MCLBYTES * (nsegs - 2))); 2588 } else 2589 m->m_len = sc->jme_cdata.jme_rxlen; 2590 m->m_pkthdr.rcvif = ifp; 2591 2592 /* 2593 * Account for 10bytes auto padding which is used 2594 * to align IP header on 32bit boundary. Also note, 2595 * CRC bytes is automatically removed by the 2596 * hardware. 2597 */ 2598 m->m_data += JME_RX_PAD_BYTES; 2599 2600 /* Set checksum information. */ 2601 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2602 (flags & JME_RD_IPV4) != 0) { 2603 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2604 if ((flags & JME_RD_IPCSUM) != 0) 2605 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2606 if (((flags & JME_RD_MORE_FRAG) == 0) && 2607 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2608 (JME_RD_TCP | JME_RD_TCPCSUM) || 2609 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2610 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2611 m->m_pkthdr.csum_flags |= 2612 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2613 m->m_pkthdr.csum_data = 0xffff; 2614 } 2615 } 2616 2617 /* Check for VLAN tagged packets. */ 2618 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2619 (flags & JME_RD_VLAN_TAG) != 0) { 2620 m->m_pkthdr.ether_vtag = 2621 flags & JME_RD_VLAN_MASK; 2622 m->m_flags |= M_VLANTAG; 2623 } 2624 2625 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2626 /* Pass it on. */ 2627 JME_UNLOCK(sc); 2628 if_input(ifp, m); 2629 JME_LOCK(sc); 2630 2631 /* Reset mbuf chains. */ 2632 JME_RXCHAIN_RESET(sc); 2633 } 2634 } 2635 2636 sc->jme_cdata.jme_rx_cons += nsegs; 2637 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2638 } 2639 2640 static int 2641 jme_rxintr(struct jme_softc *sc, int count) 2642 { 2643 struct jme_desc *desc; 2644 int nsegs, prog, pktlen; 2645 2646 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2647 sc->jme_cdata.jme_rx_ring_map, 2648 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2649 2650 for (prog = 0; count > 0; prog++) { 2651 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2652 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2653 break; 2654 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2655 break; 2656 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2657 /* 2658 * Check number of segments against received bytes. 2659 * Non-matching value would indicate that hardware 2660 * is still trying to update Rx descriptors. I'm not 2661 * sure whether this check is needed. 2662 */ 2663 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2664 if (nsegs != howmany(pktlen, MCLBYTES)) 2665 break; 2666 prog++; 2667 /* Received a frame. */ 2668 jme_rxeof(sc); 2669 count -= nsegs; 2670 } 2671 2672 if (prog > 0) 2673 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2674 sc->jme_cdata.jme_rx_ring_map, 2675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2676 2677 return (count > 0 ? 0 : EAGAIN); 2678 } 2679 2680 static void 2681 jme_tick(void *arg) 2682 { 2683 struct jme_softc *sc; 2684 struct mii_data *mii; 2685 2686 sc = (struct jme_softc *)arg; 2687 2688 JME_LOCK_ASSERT(sc); 2689 2690 mii = device_get_softc(sc->jme_miibus); 2691 mii_tick(mii); 2692 /* 2693 * Reclaim Tx buffers that have been completed. It's not 2694 * needed here but it would release allocated mbuf chains 2695 * faster and limit the maximum delay to a hz. 2696 */ 2697 jme_txeof(sc); 2698 jme_stats_update(sc); 2699 jme_watchdog(sc); 2700 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2701 } 2702 2703 static void 2704 jme_reset(struct jme_softc *sc) 2705 { 2706 uint32_t ghc, gpreg; 2707 2708 /* Stop receiver, transmitter. */ 2709 jme_stop_rx(sc); 2710 jme_stop_tx(sc); 2711 2712 /* Reset controller. */ 2713 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2714 CSR_READ_4(sc, JME_GHC); 2715 DELAY(10); 2716 /* 2717 * Workaround Rx FIFO overruns seen under certain conditions. 2718 * Explicitly synchorize TX/RX clock. TX/RX clock should be 2719 * enabled only after enabling TX/RX MACs. 2720 */ 2721 if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) { 2722 /* Disable TX clock. */ 2723 CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS); 2724 /* Disable RX clock. */ 2725 gpreg = CSR_READ_4(sc, JME_GPREG1); 2726 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2727 gpreg = CSR_READ_4(sc, JME_GPREG1); 2728 /* De-assert RESET but still disable TX clock. */ 2729 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2730 ghc = CSR_READ_4(sc, JME_GHC); 2731 2732 /* Enable TX clock. */ 2733 CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS); 2734 /* Enable RX clock. */ 2735 CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS); 2736 CSR_READ_4(sc, JME_GPREG1); 2737 2738 /* Disable TX/RX clock again. */ 2739 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2740 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2741 } else 2742 CSR_WRITE_4(sc, JME_GHC, 0); 2743 CSR_READ_4(sc, JME_GHC); 2744 DELAY(10); 2745 } 2746 2747 static void 2748 jme_init(void *xsc) 2749 { 2750 struct jme_softc *sc; 2751 2752 sc = (struct jme_softc *)xsc; 2753 JME_LOCK(sc); 2754 jme_init_locked(sc); 2755 JME_UNLOCK(sc); 2756 } 2757 2758 static void 2759 jme_init_locked(struct jme_softc *sc) 2760 { 2761 if_t ifp; 2762 struct mii_data *mii; 2763 bus_addr_t paddr; 2764 uint32_t reg; 2765 int error; 2766 2767 JME_LOCK_ASSERT(sc); 2768 2769 ifp = sc->jme_ifp; 2770 mii = device_get_softc(sc->jme_miibus); 2771 2772 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2773 return; 2774 /* 2775 * Cancel any pending I/O. 2776 */ 2777 jme_stop(sc); 2778 2779 /* 2780 * Reset the chip to a known state. 2781 */ 2782 jme_reset(sc); 2783 2784 /* Init descriptors. */ 2785 error = jme_init_rx_ring(sc); 2786 if (error != 0) { 2787 device_printf(sc->jme_dev, 2788 "%s: initialization failed: no memory for Rx buffers.\n", 2789 __func__); 2790 jme_stop(sc); 2791 return; 2792 } 2793 jme_init_tx_ring(sc); 2794 /* Initialize shadow status block. */ 2795 jme_init_ssb(sc); 2796 2797 /* Reprogram the station address. */ 2798 jme_set_macaddr(sc, if_getlladdr(sc->jme_ifp)); 2799 2800 /* 2801 * Configure Tx queue. 2802 * Tx priority queue weight value : 0 2803 * Tx FIFO threshold for processing next packet : 16QW 2804 * Maximum Tx DMA length : 512 2805 * Allow Tx DMA burst. 2806 */ 2807 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2808 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2809 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2810 sc->jme_txcsr |= sc->jme_tx_dma_size; 2811 sc->jme_txcsr |= TXCSR_DMA_BURST; 2812 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2813 2814 /* Set Tx descriptor counter. */ 2815 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2816 2817 /* Set Tx ring address to the hardware. */ 2818 paddr = JME_TX_RING_ADDR(sc, 0); 2819 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2820 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2821 2822 /* Configure TxMAC parameters. */ 2823 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2824 reg |= TXMAC_THRESH_1_PKT; 2825 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2826 CSR_WRITE_4(sc, JME_TXMAC, reg); 2827 2828 /* 2829 * Configure Rx queue. 2830 * FIFO full threshold for transmitting Tx pause packet : 128T 2831 * FIFO threshold for processing next packet : 128QW 2832 * Rx queue 0 select 2833 * Max Rx DMA length : 128 2834 * Rx descriptor retry : 32 2835 * Rx descriptor retry time gap : 256ns 2836 * Don't receive runt/bad frame. 2837 */ 2838 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2839 /* 2840 * Since Rx FIFO size is 4K bytes, receiving frames larger 2841 * than 4K bytes will suffer from Rx FIFO overruns. So 2842 * decrease FIFO threshold to reduce the FIFO overruns for 2843 * frames larger than 4000 bytes. 2844 * For best performance of standard MTU sized frames use 2845 * maximum allowable FIFO threshold, 128QW. Note these do 2846 * not hold on chip full mask version >=2. For these 2847 * controllers 64QW and 128QW are not valid value. 2848 */ 2849 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2850 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2851 else { 2852 if ((if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2853 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2854 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2855 else 2856 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2857 } 2858 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2859 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2860 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2861 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2862 2863 /* Set Rx descriptor counter. */ 2864 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2865 2866 /* Set Rx ring address to the hardware. */ 2867 paddr = JME_RX_RING_ADDR(sc, 0); 2868 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2869 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2870 2871 /* Clear receive filter. */ 2872 CSR_WRITE_4(sc, JME_RXMAC, 0); 2873 /* Set up the receive filter. */ 2874 jme_set_filter(sc); 2875 jme_set_vlan(sc); 2876 2877 /* 2878 * Disable all WOL bits as WOL can interfere normal Rx 2879 * operation. Also clear WOL detection status bits. 2880 */ 2881 reg = CSR_READ_4(sc, JME_PMCS); 2882 reg &= ~PMCS_WOL_ENB_MASK; 2883 CSR_WRITE_4(sc, JME_PMCS, reg); 2884 2885 reg = CSR_READ_4(sc, JME_RXMAC); 2886 /* 2887 * Pad 10bytes right before received frame. This will greatly 2888 * help Rx performance on strict-alignment architectures as 2889 * it does not need to copy the frame to align the payload. 2890 */ 2891 reg |= RXMAC_PAD_10BYTES; 2892 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2893 reg |= RXMAC_CSUM_ENB; 2894 CSR_WRITE_4(sc, JME_RXMAC, reg); 2895 2896 /* Configure general purpose reg0 */ 2897 reg = CSR_READ_4(sc, JME_GPREG0); 2898 reg &= ~GPREG0_PCC_UNIT_MASK; 2899 /* Set PCC timer resolution to micro-seconds unit. */ 2900 reg |= GPREG0_PCC_UNIT_US; 2901 /* 2902 * Disable all shadow register posting as we have to read 2903 * JME_INTR_STATUS register in jme_int_task. Also it seems 2904 * that it's hard to synchronize interrupt status between 2905 * hardware and software with shadow posting due to 2906 * requirements of bus_dmamap_sync(9). 2907 */ 2908 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2909 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2910 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2911 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2912 /* Disable posting of DW0. */ 2913 reg &= ~GPREG0_POST_DW0_ENB; 2914 /* Clear PME message. */ 2915 reg &= ~GPREG0_PME_ENB; 2916 /* Set PHY address. */ 2917 reg &= ~GPREG0_PHY_ADDR_MASK; 2918 reg |= sc->jme_phyaddr; 2919 CSR_WRITE_4(sc, JME_GPREG0, reg); 2920 2921 /* Configure Tx queue 0 packet completion coalescing. */ 2922 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2923 PCCTX_COAL_TO_MASK; 2924 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2925 PCCTX_COAL_PKT_MASK; 2926 reg |= PCCTX_COAL_TXQ0; 2927 CSR_WRITE_4(sc, JME_PCCTX, reg); 2928 2929 /* Configure Rx queue 0 packet completion coalescing. */ 2930 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2931 PCCRX_COAL_TO_MASK; 2932 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2933 PCCRX_COAL_PKT_MASK; 2934 CSR_WRITE_4(sc, JME_PCCRX0, reg); 2935 2936 /* 2937 * Configure PCD(Packet Completion Deferring). It seems PCD 2938 * generates an interrupt when the time interval between two 2939 * back-to-back incoming/outgoing packet is long enough for 2940 * it to reach its timer value 0. The arrival of new packets 2941 * after timer has started causes the PCD timer to restart. 2942 * Unfortunately, it's not clear how PCD is useful at this 2943 * moment, so just use the same of PCC parameters. 2944 */ 2945 if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) { 2946 sc->jme_rx_pcd_to = sc->jme_rx_coal_to; 2947 if (sc->jme_rx_coal_to > PCDRX_TO_MAX) 2948 sc->jme_rx_pcd_to = PCDRX_TO_MAX; 2949 sc->jme_tx_pcd_to = sc->jme_tx_coal_to; 2950 if (sc->jme_tx_coal_to > PCDTX_TO_MAX) 2951 sc->jme_tx_pcd_to = PCDTX_TO_MAX; 2952 reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT; 2953 reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT; 2954 CSR_WRITE_4(sc, PCDRX_REG(0), reg); 2955 reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT; 2956 reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT; 2957 CSR_WRITE_4(sc, JME_PCDTX, reg); 2958 } 2959 2960 /* Configure shadow status block but don't enable posting. */ 2961 paddr = sc->jme_rdata.jme_ssb_block_paddr; 2962 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2963 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2964 2965 /* Disable Timer 1 and Timer 2. */ 2966 CSR_WRITE_4(sc, JME_TIMER1, 0); 2967 CSR_WRITE_4(sc, JME_TIMER2, 0); 2968 2969 /* Configure retry transmit period, retry limit value. */ 2970 CSR_WRITE_4(sc, JME_TXTRHD, 2971 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2972 TXTRHD_RT_PERIOD_MASK) | 2973 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2974 TXTRHD_RT_LIMIT_SHIFT)); 2975 2976 /* Disable RSS. */ 2977 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2978 2979 /* Initialize the interrupt mask. */ 2980 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2981 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2982 2983 /* 2984 * Enabling Tx/Rx DMA engines and Rx queue processing is 2985 * done after detection of valid link in jme_link_task. 2986 */ 2987 2988 sc->jme_flags &= ~JME_FLAG_LINK; 2989 /* Set the current media. */ 2990 mii_mediachg(mii); 2991 2992 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2993 2994 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2995 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2996 } 2997 2998 static void 2999 jme_stop(struct jme_softc *sc) 3000 { 3001 if_t ifp; 3002 struct jme_txdesc *txd; 3003 struct jme_rxdesc *rxd; 3004 int i; 3005 3006 JME_LOCK_ASSERT(sc); 3007 /* 3008 * Mark the interface down and cancel the watchdog timer. 3009 */ 3010 ifp = sc->jme_ifp; 3011 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3012 sc->jme_flags &= ~JME_FLAG_LINK; 3013 callout_stop(&sc->jme_tick_ch); 3014 sc->jme_watchdog_timer = 0; 3015 3016 /* 3017 * Disable interrupts. 3018 */ 3019 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 3020 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 3021 3022 /* Disable updating shadow status block. */ 3023 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 3024 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 3025 3026 /* Stop receiver, transmitter. */ 3027 jme_stop_rx(sc); 3028 jme_stop_tx(sc); 3029 3030 /* Reclaim Rx/Tx buffers that have been completed. */ 3031 jme_rxintr(sc, JME_RX_RING_CNT); 3032 if (sc->jme_cdata.jme_rxhead != NULL) 3033 m_freem(sc->jme_cdata.jme_rxhead); 3034 JME_RXCHAIN_RESET(sc); 3035 jme_txeof(sc); 3036 /* 3037 * Free RX and TX mbufs still in the queues. 3038 */ 3039 for (i = 0; i < JME_RX_RING_CNT; i++) { 3040 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3041 if (rxd->rx_m != NULL) { 3042 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 3043 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3044 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 3045 rxd->rx_dmamap); 3046 m_freem(rxd->rx_m); 3047 rxd->rx_m = NULL; 3048 } 3049 } 3050 for (i = 0; i < JME_TX_RING_CNT; i++) { 3051 txd = &sc->jme_cdata.jme_txdesc[i]; 3052 if (txd->tx_m != NULL) { 3053 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 3054 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3055 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 3056 txd->tx_dmamap); 3057 m_freem(txd->tx_m); 3058 txd->tx_m = NULL; 3059 txd->tx_ndesc = 0; 3060 } 3061 } 3062 jme_stats_update(sc); 3063 jme_stats_save(sc); 3064 } 3065 3066 static void 3067 jme_stop_tx(struct jme_softc *sc) 3068 { 3069 uint32_t reg; 3070 int i; 3071 3072 reg = CSR_READ_4(sc, JME_TXCSR); 3073 if ((reg & TXCSR_TX_ENB) == 0) 3074 return; 3075 reg &= ~TXCSR_TX_ENB; 3076 CSR_WRITE_4(sc, JME_TXCSR, reg); 3077 for (i = JME_TIMEOUT; i > 0; i--) { 3078 DELAY(1); 3079 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 3080 break; 3081 } 3082 if (i == 0) 3083 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 3084 } 3085 3086 static void 3087 jme_stop_rx(struct jme_softc *sc) 3088 { 3089 uint32_t reg; 3090 int i; 3091 3092 reg = CSR_READ_4(sc, JME_RXCSR); 3093 if ((reg & RXCSR_RX_ENB) == 0) 3094 return; 3095 reg &= ~RXCSR_RX_ENB; 3096 CSR_WRITE_4(sc, JME_RXCSR, reg); 3097 for (i = JME_TIMEOUT; i > 0; i--) { 3098 DELAY(1); 3099 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 3100 break; 3101 } 3102 if (i == 0) 3103 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 3104 } 3105 3106 static void 3107 jme_init_tx_ring(struct jme_softc *sc) 3108 { 3109 struct jme_ring_data *rd; 3110 struct jme_txdesc *txd; 3111 int i; 3112 3113 sc->jme_cdata.jme_tx_prod = 0; 3114 sc->jme_cdata.jme_tx_cons = 0; 3115 sc->jme_cdata.jme_tx_cnt = 0; 3116 3117 rd = &sc->jme_rdata; 3118 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 3119 for (i = 0; i < JME_TX_RING_CNT; i++) { 3120 txd = &sc->jme_cdata.jme_txdesc[i]; 3121 txd->tx_m = NULL; 3122 txd->tx_desc = &rd->jme_tx_ring[i]; 3123 txd->tx_ndesc = 0; 3124 } 3125 3126 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 3127 sc->jme_cdata.jme_tx_ring_map, 3128 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3129 } 3130 3131 static void 3132 jme_init_ssb(struct jme_softc *sc) 3133 { 3134 struct jme_ring_data *rd; 3135 3136 rd = &sc->jme_rdata; 3137 bzero(rd->jme_ssb_block, JME_SSB_SIZE); 3138 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 3139 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3140 } 3141 3142 static int 3143 jme_init_rx_ring(struct jme_softc *sc) 3144 { 3145 struct jme_ring_data *rd; 3146 struct jme_rxdesc *rxd; 3147 int i; 3148 3149 sc->jme_cdata.jme_rx_cons = 0; 3150 JME_RXCHAIN_RESET(sc); 3151 sc->jme_morework = 0; 3152 3153 rd = &sc->jme_rdata; 3154 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 3155 for (i = 0; i < JME_RX_RING_CNT; i++) { 3156 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3157 rxd->rx_m = NULL; 3158 rxd->rx_desc = &rd->jme_rx_ring[i]; 3159 if (jme_newbuf(sc, rxd) != 0) 3160 return (ENOBUFS); 3161 } 3162 3163 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 3164 sc->jme_cdata.jme_rx_ring_map, 3165 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3166 3167 return (0); 3168 } 3169 3170 static int 3171 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 3172 { 3173 struct jme_desc *desc; 3174 struct mbuf *m; 3175 bus_dma_segment_t segs[1]; 3176 bus_dmamap_t map; 3177 int nsegs; 3178 3179 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3180 if (m == NULL) 3181 return (ENOBUFS); 3182 /* 3183 * JMC250 has 64bit boundary alignment limitation so jme(4) 3184 * takes advantage of 10 bytes padding feature of hardware 3185 * in order not to copy entire frame to align IP header on 3186 * 32bit boundary. 3187 */ 3188 m->m_len = m->m_pkthdr.len = MCLBYTES; 3189 3190 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 3191 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3192 m_freem(m); 3193 return (ENOBUFS); 3194 } 3195 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3196 3197 if (rxd->rx_m != NULL) { 3198 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3199 BUS_DMASYNC_POSTREAD); 3200 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3201 } 3202 map = rxd->rx_dmamap; 3203 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3204 sc->jme_cdata.jme_rx_sparemap = map; 3205 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3206 BUS_DMASYNC_PREREAD); 3207 rxd->rx_m = m; 3208 3209 desc = rxd->rx_desc; 3210 desc->buflen = htole32(segs[0].ds_len); 3211 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3212 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3213 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3214 3215 return (0); 3216 } 3217 3218 static void 3219 jme_set_vlan(struct jme_softc *sc) 3220 { 3221 if_t ifp; 3222 uint32_t reg; 3223 3224 JME_LOCK_ASSERT(sc); 3225 3226 ifp = sc->jme_ifp; 3227 reg = CSR_READ_4(sc, JME_RXMAC); 3228 reg &= ~RXMAC_VLAN_ENB; 3229 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3230 reg |= RXMAC_VLAN_ENB; 3231 CSR_WRITE_4(sc, JME_RXMAC, reg); 3232 } 3233 3234 static u_int 3235 jme_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3236 { 3237 uint32_t crc, *mchash = arg; 3238 3239 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3240 3241 /* Just want the 6 least significant bits. */ 3242 crc &= 0x3f; 3243 3244 /* Set the corresponding bit in the hash table. */ 3245 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3246 3247 return (1); 3248 } 3249 3250 static void 3251 jme_set_filter(struct jme_softc *sc) 3252 { 3253 if_t ifp; 3254 uint32_t mchash[2]; 3255 uint32_t rxcfg; 3256 3257 JME_LOCK_ASSERT(sc); 3258 3259 ifp = sc->jme_ifp; 3260 3261 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3262 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3263 RXMAC_ALLMULTI); 3264 /* Always accept frames destined to our station address. */ 3265 rxcfg |= RXMAC_UNICAST; 3266 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3267 rxcfg |= RXMAC_BROADCAST; 3268 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3269 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3270 rxcfg |= RXMAC_PROMISC; 3271 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3272 rxcfg |= RXMAC_ALLMULTI; 3273 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3274 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3275 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3276 return; 3277 } 3278 3279 /* 3280 * Set up the multicast address filter by passing all multicast 3281 * addresses through a CRC generator, and then using the low-order 3282 * 6 bits as an index into the 64 bit multicast hash table. The 3283 * high order bits select the register, while the rest of the bits 3284 * select the bit within the register. 3285 */ 3286 rxcfg |= RXMAC_MULTICAST; 3287 bzero(mchash, sizeof(mchash)); 3288 if_foreach_llmaddr(ifp, jme_hash_maddr, &mchash); 3289 3290 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3291 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3292 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3293 } 3294 3295 static void 3296 jme_stats_clear(struct jme_softc *sc) 3297 { 3298 3299 JME_LOCK_ASSERT(sc); 3300 3301 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3302 return; 3303 3304 /* Disable and clear counters. */ 3305 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3306 /* Activate hw counters. */ 3307 CSR_WRITE_4(sc, JME_STATCSR, 0); 3308 CSR_READ_4(sc, JME_STATCSR); 3309 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats)); 3310 } 3311 3312 static void 3313 jme_stats_save(struct jme_softc *sc) 3314 { 3315 3316 JME_LOCK_ASSERT(sc); 3317 3318 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3319 return; 3320 /* Save current counters. */ 3321 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats)); 3322 /* Disable and clear counters. */ 3323 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3324 } 3325 3326 static void 3327 jme_stats_update(struct jme_softc *sc) 3328 { 3329 struct jme_hw_stats *stat, *ostat; 3330 uint32_t reg; 3331 3332 JME_LOCK_ASSERT(sc); 3333 3334 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3335 return; 3336 stat = &sc->jme_stats; 3337 ostat = &sc->jme_ostats; 3338 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD); 3339 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD); 3340 reg = CSR_READ_4(sc, JME_STAT_CRCMII); 3341 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >> 3342 STAT_RX_CRC_ERR_SHIFT; 3343 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >> 3344 STAT_RX_MII_ERR_SHIFT; 3345 reg = CSR_READ_4(sc, JME_STAT_RXERR); 3346 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >> 3347 STAT_RXERR_OFLOW_SHIFT; 3348 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >> 3349 STAT_RXERR_MPTY_SHIFT; 3350 reg = CSR_READ_4(sc, JME_STAT_FAIL); 3351 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT; 3352 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT; 3353 3354 /* Account for previous counters. */ 3355 stat->rx_good_frames += ostat->rx_good_frames; 3356 stat->rx_crc_errs += ostat->rx_crc_errs; 3357 stat->rx_mii_errs += ostat->rx_mii_errs; 3358 stat->rx_fifo_oflows += ostat->rx_fifo_oflows; 3359 stat->rx_desc_empty += ostat->rx_desc_empty; 3360 stat->rx_bad_frames += ostat->rx_bad_frames; 3361 stat->tx_good_frames += ostat->tx_good_frames; 3362 stat->tx_bad_frames += ostat->tx_bad_frames; 3363 } 3364 3365 static void 3366 jme_phy_down(struct jme_softc *sc) 3367 { 3368 uint32_t reg; 3369 3370 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN); 3371 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3372 reg = CSR_READ_4(sc, JME_PHYPOWDN); 3373 reg |= 0x0000000F; 3374 CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3375 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3376 reg &= ~PE1_GIGA_PDOWN_MASK; 3377 reg |= PE1_GIGA_PDOWN_D3; 3378 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3379 } 3380 } 3381 3382 static void 3383 jme_phy_up(struct jme_softc *sc) 3384 { 3385 uint32_t reg; 3386 uint16_t bmcr; 3387 3388 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR); 3389 bmcr &= ~BMCR_PDOWN; 3390 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr); 3391 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3392 reg = CSR_READ_4(sc, JME_PHYPOWDN); 3393 reg &= ~0x0000000F; 3394 CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3395 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3396 reg &= ~PE1_GIGA_PDOWN_MASK; 3397 reg |= PE1_GIGA_PDOWN_DIS; 3398 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3399 } 3400 } 3401 3402 static int 3403 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3404 { 3405 int error, value; 3406 3407 if (arg1 == NULL) 3408 return (EINVAL); 3409 value = *(int *)arg1; 3410 error = sysctl_handle_int(oidp, &value, 0, req); 3411 if (error || req->newptr == NULL) 3412 return (error); 3413 if (value < low || value > high) 3414 return (EINVAL); 3415 *(int *)arg1 = value; 3416 3417 return (0); 3418 } 3419 3420 static int 3421 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3422 { 3423 return (sysctl_int_range(oidp, arg1, arg2, req, 3424 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3425 } 3426 3427 static int 3428 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3429 { 3430 return (sysctl_int_range(oidp, arg1, arg2, req, 3431 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3432 } 3433 3434 static int 3435 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3436 { 3437 return (sysctl_int_range(oidp, arg1, arg2, req, 3438 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3439 } 3440 3441 static int 3442 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3443 { 3444 return (sysctl_int_range(oidp, arg1, arg2, req, 3445 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3446 } 3447 3448 static int 3449 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3450 { 3451 return (sysctl_int_range(oidp, arg1, arg2, req, 3452 JME_PROC_MIN, JME_PROC_MAX)); 3453 } 3454