1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/rman.h> 39 #include <sys/module.h> 40 #include <sys/proc.h> 41 #include <sys/queue.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <machine/bus.h> 69 #include <machine/in_cksum.h> 70 71 #include <dev/jme/if_jmereg.h> 72 #include <dev/jme/if_jmevar.h> 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 /* Define the following to disable printing Rx errors. */ 78 #undef JME_SHOW_ERRORS 79 80 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(jme, pci, 1, 1, 1); 83 MODULE_DEPEND(jme, ether, 1, 1, 1); 84 MODULE_DEPEND(jme, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.jme.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.jme.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static struct jme_dev { 96 uint16_t jme_vendorid; 97 uint16_t jme_deviceid; 98 const char *jme_name; 99 } jme_devs[] = { 100 { VENDORID_JMICRON, DEVICEID_JMC250, 101 "JMicron Inc, JMC25x Gigabit Ethernet" }, 102 { VENDORID_JMICRON, DEVICEID_JMC260, 103 "JMicron Inc, JMC26x Fast Ethernet" }, 104 }; 105 106 static int jme_miibus_readreg(device_t, int, int); 107 static int jme_miibus_writereg(device_t, int, int, int); 108 static void jme_miibus_statchg(device_t); 109 static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 110 static int jme_mediachange(struct ifnet *); 111 static int jme_probe(device_t); 112 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 113 static int jme_eeprom_macaddr(struct jme_softc *); 114 static int jme_efuse_macaddr(struct jme_softc *); 115 static void jme_reg_macaddr(struct jme_softc *); 116 static void jme_set_macaddr(struct jme_softc *, uint8_t *); 117 static void jme_map_intr_vector(struct jme_softc *); 118 static int jme_attach(device_t); 119 static int jme_detach(device_t); 120 static void jme_sysctl_node(struct jme_softc *); 121 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 122 static int jme_dma_alloc(struct jme_softc *); 123 static void jme_dma_free(struct jme_softc *); 124 static int jme_shutdown(device_t); 125 static void jme_setlinkspeed(struct jme_softc *); 126 static void jme_setwol(struct jme_softc *); 127 static int jme_suspend(device_t); 128 static int jme_resume(device_t); 129 static int jme_encap(struct jme_softc *, struct mbuf **); 130 static void jme_start(struct ifnet *); 131 static void jme_start_locked(struct ifnet *); 132 static void jme_watchdog(struct jme_softc *); 133 static int jme_ioctl(struct ifnet *, u_long, caddr_t); 134 static void jme_mac_config(struct jme_softc *); 135 static void jme_link_task(void *, int); 136 static int jme_intr(void *); 137 static void jme_int_task(void *, int); 138 static void jme_txeof(struct jme_softc *); 139 static __inline void jme_discard_rxbuf(struct jme_softc *, int); 140 static void jme_rxeof(struct jme_softc *); 141 static int jme_rxintr(struct jme_softc *, int); 142 static void jme_tick(void *); 143 static void jme_reset(struct jme_softc *); 144 static void jme_init(void *); 145 static void jme_init_locked(struct jme_softc *); 146 static void jme_stop(struct jme_softc *); 147 static void jme_stop_tx(struct jme_softc *); 148 static void jme_stop_rx(struct jme_softc *); 149 static int jme_init_rx_ring(struct jme_softc *); 150 static void jme_init_tx_ring(struct jme_softc *); 151 static void jme_init_ssb(struct jme_softc *); 152 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 153 static void jme_set_vlan(struct jme_softc *); 154 static void jme_set_filter(struct jme_softc *); 155 static void jme_stats_clear(struct jme_softc *); 156 static void jme_stats_save(struct jme_softc *); 157 static void jme_stats_update(struct jme_softc *); 158 static void jme_phy_down(struct jme_softc *); 159 static void jme_phy_up(struct jme_softc *); 160 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 161 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 162 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 163 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 164 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 165 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 166 167 168 static device_method_t jme_methods[] = { 169 /* Device interface. */ 170 DEVMETHOD(device_probe, jme_probe), 171 DEVMETHOD(device_attach, jme_attach), 172 DEVMETHOD(device_detach, jme_detach), 173 DEVMETHOD(device_shutdown, jme_shutdown), 174 DEVMETHOD(device_suspend, jme_suspend), 175 DEVMETHOD(device_resume, jme_resume), 176 177 /* MII interface. */ 178 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 179 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 180 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 181 182 { NULL, NULL } 183 }; 184 185 static driver_t jme_driver = { 186 "jme", 187 jme_methods, 188 sizeof(struct jme_softc) 189 }; 190 191 static devclass_t jme_devclass; 192 193 DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0); 194 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0); 195 196 static struct resource_spec jme_res_spec_mem[] = { 197 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 198 { -1, 0, 0 } 199 }; 200 201 static struct resource_spec jme_irq_spec_legacy[] = { 202 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 203 { -1, 0, 0 } 204 }; 205 206 static struct resource_spec jme_irq_spec_msi[] = { 207 { SYS_RES_IRQ, 1, RF_ACTIVE }, 208 { -1, 0, 0 } 209 }; 210 211 /* 212 * Read a PHY register on the MII of the JMC250. 213 */ 214 static int 215 jme_miibus_readreg(device_t dev, int phy, int reg) 216 { 217 struct jme_softc *sc; 218 uint32_t val; 219 int i; 220 221 sc = device_get_softc(dev); 222 223 /* For FPGA version, PHY address 0 should be ignored. */ 224 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 225 return (0); 226 227 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 228 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 229 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 230 DELAY(1); 231 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 232 break; 233 } 234 235 if (i == 0) { 236 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 237 return (0); 238 } 239 240 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 241 } 242 243 /* 244 * Write a PHY register on the MII of the JMC250. 245 */ 246 static int 247 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 248 { 249 struct jme_softc *sc; 250 int i; 251 252 sc = device_get_softc(dev); 253 254 /* For FPGA version, PHY address 0 should be ignored. */ 255 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 256 return (0); 257 258 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 259 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 260 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 261 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 262 DELAY(1); 263 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 264 break; 265 } 266 267 if (i == 0) 268 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 269 270 return (0); 271 } 272 273 /* 274 * Callback from MII layer when media changes. 275 */ 276 static void 277 jme_miibus_statchg(device_t dev) 278 { 279 struct jme_softc *sc; 280 281 sc = device_get_softc(dev); 282 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 283 } 284 285 /* 286 * Get the current interface media status. 287 */ 288 static void 289 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 290 { 291 struct jme_softc *sc; 292 struct mii_data *mii; 293 294 sc = ifp->if_softc; 295 JME_LOCK(sc); 296 if ((ifp->if_flags & IFF_UP) == 0) { 297 JME_UNLOCK(sc); 298 return; 299 } 300 mii = device_get_softc(sc->jme_miibus); 301 302 mii_pollstat(mii); 303 ifmr->ifm_status = mii->mii_media_status; 304 ifmr->ifm_active = mii->mii_media_active; 305 JME_UNLOCK(sc); 306 } 307 308 /* 309 * Set hardware to newly-selected media. 310 */ 311 static int 312 jme_mediachange(struct ifnet *ifp) 313 { 314 struct jme_softc *sc; 315 struct mii_data *mii; 316 struct mii_softc *miisc; 317 int error; 318 319 sc = ifp->if_softc; 320 JME_LOCK(sc); 321 mii = device_get_softc(sc->jme_miibus); 322 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 323 PHY_RESET(miisc); 324 error = mii_mediachg(mii); 325 JME_UNLOCK(sc); 326 327 return (error); 328 } 329 330 static int 331 jme_probe(device_t dev) 332 { 333 struct jme_dev *sp; 334 int i; 335 uint16_t vendor, devid; 336 337 vendor = pci_get_vendor(dev); 338 devid = pci_get_device(dev); 339 sp = jme_devs; 340 for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]); 341 i++, sp++) { 342 if (vendor == sp->jme_vendorid && 343 devid == sp->jme_deviceid) { 344 device_set_desc(dev, sp->jme_name); 345 return (BUS_PROBE_DEFAULT); 346 } 347 } 348 349 return (ENXIO); 350 } 351 352 static int 353 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 354 { 355 uint32_t reg; 356 int i; 357 358 *val = 0; 359 for (i = JME_TIMEOUT; i > 0; i--) { 360 reg = CSR_READ_4(sc, JME_SMBCSR); 361 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 362 break; 363 DELAY(1); 364 } 365 366 if (i == 0) { 367 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 368 return (ETIMEDOUT); 369 } 370 371 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 372 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 373 for (i = JME_TIMEOUT; i > 0; i--) { 374 DELAY(1); 375 reg = CSR_READ_4(sc, JME_SMBINTF); 376 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 377 break; 378 } 379 380 if (i == 0) { 381 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 382 return (ETIMEDOUT); 383 } 384 385 reg = CSR_READ_4(sc, JME_SMBINTF); 386 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 387 388 return (0); 389 } 390 391 static int 392 jme_eeprom_macaddr(struct jme_softc *sc) 393 { 394 uint8_t eaddr[ETHER_ADDR_LEN]; 395 uint8_t fup, reg, val; 396 uint32_t offset; 397 int match; 398 399 offset = 0; 400 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 401 fup != JME_EEPROM_SIG0) 402 return (ENOENT); 403 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 404 fup != JME_EEPROM_SIG1) 405 return (ENOENT); 406 match = 0; 407 do { 408 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 409 break; 410 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 411 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 412 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 413 break; 414 if (reg >= JME_PAR0 && 415 reg < JME_PAR0 + ETHER_ADDR_LEN) { 416 if (jme_eeprom_read_byte(sc, offset + 2, 417 &val) != 0) 418 break; 419 eaddr[reg - JME_PAR0] = val; 420 match++; 421 } 422 } 423 /* Check for the end of EEPROM descriptor. */ 424 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 425 break; 426 /* Try next eeprom descriptor. */ 427 offset += JME_EEPROM_DESC_BYTES; 428 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 429 430 if (match == ETHER_ADDR_LEN) { 431 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 432 return (0); 433 } 434 435 return (ENOENT); 436 } 437 438 static int 439 jme_efuse_macaddr(struct jme_softc *sc) 440 { 441 uint32_t reg; 442 int i; 443 444 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 445 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) != 446 EFUSE_CTL1_AUTOLAOD_DONE) 447 return (ENOENT); 448 /* Reset eFuse controller. */ 449 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 450 reg |= EFUSE_CTL2_RESET; 451 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 452 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 453 reg &= ~EFUSE_CTL2_RESET; 454 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 455 456 /* Have eFuse reload station address to MAC controller. */ 457 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 458 reg &= ~EFUSE_CTL1_CMD_MASK; 459 reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE; 460 pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4); 461 462 /* 463 * Verify completion of eFuse autload command. It should be 464 * completed within 108us. 465 */ 466 DELAY(110); 467 for (i = 10; i > 0; i--) { 468 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 469 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | 470 EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) { 471 DELAY(20); 472 continue; 473 } 474 if ((reg & EFUSE_CTL1_EXECUTE) == 0) 475 break; 476 /* Station address loading is still in progress. */ 477 DELAY(20); 478 } 479 if (i == 0) { 480 device_printf(sc->jme_dev, "eFuse autoload timed out.\n"); 481 return (ETIMEDOUT); 482 } 483 484 return (0); 485 } 486 487 static void 488 jme_reg_macaddr(struct jme_softc *sc) 489 { 490 uint32_t par0, par1; 491 492 /* Read station address. */ 493 par0 = CSR_READ_4(sc, JME_PAR0); 494 par1 = CSR_READ_4(sc, JME_PAR1); 495 par1 &= 0xFFFF; 496 if ((par0 == 0 && par1 == 0) || 497 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 498 device_printf(sc->jme_dev, 499 "Failed to retrieve Ethernet address.\n"); 500 } else { 501 /* 502 * For controllers that use eFuse, the station address 503 * could also be extracted from JME_PCI_PAR0 and 504 * JME_PCI_PAR1 registers in PCI configuration space. 505 * Each register holds exactly half of station address(24bits) 506 * so use JME_PAR0, JME_PAR1 registers instead. 507 */ 508 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 509 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 510 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 511 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 512 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 513 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 514 } 515 } 516 517 static void 518 jme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr) 519 { 520 uint32_t val; 521 int i; 522 523 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 524 /* 525 * Avoid reprogramming station address if the address 526 * is the same as previous one. Note, reprogrammed 527 * station address is permanent as if it was written 528 * to EEPROM. So if station address was changed by 529 * admistrator it's possible to lose factory configured 530 * address when driver fails to restore its address. 531 * (e.g. reboot or system crash) 532 */ 533 if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) { 534 for (i = 0; i < ETHER_ADDR_LEN; i++) { 535 val = JME_EFUSE_EEPROM_FUNC0 << 536 JME_EFUSE_EEPROM_FUNC_SHIFT; 537 val |= JME_EFUSE_EEPROM_PAGE_BAR1 << 538 JME_EFUSE_EEPROM_PAGE_SHIFT; 539 val |= (JME_PAR0 + i) << 540 JME_EFUSE_EEPROM_ADDR_SHIFT; 541 val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT; 542 pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM, 543 val | JME_EFUSE_EEPROM_WRITE, 4); 544 } 545 } 546 } else { 547 CSR_WRITE_4(sc, JME_PAR0, 548 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 549 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 550 } 551 } 552 553 static void 554 jme_map_intr_vector(struct jme_softc *sc) 555 { 556 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 557 558 bzero(map, sizeof(map)); 559 560 /* Map Tx interrupts source to MSI/MSIX vector 2. */ 561 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 562 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 563 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 564 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 565 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 566 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 567 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 568 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 569 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 570 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 571 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 572 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 573 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 574 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 575 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 576 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 577 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 578 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 579 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 580 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 581 582 /* Map Rx interrupts source to MSI/MSIX vector 1. */ 583 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 584 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 585 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 586 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 587 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 588 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 589 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 590 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 591 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 592 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 593 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 594 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 595 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 596 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 597 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 598 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 599 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 600 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 601 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 602 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 603 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 604 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 605 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 606 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 607 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 608 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 609 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 610 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 611 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 612 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 613 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 614 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 615 616 /* Map all other interrupts source to MSI/MSIX vector 0. */ 617 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 618 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 619 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 620 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 621 } 622 623 static int 624 jme_attach(device_t dev) 625 { 626 struct jme_softc *sc; 627 struct ifnet *ifp; 628 struct mii_softc *miisc; 629 struct mii_data *mii; 630 uint32_t reg; 631 uint16_t burst; 632 int error, i, mii_flags, msic, msixc, pmc; 633 634 error = 0; 635 sc = device_get_softc(dev); 636 sc->jme_dev = dev; 637 638 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 639 MTX_DEF); 640 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 641 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 642 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 643 644 /* 645 * Map the device. JMC250 supports both memory mapped and I/O 646 * register space access. Because I/O register access should 647 * use different BARs to access registers it's waste of time 648 * to use I/O register spce access. JMC250 uses 16K to map 649 * entire memory space. 650 */ 651 pci_enable_busmaster(dev); 652 sc->jme_res_spec = jme_res_spec_mem; 653 sc->jme_irq_spec = jme_irq_spec_legacy; 654 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 655 if (error != 0) { 656 device_printf(dev, "cannot allocate memory resources.\n"); 657 goto fail; 658 } 659 660 /* Allocate IRQ resources. */ 661 msixc = pci_msix_count(dev); 662 msic = pci_msi_count(dev); 663 if (bootverbose) { 664 device_printf(dev, "MSIX count : %d\n", msixc); 665 device_printf(dev, "MSI count : %d\n", msic); 666 } 667 668 /* Use 1 MSI/MSI-X. */ 669 if (msixc > 1) 670 msixc = 1; 671 if (msic > 1) 672 msic = 1; 673 /* Prefer MSIX over MSI. */ 674 if (msix_disable == 0 || msi_disable == 0) { 675 if (msix_disable == 0 && msixc > 0 && 676 pci_alloc_msix(dev, &msixc) == 0) { 677 if (msixc == 1) { 678 device_printf(dev, "Using %d MSIX messages.\n", 679 msixc); 680 sc->jme_flags |= JME_FLAG_MSIX; 681 sc->jme_irq_spec = jme_irq_spec_msi; 682 } else 683 pci_release_msi(dev); 684 } 685 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 686 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 687 if (msic == 1) { 688 device_printf(dev, "Using %d MSI messages.\n", 689 msic); 690 sc->jme_flags |= JME_FLAG_MSI; 691 sc->jme_irq_spec = jme_irq_spec_msi; 692 } else 693 pci_release_msi(dev); 694 } 695 /* Map interrupt vector 0, 1 and 2. */ 696 if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 697 (sc->jme_flags & JME_FLAG_MSIX) != 0) 698 jme_map_intr_vector(sc); 699 } 700 701 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 702 if (error != 0) { 703 device_printf(dev, "cannot allocate IRQ resources.\n"); 704 goto fail; 705 } 706 707 sc->jme_rev = pci_get_device(dev); 708 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 709 sc->jme_flags |= JME_FLAG_FASTETH; 710 sc->jme_flags |= JME_FLAG_NOJUMBO; 711 } 712 reg = CSR_READ_4(sc, JME_CHIPMODE); 713 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 714 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 715 CHIPMODE_NOT_FPGA) 716 sc->jme_flags |= JME_FLAG_FPGA; 717 if (bootverbose) { 718 device_printf(dev, "PCI device revision : 0x%04x\n", 719 sc->jme_rev); 720 device_printf(dev, "Chip revision : 0x%02x\n", 721 sc->jme_chip_rev); 722 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 723 device_printf(dev, "FPGA revision : 0x%04x\n", 724 (reg & CHIPMODE_FPGA_REV_MASK) >> 725 CHIPMODE_FPGA_REV_SHIFT); 726 } 727 if (sc->jme_chip_rev == 0xFF) { 728 device_printf(dev, "Unknown chip revision : 0x%02x\n", 729 sc->jme_rev); 730 error = ENXIO; 731 goto fail; 732 } 733 734 /* Identify controller features and bugs. */ 735 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 736 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 737 CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 738 sc->jme_flags |= JME_FLAG_DMA32BIT; 739 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 740 sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD; 741 sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK; 742 sc->jme_flags |= JME_FLAG_HWMIB; 743 } 744 745 /* Reset the ethernet controller. */ 746 jme_reset(sc); 747 748 /* Get station address. */ 749 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 750 error = jme_efuse_macaddr(sc); 751 if (error == 0) 752 jme_reg_macaddr(sc); 753 } else { 754 error = ENOENT; 755 reg = CSR_READ_4(sc, JME_SMBCSR); 756 if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 757 error = jme_eeprom_macaddr(sc); 758 if (error != 0 && bootverbose) 759 device_printf(sc->jme_dev, 760 "ethernet hardware address not found in EEPROM.\n"); 761 if (error != 0) 762 jme_reg_macaddr(sc); 763 } 764 765 /* 766 * Save PHY address. 767 * Integrated JR0211 has fixed PHY address whereas FPGA version 768 * requires PHY probing to get correct PHY address. 769 */ 770 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 771 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 772 GPREG0_PHY_ADDR_MASK; 773 if (bootverbose) 774 device_printf(dev, "PHY is at address %d.\n", 775 sc->jme_phyaddr); 776 } else 777 sc->jme_phyaddr = 0; 778 779 /* Set max allowable DMA size. */ 780 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 781 sc->jme_flags |= JME_FLAG_PCIE; 782 burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 783 if (bootverbose) { 784 device_printf(dev, "Read request size : %d bytes.\n", 785 128 << ((burst >> 12) & 0x07)); 786 device_printf(dev, "TLP payload size : %d bytes.\n", 787 128 << ((burst >> 5) & 0x07)); 788 } 789 switch ((burst >> 12) & 0x07) { 790 case 0: 791 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 792 break; 793 case 1: 794 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 795 break; 796 default: 797 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 798 break; 799 } 800 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 801 } else { 802 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 803 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 804 } 805 /* Create coalescing sysctl node. */ 806 jme_sysctl_node(sc); 807 if ((error = jme_dma_alloc(sc) != 0)) 808 goto fail; 809 810 ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 811 if (ifp == NULL) { 812 device_printf(dev, "cannot allocate ifnet structure.\n"); 813 error = ENXIO; 814 goto fail; 815 } 816 817 ifp->if_softc = sc; 818 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 819 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 820 ifp->if_ioctl = jme_ioctl; 821 ifp->if_start = jme_start; 822 ifp->if_init = jme_init; 823 ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1; 824 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 825 IFQ_SET_READY(&ifp->if_snd); 826 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 827 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 828 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO; 829 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 830 sc->jme_flags |= JME_FLAG_PMCAP; 831 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 832 } 833 ifp->if_capenable = ifp->if_capabilities; 834 835 /* Wakeup PHY. */ 836 jme_phy_up(sc); 837 mii_flags = MIIF_DOPAUSE; 838 /* Ask PHY calibration to PHY driver. */ 839 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 840 mii_flags |= MIIF_MACPRIV0; 841 /* Set up MII bus. */ 842 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange, 843 jme_mediastatus, BMSR_DEFCAPMASK, 844 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr, 845 MII_OFFSET_ANY, mii_flags); 846 if (error != 0) { 847 device_printf(dev, "attaching PHYs failed\n"); 848 goto fail; 849 } 850 851 /* 852 * Force PHY to FPGA mode. 853 */ 854 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 855 mii = device_get_softc(sc->jme_miibus); 856 if (mii->mii_instance != 0) { 857 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 858 if (miisc->mii_phy != 0) { 859 sc->jme_phyaddr = miisc->mii_phy; 860 break; 861 } 862 } 863 if (sc->jme_phyaddr != 0) { 864 device_printf(sc->jme_dev, 865 "FPGA PHY is at %d\n", sc->jme_phyaddr); 866 /* vendor magic. */ 867 jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 868 0x0004); 869 } 870 } 871 } 872 873 ether_ifattach(ifp, sc->jme_eaddr); 874 875 /* VLAN capability setup */ 876 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 877 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 878 ifp->if_capenable = ifp->if_capabilities; 879 880 /* Tell the upper layer(s) we support long frames. */ 881 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 882 883 /* Create local taskq. */ 884 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 885 taskqueue_thread_enqueue, &sc->jme_tq); 886 if (sc->jme_tq == NULL) { 887 device_printf(dev, "could not create taskqueue.\n"); 888 ether_ifdetach(ifp); 889 error = ENXIO; 890 goto fail; 891 } 892 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 893 device_get_nameunit(sc->jme_dev)); 894 895 for (i = 0; i < 1; i++) { 896 error = bus_setup_intr(dev, sc->jme_irq[i], 897 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 898 &sc->jme_intrhand[i]); 899 if (error != 0) 900 break; 901 } 902 903 if (error != 0) { 904 device_printf(dev, "could not set up interrupt handler.\n"); 905 taskqueue_free(sc->jme_tq); 906 sc->jme_tq = NULL; 907 ether_ifdetach(ifp); 908 goto fail; 909 } 910 911 fail: 912 if (error != 0) 913 jme_detach(dev); 914 915 return (error); 916 } 917 918 static int 919 jme_detach(device_t dev) 920 { 921 struct jme_softc *sc; 922 struct ifnet *ifp; 923 int i; 924 925 sc = device_get_softc(dev); 926 927 ifp = sc->jme_ifp; 928 if (device_is_attached(dev)) { 929 JME_LOCK(sc); 930 sc->jme_flags |= JME_FLAG_DETACH; 931 jme_stop(sc); 932 JME_UNLOCK(sc); 933 callout_drain(&sc->jme_tick_ch); 934 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 935 taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 936 /* Restore possibly modified station address. */ 937 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) 938 jme_set_macaddr(sc, sc->jme_eaddr); 939 ether_ifdetach(ifp); 940 } 941 942 if (sc->jme_tq != NULL) { 943 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 944 taskqueue_free(sc->jme_tq); 945 sc->jme_tq = NULL; 946 } 947 948 if (sc->jme_miibus != NULL) { 949 device_delete_child(dev, sc->jme_miibus); 950 sc->jme_miibus = NULL; 951 } 952 bus_generic_detach(dev); 953 jme_dma_free(sc); 954 955 if (ifp != NULL) { 956 if_free(ifp); 957 sc->jme_ifp = NULL; 958 } 959 960 for (i = 0; i < 1; i++) { 961 if (sc->jme_intrhand[i] != NULL) { 962 bus_teardown_intr(dev, sc->jme_irq[i], 963 sc->jme_intrhand[i]); 964 sc->jme_intrhand[i] = NULL; 965 } 966 } 967 968 if (sc->jme_irq[0] != NULL) 969 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 970 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 971 pci_release_msi(dev); 972 if (sc->jme_res[0] != NULL) 973 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 974 mtx_destroy(&sc->jme_mtx); 975 976 return (0); 977 } 978 979 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 980 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 981 982 static void 983 jme_sysctl_node(struct jme_softc *sc) 984 { 985 struct sysctl_ctx_list *ctx; 986 struct sysctl_oid_list *child, *parent; 987 struct sysctl_oid *tree; 988 struct jme_hw_stats *stats; 989 int error; 990 991 stats = &sc->jme_stats; 992 ctx = device_get_sysctl_ctx(sc->jme_dev); 993 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)); 994 995 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to", 996 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0, 997 sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 998 999 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", 1000 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0, 1001 sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 1002 1003 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to", 1004 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0, 1005 sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 1006 1007 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", 1008 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0, 1009 sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 1010 1011 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1012 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0, 1013 sysctl_hw_jme_proc_limit, "I", 1014 "max number of Rx events to process"); 1015 1016 /* Pull in device tunables. */ 1017 sc->jme_process_limit = JME_PROC_DEFAULT; 1018 error = resource_int_value(device_get_name(sc->jme_dev), 1019 device_get_unit(sc->jme_dev), "process_limit", 1020 &sc->jme_process_limit); 1021 if (error == 0) { 1022 if (sc->jme_process_limit < JME_PROC_MIN || 1023 sc->jme_process_limit > JME_PROC_MAX) { 1024 device_printf(sc->jme_dev, 1025 "process_limit value out of range; " 1026 "using default: %d\n", JME_PROC_DEFAULT); 1027 sc->jme_process_limit = JME_PROC_DEFAULT; 1028 } 1029 } 1030 1031 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1032 error = resource_int_value(device_get_name(sc->jme_dev), 1033 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 1034 if (error == 0) { 1035 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 1036 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 1037 device_printf(sc->jme_dev, 1038 "tx_coal_to value out of range; " 1039 "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 1040 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1041 } 1042 } 1043 1044 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1045 error = resource_int_value(device_get_name(sc->jme_dev), 1046 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 1047 if (error == 0) { 1048 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 1049 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 1050 device_printf(sc->jme_dev, 1051 "tx_coal_pkt value out of range; " 1052 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 1053 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1054 } 1055 } 1056 1057 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1058 error = resource_int_value(device_get_name(sc->jme_dev), 1059 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 1060 if (error == 0) { 1061 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 1062 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 1063 device_printf(sc->jme_dev, 1064 "rx_coal_to value out of range; " 1065 "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 1066 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1067 } 1068 } 1069 1070 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1071 error = resource_int_value(device_get_name(sc->jme_dev), 1072 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 1073 if (error == 0) { 1074 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 1075 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 1076 device_printf(sc->jme_dev, 1077 "tx_coal_pkt value out of range; " 1078 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 1079 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1080 } 1081 } 1082 1083 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 1084 return; 1085 1086 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1087 NULL, "JME statistics"); 1088 parent = SYSCTL_CHILDREN(tree); 1089 1090 /* Rx statistics. */ 1091 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1092 NULL, "Rx MAC statistics"); 1093 child = SYSCTL_CHILDREN(tree); 1094 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1095 &stats->rx_good_frames, "Good frames"); 1096 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1097 &stats->rx_crc_errs, "CRC errors"); 1098 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs", 1099 &stats->rx_mii_errs, "MII errors"); 1100 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1101 &stats->rx_fifo_oflows, "FIFO overflows"); 1102 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty", 1103 &stats->rx_desc_empty, "Descriptor empty"); 1104 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1105 &stats->rx_bad_frames, "Bad frames"); 1106 1107 /* Tx statistics. */ 1108 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1109 NULL, "Tx MAC statistics"); 1110 child = SYSCTL_CHILDREN(tree); 1111 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1112 &stats->tx_good_frames, "Good frames"); 1113 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1114 &stats->tx_bad_frames, "Bad frames"); 1115 } 1116 1117 #undef JME_SYSCTL_STAT_ADD32 1118 1119 struct jme_dmamap_arg { 1120 bus_addr_t jme_busaddr; 1121 }; 1122 1123 static void 1124 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1125 { 1126 struct jme_dmamap_arg *ctx; 1127 1128 if (error != 0) 1129 return; 1130 1131 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1132 1133 ctx = (struct jme_dmamap_arg *)arg; 1134 ctx->jme_busaddr = segs[0].ds_addr; 1135 } 1136 1137 static int 1138 jme_dma_alloc(struct jme_softc *sc) 1139 { 1140 struct jme_dmamap_arg ctx; 1141 struct jme_txdesc *txd; 1142 struct jme_rxdesc *rxd; 1143 bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1144 int error, i; 1145 1146 lowaddr = BUS_SPACE_MAXADDR; 1147 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1148 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1149 1150 again: 1151 /* Create parent ring tag. */ 1152 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1153 1, 0, /* algnmnt, boundary */ 1154 lowaddr, /* lowaddr */ 1155 BUS_SPACE_MAXADDR, /* highaddr */ 1156 NULL, NULL, /* filter, filterarg */ 1157 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1158 0, /* nsegments */ 1159 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1160 0, /* flags */ 1161 NULL, NULL, /* lockfunc, lockarg */ 1162 &sc->jme_cdata.jme_ring_tag); 1163 if (error != 0) { 1164 device_printf(sc->jme_dev, 1165 "could not create parent ring DMA tag.\n"); 1166 goto fail; 1167 } 1168 /* Create tag for Tx ring. */ 1169 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1170 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1171 BUS_SPACE_MAXADDR, /* lowaddr */ 1172 BUS_SPACE_MAXADDR, /* highaddr */ 1173 NULL, NULL, /* filter, filterarg */ 1174 JME_TX_RING_SIZE, /* maxsize */ 1175 1, /* nsegments */ 1176 JME_TX_RING_SIZE, /* maxsegsize */ 1177 0, /* flags */ 1178 NULL, NULL, /* lockfunc, lockarg */ 1179 &sc->jme_cdata.jme_tx_ring_tag); 1180 if (error != 0) { 1181 device_printf(sc->jme_dev, 1182 "could not allocate Tx ring DMA tag.\n"); 1183 goto fail; 1184 } 1185 1186 /* Create tag for Rx ring. */ 1187 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1188 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1189 lowaddr, /* lowaddr */ 1190 BUS_SPACE_MAXADDR, /* highaddr */ 1191 NULL, NULL, /* filter, filterarg */ 1192 JME_RX_RING_SIZE, /* maxsize */ 1193 1, /* nsegments */ 1194 JME_RX_RING_SIZE, /* maxsegsize */ 1195 0, /* flags */ 1196 NULL, NULL, /* lockfunc, lockarg */ 1197 &sc->jme_cdata.jme_rx_ring_tag); 1198 if (error != 0) { 1199 device_printf(sc->jme_dev, 1200 "could not allocate Rx ring DMA tag.\n"); 1201 goto fail; 1202 } 1203 1204 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1205 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1206 (void **)&sc->jme_rdata.jme_tx_ring, 1207 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1208 &sc->jme_cdata.jme_tx_ring_map); 1209 if (error != 0) { 1210 device_printf(sc->jme_dev, 1211 "could not allocate DMA'able memory for Tx ring.\n"); 1212 goto fail; 1213 } 1214 1215 ctx.jme_busaddr = 0; 1216 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1217 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1218 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1219 if (error != 0 || ctx.jme_busaddr == 0) { 1220 device_printf(sc->jme_dev, 1221 "could not load DMA'able memory for Tx ring.\n"); 1222 goto fail; 1223 } 1224 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1225 1226 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1227 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1228 (void **)&sc->jme_rdata.jme_rx_ring, 1229 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1230 &sc->jme_cdata.jme_rx_ring_map); 1231 if (error != 0) { 1232 device_printf(sc->jme_dev, 1233 "could not allocate DMA'able memory for Rx ring.\n"); 1234 goto fail; 1235 } 1236 1237 ctx.jme_busaddr = 0; 1238 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1239 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1240 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1241 if (error != 0 || ctx.jme_busaddr == 0) { 1242 device_printf(sc->jme_dev, 1243 "could not load DMA'able memory for Rx ring.\n"); 1244 goto fail; 1245 } 1246 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1247 1248 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1249 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1250 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1251 JME_TX_RING_SIZE; 1252 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1253 JME_RX_RING_SIZE; 1254 if ((JME_ADDR_HI(tx_ring_end) != 1255 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1256 (JME_ADDR_HI(rx_ring_end) != 1257 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1258 device_printf(sc->jme_dev, "4GB boundary crossed, " 1259 "switching to 32bit DMA address mode.\n"); 1260 jme_dma_free(sc); 1261 /* Limit DMA address space to 32bit and try again. */ 1262 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1263 goto again; 1264 } 1265 } 1266 1267 lowaddr = BUS_SPACE_MAXADDR; 1268 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1269 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1270 /* Create parent buffer tag. */ 1271 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1272 1, 0, /* algnmnt, boundary */ 1273 lowaddr, /* lowaddr */ 1274 BUS_SPACE_MAXADDR, /* highaddr */ 1275 NULL, NULL, /* filter, filterarg */ 1276 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1277 0, /* nsegments */ 1278 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1279 0, /* flags */ 1280 NULL, NULL, /* lockfunc, lockarg */ 1281 &sc->jme_cdata.jme_buffer_tag); 1282 if (error != 0) { 1283 device_printf(sc->jme_dev, 1284 "could not create parent buffer DMA tag.\n"); 1285 goto fail; 1286 } 1287 1288 /* Create shadow status block tag. */ 1289 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1290 JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1291 BUS_SPACE_MAXADDR, /* lowaddr */ 1292 BUS_SPACE_MAXADDR, /* highaddr */ 1293 NULL, NULL, /* filter, filterarg */ 1294 JME_SSB_SIZE, /* maxsize */ 1295 1, /* nsegments */ 1296 JME_SSB_SIZE, /* maxsegsize */ 1297 0, /* flags */ 1298 NULL, NULL, /* lockfunc, lockarg */ 1299 &sc->jme_cdata.jme_ssb_tag); 1300 if (error != 0) { 1301 device_printf(sc->jme_dev, 1302 "could not create shared status block DMA tag.\n"); 1303 goto fail; 1304 } 1305 1306 /* Create tag for Tx buffers. */ 1307 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1308 1, 0, /* algnmnt, boundary */ 1309 BUS_SPACE_MAXADDR, /* lowaddr */ 1310 BUS_SPACE_MAXADDR, /* highaddr */ 1311 NULL, NULL, /* filter, filterarg */ 1312 JME_TSO_MAXSIZE, /* maxsize */ 1313 JME_MAXTXSEGS, /* nsegments */ 1314 JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1315 0, /* flags */ 1316 NULL, NULL, /* lockfunc, lockarg */ 1317 &sc->jme_cdata.jme_tx_tag); 1318 if (error != 0) { 1319 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1320 goto fail; 1321 } 1322 1323 /* Create tag for Rx buffers. */ 1324 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1325 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1326 BUS_SPACE_MAXADDR, /* lowaddr */ 1327 BUS_SPACE_MAXADDR, /* highaddr */ 1328 NULL, NULL, /* filter, filterarg */ 1329 MCLBYTES, /* maxsize */ 1330 1, /* nsegments */ 1331 MCLBYTES, /* maxsegsize */ 1332 0, /* flags */ 1333 NULL, NULL, /* lockfunc, lockarg */ 1334 &sc->jme_cdata.jme_rx_tag); 1335 if (error != 0) { 1336 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1337 goto fail; 1338 } 1339 1340 /* 1341 * Allocate DMA'able memory and load the DMA map for shared 1342 * status block. 1343 */ 1344 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1345 (void **)&sc->jme_rdata.jme_ssb_block, 1346 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1347 &sc->jme_cdata.jme_ssb_map); 1348 if (error != 0) { 1349 device_printf(sc->jme_dev, "could not allocate DMA'able " 1350 "memory for shared status block.\n"); 1351 goto fail; 1352 } 1353 1354 ctx.jme_busaddr = 0; 1355 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1356 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1357 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1358 if (error != 0 || ctx.jme_busaddr == 0) { 1359 device_printf(sc->jme_dev, "could not load DMA'able memory " 1360 "for shared status block.\n"); 1361 goto fail; 1362 } 1363 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1364 1365 /* Create DMA maps for Tx buffers. */ 1366 for (i = 0; i < JME_TX_RING_CNT; i++) { 1367 txd = &sc->jme_cdata.jme_txdesc[i]; 1368 txd->tx_m = NULL; 1369 txd->tx_dmamap = NULL; 1370 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1371 &txd->tx_dmamap); 1372 if (error != 0) { 1373 device_printf(sc->jme_dev, 1374 "could not create Tx dmamap.\n"); 1375 goto fail; 1376 } 1377 } 1378 /* Create DMA maps for Rx buffers. */ 1379 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1380 &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1381 device_printf(sc->jme_dev, 1382 "could not create spare Rx dmamap.\n"); 1383 goto fail; 1384 } 1385 for (i = 0; i < JME_RX_RING_CNT; i++) { 1386 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1387 rxd->rx_m = NULL; 1388 rxd->rx_dmamap = NULL; 1389 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1390 &rxd->rx_dmamap); 1391 if (error != 0) { 1392 device_printf(sc->jme_dev, 1393 "could not create Rx dmamap.\n"); 1394 goto fail; 1395 } 1396 } 1397 1398 fail: 1399 return (error); 1400 } 1401 1402 static void 1403 jme_dma_free(struct jme_softc *sc) 1404 { 1405 struct jme_txdesc *txd; 1406 struct jme_rxdesc *rxd; 1407 int i; 1408 1409 /* Tx ring */ 1410 if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1411 if (sc->jme_rdata.jme_tx_ring_paddr) 1412 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1413 sc->jme_cdata.jme_tx_ring_map); 1414 if (sc->jme_rdata.jme_tx_ring) 1415 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1416 sc->jme_rdata.jme_tx_ring, 1417 sc->jme_cdata.jme_tx_ring_map); 1418 sc->jme_rdata.jme_tx_ring = NULL; 1419 sc->jme_rdata.jme_tx_ring_paddr = 0; 1420 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1421 sc->jme_cdata.jme_tx_ring_tag = NULL; 1422 } 1423 /* Rx ring */ 1424 if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1425 if (sc->jme_rdata.jme_rx_ring_paddr) 1426 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1427 sc->jme_cdata.jme_rx_ring_map); 1428 if (sc->jme_rdata.jme_rx_ring) 1429 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1430 sc->jme_rdata.jme_rx_ring, 1431 sc->jme_cdata.jme_rx_ring_map); 1432 sc->jme_rdata.jme_rx_ring = NULL; 1433 sc->jme_rdata.jme_rx_ring_paddr = 0; 1434 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1435 sc->jme_cdata.jme_rx_ring_tag = NULL; 1436 } 1437 /* Tx buffers */ 1438 if (sc->jme_cdata.jme_tx_tag != NULL) { 1439 for (i = 0; i < JME_TX_RING_CNT; i++) { 1440 txd = &sc->jme_cdata.jme_txdesc[i]; 1441 if (txd->tx_dmamap != NULL) { 1442 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1443 txd->tx_dmamap); 1444 txd->tx_dmamap = NULL; 1445 } 1446 } 1447 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1448 sc->jme_cdata.jme_tx_tag = NULL; 1449 } 1450 /* Rx buffers */ 1451 if (sc->jme_cdata.jme_rx_tag != NULL) { 1452 for (i = 0; i < JME_RX_RING_CNT; i++) { 1453 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1454 if (rxd->rx_dmamap != NULL) { 1455 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1456 rxd->rx_dmamap); 1457 rxd->rx_dmamap = NULL; 1458 } 1459 } 1460 if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1461 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1462 sc->jme_cdata.jme_rx_sparemap); 1463 sc->jme_cdata.jme_rx_sparemap = NULL; 1464 } 1465 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1466 sc->jme_cdata.jme_rx_tag = NULL; 1467 } 1468 1469 /* Shared status block. */ 1470 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1471 if (sc->jme_rdata.jme_ssb_block_paddr) 1472 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1473 sc->jme_cdata.jme_ssb_map); 1474 if (sc->jme_rdata.jme_ssb_block) 1475 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1476 sc->jme_rdata.jme_ssb_block, 1477 sc->jme_cdata.jme_ssb_map); 1478 sc->jme_rdata.jme_ssb_block = NULL; 1479 sc->jme_rdata.jme_ssb_block_paddr = 0; 1480 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1481 sc->jme_cdata.jme_ssb_tag = NULL; 1482 } 1483 1484 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1485 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1486 sc->jme_cdata.jme_buffer_tag = NULL; 1487 } 1488 if (sc->jme_cdata.jme_ring_tag != NULL) { 1489 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1490 sc->jme_cdata.jme_ring_tag = NULL; 1491 } 1492 } 1493 1494 /* 1495 * Make sure the interface is stopped at reboot time. 1496 */ 1497 static int 1498 jme_shutdown(device_t dev) 1499 { 1500 1501 return (jme_suspend(dev)); 1502 } 1503 1504 /* 1505 * Unlike other ethernet controllers, JMC250 requires 1506 * explicit resetting link speed to 10/100Mbps as gigabit 1507 * link will cunsume more power than 375mA. 1508 * Note, we reset the link speed to 10/100Mbps with 1509 * auto-negotiation but we don't know whether that operation 1510 * would succeed or not as we have no control after powering 1511 * off. If the renegotiation fail WOL may not work. Running 1512 * at 1Gbps draws more power than 375mA at 3.3V which is 1513 * specified in PCI specification and that would result in 1514 * complete shutdowning power to ethernet controller. 1515 * 1516 * TODO 1517 * Save current negotiated media speed/duplex/flow-control 1518 * to softc and restore the same link again after resuming. 1519 * PHY handling such as power down/resetting to 100Mbps 1520 * may be better handled in suspend method in phy driver. 1521 */ 1522 static void 1523 jme_setlinkspeed(struct jme_softc *sc) 1524 { 1525 struct mii_data *mii; 1526 int aneg, i; 1527 1528 JME_LOCK_ASSERT(sc); 1529 1530 mii = device_get_softc(sc->jme_miibus); 1531 mii_pollstat(mii); 1532 aneg = 0; 1533 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1534 switch IFM_SUBTYPE(mii->mii_media_active) { 1535 case IFM_10_T: 1536 case IFM_100_TX: 1537 return; 1538 case IFM_1000_T: 1539 aneg++; 1540 default: 1541 break; 1542 } 1543 } 1544 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1545 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1546 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1547 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1548 BMCR_AUTOEN | BMCR_STARTNEG); 1549 DELAY(1000); 1550 if (aneg != 0) { 1551 /* Poll link state until jme(4) get a 10/100 link. */ 1552 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1553 mii_pollstat(mii); 1554 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1555 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1556 case IFM_10_T: 1557 case IFM_100_TX: 1558 jme_mac_config(sc); 1559 return; 1560 default: 1561 break; 1562 } 1563 } 1564 JME_UNLOCK(sc); 1565 pause("jmelnk", hz); 1566 JME_LOCK(sc); 1567 } 1568 if (i == MII_ANEGTICKS_GIGE) 1569 device_printf(sc->jme_dev, "establishing link failed, " 1570 "WOL may not work!"); 1571 } 1572 /* 1573 * No link, force MAC to have 100Mbps, full-duplex link. 1574 * This is the last resort and may/may not work. 1575 */ 1576 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1577 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1578 jme_mac_config(sc); 1579 } 1580 1581 static void 1582 jme_setwol(struct jme_softc *sc) 1583 { 1584 struct ifnet *ifp; 1585 uint32_t gpr, pmcs; 1586 uint16_t pmstat; 1587 int pmc; 1588 1589 JME_LOCK_ASSERT(sc); 1590 1591 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1592 /* Remove Tx MAC/offload clock to save more power. */ 1593 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1594 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1595 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1596 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1597 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 1598 CSR_WRITE_4(sc, JME_GPREG1, 1599 CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS); 1600 /* No PME capability, PHY power down. */ 1601 jme_phy_down(sc); 1602 return; 1603 } 1604 1605 ifp = sc->jme_ifp; 1606 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1607 pmcs = CSR_READ_4(sc, JME_PMCS); 1608 pmcs &= ~PMCS_WOL_ENB_MASK; 1609 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1610 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1611 /* Enable PME message. */ 1612 gpr |= GPREG0_PME_ENB; 1613 /* For gigabit controllers, reset link speed to 10/100. */ 1614 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1615 jme_setlinkspeed(sc); 1616 } 1617 1618 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1619 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1620 /* Remove Tx MAC/offload clock to save more power. */ 1621 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1622 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1623 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1624 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1625 /* Request PME. */ 1626 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1627 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1628 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1629 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1630 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1631 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1632 /* No WOL, PHY power down. */ 1633 jme_phy_down(sc); 1634 } 1635 } 1636 1637 static int 1638 jme_suspend(device_t dev) 1639 { 1640 struct jme_softc *sc; 1641 1642 sc = device_get_softc(dev); 1643 1644 JME_LOCK(sc); 1645 jme_stop(sc); 1646 jme_setwol(sc); 1647 JME_UNLOCK(sc); 1648 1649 return (0); 1650 } 1651 1652 static int 1653 jme_resume(device_t dev) 1654 { 1655 struct jme_softc *sc; 1656 struct ifnet *ifp; 1657 uint16_t pmstat; 1658 int pmc; 1659 1660 sc = device_get_softc(dev); 1661 1662 JME_LOCK(sc); 1663 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) == 0) { 1664 pmstat = pci_read_config(sc->jme_dev, 1665 pmc + PCIR_POWER_STATUS, 2); 1666 /* Disable PME clear PME status. */ 1667 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1668 pci_write_config(sc->jme_dev, 1669 pmc + PCIR_POWER_STATUS, pmstat, 2); 1670 } 1671 /* Wakeup PHY. */ 1672 jme_phy_up(sc); 1673 ifp = sc->jme_ifp; 1674 if ((ifp->if_flags & IFF_UP) != 0) { 1675 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1676 jme_init_locked(sc); 1677 } 1678 1679 JME_UNLOCK(sc); 1680 1681 return (0); 1682 } 1683 1684 static int 1685 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1686 { 1687 struct jme_txdesc *txd; 1688 struct jme_desc *desc; 1689 struct mbuf *m; 1690 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1691 int error, i, nsegs, prod; 1692 uint32_t cflags, tsosegsz; 1693 1694 JME_LOCK_ASSERT(sc); 1695 1696 M_ASSERTPKTHDR((*m_head)); 1697 1698 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1699 /* 1700 * Due to the adherence to NDIS specification JMC250 1701 * assumes upper stack computed TCP pseudo checksum 1702 * without including payload length. This breaks 1703 * checksum offload for TSO case so recompute TCP 1704 * pseudo checksum for JMC250. Hopefully this wouldn't 1705 * be much burden on modern CPUs. 1706 */ 1707 struct ether_header *eh; 1708 struct ip *ip; 1709 struct tcphdr *tcp; 1710 uint32_t ip_off, poff; 1711 1712 if (M_WRITABLE(*m_head) == 0) { 1713 /* Get a writable copy. */ 1714 m = m_dup(*m_head, M_NOWAIT); 1715 m_freem(*m_head); 1716 if (m == NULL) { 1717 *m_head = NULL; 1718 return (ENOBUFS); 1719 } 1720 *m_head = m; 1721 } 1722 ip_off = sizeof(struct ether_header); 1723 m = m_pullup(*m_head, ip_off); 1724 if (m == NULL) { 1725 *m_head = NULL; 1726 return (ENOBUFS); 1727 } 1728 eh = mtod(m, struct ether_header *); 1729 /* Check the existence of VLAN tag. */ 1730 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1731 ip_off = sizeof(struct ether_vlan_header); 1732 m = m_pullup(m, ip_off); 1733 if (m == NULL) { 1734 *m_head = NULL; 1735 return (ENOBUFS); 1736 } 1737 } 1738 m = m_pullup(m, ip_off + sizeof(struct ip)); 1739 if (m == NULL) { 1740 *m_head = NULL; 1741 return (ENOBUFS); 1742 } 1743 ip = (struct ip *)(mtod(m, char *) + ip_off); 1744 poff = ip_off + (ip->ip_hl << 2); 1745 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1746 if (m == NULL) { 1747 *m_head = NULL; 1748 return (ENOBUFS); 1749 } 1750 /* 1751 * Reset IP checksum and recompute TCP pseudo 1752 * checksum that NDIS specification requires. 1753 */ 1754 ip = (struct ip *)(mtod(m, char *) + ip_off); 1755 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1756 ip->ip_sum = 0; 1757 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1758 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1759 ip->ip_dst.s_addr, 1760 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1761 /* No need to TSO, force IP checksum offload. */ 1762 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1763 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1764 } else 1765 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1766 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1767 *m_head = m; 1768 } 1769 1770 prod = sc->jme_cdata.jme_tx_prod; 1771 txd = &sc->jme_cdata.jme_txdesc[prod]; 1772 1773 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1774 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1775 if (error == EFBIG) { 1776 m = m_collapse(*m_head, M_NOWAIT, JME_MAXTXSEGS); 1777 if (m == NULL) { 1778 m_freem(*m_head); 1779 *m_head = NULL; 1780 return (ENOMEM); 1781 } 1782 *m_head = m; 1783 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1784 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1785 if (error != 0) { 1786 m_freem(*m_head); 1787 *m_head = NULL; 1788 return (error); 1789 } 1790 } else if (error != 0) 1791 return (error); 1792 if (nsegs == 0) { 1793 m_freem(*m_head); 1794 *m_head = NULL; 1795 return (EIO); 1796 } 1797 1798 /* 1799 * Check descriptor overrun. Leave one free descriptor. 1800 * Since we always use 64bit address mode for transmitting, 1801 * each Tx request requires one more dummy descriptor. 1802 */ 1803 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1804 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1805 return (ENOBUFS); 1806 } 1807 1808 m = *m_head; 1809 cflags = 0; 1810 tsosegsz = 0; 1811 /* Configure checksum offload and TSO. */ 1812 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1813 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 1814 JME_TD_MSS_SHIFT; 1815 cflags |= JME_TD_TSO; 1816 } else { 1817 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1818 cflags |= JME_TD_IPCSUM; 1819 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1820 cflags |= JME_TD_TCPCSUM; 1821 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1822 cflags |= JME_TD_UDPCSUM; 1823 } 1824 /* Configure VLAN. */ 1825 if ((m->m_flags & M_VLANTAG) != 0) { 1826 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1827 cflags |= JME_TD_VLAN_TAG; 1828 } 1829 1830 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1831 desc->flags = htole32(cflags); 1832 desc->buflen = htole32(tsosegsz); 1833 desc->addr_hi = htole32(m->m_pkthdr.len); 1834 desc->addr_lo = 0; 1835 sc->jme_cdata.jme_tx_cnt++; 1836 JME_DESC_INC(prod, JME_TX_RING_CNT); 1837 for (i = 0; i < nsegs; i++) { 1838 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1839 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1840 desc->buflen = htole32(txsegs[i].ds_len); 1841 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1842 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1843 sc->jme_cdata.jme_tx_cnt++; 1844 JME_DESC_INC(prod, JME_TX_RING_CNT); 1845 } 1846 1847 /* Update producer index. */ 1848 sc->jme_cdata.jme_tx_prod = prod; 1849 /* 1850 * Finally request interrupt and give the first descriptor 1851 * owenership to hardware. 1852 */ 1853 desc = txd->tx_desc; 1854 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1855 1856 txd->tx_m = m; 1857 txd->tx_ndesc = nsegs + 1; 1858 1859 /* Sync descriptors. */ 1860 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1861 BUS_DMASYNC_PREWRITE); 1862 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1863 sc->jme_cdata.jme_tx_ring_map, 1864 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1865 1866 return (0); 1867 } 1868 1869 static void 1870 jme_start(struct ifnet *ifp) 1871 { 1872 struct jme_softc *sc; 1873 1874 sc = ifp->if_softc; 1875 JME_LOCK(sc); 1876 jme_start_locked(ifp); 1877 JME_UNLOCK(sc); 1878 } 1879 1880 static void 1881 jme_start_locked(struct ifnet *ifp) 1882 { 1883 struct jme_softc *sc; 1884 struct mbuf *m_head; 1885 int enq; 1886 1887 sc = ifp->if_softc; 1888 1889 JME_LOCK_ASSERT(sc); 1890 1891 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1892 jme_txeof(sc); 1893 1894 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1895 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) 1896 return; 1897 1898 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1899 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1900 if (m_head == NULL) 1901 break; 1902 /* 1903 * Pack the data into the transmit ring. If we 1904 * don't have room, set the OACTIVE flag and wait 1905 * for the NIC to drain the ring. 1906 */ 1907 if (jme_encap(sc, &m_head)) { 1908 if (m_head == NULL) 1909 break; 1910 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1911 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1912 break; 1913 } 1914 1915 enq++; 1916 /* 1917 * If there's a BPF listener, bounce a copy of this frame 1918 * to him. 1919 */ 1920 ETHER_BPF_MTAP(ifp, m_head); 1921 } 1922 1923 if (enq > 0) { 1924 /* 1925 * Reading TXCSR takes very long time under heavy load 1926 * so cache TXCSR value and writes the ORed value with 1927 * the kick command to the TXCSR. This saves one register 1928 * access cycle. 1929 */ 1930 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1931 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1932 /* Set a timeout in case the chip goes out to lunch. */ 1933 sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1934 } 1935 } 1936 1937 static void 1938 jme_watchdog(struct jme_softc *sc) 1939 { 1940 struct ifnet *ifp; 1941 1942 JME_LOCK_ASSERT(sc); 1943 1944 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1945 return; 1946 1947 ifp = sc->jme_ifp; 1948 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1949 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1950 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1951 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1952 jme_init_locked(sc); 1953 return; 1954 } 1955 jme_txeof(sc); 1956 if (sc->jme_cdata.jme_tx_cnt == 0) { 1957 if_printf(sc->jme_ifp, 1958 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1959 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1960 jme_start_locked(ifp); 1961 return; 1962 } 1963 1964 if_printf(sc->jme_ifp, "watchdog timeout\n"); 1965 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1966 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1967 jme_init_locked(sc); 1968 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1969 jme_start_locked(ifp); 1970 } 1971 1972 static int 1973 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1974 { 1975 struct jme_softc *sc; 1976 struct ifreq *ifr; 1977 struct mii_data *mii; 1978 uint32_t reg; 1979 int error, mask; 1980 1981 sc = ifp->if_softc; 1982 ifr = (struct ifreq *)data; 1983 error = 0; 1984 switch (cmd) { 1985 case SIOCSIFMTU: 1986 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1987 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1988 ifr->ifr_mtu > JME_MAX_MTU)) { 1989 error = EINVAL; 1990 break; 1991 } 1992 1993 if (ifp->if_mtu != ifr->ifr_mtu) { 1994 /* 1995 * No special configuration is required when interface 1996 * MTU is changed but availability of TSO/Tx checksum 1997 * offload should be chcked against new MTU size as 1998 * FIFO size is just 2K. 1999 */ 2000 JME_LOCK(sc); 2001 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 2002 ifp->if_capenable &= 2003 ~(IFCAP_TXCSUM | IFCAP_TSO4); 2004 ifp->if_hwassist &= 2005 ~(JME_CSUM_FEATURES | CSUM_TSO); 2006 VLAN_CAPABILITIES(ifp); 2007 } 2008 ifp->if_mtu = ifr->ifr_mtu; 2009 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2010 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2011 jme_init_locked(sc); 2012 } 2013 JME_UNLOCK(sc); 2014 } 2015 break; 2016 case SIOCSIFFLAGS: 2017 JME_LOCK(sc); 2018 if ((ifp->if_flags & IFF_UP) != 0) { 2019 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2020 if (((ifp->if_flags ^ sc->jme_if_flags) 2021 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2022 jme_set_filter(sc); 2023 } else { 2024 if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 2025 jme_init_locked(sc); 2026 } 2027 } else { 2028 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2029 jme_stop(sc); 2030 } 2031 sc->jme_if_flags = ifp->if_flags; 2032 JME_UNLOCK(sc); 2033 break; 2034 case SIOCADDMULTI: 2035 case SIOCDELMULTI: 2036 JME_LOCK(sc); 2037 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2038 jme_set_filter(sc); 2039 JME_UNLOCK(sc); 2040 break; 2041 case SIOCSIFMEDIA: 2042 case SIOCGIFMEDIA: 2043 mii = device_get_softc(sc->jme_miibus); 2044 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2045 break; 2046 case SIOCSIFCAP: 2047 JME_LOCK(sc); 2048 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2049 if ((mask & IFCAP_TXCSUM) != 0 && 2050 ifp->if_mtu < JME_TX_FIFO_SIZE) { 2051 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2052 ifp->if_capenable ^= IFCAP_TXCSUM; 2053 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2054 ifp->if_hwassist |= JME_CSUM_FEATURES; 2055 else 2056 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 2057 } 2058 } 2059 if ((mask & IFCAP_RXCSUM) != 0 && 2060 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 2061 ifp->if_capenable ^= IFCAP_RXCSUM; 2062 reg = CSR_READ_4(sc, JME_RXMAC); 2063 reg &= ~RXMAC_CSUM_ENB; 2064 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2065 reg |= RXMAC_CSUM_ENB; 2066 CSR_WRITE_4(sc, JME_RXMAC, reg); 2067 } 2068 if ((mask & IFCAP_TSO4) != 0 && 2069 ifp->if_mtu < JME_TX_FIFO_SIZE) { 2070 if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) { 2071 ifp->if_capenable ^= IFCAP_TSO4; 2072 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 2073 ifp->if_hwassist |= CSUM_TSO; 2074 else 2075 ifp->if_hwassist &= ~CSUM_TSO; 2076 } 2077 } 2078 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2079 (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0) 2080 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2081 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2082 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2083 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2084 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2085 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2086 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2087 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2088 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 2089 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2090 jme_set_vlan(sc); 2091 } 2092 JME_UNLOCK(sc); 2093 VLAN_CAPABILITIES(ifp); 2094 break; 2095 default: 2096 error = ether_ioctl(ifp, cmd, data); 2097 break; 2098 } 2099 2100 return (error); 2101 } 2102 2103 static void 2104 jme_mac_config(struct jme_softc *sc) 2105 { 2106 struct mii_data *mii; 2107 uint32_t ghc, gpreg, rxmac, txmac, txpause; 2108 uint32_t txclk; 2109 2110 JME_LOCK_ASSERT(sc); 2111 2112 mii = device_get_softc(sc->jme_miibus); 2113 2114 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2115 DELAY(10); 2116 CSR_WRITE_4(sc, JME_GHC, 0); 2117 ghc = 0; 2118 txclk = 0; 2119 rxmac = CSR_READ_4(sc, JME_RXMAC); 2120 rxmac &= ~RXMAC_FC_ENB; 2121 txmac = CSR_READ_4(sc, JME_TXMAC); 2122 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2123 txpause = CSR_READ_4(sc, JME_TXPFC); 2124 txpause &= ~TXPFC_PAUSE_ENB; 2125 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2126 ghc |= GHC_FULL_DUPLEX; 2127 rxmac &= ~RXMAC_COLL_DET_ENB; 2128 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2129 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2130 TXMAC_FRAME_BURST); 2131 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2132 txpause |= TXPFC_PAUSE_ENB; 2133 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2134 rxmac |= RXMAC_FC_ENB; 2135 /* Disable retry transmit timer/retry limit. */ 2136 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2137 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2138 } else { 2139 rxmac |= RXMAC_COLL_DET_ENB; 2140 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2141 /* Enable retry transmit timer/retry limit. */ 2142 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2143 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2144 } 2145 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2146 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2147 case IFM_10_T: 2148 ghc |= GHC_SPEED_10; 2149 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2150 break; 2151 case IFM_100_TX: 2152 ghc |= GHC_SPEED_100; 2153 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2154 break; 2155 case IFM_1000_T: 2156 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2157 break; 2158 ghc |= GHC_SPEED_1000; 2159 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2160 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2161 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2162 break; 2163 default: 2164 break; 2165 } 2166 if (sc->jme_rev == DEVICEID_JMC250 && 2167 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2168 /* 2169 * Workaround occasional packet loss issue of JMC250 A2 2170 * when it runs on half-duplex media. 2171 */ 2172 gpreg = CSR_READ_4(sc, JME_GPREG1); 2173 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2174 gpreg &= ~GPREG1_HDPX_FIX; 2175 else 2176 gpreg |= GPREG1_HDPX_FIX; 2177 CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2178 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 2179 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2180 /* Extend interface FIFO depth. */ 2181 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2182 0x1B, 0x0000); 2183 } else { 2184 /* Select default interface FIFO depth. */ 2185 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2186 0x1B, 0x0004); 2187 } 2188 } 2189 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2190 ghc |= txclk; 2191 CSR_WRITE_4(sc, JME_GHC, ghc); 2192 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2193 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2194 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2195 } 2196 2197 static void 2198 jme_link_task(void *arg, int pending) 2199 { 2200 struct jme_softc *sc; 2201 struct mii_data *mii; 2202 struct ifnet *ifp; 2203 struct jme_txdesc *txd; 2204 bus_addr_t paddr; 2205 int i; 2206 2207 sc = (struct jme_softc *)arg; 2208 2209 JME_LOCK(sc); 2210 mii = device_get_softc(sc->jme_miibus); 2211 ifp = sc->jme_ifp; 2212 if (mii == NULL || ifp == NULL || 2213 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2214 JME_UNLOCK(sc); 2215 return; 2216 } 2217 2218 sc->jme_flags &= ~JME_FLAG_LINK; 2219 if ((mii->mii_media_status & IFM_AVALID) != 0) { 2220 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2221 case IFM_10_T: 2222 case IFM_100_TX: 2223 sc->jme_flags |= JME_FLAG_LINK; 2224 break; 2225 case IFM_1000_T: 2226 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2227 break; 2228 sc->jme_flags |= JME_FLAG_LINK; 2229 break; 2230 default: 2231 break; 2232 } 2233 } 2234 2235 /* 2236 * Disabling Rx/Tx MACs have a side-effect of resetting 2237 * JME_TXNDA/JME_RXNDA register to the first address of 2238 * Tx/Rx descriptor address. So driver should reset its 2239 * internal procucer/consumer pointer and reclaim any 2240 * allocated resources. Note, just saving the value of 2241 * JME_TXNDA and JME_RXNDA registers before stopping MAC 2242 * and restoring JME_TXNDA/JME_RXNDA register is not 2243 * sufficient to make sure correct MAC state because 2244 * stopping MAC operation can take a while and hardware 2245 * might have updated JME_TXNDA/JME_RXNDA registers 2246 * during the stop operation. 2247 */ 2248 /* Block execution of task. */ 2249 taskqueue_block(sc->jme_tq); 2250 /* Disable interrupts and stop driver. */ 2251 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2252 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2253 callout_stop(&sc->jme_tick_ch); 2254 sc->jme_watchdog_timer = 0; 2255 2256 /* Stop receiver/transmitter. */ 2257 jme_stop_rx(sc); 2258 jme_stop_tx(sc); 2259 2260 /* XXX Drain all queued tasks. */ 2261 JME_UNLOCK(sc); 2262 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2263 JME_LOCK(sc); 2264 2265 if (sc->jme_cdata.jme_rxhead != NULL) 2266 m_freem(sc->jme_cdata.jme_rxhead); 2267 JME_RXCHAIN_RESET(sc); 2268 jme_txeof(sc); 2269 if (sc->jme_cdata.jme_tx_cnt != 0) { 2270 /* Remove queued packets for transmit. */ 2271 for (i = 0; i < JME_TX_RING_CNT; i++) { 2272 txd = &sc->jme_cdata.jme_txdesc[i]; 2273 if (txd->tx_m != NULL) { 2274 bus_dmamap_sync( 2275 sc->jme_cdata.jme_tx_tag, 2276 txd->tx_dmamap, 2277 BUS_DMASYNC_POSTWRITE); 2278 bus_dmamap_unload( 2279 sc->jme_cdata.jme_tx_tag, 2280 txd->tx_dmamap); 2281 m_freem(txd->tx_m); 2282 txd->tx_m = NULL; 2283 txd->tx_ndesc = 0; 2284 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2285 } 2286 } 2287 } 2288 2289 /* 2290 * Reuse configured Rx descriptors and reset 2291 * producer/consumer index. 2292 */ 2293 sc->jme_cdata.jme_rx_cons = 0; 2294 sc->jme_morework = 0; 2295 jme_init_tx_ring(sc); 2296 /* Initialize shadow status block. */ 2297 jme_init_ssb(sc); 2298 2299 /* Program MAC with resolved speed/duplex/flow-control. */ 2300 if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2301 jme_mac_config(sc); 2302 jme_stats_clear(sc); 2303 2304 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2305 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2306 2307 /* Set Tx ring address to the hardware. */ 2308 paddr = JME_TX_RING_ADDR(sc, 0); 2309 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2310 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2311 2312 /* Set Rx ring address to the hardware. */ 2313 paddr = JME_RX_RING_ADDR(sc, 0); 2314 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2315 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2316 2317 /* Restart receiver/transmitter. */ 2318 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2319 RXCSR_RXQ_START); 2320 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2321 /* Lastly enable TX/RX clock. */ 2322 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2323 CSR_WRITE_4(sc, JME_GHC, 2324 CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS); 2325 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 2326 CSR_WRITE_4(sc, JME_GPREG1, 2327 CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS); 2328 } 2329 2330 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2331 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2332 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2333 /* Unblock execution of task. */ 2334 taskqueue_unblock(sc->jme_tq); 2335 /* Reenable interrupts. */ 2336 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2337 2338 JME_UNLOCK(sc); 2339 } 2340 2341 static int 2342 jme_intr(void *arg) 2343 { 2344 struct jme_softc *sc; 2345 uint32_t status; 2346 2347 sc = (struct jme_softc *)arg; 2348 2349 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2350 if (status == 0 || status == 0xFFFFFFFF) 2351 return (FILTER_STRAY); 2352 /* Disable interrupts. */ 2353 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2354 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2355 2356 return (FILTER_HANDLED); 2357 } 2358 2359 static void 2360 jme_int_task(void *arg, int pending) 2361 { 2362 struct jme_softc *sc; 2363 struct ifnet *ifp; 2364 uint32_t status; 2365 int more; 2366 2367 sc = (struct jme_softc *)arg; 2368 ifp = sc->jme_ifp; 2369 2370 JME_LOCK(sc); 2371 status = CSR_READ_4(sc, JME_INTR_STATUS); 2372 if (sc->jme_morework != 0) { 2373 sc->jme_morework = 0; 2374 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2375 } 2376 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2377 goto done; 2378 /* Reset PCC counter/timer and Ack interrupts. */ 2379 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2380 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2381 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2382 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2383 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2384 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2385 more = 0; 2386 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2387 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2388 more = jme_rxintr(sc, sc->jme_process_limit); 2389 if (more != 0) 2390 sc->jme_morework = 1; 2391 } 2392 if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2393 /* 2394 * Notify hardware availability of new Rx 2395 * buffers. 2396 * Reading RXCSR takes very long time under 2397 * heavy load so cache RXCSR value and writes 2398 * the ORed value with the kick command to 2399 * the RXCSR. This saves one register access 2400 * cycle. 2401 */ 2402 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2403 RXCSR_RX_ENB | RXCSR_RXQ_START); 2404 } 2405 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2406 jme_start_locked(ifp); 2407 } 2408 2409 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2410 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2411 JME_UNLOCK(sc); 2412 return; 2413 } 2414 done: 2415 JME_UNLOCK(sc); 2416 2417 /* Reenable interrupts. */ 2418 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2419 } 2420 2421 static void 2422 jme_txeof(struct jme_softc *sc) 2423 { 2424 struct ifnet *ifp; 2425 struct jme_txdesc *txd; 2426 uint32_t status; 2427 int cons, nsegs; 2428 2429 JME_LOCK_ASSERT(sc); 2430 2431 ifp = sc->jme_ifp; 2432 2433 cons = sc->jme_cdata.jme_tx_cons; 2434 if (cons == sc->jme_cdata.jme_tx_prod) 2435 return; 2436 2437 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2438 sc->jme_cdata.jme_tx_ring_map, 2439 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2440 2441 /* 2442 * Go through our Tx list and free mbufs for those 2443 * frames which have been transmitted. 2444 */ 2445 for (; cons != sc->jme_cdata.jme_tx_prod;) { 2446 txd = &sc->jme_cdata.jme_txdesc[cons]; 2447 status = le32toh(txd->tx_desc->flags); 2448 if ((status & JME_TD_OWN) == JME_TD_OWN) 2449 break; 2450 2451 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2452 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2453 else { 2454 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2455 if ((status & JME_TD_COLLISION) != 0) 2456 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2457 le32toh(txd->tx_desc->buflen) & 2458 JME_TD_BUF_LEN_MASK); 2459 } 2460 /* 2461 * Only the first descriptor of multi-descriptor 2462 * transmission is updated so driver have to skip entire 2463 * chained buffers for the transmiited frame. In other 2464 * words, JME_TD_OWN bit is valid only at the first 2465 * descriptor of a multi-descriptor transmission. 2466 */ 2467 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2468 sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2469 JME_DESC_INC(cons, JME_TX_RING_CNT); 2470 } 2471 2472 /* Reclaim transferred mbufs. */ 2473 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2474 BUS_DMASYNC_POSTWRITE); 2475 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2476 2477 KASSERT(txd->tx_m != NULL, 2478 ("%s: freeing NULL mbuf!\n", __func__)); 2479 m_freem(txd->tx_m); 2480 txd->tx_m = NULL; 2481 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2482 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2483 ("%s: Active Tx desc counter was garbled\n", __func__)); 2484 txd->tx_ndesc = 0; 2485 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2486 } 2487 sc->jme_cdata.jme_tx_cons = cons; 2488 /* Unarm watchog timer when there is no pending descriptors in queue. */ 2489 if (sc->jme_cdata.jme_tx_cnt == 0) 2490 sc->jme_watchdog_timer = 0; 2491 2492 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2493 sc->jme_cdata.jme_tx_ring_map, 2494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2495 } 2496 2497 static __inline void 2498 jme_discard_rxbuf(struct jme_softc *sc, int cons) 2499 { 2500 struct jme_desc *desc; 2501 2502 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2503 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2504 desc->buflen = htole32(MCLBYTES); 2505 } 2506 2507 /* Receive a frame. */ 2508 static void 2509 jme_rxeof(struct jme_softc *sc) 2510 { 2511 struct ifnet *ifp; 2512 struct jme_desc *desc; 2513 struct jme_rxdesc *rxd; 2514 struct mbuf *mp, *m; 2515 uint32_t flags, status; 2516 int cons, count, nsegs; 2517 2518 JME_LOCK_ASSERT(sc); 2519 2520 ifp = sc->jme_ifp; 2521 2522 cons = sc->jme_cdata.jme_rx_cons; 2523 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2524 flags = le32toh(desc->flags); 2525 status = le32toh(desc->buflen); 2526 nsegs = JME_RX_NSEGS(status); 2527 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2528 if ((status & JME_RX_ERR_STAT) != 0) { 2529 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2530 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2531 #ifdef JME_SHOW_ERRORS 2532 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2533 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2534 #endif 2535 sc->jme_cdata.jme_rx_cons += nsegs; 2536 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2537 return; 2538 } 2539 2540 for (count = 0; count < nsegs; count++, 2541 JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2542 rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2543 mp = rxd->rx_m; 2544 /* Add a new receive buffer to the ring. */ 2545 if (jme_newbuf(sc, rxd) != 0) { 2546 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2547 /* Reuse buffer. */ 2548 for (; count < nsegs; count++) { 2549 jme_discard_rxbuf(sc, cons); 2550 JME_DESC_INC(cons, JME_RX_RING_CNT); 2551 } 2552 if (sc->jme_cdata.jme_rxhead != NULL) { 2553 m_freem(sc->jme_cdata.jme_rxhead); 2554 JME_RXCHAIN_RESET(sc); 2555 } 2556 break; 2557 } 2558 2559 /* 2560 * Assume we've received a full sized frame. 2561 * Actual size is fixed when we encounter the end of 2562 * multi-segmented frame. 2563 */ 2564 mp->m_len = MCLBYTES; 2565 2566 /* Chain received mbufs. */ 2567 if (sc->jme_cdata.jme_rxhead == NULL) { 2568 sc->jme_cdata.jme_rxhead = mp; 2569 sc->jme_cdata.jme_rxtail = mp; 2570 } else { 2571 /* 2572 * Receive processor can receive a maximum frame 2573 * size of 65535 bytes. 2574 */ 2575 mp->m_flags &= ~M_PKTHDR; 2576 sc->jme_cdata.jme_rxtail->m_next = mp; 2577 sc->jme_cdata.jme_rxtail = mp; 2578 } 2579 2580 if (count == nsegs - 1) { 2581 /* Last desc. for this frame. */ 2582 m = sc->jme_cdata.jme_rxhead; 2583 m->m_flags |= M_PKTHDR; 2584 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2585 if (nsegs > 1) { 2586 /* Set first mbuf size. */ 2587 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2588 /* Set last mbuf size. */ 2589 mp->m_len = sc->jme_cdata.jme_rxlen - 2590 ((MCLBYTES - JME_RX_PAD_BYTES) + 2591 (MCLBYTES * (nsegs - 2))); 2592 } else 2593 m->m_len = sc->jme_cdata.jme_rxlen; 2594 m->m_pkthdr.rcvif = ifp; 2595 2596 /* 2597 * Account for 10bytes auto padding which is used 2598 * to align IP header on 32bit boundary. Also note, 2599 * CRC bytes is automatically removed by the 2600 * hardware. 2601 */ 2602 m->m_data += JME_RX_PAD_BYTES; 2603 2604 /* Set checksum information. */ 2605 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2606 (flags & JME_RD_IPV4) != 0) { 2607 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2608 if ((flags & JME_RD_IPCSUM) != 0) 2609 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2610 if (((flags & JME_RD_MORE_FRAG) == 0) && 2611 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2612 (JME_RD_TCP | JME_RD_TCPCSUM) || 2613 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2614 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2615 m->m_pkthdr.csum_flags |= 2616 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2617 m->m_pkthdr.csum_data = 0xffff; 2618 } 2619 } 2620 2621 /* Check for VLAN tagged packets. */ 2622 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2623 (flags & JME_RD_VLAN_TAG) != 0) { 2624 m->m_pkthdr.ether_vtag = 2625 flags & JME_RD_VLAN_MASK; 2626 m->m_flags |= M_VLANTAG; 2627 } 2628 2629 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2630 /* Pass it on. */ 2631 JME_UNLOCK(sc); 2632 (*ifp->if_input)(ifp, m); 2633 JME_LOCK(sc); 2634 2635 /* Reset mbuf chains. */ 2636 JME_RXCHAIN_RESET(sc); 2637 } 2638 } 2639 2640 sc->jme_cdata.jme_rx_cons += nsegs; 2641 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2642 } 2643 2644 static int 2645 jme_rxintr(struct jme_softc *sc, int count) 2646 { 2647 struct jme_desc *desc; 2648 int nsegs, prog, pktlen; 2649 2650 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2651 sc->jme_cdata.jme_rx_ring_map, 2652 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2653 2654 for (prog = 0; count > 0; prog++) { 2655 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2656 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2657 break; 2658 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2659 break; 2660 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2661 /* 2662 * Check number of segments against received bytes. 2663 * Non-matching value would indicate that hardware 2664 * is still trying to update Rx descriptors. I'm not 2665 * sure whether this check is needed. 2666 */ 2667 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2668 if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES)) 2669 break; 2670 prog++; 2671 /* Received a frame. */ 2672 jme_rxeof(sc); 2673 count -= nsegs; 2674 } 2675 2676 if (prog > 0) 2677 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2678 sc->jme_cdata.jme_rx_ring_map, 2679 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2680 2681 return (count > 0 ? 0 : EAGAIN); 2682 } 2683 2684 static void 2685 jme_tick(void *arg) 2686 { 2687 struct jme_softc *sc; 2688 struct mii_data *mii; 2689 2690 sc = (struct jme_softc *)arg; 2691 2692 JME_LOCK_ASSERT(sc); 2693 2694 mii = device_get_softc(sc->jme_miibus); 2695 mii_tick(mii); 2696 /* 2697 * Reclaim Tx buffers that have been completed. It's not 2698 * needed here but it would release allocated mbuf chains 2699 * faster and limit the maximum delay to a hz. 2700 */ 2701 jme_txeof(sc); 2702 jme_stats_update(sc); 2703 jme_watchdog(sc); 2704 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2705 } 2706 2707 static void 2708 jme_reset(struct jme_softc *sc) 2709 { 2710 uint32_t ghc, gpreg; 2711 2712 /* Stop receiver, transmitter. */ 2713 jme_stop_rx(sc); 2714 jme_stop_tx(sc); 2715 2716 /* Reset controller. */ 2717 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2718 CSR_READ_4(sc, JME_GHC); 2719 DELAY(10); 2720 /* 2721 * Workaround Rx FIFO overruns seen under certain conditions. 2722 * Explicitly synchorize TX/RX clock. TX/RX clock should be 2723 * enabled only after enabling TX/RX MACs. 2724 */ 2725 if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) { 2726 /* Disable TX clock. */ 2727 CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS); 2728 /* Disable RX clock. */ 2729 gpreg = CSR_READ_4(sc, JME_GPREG1); 2730 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2731 gpreg = CSR_READ_4(sc, JME_GPREG1); 2732 /* De-assert RESET but still disable TX clock. */ 2733 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2734 ghc = CSR_READ_4(sc, JME_GHC); 2735 2736 /* Enable TX clock. */ 2737 CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS); 2738 /* Enable RX clock. */ 2739 CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS); 2740 CSR_READ_4(sc, JME_GPREG1); 2741 2742 /* Disable TX/RX clock again. */ 2743 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2744 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2745 } else 2746 CSR_WRITE_4(sc, JME_GHC, 0); 2747 CSR_READ_4(sc, JME_GHC); 2748 DELAY(10); 2749 } 2750 2751 static void 2752 jme_init(void *xsc) 2753 { 2754 struct jme_softc *sc; 2755 2756 sc = (struct jme_softc *)xsc; 2757 JME_LOCK(sc); 2758 jme_init_locked(sc); 2759 JME_UNLOCK(sc); 2760 } 2761 2762 static void 2763 jme_init_locked(struct jme_softc *sc) 2764 { 2765 struct ifnet *ifp; 2766 struct mii_data *mii; 2767 bus_addr_t paddr; 2768 uint32_t reg; 2769 int error; 2770 2771 JME_LOCK_ASSERT(sc); 2772 2773 ifp = sc->jme_ifp; 2774 mii = device_get_softc(sc->jme_miibus); 2775 2776 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2777 return; 2778 /* 2779 * Cancel any pending I/O. 2780 */ 2781 jme_stop(sc); 2782 2783 /* 2784 * Reset the chip to a known state. 2785 */ 2786 jme_reset(sc); 2787 2788 /* Init descriptors. */ 2789 error = jme_init_rx_ring(sc); 2790 if (error != 0) { 2791 device_printf(sc->jme_dev, 2792 "%s: initialization failed: no memory for Rx buffers.\n", 2793 __func__); 2794 jme_stop(sc); 2795 return; 2796 } 2797 jme_init_tx_ring(sc); 2798 /* Initialize shadow status block. */ 2799 jme_init_ssb(sc); 2800 2801 /* Reprogram the station address. */ 2802 jme_set_macaddr(sc, IF_LLADDR(sc->jme_ifp)); 2803 2804 /* 2805 * Configure Tx queue. 2806 * Tx priority queue weight value : 0 2807 * Tx FIFO threshold for processing next packet : 16QW 2808 * Maximum Tx DMA length : 512 2809 * Allow Tx DMA burst. 2810 */ 2811 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2812 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2813 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2814 sc->jme_txcsr |= sc->jme_tx_dma_size; 2815 sc->jme_txcsr |= TXCSR_DMA_BURST; 2816 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2817 2818 /* Set Tx descriptor counter. */ 2819 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2820 2821 /* Set Tx ring address to the hardware. */ 2822 paddr = JME_TX_RING_ADDR(sc, 0); 2823 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2824 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2825 2826 /* Configure TxMAC parameters. */ 2827 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2828 reg |= TXMAC_THRESH_1_PKT; 2829 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2830 CSR_WRITE_4(sc, JME_TXMAC, reg); 2831 2832 /* 2833 * Configure Rx queue. 2834 * FIFO full threshold for transmitting Tx pause packet : 128T 2835 * FIFO threshold for processing next packet : 128QW 2836 * Rx queue 0 select 2837 * Max Rx DMA length : 128 2838 * Rx descriptor retry : 32 2839 * Rx descriptor retry time gap : 256ns 2840 * Don't receive runt/bad frame. 2841 */ 2842 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2843 /* 2844 * Since Rx FIFO size is 4K bytes, receiving frames larger 2845 * than 4K bytes will suffer from Rx FIFO overruns. So 2846 * decrease FIFO threshold to reduce the FIFO overruns for 2847 * frames larger than 4000 bytes. 2848 * For best performance of standard MTU sized frames use 2849 * maximum allowable FIFO threshold, 128QW. Note these do 2850 * not hold on chip full mask verion >=2. For these 2851 * controllers 64QW and 128QW are not valid value. 2852 */ 2853 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2854 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2855 else { 2856 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2857 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2858 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2859 else 2860 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2861 } 2862 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2863 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2864 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2865 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2866 2867 /* Set Rx descriptor counter. */ 2868 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2869 2870 /* Set Rx ring address to the hardware. */ 2871 paddr = JME_RX_RING_ADDR(sc, 0); 2872 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2873 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2874 2875 /* Clear receive filter. */ 2876 CSR_WRITE_4(sc, JME_RXMAC, 0); 2877 /* Set up the receive filter. */ 2878 jme_set_filter(sc); 2879 jme_set_vlan(sc); 2880 2881 /* 2882 * Disable all WOL bits as WOL can interfere normal Rx 2883 * operation. Also clear WOL detection status bits. 2884 */ 2885 reg = CSR_READ_4(sc, JME_PMCS); 2886 reg &= ~PMCS_WOL_ENB_MASK; 2887 CSR_WRITE_4(sc, JME_PMCS, reg); 2888 2889 reg = CSR_READ_4(sc, JME_RXMAC); 2890 /* 2891 * Pad 10bytes right before received frame. This will greatly 2892 * help Rx performance on strict-alignment architectures as 2893 * it does not need to copy the frame to align the payload. 2894 */ 2895 reg |= RXMAC_PAD_10BYTES; 2896 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2897 reg |= RXMAC_CSUM_ENB; 2898 CSR_WRITE_4(sc, JME_RXMAC, reg); 2899 2900 /* Configure general purpose reg0 */ 2901 reg = CSR_READ_4(sc, JME_GPREG0); 2902 reg &= ~GPREG0_PCC_UNIT_MASK; 2903 /* Set PCC timer resolution to micro-seconds unit. */ 2904 reg |= GPREG0_PCC_UNIT_US; 2905 /* 2906 * Disable all shadow register posting as we have to read 2907 * JME_INTR_STATUS register in jme_int_task. Also it seems 2908 * that it's hard to synchronize interrupt status between 2909 * hardware and software with shadow posting due to 2910 * requirements of bus_dmamap_sync(9). 2911 */ 2912 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2913 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2914 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2915 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2916 /* Disable posting of DW0. */ 2917 reg &= ~GPREG0_POST_DW0_ENB; 2918 /* Clear PME message. */ 2919 reg &= ~GPREG0_PME_ENB; 2920 /* Set PHY address. */ 2921 reg &= ~GPREG0_PHY_ADDR_MASK; 2922 reg |= sc->jme_phyaddr; 2923 CSR_WRITE_4(sc, JME_GPREG0, reg); 2924 2925 /* Configure Tx queue 0 packet completion coalescing. */ 2926 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2927 PCCTX_COAL_TO_MASK; 2928 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2929 PCCTX_COAL_PKT_MASK; 2930 reg |= PCCTX_COAL_TXQ0; 2931 CSR_WRITE_4(sc, JME_PCCTX, reg); 2932 2933 /* Configure Rx queue 0 packet completion coalescing. */ 2934 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2935 PCCRX_COAL_TO_MASK; 2936 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2937 PCCRX_COAL_PKT_MASK; 2938 CSR_WRITE_4(sc, JME_PCCRX0, reg); 2939 2940 /* 2941 * Configure PCD(Packet Completion Deferring). It seems PCD 2942 * generates an interrupt when the time interval between two 2943 * back-to-back incoming/outgoing packet is long enough for 2944 * it to reach its timer value 0. The arrival of new packets 2945 * after timer has started causes the PCD timer to restart. 2946 * Unfortunately, it's not clear how PCD is useful at this 2947 * moment, so just use the same of PCC parameters. 2948 */ 2949 if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) { 2950 sc->jme_rx_pcd_to = sc->jme_rx_coal_to; 2951 if (sc->jme_rx_coal_to > PCDRX_TO_MAX) 2952 sc->jme_rx_pcd_to = PCDRX_TO_MAX; 2953 sc->jme_tx_pcd_to = sc->jme_tx_coal_to; 2954 if (sc->jme_tx_coal_to > PCDTX_TO_MAX) 2955 sc->jme_tx_pcd_to = PCDTX_TO_MAX; 2956 reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT; 2957 reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT; 2958 CSR_WRITE_4(sc, PCDRX_REG(0), reg); 2959 reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT; 2960 reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT; 2961 CSR_WRITE_4(sc, JME_PCDTX, reg); 2962 } 2963 2964 /* Configure shadow status block but don't enable posting. */ 2965 paddr = sc->jme_rdata.jme_ssb_block_paddr; 2966 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2967 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2968 2969 /* Disable Timer 1 and Timer 2. */ 2970 CSR_WRITE_4(sc, JME_TIMER1, 0); 2971 CSR_WRITE_4(sc, JME_TIMER2, 0); 2972 2973 /* Configure retry transmit period, retry limit value. */ 2974 CSR_WRITE_4(sc, JME_TXTRHD, 2975 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2976 TXTRHD_RT_PERIOD_MASK) | 2977 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2978 TXTRHD_RT_LIMIT_SHIFT)); 2979 2980 /* Disable RSS. */ 2981 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2982 2983 /* Initialize the interrupt mask. */ 2984 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2985 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2986 2987 /* 2988 * Enabling Tx/Rx DMA engines and Rx queue processing is 2989 * done after detection of valid link in jme_link_task. 2990 */ 2991 2992 sc->jme_flags &= ~JME_FLAG_LINK; 2993 /* Set the current media. */ 2994 mii_mediachg(mii); 2995 2996 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2997 2998 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2999 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3000 } 3001 3002 static void 3003 jme_stop(struct jme_softc *sc) 3004 { 3005 struct ifnet *ifp; 3006 struct jme_txdesc *txd; 3007 struct jme_rxdesc *rxd; 3008 int i; 3009 3010 JME_LOCK_ASSERT(sc); 3011 /* 3012 * Mark the interface down and cancel the watchdog timer. 3013 */ 3014 ifp = sc->jme_ifp; 3015 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3016 sc->jme_flags &= ~JME_FLAG_LINK; 3017 callout_stop(&sc->jme_tick_ch); 3018 sc->jme_watchdog_timer = 0; 3019 3020 /* 3021 * Disable interrupts. 3022 */ 3023 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 3024 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 3025 3026 /* Disable updating shadow status block. */ 3027 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 3028 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 3029 3030 /* Stop receiver, transmitter. */ 3031 jme_stop_rx(sc); 3032 jme_stop_tx(sc); 3033 3034 /* Reclaim Rx/Tx buffers that have been completed. */ 3035 jme_rxintr(sc, JME_RX_RING_CNT); 3036 if (sc->jme_cdata.jme_rxhead != NULL) 3037 m_freem(sc->jme_cdata.jme_rxhead); 3038 JME_RXCHAIN_RESET(sc); 3039 jme_txeof(sc); 3040 /* 3041 * Free RX and TX mbufs still in the queues. 3042 */ 3043 for (i = 0; i < JME_RX_RING_CNT; i++) { 3044 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3045 if (rxd->rx_m != NULL) { 3046 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 3047 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3048 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 3049 rxd->rx_dmamap); 3050 m_freem(rxd->rx_m); 3051 rxd->rx_m = NULL; 3052 } 3053 } 3054 for (i = 0; i < JME_TX_RING_CNT; i++) { 3055 txd = &sc->jme_cdata.jme_txdesc[i]; 3056 if (txd->tx_m != NULL) { 3057 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 3058 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3059 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 3060 txd->tx_dmamap); 3061 m_freem(txd->tx_m); 3062 txd->tx_m = NULL; 3063 txd->tx_ndesc = 0; 3064 } 3065 } 3066 jme_stats_update(sc); 3067 jme_stats_save(sc); 3068 } 3069 3070 static void 3071 jme_stop_tx(struct jme_softc *sc) 3072 { 3073 uint32_t reg; 3074 int i; 3075 3076 reg = CSR_READ_4(sc, JME_TXCSR); 3077 if ((reg & TXCSR_TX_ENB) == 0) 3078 return; 3079 reg &= ~TXCSR_TX_ENB; 3080 CSR_WRITE_4(sc, JME_TXCSR, reg); 3081 for (i = JME_TIMEOUT; i > 0; i--) { 3082 DELAY(1); 3083 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 3084 break; 3085 } 3086 if (i == 0) 3087 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 3088 } 3089 3090 static void 3091 jme_stop_rx(struct jme_softc *sc) 3092 { 3093 uint32_t reg; 3094 int i; 3095 3096 reg = CSR_READ_4(sc, JME_RXCSR); 3097 if ((reg & RXCSR_RX_ENB) == 0) 3098 return; 3099 reg &= ~RXCSR_RX_ENB; 3100 CSR_WRITE_4(sc, JME_RXCSR, reg); 3101 for (i = JME_TIMEOUT; i > 0; i--) { 3102 DELAY(1); 3103 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 3104 break; 3105 } 3106 if (i == 0) 3107 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 3108 } 3109 3110 static void 3111 jme_init_tx_ring(struct jme_softc *sc) 3112 { 3113 struct jme_ring_data *rd; 3114 struct jme_txdesc *txd; 3115 int i; 3116 3117 sc->jme_cdata.jme_tx_prod = 0; 3118 sc->jme_cdata.jme_tx_cons = 0; 3119 sc->jme_cdata.jme_tx_cnt = 0; 3120 3121 rd = &sc->jme_rdata; 3122 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 3123 for (i = 0; i < JME_TX_RING_CNT; i++) { 3124 txd = &sc->jme_cdata.jme_txdesc[i]; 3125 txd->tx_m = NULL; 3126 txd->tx_desc = &rd->jme_tx_ring[i]; 3127 txd->tx_ndesc = 0; 3128 } 3129 3130 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 3131 sc->jme_cdata.jme_tx_ring_map, 3132 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3133 } 3134 3135 static void 3136 jme_init_ssb(struct jme_softc *sc) 3137 { 3138 struct jme_ring_data *rd; 3139 3140 rd = &sc->jme_rdata; 3141 bzero(rd->jme_ssb_block, JME_SSB_SIZE); 3142 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 3143 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3144 } 3145 3146 static int 3147 jme_init_rx_ring(struct jme_softc *sc) 3148 { 3149 struct jme_ring_data *rd; 3150 struct jme_rxdesc *rxd; 3151 int i; 3152 3153 sc->jme_cdata.jme_rx_cons = 0; 3154 JME_RXCHAIN_RESET(sc); 3155 sc->jme_morework = 0; 3156 3157 rd = &sc->jme_rdata; 3158 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 3159 for (i = 0; i < JME_RX_RING_CNT; i++) { 3160 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3161 rxd->rx_m = NULL; 3162 rxd->rx_desc = &rd->jme_rx_ring[i]; 3163 if (jme_newbuf(sc, rxd) != 0) 3164 return (ENOBUFS); 3165 } 3166 3167 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 3168 sc->jme_cdata.jme_rx_ring_map, 3169 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3170 3171 return (0); 3172 } 3173 3174 static int 3175 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 3176 { 3177 struct jme_desc *desc; 3178 struct mbuf *m; 3179 bus_dma_segment_t segs[1]; 3180 bus_dmamap_t map; 3181 int nsegs; 3182 3183 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3184 if (m == NULL) 3185 return (ENOBUFS); 3186 /* 3187 * JMC250 has 64bit boundary alignment limitation so jme(4) 3188 * takes advantage of 10 bytes padding feature of hardware 3189 * in order not to copy entire frame to align IP header on 3190 * 32bit boundary. 3191 */ 3192 m->m_len = m->m_pkthdr.len = MCLBYTES; 3193 3194 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 3195 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3196 m_freem(m); 3197 return (ENOBUFS); 3198 } 3199 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3200 3201 if (rxd->rx_m != NULL) { 3202 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3203 BUS_DMASYNC_POSTREAD); 3204 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3205 } 3206 map = rxd->rx_dmamap; 3207 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3208 sc->jme_cdata.jme_rx_sparemap = map; 3209 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3210 BUS_DMASYNC_PREREAD); 3211 rxd->rx_m = m; 3212 3213 desc = rxd->rx_desc; 3214 desc->buflen = htole32(segs[0].ds_len); 3215 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3216 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3217 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3218 3219 return (0); 3220 } 3221 3222 static void 3223 jme_set_vlan(struct jme_softc *sc) 3224 { 3225 struct ifnet *ifp; 3226 uint32_t reg; 3227 3228 JME_LOCK_ASSERT(sc); 3229 3230 ifp = sc->jme_ifp; 3231 reg = CSR_READ_4(sc, JME_RXMAC); 3232 reg &= ~RXMAC_VLAN_ENB; 3233 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3234 reg |= RXMAC_VLAN_ENB; 3235 CSR_WRITE_4(sc, JME_RXMAC, reg); 3236 } 3237 3238 static void 3239 jme_set_filter(struct jme_softc *sc) 3240 { 3241 struct ifnet *ifp; 3242 struct ifmultiaddr *ifma; 3243 uint32_t crc; 3244 uint32_t mchash[2]; 3245 uint32_t rxcfg; 3246 3247 JME_LOCK_ASSERT(sc); 3248 3249 ifp = sc->jme_ifp; 3250 3251 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3252 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3253 RXMAC_ALLMULTI); 3254 /* Always accept frames destined to our station address. */ 3255 rxcfg |= RXMAC_UNICAST; 3256 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3257 rxcfg |= RXMAC_BROADCAST; 3258 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3259 if ((ifp->if_flags & IFF_PROMISC) != 0) 3260 rxcfg |= RXMAC_PROMISC; 3261 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3262 rxcfg |= RXMAC_ALLMULTI; 3263 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3264 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3265 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3266 return; 3267 } 3268 3269 /* 3270 * Set up the multicast address filter by passing all multicast 3271 * addresses through a CRC generator, and then using the low-order 3272 * 6 bits as an index into the 64 bit multicast hash table. The 3273 * high order bits select the register, while the rest of the bits 3274 * select the bit within the register. 3275 */ 3276 rxcfg |= RXMAC_MULTICAST; 3277 bzero(mchash, sizeof(mchash)); 3278 3279 if_maddr_rlock(ifp); 3280 TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) { 3281 if (ifma->ifma_addr->sa_family != AF_LINK) 3282 continue; 3283 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3284 ifma->ifma_addr), ETHER_ADDR_LEN); 3285 3286 /* Just want the 6 least significant bits. */ 3287 crc &= 0x3f; 3288 3289 /* Set the corresponding bit in the hash table. */ 3290 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3291 } 3292 if_maddr_runlock(ifp); 3293 3294 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3295 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3296 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3297 } 3298 3299 static void 3300 jme_stats_clear(struct jme_softc *sc) 3301 { 3302 3303 JME_LOCK_ASSERT(sc); 3304 3305 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3306 return; 3307 3308 /* Disable and clear counters. */ 3309 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3310 /* Activate hw counters. */ 3311 CSR_WRITE_4(sc, JME_STATCSR, 0); 3312 CSR_READ_4(sc, JME_STATCSR); 3313 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats)); 3314 } 3315 3316 static void 3317 jme_stats_save(struct jme_softc *sc) 3318 { 3319 3320 JME_LOCK_ASSERT(sc); 3321 3322 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3323 return; 3324 /* Save current counters. */ 3325 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats)); 3326 /* Disable and clear counters. */ 3327 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3328 } 3329 3330 static void 3331 jme_stats_update(struct jme_softc *sc) 3332 { 3333 struct jme_hw_stats *stat, *ostat; 3334 uint32_t reg; 3335 3336 JME_LOCK_ASSERT(sc); 3337 3338 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3339 return; 3340 stat = &sc->jme_stats; 3341 ostat = &sc->jme_ostats; 3342 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD); 3343 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD); 3344 reg = CSR_READ_4(sc, JME_STAT_CRCMII); 3345 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >> 3346 STAT_RX_CRC_ERR_SHIFT; 3347 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >> 3348 STAT_RX_MII_ERR_SHIFT; 3349 reg = CSR_READ_4(sc, JME_STAT_RXERR); 3350 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >> 3351 STAT_RXERR_OFLOW_SHIFT; 3352 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >> 3353 STAT_RXERR_MPTY_SHIFT; 3354 reg = CSR_READ_4(sc, JME_STAT_FAIL); 3355 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT; 3356 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT; 3357 3358 /* Account for previous counters. */ 3359 stat->rx_good_frames += ostat->rx_good_frames; 3360 stat->rx_crc_errs += ostat->rx_crc_errs; 3361 stat->rx_mii_errs += ostat->rx_mii_errs; 3362 stat->rx_fifo_oflows += ostat->rx_fifo_oflows; 3363 stat->rx_desc_empty += ostat->rx_desc_empty; 3364 stat->rx_bad_frames += ostat->rx_bad_frames; 3365 stat->tx_good_frames += ostat->tx_good_frames; 3366 stat->tx_bad_frames += ostat->tx_bad_frames; 3367 } 3368 3369 static void 3370 jme_phy_down(struct jme_softc *sc) 3371 { 3372 uint32_t reg; 3373 3374 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN); 3375 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3376 reg = CSR_READ_4(sc, JME_PHYPOWDN); 3377 reg |= 0x0000000F; 3378 CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3379 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3380 reg &= ~PE1_GIGA_PDOWN_MASK; 3381 reg |= PE1_GIGA_PDOWN_D3; 3382 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3383 } 3384 } 3385 3386 static void 3387 jme_phy_up(struct jme_softc *sc) 3388 { 3389 uint32_t reg; 3390 uint16_t bmcr; 3391 3392 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR); 3393 bmcr &= ~BMCR_PDOWN; 3394 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr); 3395 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3396 reg = CSR_READ_4(sc, JME_PHYPOWDN); 3397 reg &= ~0x0000000F; 3398 CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3399 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3400 reg &= ~PE1_GIGA_PDOWN_MASK; 3401 reg |= PE1_GIGA_PDOWN_DIS; 3402 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3403 } 3404 } 3405 3406 static int 3407 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3408 { 3409 int error, value; 3410 3411 if (arg1 == NULL) 3412 return (EINVAL); 3413 value = *(int *)arg1; 3414 error = sysctl_handle_int(oidp, &value, 0, req); 3415 if (error || req->newptr == NULL) 3416 return (error); 3417 if (value < low || value > high) 3418 return (EINVAL); 3419 *(int *)arg1 = value; 3420 3421 return (0); 3422 } 3423 3424 static int 3425 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3426 { 3427 return (sysctl_int_range(oidp, arg1, arg2, req, 3428 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3429 } 3430 3431 static int 3432 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3433 { 3434 return (sysctl_int_range(oidp, arg1, arg2, req, 3435 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3436 } 3437 3438 static int 3439 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3440 { 3441 return (sysctl_int_range(oidp, arg1, arg2, req, 3442 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3443 } 3444 3445 static int 3446 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3447 { 3448 return (sysctl_int_range(oidp, arg1, arg2, req, 3449 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3450 } 3451 3452 static int 3453 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3454 { 3455 return (sysctl_int_range(oidp, arg1, arg2, req, 3456 JME_PROC_MIN, JME_PROC_MAX)); 3457 } 3458