1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 6 * Bill Paul <william.paul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 41 * documentation not available, but ask me nicely. 42 * 43 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 44 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 45 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 46 * are three supported methods for data transfer between host and 47 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 48 * Propulsion Technology (tm) DMA. The latter mechanism is a form 49 * of double buffer DMA where the packet data is copied to a 50 * pre-allocated DMA buffer who's physical address has been loaded 51 * into a table at device initialization time. The rationale is that 52 * the virtual to physical address translation needed for normal 53 * scatter/gather DMA is more expensive than the data copy needed 54 * for double buffering. This may be true in Windows NT and the like, 55 * but it isn't true for us, at least on the x86 arch. This driver 56 * uses the scatter/gather I/O method for both TX and RX. 57 * 58 * The LXT1001 only supports TCP/IP checksum offload on receive. 59 * Also, the VLAN tagging is done using a 16-entry table which allows 60 * the chip to perform hardware filtering based on VLAN tags. Sadly, 61 * our vlan support doesn't currently play well with this kind of 62 * hardware support. 63 * 64 * Special thanks to: 65 * - Jeff James at Intel, for arranging to have the LXT1001 manual 66 * released (at long last) 67 * - Beny Chen at D-Link, for actually sending it to me 68 * - Brad Short and Keith Alexis at SMC, for sending me sample 69 * SMC9462SX and SMC9462TX adapters for testing 70 * - Paul Saab at Y!, for not killing me (though it remains to be seen 71 * if in fact he did me much of a favor) 72 */ 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 83 #include <net/if.h> 84 #include <net/if_var.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 #include <net/if_types.h> 90 91 #include <net/bpf.h> 92 93 #include <vm/vm.h> /* for vtophys */ 94 #include <vm/pmap.h> /* for vtophys */ 95 #include <machine/bus.h> 96 #include <machine/resource.h> 97 #include <sys/bus.h> 98 #include <sys/rman.h> 99 100 #include <dev/mii/mii.h> 101 #include <dev/mii/miivar.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 106 #define LGE_USEIOSPACE 107 108 #include <dev/lge/if_lgereg.h> 109 110 /* "device miibus" required. See GENERIC if you get errors here. */ 111 #include "miibus_if.h" 112 113 /* 114 * Various supported device vendors/types and their names. 115 */ 116 static const struct lge_type lge_devs[] = { 117 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 118 { 0, 0, NULL } 119 }; 120 121 static int lge_probe(device_t); 122 static int lge_attach(device_t); 123 static int lge_detach(device_t); 124 125 static int lge_alloc_jumbo_mem(struct lge_softc *); 126 static void lge_free_jumbo_mem(struct lge_softc *); 127 static void *lge_jalloc(struct lge_softc *); 128 static void lge_jfree(struct mbuf *); 129 130 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 131 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 132 static void lge_rxeof(struct lge_softc *, int); 133 static void lge_rxeoc(struct lge_softc *); 134 static void lge_txeof(struct lge_softc *); 135 static void lge_intr(void *); 136 static void lge_tick(void *); 137 static void lge_start(struct ifnet *); 138 static void lge_start_locked(struct ifnet *); 139 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 140 static void lge_init(void *); 141 static void lge_init_locked(struct lge_softc *); 142 static void lge_stop(struct lge_softc *); 143 static void lge_watchdog(struct lge_softc *); 144 static int lge_shutdown(device_t); 145 static int lge_ifmedia_upd(struct ifnet *); 146 static void lge_ifmedia_upd_locked(struct ifnet *); 147 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 149 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 150 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 151 152 static int lge_miibus_readreg(device_t, int, int); 153 static int lge_miibus_writereg(device_t, int, int, int); 154 static void lge_miibus_statchg(device_t); 155 156 static void lge_setmulti(struct lge_softc *); 157 static void lge_reset(struct lge_softc *); 158 static int lge_list_rx_init(struct lge_softc *); 159 static int lge_list_tx_init(struct lge_softc *); 160 161 #ifdef LGE_USEIOSPACE 162 #define LGE_RES SYS_RES_IOPORT 163 #define LGE_RID LGE_PCI_LOIO 164 #else 165 #define LGE_RES SYS_RES_MEMORY 166 #define LGE_RID LGE_PCI_LOMEM 167 #endif 168 169 static device_method_t lge_methods[] = { 170 /* Device interface */ 171 DEVMETHOD(device_probe, lge_probe), 172 DEVMETHOD(device_attach, lge_attach), 173 DEVMETHOD(device_detach, lge_detach), 174 DEVMETHOD(device_shutdown, lge_shutdown), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 DEVMETHOD_END 182 }; 183 184 static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188 }; 189 190 static devclass_t lge_devclass; 191 192 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 193 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194 MODULE_DEPEND(lge, pci, 1, 1, 1); 195 MODULE_DEPEND(lge, ether, 1, 1, 1); 196 MODULE_DEPEND(lge, miibus, 1, 1, 1); 197 198 #define LGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202 #define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206 #define SIO_SET(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 209 #define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 211 212 /* 213 * Read a word of data stored in the EEPROM at address 'addr.' 214 */ 215 static void 216 lge_eeprom_getword(sc, addr, dest) 217 struct lge_softc *sc; 218 int addr; 219 u_int16_t *dest; 220 { 221 int i; 222 u_int32_t val; 223 224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 226 227 for (i = 0; i < LGE_TIMEOUT; i++) 228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 229 break; 230 231 if (i == LGE_TIMEOUT) { 232 device_printf(sc->lge_dev, "EEPROM read timed out\n"); 233 return; 234 } 235 236 val = CSR_READ_4(sc, LGE_EEDATA); 237 238 if (addr & 1) 239 *dest = (val >> 16) & 0xFFFF; 240 else 241 *dest = val & 0xFFFF; 242 243 return; 244 } 245 246 /* 247 * Read a sequence of words from the EEPROM. 248 */ 249 static void 250 lge_read_eeprom(sc, dest, off, cnt, swap) 251 struct lge_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256 { 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 lge_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270 } 271 272 static int 273 lge_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276 { 277 struct lge_softc *sc; 278 int i; 279 280 sc = device_get_softc(dev); 281 282 /* 283 * If we have a non-PCS PHY, pretend that the internal 284 * autoneg stuff at PHY address 0 isn't there so that 285 * the miibus code will find only the GMII PHY. 286 */ 287 if (sc->lge_pcs == 0 && phy == 0) 288 return(0); 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) 293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 294 break; 295 296 if (i == LGE_TIMEOUT) { 297 device_printf(sc->lge_dev, "PHY read timed out\n"); 298 return(0); 299 } 300 301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 302 } 303 304 static int 305 lge_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308 { 309 struct lge_softc *sc; 310 int i; 311 312 sc = device_get_softc(dev); 313 314 CSR_WRITE_4(sc, LGE_GMIICTL, 315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 316 317 for (i = 0; i < LGE_TIMEOUT; i++) 318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 319 break; 320 321 if (i == LGE_TIMEOUT) { 322 device_printf(sc->lge_dev, "PHY write timed out\n"); 323 return(0); 324 } 325 326 return(0); 327 } 328 329 static void 330 lge_miibus_statchg(dev) 331 device_t dev; 332 { 333 struct lge_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->lge_miibus); 338 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_1000_T: 342 case IFM_1000_SX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 344 break; 345 case IFM_100_TX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 347 break; 348 case IFM_10_T: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 350 break; 351 default: 352 /* 353 * Choose something, even if it's wrong. Clearing 354 * all the bits will hose autoneg on the internal 355 * PHY. 356 */ 357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 358 break; 359 } 360 361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } else { 364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 365 } 366 367 return; 368 } 369 370 static void 371 lge_setmulti(sc) 372 struct lge_softc *sc; 373 { 374 struct ifnet *ifp; 375 struct ifmultiaddr *ifma; 376 u_int32_t h = 0, hashes[2] = { 0, 0 }; 377 378 ifp = sc->lge_ifp; 379 LGE_LOCK_ASSERT(sc); 380 381 /* Make sure multicast hash table is enabled. */ 382 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 383 384 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 385 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 386 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 387 return; 388 } 389 390 /* first, zot all the existing hash bits */ 391 CSR_WRITE_4(sc, LGE_MAR0, 0); 392 CSR_WRITE_4(sc, LGE_MAR1, 0); 393 394 /* now program new ones */ 395 if_maddr_rlock(ifp); 396 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 397 if (ifma->ifma_addr->sa_family != AF_LINK) 398 continue; 399 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 400 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 401 if (h < 32) 402 hashes[0] |= (1 << h); 403 else 404 hashes[1] |= (1 << (h - 32)); 405 } 406 if_maddr_runlock(ifp); 407 408 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 409 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 410 411 return; 412 } 413 414 static void 415 lge_reset(sc) 416 struct lge_softc *sc; 417 { 418 int i; 419 420 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 421 422 for (i = 0; i < LGE_TIMEOUT; i++) { 423 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 424 break; 425 } 426 427 if (i == LGE_TIMEOUT) 428 device_printf(sc->lge_dev, "reset never completed\n"); 429 430 /* Wait a little while for the chip to get its brains in order. */ 431 DELAY(1000); 432 433 return; 434 } 435 436 /* 437 * Probe for a Level 1 chip. Check the PCI vendor and device 438 * IDs against our list and return a device name if we find a match. 439 */ 440 static int 441 lge_probe(dev) 442 device_t dev; 443 { 444 const struct lge_type *t; 445 446 t = lge_devs; 447 448 while(t->lge_name != NULL) { 449 if ((pci_get_vendor(dev) == t->lge_vid) && 450 (pci_get_device(dev) == t->lge_did)) { 451 device_set_desc(dev, t->lge_name); 452 return(BUS_PROBE_DEFAULT); 453 } 454 t++; 455 } 456 457 return(ENXIO); 458 } 459 460 /* 461 * Attach the interface. Allocate softc structures, do ifmedia 462 * setup and ethernet/BPF attach. 463 */ 464 static int 465 lge_attach(dev) 466 device_t dev; 467 { 468 u_char eaddr[ETHER_ADDR_LEN]; 469 struct lge_softc *sc; 470 struct ifnet *ifp = NULL; 471 int error = 0, rid; 472 473 sc = device_get_softc(dev); 474 sc->lge_dev = dev; 475 476 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 477 MTX_DEF); 478 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0); 479 480 /* 481 * Map control/status registers. 482 */ 483 pci_enable_busmaster(dev); 484 485 rid = LGE_RID; 486 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 487 488 if (sc->lge_res == NULL) { 489 device_printf(dev, "couldn't map ports/memory\n"); 490 error = ENXIO; 491 goto fail; 492 } 493 494 sc->lge_btag = rman_get_bustag(sc->lge_res); 495 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 496 497 /* Allocate interrupt */ 498 rid = 0; 499 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 500 RF_SHAREABLE | RF_ACTIVE); 501 502 if (sc->lge_irq == NULL) { 503 device_printf(dev, "couldn't map interrupt\n"); 504 error = ENXIO; 505 goto fail; 506 } 507 508 /* Reset the adapter. */ 509 lge_reset(sc); 510 511 /* 512 * Get station address from the EEPROM. 513 */ 514 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 515 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 516 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 517 518 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 519 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 520 521 if (sc->lge_ldata == NULL) { 522 device_printf(dev, "no memory for list buffers!\n"); 523 error = ENXIO; 524 goto fail; 525 } 526 527 /* Try to allocate memory for jumbo buffers. */ 528 if (lge_alloc_jumbo_mem(sc)) { 529 device_printf(dev, "jumbo buffer allocation failed\n"); 530 error = ENXIO; 531 goto fail; 532 } 533 534 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 535 if (ifp == NULL) { 536 device_printf(dev, "can not if_alloc()\n"); 537 error = ENOSPC; 538 goto fail; 539 } 540 ifp->if_softc = sc; 541 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 542 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 543 ifp->if_ioctl = lge_ioctl; 544 ifp->if_start = lge_start; 545 ifp->if_init = lge_init; 546 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 547 ifp->if_capabilities = IFCAP_RXCSUM; 548 ifp->if_capenable = ifp->if_capabilities; 549 550 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 551 sc->lge_pcs = 1; 552 else 553 sc->lge_pcs = 0; 554 555 /* 556 * Do MII setup. 557 */ 558 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd, 559 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 560 if (error != 0) { 561 device_printf(dev, "attaching PHYs failed\n"); 562 goto fail; 563 } 564 565 /* 566 * Call MI attach routine. 567 */ 568 ether_ifattach(ifp, eaddr); 569 570 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE, 571 NULL, lge_intr, sc, &sc->lge_intrhand); 572 573 if (error) { 574 ether_ifdetach(ifp); 575 device_printf(dev, "couldn't set up irq\n"); 576 goto fail; 577 } 578 return (0); 579 580 fail: 581 lge_free_jumbo_mem(sc); 582 if (sc->lge_ldata) 583 contigfree(sc->lge_ldata, 584 sizeof(struct lge_list_data), M_DEVBUF); 585 if (ifp) 586 if_free(ifp); 587 if (sc->lge_irq) 588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 589 if (sc->lge_res) 590 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 591 mtx_destroy(&sc->lge_mtx); 592 return(error); 593 } 594 595 static int 596 lge_detach(dev) 597 device_t dev; 598 { 599 struct lge_softc *sc; 600 struct ifnet *ifp; 601 602 sc = device_get_softc(dev); 603 ifp = sc->lge_ifp; 604 605 LGE_LOCK(sc); 606 lge_reset(sc); 607 lge_stop(sc); 608 LGE_UNLOCK(sc); 609 callout_drain(&sc->lge_stat_callout); 610 ether_ifdetach(ifp); 611 612 bus_generic_detach(dev); 613 device_delete_child(dev, sc->lge_miibus); 614 615 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 617 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 618 619 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 620 if_free(ifp); 621 lge_free_jumbo_mem(sc); 622 mtx_destroy(&sc->lge_mtx); 623 624 return(0); 625 } 626 627 /* 628 * Initialize the transmit descriptors. 629 */ 630 static int 631 lge_list_tx_init(sc) 632 struct lge_softc *sc; 633 { 634 struct lge_list_data *ld; 635 struct lge_ring_data *cd; 636 int i; 637 638 cd = &sc->lge_cdata; 639 ld = sc->lge_ldata; 640 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 641 ld->lge_tx_list[i].lge_mbuf = NULL; 642 ld->lge_tx_list[i].lge_ctl = 0; 643 } 644 645 cd->lge_tx_prod = cd->lge_tx_cons = 0; 646 647 return(0); 648 } 649 650 651 /* 652 * Initialize the RX descriptors and allocate mbufs for them. Note that 653 * we arralge the descriptors in a closed ring, so that the last descriptor 654 * points back to the first. 655 */ 656 static int 657 lge_list_rx_init(sc) 658 struct lge_softc *sc; 659 { 660 struct lge_list_data *ld; 661 struct lge_ring_data *cd; 662 int i; 663 664 ld = sc->lge_ldata; 665 cd = &sc->lge_cdata; 666 667 cd->lge_rx_prod = cd->lge_rx_cons = 0; 668 669 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 670 671 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 672 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 673 break; 674 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 675 return(ENOBUFS); 676 } 677 678 /* Clear possible 'rx command queue empty' interrupt. */ 679 CSR_READ_4(sc, LGE_ISR); 680 681 return(0); 682 } 683 684 /* 685 * Initialize an RX descriptor and attach an MBUF cluster. 686 */ 687 static int 688 lge_newbuf(sc, c, m) 689 struct lge_softc *sc; 690 struct lge_rx_desc *c; 691 struct mbuf *m; 692 { 693 struct mbuf *m_new = NULL; 694 char *buf = NULL; 695 696 if (m == NULL) { 697 MGETHDR(m_new, M_NOWAIT, MT_DATA); 698 if (m_new == NULL) { 699 device_printf(sc->lge_dev, "no memory for rx list " 700 "-- packet dropped!\n"); 701 return(ENOBUFS); 702 } 703 704 /* Allocate the jumbo buffer */ 705 buf = lge_jalloc(sc); 706 if (buf == NULL) { 707 #ifdef LGE_VERBOSE 708 device_printf(sc->lge_dev, "jumbo allocation failed " 709 "-- packet dropped!\n"); 710 #endif 711 m_freem(m_new); 712 return(ENOBUFS); 713 } 714 /* Attach the buffer to the mbuf */ 715 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 716 m_extadd(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, sc, NULL, 717 0, EXT_NET_DRV); 718 } else { 719 m_new = m; 720 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 721 m_new->m_data = m_new->m_ext.ext_buf; 722 } 723 724 /* 725 * Adjust alignment so packet payload begins on a 726 * longword boundary. Mandatory for Alpha, useful on 727 * x86 too. 728 */ 729 m_adj(m_new, ETHER_ALIGN); 730 731 c->lge_mbuf = m_new; 732 c->lge_fragptr_hi = 0; 733 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 734 c->lge_fraglen = m_new->m_len; 735 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 736 c->lge_sts = 0; 737 738 /* 739 * Put this buffer in the RX command FIFO. To do this, 740 * we just write the physical address of the descriptor 741 * into the RX descriptor address registers. Note that 742 * there are two registers, one high DWORD and one low 743 * DWORD, which lets us specify a 64-bit address if 744 * desired. We only use a 32-bit address for now. 745 * Writing to the low DWORD register is what actually 746 * causes the command to be issued, so we do that 747 * last. 748 */ 749 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 750 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 751 752 return(0); 753 } 754 755 static int 756 lge_alloc_jumbo_mem(sc) 757 struct lge_softc *sc; 758 { 759 caddr_t ptr; 760 int i; 761 struct lge_jpool_entry *entry; 762 763 /* Grab a big chunk o' storage. */ 764 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 765 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 766 767 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 768 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n"); 769 return(ENOBUFS); 770 } 771 772 SLIST_INIT(&sc->lge_jfree_listhead); 773 SLIST_INIT(&sc->lge_jinuse_listhead); 774 775 /* 776 * Now divide it up into 9K pieces and save the addresses 777 * in an array. 778 */ 779 ptr = sc->lge_cdata.lge_jumbo_buf; 780 for (i = 0; i < LGE_JSLOTS; i++) { 781 sc->lge_cdata.lge_jslots[i] = ptr; 782 ptr += LGE_JLEN; 783 entry = malloc(sizeof(struct lge_jpool_entry), 784 M_DEVBUF, M_NOWAIT); 785 if (entry == NULL) { 786 device_printf(sc->lge_dev, "no memory for jumbo " 787 "buffer queue!\n"); 788 return(ENOBUFS); 789 } 790 entry->slot = i; 791 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 792 entry, jpool_entries); 793 } 794 795 return(0); 796 } 797 798 static void 799 lge_free_jumbo_mem(sc) 800 struct lge_softc *sc; 801 { 802 struct lge_jpool_entry *entry; 803 804 if (sc->lge_cdata.lge_jumbo_buf == NULL) 805 return; 806 807 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) { 808 device_printf(sc->lge_dev, 809 "asked to free buffer that is in use!\n"); 810 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 811 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, 812 jpool_entries); 813 } 814 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) { 815 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 816 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 817 free(entry, M_DEVBUF); 818 } 819 820 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 821 822 return; 823 } 824 825 /* 826 * Allocate a jumbo buffer. 827 */ 828 static void * 829 lge_jalloc(sc) 830 struct lge_softc *sc; 831 { 832 struct lge_jpool_entry *entry; 833 834 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 835 836 if (entry == NULL) { 837 #ifdef LGE_VERBOSE 838 device_printf(sc->lge_dev, "no free jumbo buffers\n"); 839 #endif 840 return(NULL); 841 } 842 843 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 844 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 845 return(sc->lge_cdata.lge_jslots[entry->slot]); 846 } 847 848 /* 849 * Release a jumbo buffer. 850 */ 851 static void 852 lge_jfree(struct mbuf *m) 853 { 854 struct lge_softc *sc; 855 int i; 856 struct lge_jpool_entry *entry; 857 858 /* Extract the softc struct pointer. */ 859 sc = m->m_ext.ext_arg1; 860 861 if (sc == NULL) 862 panic("lge_jfree: can't find softc pointer!"); 863 864 /* calculate the slot this buffer belongs to */ 865 i = ((vm_offset_t)m->m_ext.ext_buf 866 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 867 868 if ((i < 0) || (i >= LGE_JSLOTS)) 869 panic("lge_jfree: asked to free buffer that we don't manage!"); 870 871 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 872 if (entry == NULL) 873 panic("lge_jfree: buffer not in use!"); 874 entry->slot = i; 875 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 876 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 877 } 878 879 /* 880 * A frame has been uploaded: pass the resulting mbuf chain up to 881 * the higher level protocols. 882 */ 883 static void 884 lge_rxeof(sc, cnt) 885 struct lge_softc *sc; 886 int cnt; 887 { 888 struct mbuf *m; 889 struct ifnet *ifp; 890 struct lge_rx_desc *cur_rx; 891 int c, i, total_len = 0; 892 u_int32_t rxsts, rxctl; 893 894 ifp = sc->lge_ifp; 895 896 /* Find out how many frames were processed. */ 897 c = cnt; 898 i = sc->lge_cdata.lge_rx_cons; 899 900 /* Suck them in. */ 901 while(c) { 902 struct mbuf *m0 = NULL; 903 904 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 905 rxctl = cur_rx->lge_ctl; 906 rxsts = cur_rx->lge_sts; 907 m = cur_rx->lge_mbuf; 908 cur_rx->lge_mbuf = NULL; 909 total_len = LGE_RXBYTES(cur_rx); 910 LGE_INC(i, LGE_RX_LIST_CNT); 911 c--; 912 913 /* 914 * If an error occurs, update stats, clear the 915 * status word and leave the mbuf cluster in place: 916 * it should simply get re-used next time this descriptor 917 * comes up in the ring. 918 */ 919 if (rxctl & LGE_RXCTL_ERRMASK) { 920 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 921 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 922 continue; 923 } 924 925 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 926 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 927 ifp, NULL); 928 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 929 if (m0 == NULL) { 930 device_printf(sc->lge_dev, "no receive buffers " 931 "available -- packet dropped!\n"); 932 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 933 continue; 934 } 935 m = m0; 936 } else { 937 m->m_pkthdr.rcvif = ifp; 938 m->m_pkthdr.len = m->m_len = total_len; 939 } 940 941 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 942 943 /* Do IP checksum checking. */ 944 if (rxsts & LGE_RXSTS_ISIP) 945 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 946 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 947 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 948 if ((rxsts & LGE_RXSTS_ISTCP && 949 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 950 (rxsts & LGE_RXSTS_ISUDP && 951 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 952 m->m_pkthdr.csum_flags |= 953 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 954 m->m_pkthdr.csum_data = 0xffff; 955 } 956 957 LGE_UNLOCK(sc); 958 (*ifp->if_input)(ifp, m); 959 LGE_LOCK(sc); 960 } 961 962 sc->lge_cdata.lge_rx_cons = i; 963 964 return; 965 } 966 967 static void 968 lge_rxeoc(sc) 969 struct lge_softc *sc; 970 { 971 struct ifnet *ifp; 972 973 ifp = sc->lge_ifp; 974 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 975 lge_init_locked(sc); 976 return; 977 } 978 979 /* 980 * A frame was downloaded to the chip. It's safe for us to clean up 981 * the list buffers. 982 */ 983 984 static void 985 lge_txeof(sc) 986 struct lge_softc *sc; 987 { 988 struct lge_tx_desc *cur_tx = NULL; 989 struct ifnet *ifp; 990 u_int32_t idx, txdone; 991 992 ifp = sc->lge_ifp; 993 994 /* Clear the timeout timer. */ 995 sc->lge_timer = 0; 996 997 /* 998 * Go through our tx list and free mbufs for those 999 * frames that have been transmitted. 1000 */ 1001 idx = sc->lge_cdata.lge_tx_cons; 1002 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1003 1004 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1005 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1006 1007 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1008 if (cur_tx->lge_mbuf != NULL) { 1009 m_freem(cur_tx->lge_mbuf); 1010 cur_tx->lge_mbuf = NULL; 1011 } 1012 cur_tx->lge_ctl = 0; 1013 1014 txdone--; 1015 LGE_INC(idx, LGE_TX_LIST_CNT); 1016 sc->lge_timer = 0; 1017 } 1018 1019 sc->lge_cdata.lge_tx_cons = idx; 1020 1021 if (cur_tx != NULL) 1022 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1023 1024 return; 1025 } 1026 1027 static void 1028 lge_tick(xsc) 1029 void *xsc; 1030 { 1031 struct lge_softc *sc; 1032 struct mii_data *mii; 1033 struct ifnet *ifp; 1034 1035 sc = xsc; 1036 ifp = sc->lge_ifp; 1037 LGE_LOCK_ASSERT(sc); 1038 1039 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1040 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1041 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1042 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1043 1044 if (!sc->lge_link) { 1045 mii = device_get_softc(sc->lge_miibus); 1046 mii_tick(mii); 1047 if (mii->mii_media_status & IFM_ACTIVE && 1048 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1049 sc->lge_link++; 1050 if (bootverbose && 1051 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1052 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1053 device_printf(sc->lge_dev, "gigabit link up\n"); 1054 if (ifp->if_snd.ifq_head != NULL) 1055 lge_start_locked(ifp); 1056 } 1057 } 1058 1059 if (sc->lge_timer != 0 && --sc->lge_timer == 0) 1060 lge_watchdog(sc); 1061 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1062 1063 return; 1064 } 1065 1066 static void 1067 lge_intr(arg) 1068 void *arg; 1069 { 1070 struct lge_softc *sc; 1071 struct ifnet *ifp; 1072 u_int32_t status; 1073 1074 sc = arg; 1075 ifp = sc->lge_ifp; 1076 LGE_LOCK(sc); 1077 1078 /* Suppress unwanted interrupts */ 1079 if (!(ifp->if_flags & IFF_UP)) { 1080 lge_stop(sc); 1081 LGE_UNLOCK(sc); 1082 return; 1083 } 1084 1085 for (;;) { 1086 /* 1087 * Reading the ISR register clears all interrupts, and 1088 * clears the 'interrupts enabled' bit in the IMR 1089 * register. 1090 */ 1091 status = CSR_READ_4(sc, LGE_ISR); 1092 1093 if ((status & LGE_INTRS) == 0) 1094 break; 1095 1096 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1097 lge_txeof(sc); 1098 1099 if (status & LGE_ISR_RXDMA_DONE) 1100 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1101 1102 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1103 lge_rxeoc(sc); 1104 1105 if (status & LGE_ISR_PHY_INTR) { 1106 sc->lge_link = 0; 1107 callout_stop(&sc->lge_stat_callout); 1108 lge_tick(sc); 1109 } 1110 } 1111 1112 /* Re-enable interrupts. */ 1113 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1114 1115 if (ifp->if_snd.ifq_head != NULL) 1116 lge_start_locked(ifp); 1117 1118 LGE_UNLOCK(sc); 1119 return; 1120 } 1121 1122 /* 1123 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1124 * pointers to the fragment pointers. 1125 */ 1126 static int 1127 lge_encap(sc, m_head, txidx) 1128 struct lge_softc *sc; 1129 struct mbuf *m_head; 1130 u_int32_t *txidx; 1131 { 1132 struct lge_frag *f = NULL; 1133 struct lge_tx_desc *cur_tx; 1134 struct mbuf *m; 1135 int frag = 0, tot_len = 0; 1136 1137 /* 1138 * Start packing the mbufs in this chain into 1139 * the fragment pointers. Stop when we run out 1140 * of fragments or hit the end of the mbuf chain. 1141 */ 1142 m = m_head; 1143 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1144 frag = 0; 1145 1146 for (m = m_head; m != NULL; m = m->m_next) { 1147 if (m->m_len != 0) { 1148 tot_len += m->m_len; 1149 f = &cur_tx->lge_frags[frag]; 1150 f->lge_fraglen = m->m_len; 1151 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1152 f->lge_fragptr_hi = 0; 1153 frag++; 1154 } 1155 } 1156 1157 if (m != NULL) 1158 return(ENOBUFS); 1159 1160 cur_tx->lge_mbuf = m_head; 1161 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1162 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1163 1164 /* Queue for transmit */ 1165 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1166 1167 return(0); 1168 } 1169 1170 /* 1171 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1172 * to the mbuf data regions directly in the transmit lists. We also save a 1173 * copy of the pointers since the transmit list fragment pointers are 1174 * physical addresses. 1175 */ 1176 1177 static void 1178 lge_start(ifp) 1179 struct ifnet *ifp; 1180 { 1181 struct lge_softc *sc; 1182 1183 sc = ifp->if_softc; 1184 LGE_LOCK(sc); 1185 lge_start_locked(ifp); 1186 LGE_UNLOCK(sc); 1187 } 1188 1189 static void 1190 lge_start_locked(ifp) 1191 struct ifnet *ifp; 1192 { 1193 struct lge_softc *sc; 1194 struct mbuf *m_head = NULL; 1195 u_int32_t idx; 1196 1197 sc = ifp->if_softc; 1198 1199 if (!sc->lge_link) 1200 return; 1201 1202 idx = sc->lge_cdata.lge_tx_prod; 1203 1204 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1205 return; 1206 1207 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1208 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1209 break; 1210 1211 IF_DEQUEUE(&ifp->if_snd, m_head); 1212 if (m_head == NULL) 1213 break; 1214 1215 if (lge_encap(sc, m_head, &idx)) { 1216 IF_PREPEND(&ifp->if_snd, m_head); 1217 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1218 break; 1219 } 1220 1221 /* 1222 * If there's a BPF listener, bounce a copy of this frame 1223 * to him. 1224 */ 1225 BPF_MTAP(ifp, m_head); 1226 } 1227 1228 sc->lge_cdata.lge_tx_prod = idx; 1229 1230 /* 1231 * Set a timeout in case the chip goes out to lunch. 1232 */ 1233 sc->lge_timer = 5; 1234 1235 return; 1236 } 1237 1238 static void 1239 lge_init(xsc) 1240 void *xsc; 1241 { 1242 struct lge_softc *sc = xsc; 1243 1244 LGE_LOCK(sc); 1245 lge_init_locked(sc); 1246 LGE_UNLOCK(sc); 1247 } 1248 1249 static void 1250 lge_init_locked(sc) 1251 struct lge_softc *sc; 1252 { 1253 struct ifnet *ifp = sc->lge_ifp; 1254 1255 LGE_LOCK_ASSERT(sc); 1256 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1257 return; 1258 1259 /* 1260 * Cancel pending I/O and free all RX/TX buffers. 1261 */ 1262 lge_stop(sc); 1263 lge_reset(sc); 1264 1265 /* Set MAC address */ 1266 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0])); 1267 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4])); 1268 1269 /* Init circular RX list. */ 1270 if (lge_list_rx_init(sc) == ENOBUFS) { 1271 device_printf(sc->lge_dev, "initialization failed: no " 1272 "memory for rx buffers\n"); 1273 lge_stop(sc); 1274 return; 1275 } 1276 1277 /* 1278 * Init tx descriptors. 1279 */ 1280 lge_list_tx_init(sc); 1281 1282 /* Set initial value for MODE1 register. */ 1283 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1284 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1285 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1286 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1287 1288 /* If we want promiscuous mode, set the allframes bit. */ 1289 if (ifp->if_flags & IFF_PROMISC) { 1290 CSR_WRITE_4(sc, LGE_MODE1, 1291 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1292 } else { 1293 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1294 } 1295 1296 /* 1297 * Set the capture broadcast bit to capture broadcast frames. 1298 */ 1299 if (ifp->if_flags & IFF_BROADCAST) { 1300 CSR_WRITE_4(sc, LGE_MODE1, 1301 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1302 } else { 1303 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1304 } 1305 1306 /* Packet padding workaround? */ 1307 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1308 1309 /* No error frames */ 1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1311 1312 /* Receive large frames */ 1313 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1314 1315 /* Workaround: disable RX/TX flow control */ 1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1318 1319 /* Make sure to strip CRC from received frames */ 1320 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1321 1322 /* Turn off magic packet mode */ 1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1324 1325 /* Turn off all VLAN stuff */ 1326 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1327 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1328 1329 /* Workarond: FIFO overflow */ 1330 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1331 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1332 1333 /* 1334 * Load the multicast filter. 1335 */ 1336 lge_setmulti(sc); 1337 1338 /* 1339 * Enable hardware checksum validation for all received IPv4 1340 * packets, do not reject packets with bad checksums. 1341 */ 1342 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1343 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1344 LGE_MODE2_RX_ERRCSUM); 1345 1346 /* 1347 * Enable the delivery of PHY interrupts based on 1348 * link/speed/duplex status chalges. 1349 */ 1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1351 1352 /* Enable receiver and transmitter. */ 1353 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1354 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1355 1356 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1358 1359 /* 1360 * Enable interrupts. 1361 */ 1362 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1363 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1364 1365 lge_ifmedia_upd_locked(ifp); 1366 1367 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1368 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1369 1370 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1371 1372 return; 1373 } 1374 1375 /* 1376 * Set media options. 1377 */ 1378 static int 1379 lge_ifmedia_upd(ifp) 1380 struct ifnet *ifp; 1381 { 1382 struct lge_softc *sc; 1383 1384 sc = ifp->if_softc; 1385 LGE_LOCK(sc); 1386 lge_ifmedia_upd_locked(ifp); 1387 LGE_UNLOCK(sc); 1388 1389 return(0); 1390 } 1391 1392 static void 1393 lge_ifmedia_upd_locked(ifp) 1394 struct ifnet *ifp; 1395 { 1396 struct lge_softc *sc; 1397 struct mii_data *mii; 1398 struct mii_softc *miisc; 1399 1400 sc = ifp->if_softc; 1401 1402 LGE_LOCK_ASSERT(sc); 1403 mii = device_get_softc(sc->lge_miibus); 1404 sc->lge_link = 0; 1405 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1406 PHY_RESET(miisc); 1407 mii_mediachg(mii); 1408 } 1409 1410 /* 1411 * Report current media status. 1412 */ 1413 static void 1414 lge_ifmedia_sts(ifp, ifmr) 1415 struct ifnet *ifp; 1416 struct ifmediareq *ifmr; 1417 { 1418 struct lge_softc *sc; 1419 struct mii_data *mii; 1420 1421 sc = ifp->if_softc; 1422 1423 LGE_LOCK(sc); 1424 mii = device_get_softc(sc->lge_miibus); 1425 mii_pollstat(mii); 1426 ifmr->ifm_active = mii->mii_media_active; 1427 ifmr->ifm_status = mii->mii_media_status; 1428 LGE_UNLOCK(sc); 1429 1430 return; 1431 } 1432 1433 static int 1434 lge_ioctl(ifp, command, data) 1435 struct ifnet *ifp; 1436 u_long command; 1437 caddr_t data; 1438 { 1439 struct lge_softc *sc = ifp->if_softc; 1440 struct ifreq *ifr = (struct ifreq *) data; 1441 struct mii_data *mii; 1442 int error = 0; 1443 1444 switch(command) { 1445 case SIOCSIFMTU: 1446 LGE_LOCK(sc); 1447 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1448 error = EINVAL; 1449 else 1450 ifp->if_mtu = ifr->ifr_mtu; 1451 LGE_UNLOCK(sc); 1452 break; 1453 case SIOCSIFFLAGS: 1454 LGE_LOCK(sc); 1455 if (ifp->if_flags & IFF_UP) { 1456 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1457 ifp->if_flags & IFF_PROMISC && 1458 !(sc->lge_if_flags & IFF_PROMISC)) { 1459 CSR_WRITE_4(sc, LGE_MODE1, 1460 LGE_MODE1_SETRST_CTL1| 1461 LGE_MODE1_RX_PROMISC); 1462 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1463 !(ifp->if_flags & IFF_PROMISC) && 1464 sc->lge_if_flags & IFF_PROMISC) { 1465 CSR_WRITE_4(sc, LGE_MODE1, 1466 LGE_MODE1_RX_PROMISC); 1467 } else { 1468 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1469 lge_init_locked(sc); 1470 } 1471 } else { 1472 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1473 lge_stop(sc); 1474 } 1475 sc->lge_if_flags = ifp->if_flags; 1476 LGE_UNLOCK(sc); 1477 error = 0; 1478 break; 1479 case SIOCADDMULTI: 1480 case SIOCDELMULTI: 1481 LGE_LOCK(sc); 1482 lge_setmulti(sc); 1483 LGE_UNLOCK(sc); 1484 error = 0; 1485 break; 1486 case SIOCGIFMEDIA: 1487 case SIOCSIFMEDIA: 1488 mii = device_get_softc(sc->lge_miibus); 1489 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1490 break; 1491 default: 1492 error = ether_ioctl(ifp, command, data); 1493 break; 1494 } 1495 1496 return(error); 1497 } 1498 1499 static void 1500 lge_watchdog(sc) 1501 struct lge_softc *sc; 1502 { 1503 struct ifnet *ifp; 1504 1505 LGE_LOCK_ASSERT(sc); 1506 ifp = sc->lge_ifp; 1507 1508 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1509 if_printf(ifp, "watchdog timeout\n"); 1510 1511 lge_stop(sc); 1512 lge_reset(sc); 1513 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1514 lge_init_locked(sc); 1515 1516 if (ifp->if_snd.ifq_head != NULL) 1517 lge_start_locked(ifp); 1518 } 1519 1520 /* 1521 * Stop the adapter and free any mbufs allocated to the 1522 * RX and TX lists. 1523 */ 1524 static void 1525 lge_stop(sc) 1526 struct lge_softc *sc; 1527 { 1528 int i; 1529 struct ifnet *ifp; 1530 1531 LGE_LOCK_ASSERT(sc); 1532 ifp = sc->lge_ifp; 1533 sc->lge_timer = 0; 1534 callout_stop(&sc->lge_stat_callout); 1535 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1536 1537 /* Disable receiver and transmitter. */ 1538 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1539 sc->lge_link = 0; 1540 1541 /* 1542 * Free data in the RX lists. 1543 */ 1544 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1545 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1546 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1547 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1548 } 1549 } 1550 bzero((char *)&sc->lge_ldata->lge_rx_list, 1551 sizeof(sc->lge_ldata->lge_rx_list)); 1552 1553 /* 1554 * Free the TX list buffers. 1555 */ 1556 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1557 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1558 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1559 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1560 } 1561 } 1562 1563 bzero((char *)&sc->lge_ldata->lge_tx_list, 1564 sizeof(sc->lge_ldata->lge_tx_list)); 1565 1566 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1567 1568 return; 1569 } 1570 1571 /* 1572 * Stop all chip I/O so that the kernel's probe routines don't 1573 * get confused by errant DMAs when rebooting. 1574 */ 1575 static int 1576 lge_shutdown(dev) 1577 device_t dev; 1578 { 1579 struct lge_softc *sc; 1580 1581 sc = device_get_softc(dev); 1582 1583 LGE_LOCK(sc); 1584 lge_reset(sc); 1585 lge_stop(sc); 1586 LGE_UNLOCK(sc); 1587 1588 return (0); 1589 } 1590