1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/module.h> 79 #include <sys/socket.h> 80 81 #include <net/if.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_types.h> 87 88 #include <net/bpf.h> 89 90 #include <vm/vm.h> /* for vtophys */ 91 #include <vm/pmap.h> /* for vtophys */ 92 #include <machine/bus.h> 93 #include <machine/resource.h> 94 #include <sys/bus.h> 95 #include <sys/rman.h> 96 97 #include <dev/mii/mii.h> 98 #include <dev/mii/miivar.h> 99 100 #include <dev/pci/pcireg.h> 101 #include <dev/pci/pcivar.h> 102 103 #define LGE_USEIOSPACE 104 105 #include <dev/lge/if_lgereg.h> 106 107 /* "device miibus" required. See GENERIC if you get errors here. */ 108 #include "miibus_if.h" 109 110 /* 111 * Various supported device vendors/types and their names. 112 */ 113 static struct lge_type lge_devs[] = { 114 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 115 { 0, 0, NULL } 116 }; 117 118 static int lge_probe(device_t); 119 static int lge_attach(device_t); 120 static int lge_detach(device_t); 121 122 static int lge_alloc_jumbo_mem(struct lge_softc *); 123 static void lge_free_jumbo_mem(struct lge_softc *); 124 static void *lge_jalloc(struct lge_softc *); 125 static void lge_jfree(void *, void *); 126 127 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 128 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 129 static void lge_rxeof(struct lge_softc *, int); 130 static void lge_rxeoc(struct lge_softc *); 131 static void lge_txeof(struct lge_softc *); 132 static void lge_intr(void *); 133 static void lge_tick(void *); 134 static void lge_start(struct ifnet *); 135 static void lge_start_locked(struct ifnet *); 136 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137 static void lge_init(void *); 138 static void lge_init_locked(struct lge_softc *); 139 static void lge_stop(struct lge_softc *); 140 static void lge_watchdog(struct ifnet *); 141 static void lge_shutdown(device_t); 142 static int lge_ifmedia_upd(struct ifnet *); 143 static void lge_ifmedia_upd_locked(struct ifnet *); 144 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 145 146 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 147 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 148 149 static int lge_miibus_readreg(device_t, int, int); 150 static int lge_miibus_writereg(device_t, int, int, int); 151 static void lge_miibus_statchg(device_t); 152 153 static void lge_setmulti(struct lge_softc *); 154 static void lge_reset(struct lge_softc *); 155 static int lge_list_rx_init(struct lge_softc *); 156 static int lge_list_tx_init(struct lge_softc *); 157 158 #ifdef LGE_USEIOSPACE 159 #define LGE_RES SYS_RES_IOPORT 160 #define LGE_RID LGE_PCI_LOIO 161 #else 162 #define LGE_RES SYS_RES_MEMORY 163 #define LGE_RID LGE_PCI_LOMEM 164 #endif 165 166 static device_method_t lge_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, lge_probe), 169 DEVMETHOD(device_attach, lge_attach), 170 DEVMETHOD(device_detach, lge_detach), 171 DEVMETHOD(device_shutdown, lge_shutdown), 172 173 /* bus interface */ 174 DEVMETHOD(bus_print_child, bus_generic_print_child), 175 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 176 177 /* MII interface */ 178 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 179 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 180 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 181 182 { 0, 0 } 183 }; 184 185 static driver_t lge_driver = { 186 "lge", 187 lge_methods, 188 sizeof(struct lge_softc) 189 }; 190 191 static devclass_t lge_devclass; 192 193 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 194 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 195 MODULE_DEPEND(lge, pci, 1, 1, 1); 196 MODULE_DEPEND(lge, ether, 1, 1, 1); 197 MODULE_DEPEND(lge, miibus, 1, 1, 1); 198 199 #define LGE_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) | (x)) 202 203 #define LGE_CLRBIT(sc, reg, x) \ 204 CSR_WRITE_4(sc, reg, \ 205 CSR_READ_4(sc, reg) & ~(x)) 206 207 #define SIO_SET(x) \ 208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 209 210 #define SIO_CLR(x) \ 211 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 212 213 /* 214 * Read a word of data stored in the EEPROM at address 'addr.' 215 */ 216 static void 217 lge_eeprom_getword(sc, addr, dest) 218 struct lge_softc *sc; 219 int addr; 220 u_int16_t *dest; 221 { 222 register int i; 223 u_int32_t val; 224 225 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 226 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 227 228 for (i = 0; i < LGE_TIMEOUT; i++) 229 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 230 break; 231 232 if (i == LGE_TIMEOUT) { 233 device_printf(sc->lge_dev, "EEPROM read timed out\n"); 234 return; 235 } 236 237 val = CSR_READ_4(sc, LGE_EEDATA); 238 239 if (addr & 1) 240 *dest = (val >> 16) & 0xFFFF; 241 else 242 *dest = val & 0xFFFF; 243 244 return; 245 } 246 247 /* 248 * Read a sequence of words from the EEPROM. 249 */ 250 static void 251 lge_read_eeprom(sc, dest, off, cnt, swap) 252 struct lge_softc *sc; 253 caddr_t dest; 254 int off; 255 int cnt; 256 int swap; 257 { 258 int i; 259 u_int16_t word = 0, *ptr; 260 261 for (i = 0; i < cnt; i++) { 262 lge_eeprom_getword(sc, off + i, &word); 263 ptr = (u_int16_t *)(dest + (i * 2)); 264 if (swap) 265 *ptr = ntohs(word); 266 else 267 *ptr = word; 268 } 269 270 return; 271 } 272 273 static int 274 lge_miibus_readreg(dev, phy, reg) 275 device_t dev; 276 int phy, reg; 277 { 278 struct lge_softc *sc; 279 int i; 280 281 sc = device_get_softc(dev); 282 283 /* 284 * If we have a non-PCS PHY, pretend that the internal 285 * autoneg stuff at PHY address 0 isn't there so that 286 * the miibus code will find only the GMII PHY. 287 */ 288 if (sc->lge_pcs == 0 && phy == 0) 289 return(0); 290 291 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 292 293 for (i = 0; i < LGE_TIMEOUT; i++) 294 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 295 break; 296 297 if (i == LGE_TIMEOUT) { 298 device_printf(sc->lge_dev, "PHY read timed out\n"); 299 return(0); 300 } 301 302 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 303 } 304 305 static int 306 lge_miibus_writereg(dev, phy, reg, data) 307 device_t dev; 308 int phy, reg, data; 309 { 310 struct lge_softc *sc; 311 int i; 312 313 sc = device_get_softc(dev); 314 315 CSR_WRITE_4(sc, LGE_GMIICTL, 316 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 317 318 for (i = 0; i < LGE_TIMEOUT; i++) 319 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 320 break; 321 322 if (i == LGE_TIMEOUT) { 323 device_printf(sc->lge_dev, "PHY write timed out\n"); 324 return(0); 325 } 326 327 return(0); 328 } 329 330 static void 331 lge_miibus_statchg(dev) 332 device_t dev; 333 { 334 struct lge_softc *sc; 335 struct mii_data *mii; 336 337 sc = device_get_softc(dev); 338 mii = device_get_softc(sc->lge_miibus); 339 340 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 341 switch (IFM_SUBTYPE(mii->mii_media_active)) { 342 case IFM_1000_T: 343 case IFM_1000_SX: 344 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 345 break; 346 case IFM_100_TX: 347 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 348 break; 349 case IFM_10_T: 350 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 351 break; 352 default: 353 /* 354 * Choose something, even if it's wrong. Clearing 355 * all the bits will hose autoneg on the internal 356 * PHY. 357 */ 358 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 359 break; 360 } 361 362 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 363 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 364 } else { 365 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 366 } 367 368 return; 369 } 370 371 static void 372 lge_setmulti(sc) 373 struct lge_softc *sc; 374 { 375 struct ifnet *ifp; 376 struct ifmultiaddr *ifma; 377 u_int32_t h = 0, hashes[2] = { 0, 0 }; 378 379 ifp = sc->lge_ifp; 380 LGE_LOCK_ASSERT(sc); 381 382 /* Make sure multicast hash table is enabled. */ 383 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 384 385 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 386 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 387 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 388 return; 389 } 390 391 /* first, zot all the existing hash bits */ 392 CSR_WRITE_4(sc, LGE_MAR0, 0); 393 CSR_WRITE_4(sc, LGE_MAR1, 0); 394 395 /* now program new ones */ 396 IF_ADDR_LOCK(ifp); 397 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 398 if (ifma->ifma_addr->sa_family != AF_LINK) 399 continue; 400 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 401 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 402 if (h < 32) 403 hashes[0] |= (1 << h); 404 else 405 hashes[1] |= (1 << (h - 32)); 406 } 407 IF_ADDR_UNLOCK(ifp); 408 409 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 410 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 411 412 return; 413 } 414 415 static void 416 lge_reset(sc) 417 struct lge_softc *sc; 418 { 419 register int i; 420 421 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 422 423 for (i = 0; i < LGE_TIMEOUT; i++) { 424 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 425 break; 426 } 427 428 if (i == LGE_TIMEOUT) 429 device_printf(sc->lge_dev, "reset never completed\n"); 430 431 /* Wait a little while for the chip to get its brains in order. */ 432 DELAY(1000); 433 434 return; 435 } 436 437 /* 438 * Probe for a Level 1 chip. Check the PCI vendor and device 439 * IDs against our list and return a device name if we find a match. 440 */ 441 static int 442 lge_probe(dev) 443 device_t dev; 444 { 445 struct lge_type *t; 446 447 t = lge_devs; 448 449 while(t->lge_name != NULL) { 450 if ((pci_get_vendor(dev) == t->lge_vid) && 451 (pci_get_device(dev) == t->lge_did)) { 452 device_set_desc(dev, t->lge_name); 453 return(BUS_PROBE_DEFAULT); 454 } 455 t++; 456 } 457 458 return(ENXIO); 459 } 460 461 /* 462 * Attach the interface. Allocate softc structures, do ifmedia 463 * setup and ethernet/BPF attach. 464 */ 465 static int 466 lge_attach(dev) 467 device_t dev; 468 { 469 u_char eaddr[ETHER_ADDR_LEN]; 470 struct lge_softc *sc; 471 struct ifnet *ifp = NULL; 472 int error = 0, rid; 473 474 sc = device_get_softc(dev); 475 sc->lge_dev = dev; 476 477 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 478 MTX_DEF); 479 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0); 480 481 /* 482 * Map control/status registers. 483 */ 484 pci_enable_busmaster(dev); 485 486 rid = LGE_RID; 487 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 488 489 if (sc->lge_res == NULL) { 490 device_printf(dev, "couldn't map ports/memory\n"); 491 error = ENXIO; 492 goto fail; 493 } 494 495 sc->lge_btag = rman_get_bustag(sc->lge_res); 496 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 497 498 /* Allocate interrupt */ 499 rid = 0; 500 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 501 RF_SHAREABLE | RF_ACTIVE); 502 503 if (sc->lge_irq == NULL) { 504 device_printf(dev, "couldn't map interrupt\n"); 505 error = ENXIO; 506 goto fail; 507 } 508 509 /* Reset the adapter. */ 510 lge_reset(sc); 511 512 /* 513 * Get station address from the EEPROM. 514 */ 515 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 516 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 517 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 518 519 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 520 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 521 522 if (sc->lge_ldata == NULL) { 523 device_printf(dev, "no memory for list buffers!\n"); 524 error = ENXIO; 525 goto fail; 526 } 527 528 /* Try to allocate memory for jumbo buffers. */ 529 if (lge_alloc_jumbo_mem(sc)) { 530 device_printf(dev, "jumbo buffer allocation failed\n"); 531 error = ENXIO; 532 goto fail; 533 } 534 535 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 536 if (ifp == NULL) { 537 device_printf(dev, "can not if_alloc()\n"); 538 lge_free_jumbo_mem(sc); 539 error = ENOSPC; 540 goto fail; 541 } 542 ifp->if_softc = sc; 543 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 544 ifp->if_mtu = ETHERMTU; 545 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 546 ifp->if_ioctl = lge_ioctl; 547 ifp->if_start = lge_start; 548 ifp->if_watchdog = lge_watchdog; 549 ifp->if_init = lge_init; 550 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 551 ifp->if_capabilities = IFCAP_RXCSUM; 552 ifp->if_capenable = ifp->if_capabilities; 553 554 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 555 sc->lge_pcs = 1; 556 else 557 sc->lge_pcs = 0; 558 559 /* 560 * Do MII setup. 561 */ 562 if (mii_phy_probe(dev, &sc->lge_miibus, 563 lge_ifmedia_upd, lge_ifmedia_sts)) { 564 device_printf(dev, "MII without any PHY!\n"); 565 lge_free_jumbo_mem(sc); 566 error = ENXIO; 567 goto fail; 568 } 569 570 /* 571 * Call MI attach routine. 572 */ 573 ether_ifattach(ifp, eaddr); 574 575 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE, 576 NULL, lge_intr, sc, &sc->lge_intrhand); 577 578 if (error) { 579 ether_ifdetach(ifp); 580 device_printf(dev, "couldn't set up irq\n"); 581 goto fail; 582 } 583 return (0); 584 585 fail: 586 if (sc->lge_ldata) 587 contigfree(sc->lge_ldata, 588 sizeof(struct lge_list_data), M_DEVBUF); 589 if (ifp) 590 if_free(ifp); 591 if (sc->lge_irq) 592 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 593 if (sc->lge_res) 594 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 595 mtx_destroy(&sc->lge_mtx); 596 return(error); 597 } 598 599 static int 600 lge_detach(dev) 601 device_t dev; 602 { 603 struct lge_softc *sc; 604 struct ifnet *ifp; 605 606 sc = device_get_softc(dev); 607 ifp = sc->lge_ifp; 608 609 LGE_LOCK(sc); 610 lge_reset(sc); 611 lge_stop(sc); 612 LGE_UNLOCK(sc); 613 callout_drain(&sc->lge_stat_callout); 614 ether_ifdetach(ifp); 615 616 bus_generic_detach(dev); 617 device_delete_child(dev, sc->lge_miibus); 618 619 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 620 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 621 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 622 623 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 624 if_free(ifp); 625 lge_free_jumbo_mem(sc); 626 mtx_destroy(&sc->lge_mtx); 627 628 return(0); 629 } 630 631 /* 632 * Initialize the transmit descriptors. 633 */ 634 static int 635 lge_list_tx_init(sc) 636 struct lge_softc *sc; 637 { 638 struct lge_list_data *ld; 639 struct lge_ring_data *cd; 640 int i; 641 642 cd = &sc->lge_cdata; 643 ld = sc->lge_ldata; 644 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 645 ld->lge_tx_list[i].lge_mbuf = NULL; 646 ld->lge_tx_list[i].lge_ctl = 0; 647 } 648 649 cd->lge_tx_prod = cd->lge_tx_cons = 0; 650 651 return(0); 652 } 653 654 655 /* 656 * Initialize the RX descriptors and allocate mbufs for them. Note that 657 * we arralge the descriptors in a closed ring, so that the last descriptor 658 * points back to the first. 659 */ 660 static int 661 lge_list_rx_init(sc) 662 struct lge_softc *sc; 663 { 664 struct lge_list_data *ld; 665 struct lge_ring_data *cd; 666 int i; 667 668 ld = sc->lge_ldata; 669 cd = &sc->lge_cdata; 670 671 cd->lge_rx_prod = cd->lge_rx_cons = 0; 672 673 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 674 675 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 676 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 677 break; 678 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 679 return(ENOBUFS); 680 } 681 682 /* Clear possible 'rx command queue empty' interrupt. */ 683 CSR_READ_4(sc, LGE_ISR); 684 685 return(0); 686 } 687 688 /* 689 * Initialize an RX descriptor and attach an MBUF cluster. 690 */ 691 static int 692 lge_newbuf(sc, c, m) 693 struct lge_softc *sc; 694 struct lge_rx_desc *c; 695 struct mbuf *m; 696 { 697 struct mbuf *m_new = NULL; 698 caddr_t *buf = NULL; 699 700 if (m == NULL) { 701 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 702 if (m_new == NULL) { 703 device_printf(sc->lge_dev, "no memory for rx list " 704 "-- packet dropped!\n"); 705 return(ENOBUFS); 706 } 707 708 /* Allocate the jumbo buffer */ 709 buf = lge_jalloc(sc); 710 if (buf == NULL) { 711 #ifdef LGE_VERBOSE 712 device_printf(sc->lge_dev, "jumbo allocation failed " 713 "-- packet dropped!\n"); 714 #endif 715 m_freem(m_new); 716 return(ENOBUFS); 717 } 718 /* Attach the buffer to the mbuf */ 719 m_new->m_data = (void *)buf; 720 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 721 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 722 (struct lge_softc *)sc, 0, EXT_NET_DRV); 723 } else { 724 m_new = m; 725 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 726 m_new->m_data = m_new->m_ext.ext_buf; 727 } 728 729 /* 730 * Adjust alignment so packet payload begins on a 731 * longword boundary. Mandatory for Alpha, useful on 732 * x86 too. 733 */ 734 m_adj(m_new, ETHER_ALIGN); 735 736 c->lge_mbuf = m_new; 737 c->lge_fragptr_hi = 0; 738 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 739 c->lge_fraglen = m_new->m_len; 740 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 741 c->lge_sts = 0; 742 743 /* 744 * Put this buffer in the RX command FIFO. To do this, 745 * we just write the physical address of the descriptor 746 * into the RX descriptor address registers. Note that 747 * there are two registers, one high DWORD and one low 748 * DWORD, which lets us specify a 64-bit address if 749 * desired. We only use a 32-bit address for now. 750 * Writing to the low DWORD register is what actually 751 * causes the command to be issued, so we do that 752 * last. 753 */ 754 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 755 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 756 757 return(0); 758 } 759 760 static int 761 lge_alloc_jumbo_mem(sc) 762 struct lge_softc *sc; 763 { 764 caddr_t ptr; 765 register int i; 766 struct lge_jpool_entry *entry; 767 768 /* Grab a big chunk o' storage. */ 769 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 770 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 771 772 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 773 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n"); 774 return(ENOBUFS); 775 } 776 777 SLIST_INIT(&sc->lge_jfree_listhead); 778 SLIST_INIT(&sc->lge_jinuse_listhead); 779 780 /* 781 * Now divide it up into 9K pieces and save the addresses 782 * in an array. 783 */ 784 ptr = sc->lge_cdata.lge_jumbo_buf; 785 for (i = 0; i < LGE_JSLOTS; i++) { 786 sc->lge_cdata.lge_jslots[i] = ptr; 787 ptr += LGE_JLEN; 788 entry = malloc(sizeof(struct lge_jpool_entry), 789 M_DEVBUF, M_NOWAIT); 790 if (entry == NULL) { 791 device_printf(sc->lge_dev, "no memory for jumbo " 792 "buffer queue!\n"); 793 return(ENOBUFS); 794 } 795 entry->slot = i; 796 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 797 entry, jpool_entries); 798 } 799 800 return(0); 801 } 802 803 static void 804 lge_free_jumbo_mem(sc) 805 struct lge_softc *sc; 806 { 807 int i; 808 struct lge_jpool_entry *entry; 809 810 for (i = 0; i < LGE_JSLOTS; i++) { 811 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 812 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 813 free(entry, M_DEVBUF); 814 } 815 816 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 817 818 return; 819 } 820 821 /* 822 * Allocate a jumbo buffer. 823 */ 824 static void * 825 lge_jalloc(sc) 826 struct lge_softc *sc; 827 { 828 struct lge_jpool_entry *entry; 829 830 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 831 832 if (entry == NULL) { 833 #ifdef LGE_VERBOSE 834 device_printf(sc->lge_dev, "no free jumbo buffers\n"); 835 #endif 836 return(NULL); 837 } 838 839 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 840 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 841 return(sc->lge_cdata.lge_jslots[entry->slot]); 842 } 843 844 /* 845 * Release a jumbo buffer. 846 */ 847 static void 848 lge_jfree(buf, args) 849 void *buf; 850 void *args; 851 { 852 struct lge_softc *sc; 853 int i; 854 struct lge_jpool_entry *entry; 855 856 /* Extract the softc struct pointer. */ 857 sc = args; 858 859 if (sc == NULL) 860 panic("lge_jfree: can't find softc pointer!"); 861 862 /* calculate the slot this buffer belongs to */ 863 i = ((vm_offset_t)buf 864 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 865 866 if ((i < 0) || (i >= LGE_JSLOTS)) 867 panic("lge_jfree: asked to free buffer that we don't manage!"); 868 869 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 870 if (entry == NULL) 871 panic("lge_jfree: buffer not in use!"); 872 entry->slot = i; 873 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 874 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 875 876 return; 877 } 878 879 /* 880 * A frame has been uploaded: pass the resulting mbuf chain up to 881 * the higher level protocols. 882 */ 883 static void 884 lge_rxeof(sc, cnt) 885 struct lge_softc *sc; 886 int cnt; 887 { 888 struct mbuf *m; 889 struct ifnet *ifp; 890 struct lge_rx_desc *cur_rx; 891 int c, i, total_len = 0; 892 u_int32_t rxsts, rxctl; 893 894 ifp = sc->lge_ifp; 895 896 /* Find out how many frames were processed. */ 897 c = cnt; 898 i = sc->lge_cdata.lge_rx_cons; 899 900 /* Suck them in. */ 901 while(c) { 902 struct mbuf *m0 = NULL; 903 904 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 905 rxctl = cur_rx->lge_ctl; 906 rxsts = cur_rx->lge_sts; 907 m = cur_rx->lge_mbuf; 908 cur_rx->lge_mbuf = NULL; 909 total_len = LGE_RXBYTES(cur_rx); 910 LGE_INC(i, LGE_RX_LIST_CNT); 911 c--; 912 913 /* 914 * If an error occurs, update stats, clear the 915 * status word and leave the mbuf cluster in place: 916 * it should simply get re-used next time this descriptor 917 * comes up in the ring. 918 */ 919 if (rxctl & LGE_RXCTL_ERRMASK) { 920 ifp->if_ierrors++; 921 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 922 continue; 923 } 924 925 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 926 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 927 ifp, NULL); 928 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 929 if (m0 == NULL) { 930 device_printf(sc->lge_dev, "no receive buffers " 931 "available -- packet dropped!\n"); 932 ifp->if_ierrors++; 933 continue; 934 } 935 m = m0; 936 } else { 937 m->m_pkthdr.rcvif = ifp; 938 m->m_pkthdr.len = m->m_len = total_len; 939 } 940 941 ifp->if_ipackets++; 942 943 /* Do IP checksum checking. */ 944 if (rxsts & LGE_RXSTS_ISIP) 945 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 946 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 947 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 948 if ((rxsts & LGE_RXSTS_ISTCP && 949 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 950 (rxsts & LGE_RXSTS_ISUDP && 951 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 952 m->m_pkthdr.csum_flags |= 953 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 954 m->m_pkthdr.csum_data = 0xffff; 955 } 956 957 LGE_UNLOCK(sc); 958 (*ifp->if_input)(ifp, m); 959 LGE_LOCK(sc); 960 } 961 962 sc->lge_cdata.lge_rx_cons = i; 963 964 return; 965 } 966 967 static void 968 lge_rxeoc(sc) 969 struct lge_softc *sc; 970 { 971 struct ifnet *ifp; 972 973 ifp = sc->lge_ifp; 974 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 975 lge_init_locked(sc); 976 return; 977 } 978 979 /* 980 * A frame was downloaded to the chip. It's safe for us to clean up 981 * the list buffers. 982 */ 983 984 static void 985 lge_txeof(sc) 986 struct lge_softc *sc; 987 { 988 struct lge_tx_desc *cur_tx = NULL; 989 struct ifnet *ifp; 990 u_int32_t idx, txdone; 991 992 ifp = sc->lge_ifp; 993 994 /* Clear the timeout timer. */ 995 ifp->if_timer = 0; 996 997 /* 998 * Go through our tx list and free mbufs for those 999 * frames that have been transmitted. 1000 */ 1001 idx = sc->lge_cdata.lge_tx_cons; 1002 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1003 1004 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1005 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1006 1007 ifp->if_opackets++; 1008 if (cur_tx->lge_mbuf != NULL) { 1009 m_freem(cur_tx->lge_mbuf); 1010 cur_tx->lge_mbuf = NULL; 1011 } 1012 cur_tx->lge_ctl = 0; 1013 1014 txdone--; 1015 LGE_INC(idx, LGE_TX_LIST_CNT); 1016 ifp->if_timer = 0; 1017 } 1018 1019 sc->lge_cdata.lge_tx_cons = idx; 1020 1021 if (cur_tx != NULL) 1022 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1023 1024 return; 1025 } 1026 1027 static void 1028 lge_tick(xsc) 1029 void *xsc; 1030 { 1031 struct lge_softc *sc; 1032 struct mii_data *mii; 1033 struct ifnet *ifp; 1034 1035 sc = xsc; 1036 ifp = sc->lge_ifp; 1037 LGE_LOCK_ASSERT(sc); 1038 1039 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1040 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1041 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1042 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1043 1044 if (!sc->lge_link) { 1045 mii = device_get_softc(sc->lge_miibus); 1046 mii_tick(mii); 1047 if (mii->mii_media_status & IFM_ACTIVE && 1048 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1049 sc->lge_link++; 1050 if (bootverbose && 1051 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1052 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1053 device_printf(sc->lge_dev, "gigabit link up\n"); 1054 if (ifp->if_snd.ifq_head != NULL) 1055 lge_start_locked(ifp); 1056 } 1057 } 1058 1059 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1060 1061 return; 1062 } 1063 1064 static void 1065 lge_intr(arg) 1066 void *arg; 1067 { 1068 struct lge_softc *sc; 1069 struct ifnet *ifp; 1070 u_int32_t status; 1071 1072 sc = arg; 1073 ifp = sc->lge_ifp; 1074 LGE_LOCK(sc); 1075 1076 /* Supress unwanted interrupts */ 1077 if (!(ifp->if_flags & IFF_UP)) { 1078 lge_stop(sc); 1079 LGE_UNLOCK(sc); 1080 return; 1081 } 1082 1083 for (;;) { 1084 /* 1085 * Reading the ISR register clears all interrupts, and 1086 * clears the 'interrupts enabled' bit in the IMR 1087 * register. 1088 */ 1089 status = CSR_READ_4(sc, LGE_ISR); 1090 1091 if ((status & LGE_INTRS) == 0) 1092 break; 1093 1094 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1095 lge_txeof(sc); 1096 1097 if (status & LGE_ISR_RXDMA_DONE) 1098 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1099 1100 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1101 lge_rxeoc(sc); 1102 1103 if (status & LGE_ISR_PHY_INTR) { 1104 sc->lge_link = 0; 1105 callout_stop(&sc->lge_stat_callout); 1106 lge_tick(sc); 1107 } 1108 } 1109 1110 /* Re-enable interrupts. */ 1111 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1112 1113 if (ifp->if_snd.ifq_head != NULL) 1114 lge_start_locked(ifp); 1115 1116 LGE_UNLOCK(sc); 1117 return; 1118 } 1119 1120 /* 1121 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1122 * pointers to the fragment pointers. 1123 */ 1124 static int 1125 lge_encap(sc, m_head, txidx) 1126 struct lge_softc *sc; 1127 struct mbuf *m_head; 1128 u_int32_t *txidx; 1129 { 1130 struct lge_frag *f = NULL; 1131 struct lge_tx_desc *cur_tx; 1132 struct mbuf *m; 1133 int frag = 0, tot_len = 0; 1134 1135 /* 1136 * Start packing the mbufs in this chain into 1137 * the fragment pointers. Stop when we run out 1138 * of fragments or hit the end of the mbuf chain. 1139 */ 1140 m = m_head; 1141 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1142 frag = 0; 1143 1144 for (m = m_head; m != NULL; m = m->m_next) { 1145 if (m->m_len != 0) { 1146 tot_len += m->m_len; 1147 f = &cur_tx->lge_frags[frag]; 1148 f->lge_fraglen = m->m_len; 1149 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1150 f->lge_fragptr_hi = 0; 1151 frag++; 1152 } 1153 } 1154 1155 if (m != NULL) 1156 return(ENOBUFS); 1157 1158 cur_tx->lge_mbuf = m_head; 1159 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1160 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1161 1162 /* Queue for transmit */ 1163 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1164 1165 return(0); 1166 } 1167 1168 /* 1169 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1170 * to the mbuf data regions directly in the transmit lists. We also save a 1171 * copy of the pointers since the transmit list fragment pointers are 1172 * physical addresses. 1173 */ 1174 1175 static void 1176 lge_start(ifp) 1177 struct ifnet *ifp; 1178 { 1179 struct lge_softc *sc; 1180 1181 sc = ifp->if_softc; 1182 LGE_LOCK(sc); 1183 lge_start_locked(ifp); 1184 LGE_UNLOCK(sc); 1185 } 1186 1187 static void 1188 lge_start_locked(ifp) 1189 struct ifnet *ifp; 1190 { 1191 struct lge_softc *sc; 1192 struct mbuf *m_head = NULL; 1193 u_int32_t idx; 1194 1195 sc = ifp->if_softc; 1196 1197 if (!sc->lge_link) 1198 return; 1199 1200 idx = sc->lge_cdata.lge_tx_prod; 1201 1202 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1203 return; 1204 1205 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1206 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1207 break; 1208 1209 IF_DEQUEUE(&ifp->if_snd, m_head); 1210 if (m_head == NULL) 1211 break; 1212 1213 if (lge_encap(sc, m_head, &idx)) { 1214 IF_PREPEND(&ifp->if_snd, m_head); 1215 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1216 break; 1217 } 1218 1219 /* 1220 * If there's a BPF listener, bounce a copy of this frame 1221 * to him. 1222 */ 1223 BPF_MTAP(ifp, m_head); 1224 } 1225 1226 sc->lge_cdata.lge_tx_prod = idx; 1227 1228 /* 1229 * Set a timeout in case the chip goes out to lunch. 1230 */ 1231 ifp->if_timer = 5; 1232 1233 return; 1234 } 1235 1236 static void 1237 lge_init(xsc) 1238 void *xsc; 1239 { 1240 struct lge_softc *sc = xsc; 1241 1242 LGE_LOCK(sc); 1243 lge_init_locked(sc); 1244 LGE_UNLOCK(sc); 1245 } 1246 1247 static void 1248 lge_init_locked(sc) 1249 struct lge_softc *sc; 1250 { 1251 struct ifnet *ifp = sc->lge_ifp; 1252 struct mii_data *mii; 1253 1254 LGE_LOCK_ASSERT(sc); 1255 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1256 return; 1257 1258 /* 1259 * Cancel pending I/O and free all RX/TX buffers. 1260 */ 1261 lge_stop(sc); 1262 lge_reset(sc); 1263 1264 mii = device_get_softc(sc->lge_miibus); 1265 1266 /* Set MAC address */ 1267 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0])); 1268 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4])); 1269 1270 /* Init circular RX list. */ 1271 if (lge_list_rx_init(sc) == ENOBUFS) { 1272 device_printf(sc->lge_dev, "initialization failed: no " 1273 "memory for rx buffers\n"); 1274 lge_stop(sc); 1275 return; 1276 } 1277 1278 /* 1279 * Init tx descriptors. 1280 */ 1281 lge_list_tx_init(sc); 1282 1283 /* Set initial value for MODE1 register. */ 1284 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1285 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1286 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1287 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1288 1289 /* If we want promiscuous mode, set the allframes bit. */ 1290 if (ifp->if_flags & IFF_PROMISC) { 1291 CSR_WRITE_4(sc, LGE_MODE1, 1292 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1293 } else { 1294 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1295 } 1296 1297 /* 1298 * Set the capture broadcast bit to capture broadcast frames. 1299 */ 1300 if (ifp->if_flags & IFF_BROADCAST) { 1301 CSR_WRITE_4(sc, LGE_MODE1, 1302 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1303 } else { 1304 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1305 } 1306 1307 /* Packet padding workaround? */ 1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1309 1310 /* No error frames */ 1311 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1312 1313 /* Receive large frames */ 1314 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1315 1316 /* Workaround: disable RX/TX flow control */ 1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1318 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1319 1320 /* Make sure to strip CRC from received frames */ 1321 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1322 1323 /* Turn off magic packet mode */ 1324 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1325 1326 /* Turn off all VLAN stuff */ 1327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1328 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1329 1330 /* Workarond: FIFO overflow */ 1331 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1332 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1333 1334 /* 1335 * Load the multicast filter. 1336 */ 1337 lge_setmulti(sc); 1338 1339 /* 1340 * Enable hardware checksum validation for all received IPv4 1341 * packets, do not reject packets with bad checksums. 1342 */ 1343 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1344 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1345 LGE_MODE2_RX_ERRCSUM); 1346 1347 /* 1348 * Enable the delivery of PHY interrupts based on 1349 * link/speed/duplex status chalges. 1350 */ 1351 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1352 1353 /* Enable receiver and transmitter. */ 1354 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1355 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1356 1357 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1358 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1359 1360 /* 1361 * Enable interrupts. 1362 */ 1363 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1364 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1365 1366 lge_ifmedia_upd_locked(ifp); 1367 1368 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1369 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1370 1371 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1372 1373 return; 1374 } 1375 1376 /* 1377 * Set media options. 1378 */ 1379 static int 1380 lge_ifmedia_upd(ifp) 1381 struct ifnet *ifp; 1382 { 1383 struct lge_softc *sc; 1384 1385 sc = ifp->if_softc; 1386 LGE_LOCK(sc); 1387 lge_ifmedia_upd_locked(ifp); 1388 LGE_UNLOCK(sc); 1389 1390 return(0); 1391 } 1392 1393 static void 1394 lge_ifmedia_upd_locked(ifp) 1395 struct ifnet *ifp; 1396 { 1397 struct lge_softc *sc; 1398 struct mii_data *mii; 1399 1400 sc = ifp->if_softc; 1401 1402 LGE_LOCK_ASSERT(sc); 1403 mii = device_get_softc(sc->lge_miibus); 1404 sc->lge_link = 0; 1405 if (mii->mii_instance) { 1406 struct mii_softc *miisc; 1407 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1408 miisc = LIST_NEXT(miisc, mii_list)) 1409 mii_phy_reset(miisc); 1410 } 1411 mii_mediachg(mii); 1412 } 1413 1414 /* 1415 * Report current media status. 1416 */ 1417 static void 1418 lge_ifmedia_sts(ifp, ifmr) 1419 struct ifnet *ifp; 1420 struct ifmediareq *ifmr; 1421 { 1422 struct lge_softc *sc; 1423 struct mii_data *mii; 1424 1425 sc = ifp->if_softc; 1426 1427 LGE_LOCK(sc); 1428 mii = device_get_softc(sc->lge_miibus); 1429 mii_pollstat(mii); 1430 LGE_UNLOCK(sc); 1431 ifmr->ifm_active = mii->mii_media_active; 1432 ifmr->ifm_status = mii->mii_media_status; 1433 1434 return; 1435 } 1436 1437 static int 1438 lge_ioctl(ifp, command, data) 1439 struct ifnet *ifp; 1440 u_long command; 1441 caddr_t data; 1442 { 1443 struct lge_softc *sc = ifp->if_softc; 1444 struct ifreq *ifr = (struct ifreq *) data; 1445 struct mii_data *mii; 1446 int error = 0; 1447 1448 switch(command) { 1449 case SIOCSIFMTU: 1450 LGE_LOCK(sc); 1451 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1452 error = EINVAL; 1453 else 1454 ifp->if_mtu = ifr->ifr_mtu; 1455 LGE_UNLOCK(sc); 1456 break; 1457 case SIOCSIFFLAGS: 1458 LGE_LOCK(sc); 1459 if (ifp->if_flags & IFF_UP) { 1460 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1461 ifp->if_flags & IFF_PROMISC && 1462 !(sc->lge_if_flags & IFF_PROMISC)) { 1463 CSR_WRITE_4(sc, LGE_MODE1, 1464 LGE_MODE1_SETRST_CTL1| 1465 LGE_MODE1_RX_PROMISC); 1466 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1467 !(ifp->if_flags & IFF_PROMISC) && 1468 sc->lge_if_flags & IFF_PROMISC) { 1469 CSR_WRITE_4(sc, LGE_MODE1, 1470 LGE_MODE1_RX_PROMISC); 1471 } else { 1472 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1473 lge_init_locked(sc); 1474 } 1475 } else { 1476 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1477 lge_stop(sc); 1478 } 1479 sc->lge_if_flags = ifp->if_flags; 1480 LGE_UNLOCK(sc); 1481 error = 0; 1482 break; 1483 case SIOCADDMULTI: 1484 case SIOCDELMULTI: 1485 LGE_LOCK(sc); 1486 lge_setmulti(sc); 1487 LGE_UNLOCK(sc); 1488 error = 0; 1489 break; 1490 case SIOCGIFMEDIA: 1491 case SIOCSIFMEDIA: 1492 mii = device_get_softc(sc->lge_miibus); 1493 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1494 break; 1495 default: 1496 error = ether_ioctl(ifp, command, data); 1497 break; 1498 } 1499 1500 return(error); 1501 } 1502 1503 static void 1504 lge_watchdog(ifp) 1505 struct ifnet *ifp; 1506 { 1507 struct lge_softc *sc; 1508 1509 sc = ifp->if_softc; 1510 1511 LGE_LOCK(sc); 1512 ifp->if_oerrors++; 1513 if_printf(ifp, "watchdog timeout\n"); 1514 1515 lge_stop(sc); 1516 lge_reset(sc); 1517 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1518 lge_init_locked(sc); 1519 1520 if (ifp->if_snd.ifq_head != NULL) 1521 lge_start_locked(ifp); 1522 LGE_UNLOCK(sc); 1523 1524 return; 1525 } 1526 1527 /* 1528 * Stop the adapter and free any mbufs allocated to the 1529 * RX and TX lists. 1530 */ 1531 static void 1532 lge_stop(sc) 1533 struct lge_softc *sc; 1534 { 1535 register int i; 1536 struct ifnet *ifp; 1537 1538 LGE_LOCK_ASSERT(sc); 1539 ifp = sc->lge_ifp; 1540 ifp->if_timer = 0; 1541 callout_stop(&sc->lge_stat_callout); 1542 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1543 1544 /* Disable receiver and transmitter. */ 1545 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1546 sc->lge_link = 0; 1547 1548 /* 1549 * Free data in the RX lists. 1550 */ 1551 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1552 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1553 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1554 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1555 } 1556 } 1557 bzero((char *)&sc->lge_ldata->lge_rx_list, 1558 sizeof(sc->lge_ldata->lge_rx_list)); 1559 1560 /* 1561 * Free the TX list buffers. 1562 */ 1563 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1564 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1565 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1566 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1567 } 1568 } 1569 1570 bzero((char *)&sc->lge_ldata->lge_tx_list, 1571 sizeof(sc->lge_ldata->lge_tx_list)); 1572 1573 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1574 1575 return; 1576 } 1577 1578 /* 1579 * Stop all chip I/O so that the kernel's probe routines don't 1580 * get confused by errant DMAs when rebooting. 1581 */ 1582 static void 1583 lge_shutdown(dev) 1584 device_t dev; 1585 { 1586 struct lge_softc *sc; 1587 1588 sc = device_get_softc(dev); 1589 1590 LGE_LOCK(sc); 1591 lge_reset(sc); 1592 lge_stop(sc); 1593 LGE_UNLOCK(sc); 1594 1595 return; 1596 } 1597