1 /* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Cavium, Inc. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /*$FreeBSD$*/ 34 35 /* 36 * \file lio_mem_ops.h 37 * \brief Host Driver: Routines used to read/write Octeon memory. 38 */ 39 40 #ifndef __LIO_MEM_OPS_H__ 41 #define __LIO_MEM_OPS_H__ 42 43 /* 44 * Read a 64-bit value from a BAR1 mapped core memory address. 45 * @param oct - pointer to the octeon device. 46 * @param core_addr - the address to read from. 47 * 48 * The range_idx gives the BAR1 index register for the range of address 49 * in which core_addr is mapped. 50 * 51 * @return 64-bit value read from Core memory 52 */ 53 uint64_t lio_read_device_mem64(struct octeon_device *oct, 54 uint64_t core_addr); 55 56 /* 57 * Read a 32-bit value from a BAR1 mapped core memory address. 58 * @param oct - pointer to the octeon device. 59 * @param core_addr - the address to read from. 60 * 61 * @return 32-bit value read from Core memory 62 */ 63 uint32_t lio_read_device_mem32(struct octeon_device *oct, 64 uint64_t core_addr); 65 66 /* 67 * Write a 32-bit value to a BAR1 mapped core memory address. 68 * @param oct - pointer to the octeon device. 69 * @param core_addr - the address to write to. 70 * @param val - 32-bit value to write. 71 */ 72 void lio_write_device_mem32(struct octeon_device *oct, 73 uint64_t core_addr, uint32_t val); 74 75 /* Read multiple bytes from Octeon memory. */ 76 void lio_pci_read_core_mem(struct octeon_device *oct, 77 uint64_t coreaddr, uint8_t *buf, 78 uint32_t len); 79 80 /* Write multiple bytes into Octeon memory. */ 81 void lio_pci_write_core_mem(struct octeon_device *oct, 82 uint64_t coreaddr, uint8_t *buf, 83 uint32_t len); 84 85 #endif /* __LIO_MEM_OPS_H__ */ 86