13c7e78d3SWeongyo Jeong /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 3718cf2ccSPedro F. Giffuni * 43c7e78d3SWeongyo Jeong * Copyright (c) 2007 Marvell Semiconductor, Inc. 53c7e78d3SWeongyo Jeong * Copyright (c) 2007 Sam Leffler, Errno Consulting 63c7e78d3SWeongyo Jeong * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org> 73c7e78d3SWeongyo Jeong * All rights reserved. 83c7e78d3SWeongyo Jeong * 93c7e78d3SWeongyo Jeong * Redistribution and use in source and binary forms, with or without 103c7e78d3SWeongyo Jeong * modification, are permitted provided that the following conditions 113c7e78d3SWeongyo Jeong * are met: 123c7e78d3SWeongyo Jeong * 1. Redistributions of source code must retain the above copyright 133c7e78d3SWeongyo Jeong * notice, this list of conditions and the following disclaimer, 143c7e78d3SWeongyo Jeong * without modification. 153c7e78d3SWeongyo Jeong * 2. Redistributions in binary form must reproduce at minimum a disclaimer 163c7e78d3SWeongyo Jeong * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 173c7e78d3SWeongyo Jeong * redistribution must be conditioned upon including a substantially 183c7e78d3SWeongyo Jeong * similar Disclaimer requirement for further binary redistribution. 193c7e78d3SWeongyo Jeong * 203c7e78d3SWeongyo Jeong * NO WARRANTY 213c7e78d3SWeongyo Jeong * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 223c7e78d3SWeongyo Jeong * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 233c7e78d3SWeongyo Jeong * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 243c7e78d3SWeongyo Jeong * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 253c7e78d3SWeongyo Jeong * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 263c7e78d3SWeongyo Jeong * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 273c7e78d3SWeongyo Jeong * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 283c7e78d3SWeongyo Jeong * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 293c7e78d3SWeongyo Jeong * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 303c7e78d3SWeongyo Jeong * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 313c7e78d3SWeongyo Jeong * THE POSSIBILITY OF SUCH DAMAGES. 323c7e78d3SWeongyo Jeong */ 333c7e78d3SWeongyo Jeong 343c7e78d3SWeongyo Jeong /* 353c7e78d3SWeongyo Jeong * Definitions for the Marvell 88W8335 Wireless LAN controller. 363c7e78d3SWeongyo Jeong */ 373c7e78d3SWeongyo Jeong #ifndef _DEV_MALO_H 383c7e78d3SWeongyo Jeong #define _DEV_MALO_H 393c7e78d3SWeongyo Jeong 403c7e78d3SWeongyo Jeong #include <net80211/ieee80211_radiotap.h> 413c7e78d3SWeongyo Jeong #include <dev/malo/if_malohal.h> 423c7e78d3SWeongyo Jeong #include <dev/malo/if_maloioctl.h> 433c7e78d3SWeongyo Jeong 443c7e78d3SWeongyo Jeong #ifndef MALO_TXBUF 453c7e78d3SWeongyo Jeong #define MALO_TXBUF 256 /* number of TX descriptors/buffers */ 463c7e78d3SWeongyo Jeong #endif 473c7e78d3SWeongyo Jeong #ifndef MALO_RXBUF 483c7e78d3SWeongyo Jeong #define MALO_RXBUF 256 /* number of RX descriptors/buffers */ 493c7e78d3SWeongyo Jeong #endif 503c7e78d3SWeongyo Jeong 513c7e78d3SWeongyo Jeong #define MALO_TXDESC 1 /* max tx descriptors/segments */ 523c7e78d3SWeongyo Jeong 533c7e78d3SWeongyo Jeong #define MALO_RXSIZE PAGE_SIZE 543c7e78d3SWeongyo Jeong #define MALO_RSSI_DUMMY_MARKER 127 553c7e78d3SWeongyo Jeong #define MALO_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 563c7e78d3SWeongyo Jeong 573c7e78d3SWeongyo Jeong #define MALO_REG_INT_CODE 0x00000C14 583c7e78d3SWeongyo Jeong /* From host to ARM */ 593c7e78d3SWeongyo Jeong #define MALO_REG_H2A_INTERRUPT_EVENTS 0x00000C18 603c7e78d3SWeongyo Jeong 613c7e78d3SWeongyo Jeong /* bit definitions for MALO_REG_H2A_INTERRUPT_CAUSE */ 623c7e78d3SWeongyo Jeong #define MALO_H2ARIC_BIT_PPA_READY 0x00000001 633c7e78d3SWeongyo Jeong #define MALO_H2ARIC_BIT_DOOR_BELL 0x00000002 /* bit 1 */ 643c7e78d3SWeongyo Jeong #define MALO_H2ARIC_BIT_PS 0x00000004 653c7e78d3SWeongyo Jeong #define MALO_H2ARIC_BIT_PSPOLL 0x00000008 /* bit 3 */ 663c7e78d3SWeongyo Jeong 673c7e78d3SWeongyo Jeong /* From ARM to host */ 683c7e78d3SWeongyo Jeong #define MALO_REG_A2H_INTERRUPT_CAUSE 0x00000C30 693c7e78d3SWeongyo Jeong #define MALO_REG_A2H_INTERRUPT_MASK 0x00000C34 703c7e78d3SWeongyo Jeong #define MALO_REG_A2H_INTERRUPT_CLEAR_SEL 0x00000C38 713c7e78d3SWeongyo Jeong #define MALO_REG_A2H_INTERRUPT_STATUS_MASK 0x00000C3C 723c7e78d3SWeongyo Jeong 733c7e78d3SWeongyo Jeong /* bit definitions for MALO_REG_A2H_INTERRUPT_CAUSE */ 743c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_TX_DONE 0x00000001 /* bit 0 */ 753c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_RX_RDY 0x00000002 /* bit 1 */ 763c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_OPC_DONE 0x00000004 773c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_MAC_EVENT 0x00000008 783c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_RX_PROBLEM 0x00000010 793c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_RADIO_OFF 0x00000020 /* bit 5 */ 803c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_RADIO_ON 0x00000040 813c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_RADAR_DETECT 0x00000080 823c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_ICV_ERROR 0x00000100 833c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_MIC_ERROR 0x00000200 /* bit 9 */ 843c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_QUEUE_EMPTY 0x00000400 853c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_QUEUE_FULL 0x00000800 863c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_CHAN_SWITCH 0x00001000 873c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_TX_WATCHDOG 0x00002000 883c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_BA_WATCHDOG 0x00004000 893c7e78d3SWeongyo Jeong 903c7e78d3SWeongyo Jeong #define MALO_ISR_SRC_BITS \ 913c7e78d3SWeongyo Jeong (MALO_A2HRIC_BIT_RX_RDY | \ 923c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_TX_DONE | \ 933c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_OPC_DONE | \ 943c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_MAC_EVENT | \ 953c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_MIC_ERROR | \ 963c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_ICV_ERROR | \ 973c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_RADAR_DETECT | \ 983c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_CHAN_SWITCH | \ 993c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_TX_WATCHDOG | \ 1003c7e78d3SWeongyo Jeong MALO_A2HRIC_BIT_QUEUE_EMPTY) 1013c7e78d3SWeongyo Jeong #define MALO_ISR_RESET (1<<15) 1023c7e78d3SWeongyo Jeong 1033c7e78d3SWeongyo Jeong #define MALO_A2HRIC_BIT_MASK MALO_ISR_SRC_BITS 1043c7e78d3SWeongyo Jeong 1053c7e78d3SWeongyo Jeong /* map to 0x80000000 on BAR1 */ 1063c7e78d3SWeongyo Jeong #define MALO_REG_GEN_PTR 0x00000C10 1073c7e78d3SWeongyo Jeong #define MALO_REG_INT_CODE 0x00000C14 1083c7e78d3SWeongyo Jeong #define MALO_REG_SCRATCH 0x00000C40 1093c7e78d3SWeongyo Jeong 1103c7e78d3SWeongyo Jeong /* 1113c7e78d3SWeongyo Jeong * define OpMode for SoftAP/Station mode 1123c7e78d3SWeongyo Jeong * 1133c7e78d3SWeongyo Jeong * the following mode signature has to be written to PCI scratch register#0 1143c7e78d3SWeongyo Jeong * right after successfully downloading the last block of firmware and 1153c7e78d3SWeongyo Jeong * before waiting for firmware ready signature 1163c7e78d3SWeongyo Jeong */ 1173c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_STA_MODE 0x5A 1183c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_STA_FWRDY_SIGNATURE 0xF0F1F2F4 1193c7e78d3SWeongyo Jeong 1203c7e78d3SWeongyo Jeong /* 1213c7e78d3SWeongyo Jeong * 16 bit host command code 1223c7e78d3SWeongyo Jeong */ 1233c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_NONE 0x0000 1243c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_CODE_DNLD 0x0001 1253c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_GET_HW_SPEC 0x0003 1263c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_HW_SPEC 0x0004 1273c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_MAC_MULTICAST_ADR 0x0010 1283c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_WEPKEY 0x0013 1293c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_802_11_RADIO_CONTROL 0x001c 1303c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_802_11_RF_TX_POWER 0x001e 1313c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_802_11_RF_ANTENNA 0x0020 1323c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_PRE_SCAN 0x0107 1333c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_POST_SCAN 0x0108 1343c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_RF_CHANNEL 0x010a 1353c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_AID 0x010d 1363c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_RATE 0x0110 1373c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_SLOT 0x0114 1383c7e78d3SWeongyo Jeong /* define DFS lab commands */ 1393c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_FIXED_RATE 0x0126 1403c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_SET_REGION_POWER 0x0128 1413c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_GET_CALTABLE 0x1134 1423c7e78d3SWeongyo Jeong 1433c7e78d3SWeongyo Jeong /* 1443c7e78d3SWeongyo Jeong * definition of action or option for each command. 1453c7e78d3SWeongyo Jeong */ 1463c7e78d3SWeongyo Jeong /* define general purpose action */ 1473c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_ACT_GEN_GET 0x0000 1483c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_ACT_GEN_SET 0x0001 1493c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_ACT_GEN_SET_LIST 0x0002 1503c7e78d3SWeongyo Jeong 1513c7e78d3SWeongyo Jeong /* define action or option for HostCmd_FW_USE_FIXED_RATE */ 1523c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_ACT_USE_FIXED_RATE 0x0001 1533c7e78d3SWeongyo Jeong #define MALO_HOSTCMD_ACT_NOT_USE_FIXED_RATE 0x0002 1543c7e78d3SWeongyo Jeong 1553c7e78d3SWeongyo Jeong /* INT code register event definition */ 1563c7e78d3SWeongyo Jeong #define MALO_INT_CODE_CMD_FINISHED 0x00000005 1573c7e78d3SWeongyo Jeong 1583c7e78d3SWeongyo Jeong struct malo_cmd_header { 1593c7e78d3SWeongyo Jeong uint16_t cmd; 1603c7e78d3SWeongyo Jeong uint16_t length; 1613c7e78d3SWeongyo Jeong uint16_t seqnum; 1623c7e78d3SWeongyo Jeong uint16_t result; 1633c7e78d3SWeongyo Jeong } __packed; 1643c7e78d3SWeongyo Jeong 1653c7e78d3SWeongyo Jeong struct malo_cmd_caltable { 1663c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 1673c7e78d3SWeongyo Jeong uint8_t annex; 1683c7e78d3SWeongyo Jeong uint8_t index; 1693c7e78d3SWeongyo Jeong uint8_t len; 1703c7e78d3SWeongyo Jeong uint8_t reserverd; 1713c7e78d3SWeongyo Jeong #define MALO_CAL_TBL_SIZE 160 1723c7e78d3SWeongyo Jeong uint8_t caltbl[MALO_CAL_TBL_SIZE]; 1733c7e78d3SWeongyo Jeong } __packed; 1743c7e78d3SWeongyo Jeong 1753c7e78d3SWeongyo Jeong struct malo_cmd_get_hwspec { 1763c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 1773c7e78d3SWeongyo Jeong u_int8_t version; /* version of the HW */ 1783c7e78d3SWeongyo Jeong u_int8_t hostif; /* host interface */ 1793c7e78d3SWeongyo Jeong /* Max. number of WCB FW can handle */ 1803c7e78d3SWeongyo Jeong u_int16_t num_wcb; 1813c7e78d3SWeongyo Jeong /* MaxNbr of MC addresses FW can handle */ 1823c7e78d3SWeongyo Jeong u_int16_t num_mcastaddr; 1833c7e78d3SWeongyo Jeong /* MAC address programmed in HW */ 1843c7e78d3SWeongyo Jeong u_int8_t permaddr[6]; 1853c7e78d3SWeongyo Jeong u_int16_t regioncode; 1863c7e78d3SWeongyo Jeong /* Number of antenna used */ 1873c7e78d3SWeongyo Jeong u_int16_t num_antenna; 1883c7e78d3SWeongyo Jeong /* 4 byte of FW release number */ 1893c7e78d3SWeongyo Jeong u_int32_t fw_releasenum; 1903c7e78d3SWeongyo Jeong u_int32_t wcbbase0; 1913c7e78d3SWeongyo Jeong u_int32_t rxpdwr_ptr; 1923c7e78d3SWeongyo Jeong u_int32_t rxpdrd_ptr; 1933c7e78d3SWeongyo Jeong u_int32_t ul_fw_awakecookie; 1943c7e78d3SWeongyo Jeong u_int32_t wcbbase1; 1953c7e78d3SWeongyo Jeong u_int32_t wcbbase2; 1963c7e78d3SWeongyo Jeong u_int32_t wcbbase3; 1973c7e78d3SWeongyo Jeong } __packed; 1983c7e78d3SWeongyo Jeong 1993c7e78d3SWeongyo Jeong struct malo_cmd_set_hwspec { 2003c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 2013c7e78d3SWeongyo Jeong uint8_t version; /* HW revision */ 2023c7e78d3SWeongyo Jeong uint8_t hostif; /* Host interface */ 2033c7e78d3SWeongyo Jeong /* Max. number of Multicast address FW can handle */ 2043c7e78d3SWeongyo Jeong uint16_t num_mcastaddr; 2053c7e78d3SWeongyo Jeong uint8_t permaddr[6]; /* MAC address */ 2063c7e78d3SWeongyo Jeong uint16_t regioncode; /* Region Code */ 2073c7e78d3SWeongyo Jeong /* 4 byte of FW release number */ 2083c7e78d3SWeongyo Jeong uint32_t fwreleasenum; 2093c7e78d3SWeongyo Jeong /* Firmware awake cookie */ 2103c7e78d3SWeongyo Jeong uint32_t ul_fw_awakecookie; 2113c7e78d3SWeongyo Jeong /* Device capabilities (see above) */ 2123c7e78d3SWeongyo Jeong uint32_t devicecaps; 2133c7e78d3SWeongyo Jeong uint32_t rxpdwrptr; /* Rx shared memory queue */ 2143c7e78d3SWeongyo Jeong /* # TX queues in WcbBase array */ 2153c7e78d3SWeongyo Jeong uint32_t num_txqueues; 2163c7e78d3SWeongyo Jeong /* TX WCB Rings */ 2173c7e78d3SWeongyo Jeong uint32_t wcbbase[MALO_MAX_TXWCB_QUEUES]; 2183c7e78d3SWeongyo Jeong uint32_t flags; 2193c7e78d3SWeongyo Jeong uint32_t txwcbnum_per_queue; 2203c7e78d3SWeongyo Jeong uint32_t total_rxwcb; 2213c7e78d3SWeongyo Jeong } __packed; 2223c7e78d3SWeongyo Jeong 2233c7e78d3SWeongyo Jeong /* DS 802.11 */ 2243c7e78d3SWeongyo Jeong struct malo_cmd_rf_antenna { 2253c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 2263c7e78d3SWeongyo Jeong uint16_t action; 2273c7e78d3SWeongyo Jeong /* Number of antennas or 0xffff (diversity) */ 2283c7e78d3SWeongyo Jeong uint16_t mode; 2293c7e78d3SWeongyo Jeong } __packed; 2303c7e78d3SWeongyo Jeong 2313c7e78d3SWeongyo Jeong struct malo_cmd_radio_control { 2323c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 2333c7e78d3SWeongyo Jeong uint16_t action; 2343c7e78d3SWeongyo Jeong /* 2353c7e78d3SWeongyo Jeong * bit 0 : 1 = on, 0 = off 2363c7e78d3SWeongyo Jeong * bit 1 : 1 = long, 0 = short 2373c7e78d3SWeongyo Jeong * bit 2 : 1 = auto, 0 = fix 2383c7e78d3SWeongyo Jeong */ 2393c7e78d3SWeongyo Jeong uint16_t control; 2403c7e78d3SWeongyo Jeong uint16_t radio_on; 2413c7e78d3SWeongyo Jeong } __packed; 2423c7e78d3SWeongyo Jeong 2433c7e78d3SWeongyo Jeong struct malo_cmd_fw_set_wmmmode { 2443c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 2453c7e78d3SWeongyo Jeong uint16_t action; /* 0 -> unset, 1 -> set */ 2463c7e78d3SWeongyo Jeong } __packed; 2473c7e78d3SWeongyo Jeong 2483c7e78d3SWeongyo Jeong struct malo_cmd_fw_set_rf_channel { 2493c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 2503c7e78d3SWeongyo Jeong uint16_t action; 2513c7e78d3SWeongyo Jeong uint8_t cur_channel; /* channel # */ 2523c7e78d3SWeongyo Jeong } __packed; 2533c7e78d3SWeongyo Jeong 2543c7e78d3SWeongyo Jeong #define MALO_TX_POWER_LEVEL_TOTAL 8 2553c7e78d3SWeongyo Jeong struct malo_cmd_rf_tx_power { 2563c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 2573c7e78d3SWeongyo Jeong uint16_t action; 2583c7e78d3SWeongyo Jeong uint16_t support_txpower_level; 2593c7e78d3SWeongyo Jeong uint16_t current_txpower_level; 2603c7e78d3SWeongyo Jeong uint16_t reserved; 2613c7e78d3SWeongyo Jeong uint16_t power_levellist[MALO_TX_POWER_LEVEL_TOTAL]; 2623c7e78d3SWeongyo Jeong } __packed; 2633c7e78d3SWeongyo Jeong 2643c7e78d3SWeongyo Jeong struct malo_fixrate_flag { 2653c7e78d3SWeongyo Jeong /* lower rate after the retry count. 0 = legacy, 1 = HT */ 2663c7e78d3SWeongyo Jeong uint32_t type; 2673c7e78d3SWeongyo Jeong /* 0: retry count is not valid, 1: use retry count specified */ 2683c7e78d3SWeongyo Jeong uint32_t retrycount_valid; 2693c7e78d3SWeongyo Jeong } __packed; 2703c7e78d3SWeongyo Jeong 2713c7e78d3SWeongyo Jeong struct malo_fixed_rate_entry { 2723c7e78d3SWeongyo Jeong struct malo_fixrate_flag typeflags; 2733c7e78d3SWeongyo Jeong /* legacy rate(not index) or an MCS code. */ 2743c7e78d3SWeongyo Jeong uint32_t fixedrate; 2753c7e78d3SWeongyo Jeong uint32_t retrycount; 2763c7e78d3SWeongyo Jeong } __packed; 2773c7e78d3SWeongyo Jeong 2783c7e78d3SWeongyo Jeong struct malo_cmd_fw_use_fixed_rate { 2793c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 2803c7e78d3SWeongyo Jeong /* 2813c7e78d3SWeongyo Jeong * MALO_HOSTCMD_ACT_GEN_GET 0x0000 2823c7e78d3SWeongyo Jeong * MALO_HOSTCMD_ACT_GEN_SET 0x0001 2833c7e78d3SWeongyo Jeong * MALO_HOSTCMD_ACT_NOT_USE_FIXED_RATE 0x0002 2843c7e78d3SWeongyo Jeong */ 2853c7e78d3SWeongyo Jeong uint32_t action; 2863c7e78d3SWeongyo Jeong /* use fixed rate specified but firmware can drop to */ 2873c7e78d3SWeongyo Jeong uint32_t allowratedrop; 2883c7e78d3SWeongyo Jeong uint32_t entrycount; 2893c7e78d3SWeongyo Jeong struct malo_fixed_rate_entry fixedrate_table[4]; 2903c7e78d3SWeongyo Jeong uint8_t multicast_rate; 2913c7e78d3SWeongyo Jeong uint8_t multirate_txtype; 2923c7e78d3SWeongyo Jeong uint8_t management_rate; 2933c7e78d3SWeongyo Jeong } __packed; 2943c7e78d3SWeongyo Jeong 2953c7e78d3SWeongyo Jeong #define MALO_RATE_INDEX_MAX_ARRAY 14 2963c7e78d3SWeongyo Jeong 2973c7e78d3SWeongyo Jeong struct malo_cmd_fw_set_aid { 2983c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 2993c7e78d3SWeongyo Jeong uint16_t associd; 3003c7e78d3SWeongyo Jeong uint8_t macaddr[6]; /* AP's Mac Address(BSSID) */ 3013c7e78d3SWeongyo Jeong uint32_t gprotection; 3023c7e78d3SWeongyo Jeong uint8_t aprates[MALO_RATE_INDEX_MAX_ARRAY]; 3033c7e78d3SWeongyo Jeong } __packed; 3043c7e78d3SWeongyo Jeong 3053c7e78d3SWeongyo Jeong struct malo_cmd_prescan { 3063c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 3073c7e78d3SWeongyo Jeong } __packed; 3083c7e78d3SWeongyo Jeong 3093c7e78d3SWeongyo Jeong struct malo_cmd_postscan { 3103c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 3113c7e78d3SWeongyo Jeong uint32_t isibss; 3123c7e78d3SWeongyo Jeong uint8_t bssid[6]; 3133c7e78d3SWeongyo Jeong } __packed; 3143c7e78d3SWeongyo Jeong 3153c7e78d3SWeongyo Jeong struct malo_cmd_fw_setslot { 3163c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 3173c7e78d3SWeongyo Jeong uint16_t action; 3183c7e78d3SWeongyo Jeong /* slot = 0 if regular, slot = 1 if short. */ 3193c7e78d3SWeongyo Jeong uint8_t slot; 3203c7e78d3SWeongyo Jeong }; 3213c7e78d3SWeongyo Jeong 3223c7e78d3SWeongyo Jeong struct malo_cmd_set_rate { 3233c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 3243c7e78d3SWeongyo Jeong uint8_t dataratetype; 3253c7e78d3SWeongyo Jeong uint8_t rateindex; 3263c7e78d3SWeongyo Jeong uint8_t aprates[14]; 3273c7e78d3SWeongyo Jeong } __packed; 3283c7e78d3SWeongyo Jeong 3293c7e78d3SWeongyo Jeong struct malo_cmd_wepkey { 3303c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 3313c7e78d3SWeongyo Jeong uint16_t action; 3323c7e78d3SWeongyo Jeong uint8_t len; 3333c7e78d3SWeongyo Jeong uint8_t flags; 3343c7e78d3SWeongyo Jeong uint16_t index; 3353c7e78d3SWeongyo Jeong uint8_t value[IEEE80211_KEYBUF_SIZE]; 3363c7e78d3SWeongyo Jeong uint8_t txmickey[IEEE80211_WEP_MICLEN]; 3373c7e78d3SWeongyo Jeong uint8_t rxmickey[IEEE80211_WEP_MICLEN]; 3383c7e78d3SWeongyo Jeong uint64_t rxseqctr; 3393c7e78d3SWeongyo Jeong uint64_t txseqctr; 3403c7e78d3SWeongyo Jeong } __packed; 3413c7e78d3SWeongyo Jeong 3423c7e78d3SWeongyo Jeong struct malo_cmd_mcast { 3433c7e78d3SWeongyo Jeong struct malo_cmd_header cmdhdr; 3443c7e78d3SWeongyo Jeong uint16_t action; 3453c7e78d3SWeongyo Jeong uint16_t numaddr; 3463c7e78d3SWeongyo Jeong #define MALO_HAL_MCAST_MAX 32 3473c7e78d3SWeongyo Jeong uint8_t maclist[6*32]; 3483c7e78d3SWeongyo Jeong } __packed; 3493c7e78d3SWeongyo Jeong 3503c7e78d3SWeongyo Jeong /* 3513c7e78d3SWeongyo Jeong * DMA state for tx/rx descriptors. 3523c7e78d3SWeongyo Jeong */ 3533c7e78d3SWeongyo Jeong 3543c7e78d3SWeongyo Jeong /* 3553c7e78d3SWeongyo Jeong * Common "base class" for tx/rx descriptor resources 3563c7e78d3SWeongyo Jeong * allocated using the bus dma api. 3573c7e78d3SWeongyo Jeong */ 3583c7e78d3SWeongyo Jeong struct malo_descdma { 3593c7e78d3SWeongyo Jeong const char* dd_name; 3603c7e78d3SWeongyo Jeong void *dd_desc; /* descriptors */ 3613c7e78d3SWeongyo Jeong bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 3623c7e78d3SWeongyo Jeong bus_size_t dd_desc_len; /* size of dd_desc */ 3633c7e78d3SWeongyo Jeong bus_dma_segment_t dd_dseg; 3643c7e78d3SWeongyo Jeong int dd_dnseg; /* number of segments */ 3653c7e78d3SWeongyo Jeong bus_dma_tag_t dd_dmat; /* bus DMA tag */ 3663c7e78d3SWeongyo Jeong bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 3673c7e78d3SWeongyo Jeong void *dd_bufptr; /* associated buffers */ 3683c7e78d3SWeongyo Jeong }; 3693c7e78d3SWeongyo Jeong 3703c7e78d3SWeongyo Jeong /* 3713c7e78d3SWeongyo Jeong * Hardware tx/rx descriptors. 3723c7e78d3SWeongyo Jeong * 3733c7e78d3SWeongyo Jeong * NB: tx descriptor size must match f/w expected size 3743c7e78d3SWeongyo Jeong * because f/w prefetch's the next descriptor linearly 3753c7e78d3SWeongyo Jeong * and doesn't chase the next pointer. 3763c7e78d3SWeongyo Jeong */ 3773c7e78d3SWeongyo Jeong struct malo_txdesc { 3783c7e78d3SWeongyo Jeong uint32_t status; 3793c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_IDLE 0x00000000 3803c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_USED 0x00000001 3813c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_OK 0x00000001 3823c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_OK_RETRY 0x00000002 3833c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_OK_MORE_RETRY 0x00000004 3843c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_MULTICAST_TX 0x00000008 3853c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_BROADCAST_TX 0x00000010 3863c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_FAILED_LINK_ERROR 0x00000020 3873c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040 3883c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_FAILED_XRETRY MALO_TXD_STATUS_FAILED_EXCEED_LIMIT 3893c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_FAILED_AGING 0x00000080 3903c7e78d3SWeongyo Jeong #define MALO_TXD_STATUS_FW_OWNED 0x80000000 3913c7e78d3SWeongyo Jeong uint8_t datarate; 3923c7e78d3SWeongyo Jeong uint8_t txpriority; 3933c7e78d3SWeongyo Jeong uint16_t qosctrl; 3943c7e78d3SWeongyo Jeong uint32_t pktptr; 3953c7e78d3SWeongyo Jeong uint16_t pktlen; 3963c7e78d3SWeongyo Jeong uint8_t destaddr[6]; 3973c7e78d3SWeongyo Jeong uint32_t physnext; 3983c7e78d3SWeongyo Jeong uint32_t sap_pktinfo; 3993c7e78d3SWeongyo Jeong uint16_t format; 4003c7e78d3SWeongyo Jeong #define MALO_TXD_FORMAT 0x0001 /* frame format/rate */ 4013c7e78d3SWeongyo Jeong #define MALO_TXD_FORMAT_LEGACY 0x0000 /* legacy rate frame */ 4023c7e78d3SWeongyo Jeong #define MALO_TXD_RATE 0x01f8 /* tx rate (legacy)/ MCS */ 4033c7e78d3SWeongyo Jeong #define MALO_TXD_RATE_S 3 4043c7e78d3SWeongyo Jeong /* NB: 3 is reserved */ 4053c7e78d3SWeongyo Jeong #define MALO_TXD_ANTENNA 0x1800 /* antenna select */ 4063c7e78d3SWeongyo Jeong #define MALO_TXD_ANTENNA_S 11 4073c7e78d3SWeongyo Jeong uint16_t pad; /* align to 4-byte boundary */ 4083c7e78d3SWeongyo Jeong } __packed; 4093c7e78d3SWeongyo Jeong 4103c7e78d3SWeongyo Jeong #define MALO_TXDESC_SYNC(txq, ds, how) do { \ 4113c7e78d3SWeongyo Jeong bus_dmamap_sync((txq)->dma.dd_dmat, (txq)->dma.dd_dmamap, how); \ 4123c7e78d3SWeongyo Jeong } while(0) 4133c7e78d3SWeongyo Jeong 4143c7e78d3SWeongyo Jeong struct malo_rxdesc { 4153c7e78d3SWeongyo Jeong uint8_t rxcontrol; /* control element */ 4163c7e78d3SWeongyo Jeong #define MALO_RXD_CTRL_DRIVER_OWN 0x00 4173c7e78d3SWeongyo Jeong #define MALO_RXD_CTRL_OS_OWN 0x04 4183c7e78d3SWeongyo Jeong #define MALO_RXD_CTRL_DMA_OWN 0x80 4193c7e78d3SWeongyo Jeong uint8_t snr; /* signal to noise ratio */ 4203c7e78d3SWeongyo Jeong uint8_t status; /* status field w/ USED bit */ 4213c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_IDLE 0x00 4223c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_OK 0x01 4233c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_MULTICAST_RX 0x02 4243c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_BROADCAST_RX 0x04 4253c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_FRAGMENT_RX 0x08 4263c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_GENERAL_DECRYPT_ERR 0xff 4273c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_DECRYPT_ERR_MASK 0x80 4283c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_TKIP_MIC_DECRYPT_ERR 0x02 4293c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_WEP_ICV_DECRYPT_ERR 0x04 4303c7e78d3SWeongyo Jeong #define MALO_RXD_STATUS_TKIP_ICV_DECRYPT_ERR 0x08 4313c7e78d3SWeongyo Jeong uint8_t channel; /* channel # pkt received on */ 4323c7e78d3SWeongyo Jeong uint16_t pktlen; /* total length of received data */ 4333c7e78d3SWeongyo Jeong uint8_t nf; /* noise floor */ 4343c7e78d3SWeongyo Jeong uint8_t rate; /* received data rate */ 4353c7e78d3SWeongyo Jeong uint32_t physbuffdata; /* physical address of payload data */ 4363c7e78d3SWeongyo Jeong uint32_t physnext; /* physical address of next RX desc */ 4373c7e78d3SWeongyo Jeong uint16_t qosctrl; /* received QosCtrl field variable */ 4383c7e78d3SWeongyo Jeong uint16_t htsig2; /* like name states */ 4393c7e78d3SWeongyo Jeong } __packed; 4403c7e78d3SWeongyo Jeong 4413c7e78d3SWeongyo Jeong #define MALO_RXDESC_SYNC(sc, ds, how) do { \ 4423c7e78d3SWeongyo Jeong bus_dmamap_sync((sc)->malo_rxdma.dd_dmat, \ 4433c7e78d3SWeongyo Jeong (sc)->malo_rxdma.dd_dmamap, how); \ 4443c7e78d3SWeongyo Jeong } while (0) 4453c7e78d3SWeongyo Jeong 4463c7e78d3SWeongyo Jeong struct malo_rxbuf { 4473c7e78d3SWeongyo Jeong STAILQ_ENTRY(malo_rxbuf) bf_list; 4483c7e78d3SWeongyo Jeong void *bf_desc; /* h/w descriptor */ 4493c7e78d3SWeongyo Jeong bus_addr_t bf_daddr; /* physical addr of desc */ 4503c7e78d3SWeongyo Jeong bus_dmamap_t bf_dmamap; 4513c7e78d3SWeongyo Jeong bus_addr_t bf_data; /* physical addr of rx data */ 4523c7e78d3SWeongyo Jeong struct mbuf *bf_m; /* jumbo mbuf */ 4533c7e78d3SWeongyo Jeong }; 4543c7e78d3SWeongyo Jeong typedef STAILQ_HEAD(, malo_rxbuf) malo_rxbufhead; 4553c7e78d3SWeongyo Jeong 4563c7e78d3SWeongyo Jeong /* 4573c7e78d3SWeongyo Jeong * Software backed version of tx/rx descriptors. We keep 4583c7e78d3SWeongyo Jeong * the software state out of the h/w descriptor structure 4593c7e78d3SWeongyo Jeong * so that may be allocated in uncached memory w/o paying 4603c7e78d3SWeongyo Jeong * performance hit. 4613c7e78d3SWeongyo Jeong */ 4623c7e78d3SWeongyo Jeong struct malo_txbuf { 4633c7e78d3SWeongyo Jeong STAILQ_ENTRY(malo_txbuf) bf_list; 4643c7e78d3SWeongyo Jeong void *bf_desc; /* h/w descriptor */ 4653c7e78d3SWeongyo Jeong bus_addr_t bf_daddr; /* physical addr of desc */ 4663c7e78d3SWeongyo Jeong bus_dmamap_t bf_dmamap; /* DMA map for descriptors */ 4673c7e78d3SWeongyo Jeong int bf_nseg; 4683c7e78d3SWeongyo Jeong bus_dma_segment_t bf_segs[MALO_TXDESC]; 4693c7e78d3SWeongyo Jeong struct mbuf *bf_m; 4703c7e78d3SWeongyo Jeong struct ieee80211_node *bf_node; 4713c7e78d3SWeongyo Jeong struct malo_txq *bf_txq; /* backpointer to tx q/ring */ 4723c7e78d3SWeongyo Jeong }; 4733c7e78d3SWeongyo Jeong typedef STAILQ_HEAD(, malo_txbuf) malo_txbufhead; 4743c7e78d3SWeongyo Jeong 4753c7e78d3SWeongyo Jeong /* 4763c7e78d3SWeongyo Jeong * TX/RX ring definitions. There are 4 tx rings, one 4773c7e78d3SWeongyo Jeong * per AC, and 1 rx ring. Note carefully that transmit 4783c7e78d3SWeongyo Jeong * descriptors are treated as a contiguous chunk and the 4793c7e78d3SWeongyo Jeong * firmware pre-fetches descriptors. This means that we 4803c7e78d3SWeongyo Jeong * must preserve order when moving descriptors between 4813c7e78d3SWeongyo Jeong * the active+free lists; otherwise we may stall transmit. 4823c7e78d3SWeongyo Jeong */ 4833c7e78d3SWeongyo Jeong struct malo_txq { 4843c7e78d3SWeongyo Jeong struct malo_descdma dma; /* bus dma resources */ 4853c7e78d3SWeongyo Jeong struct mtx lock; /* tx q lock */ 4863c7e78d3SWeongyo Jeong char name[12]; /* e.g. "malo0_txq4" */ 4873c7e78d3SWeongyo Jeong int qnum; /* f/w q number */ 4883c7e78d3SWeongyo Jeong int txpri; /* f/w tx priority */ 4893c7e78d3SWeongyo Jeong int nfree; /* # buffers on free list */ 4903c7e78d3SWeongyo Jeong malo_txbufhead free; /* queue of free buffers */ 4913c7e78d3SWeongyo Jeong malo_txbufhead active; /* queue of active buffers */ 4923c7e78d3SWeongyo Jeong }; 4933c7e78d3SWeongyo Jeong 4943c7e78d3SWeongyo Jeong #define MALO_TXQ_LOCK_INIT(_sc, _tq) do { \ 4953c7e78d3SWeongyo Jeong snprintf((_tq)->name, sizeof((_tq)->name), "%s_txq%u", \ 4963c7e78d3SWeongyo Jeong device_get_nameunit((_sc)->malo_dev), (_tq)->qnum); \ 4973c7e78d3SWeongyo Jeong mtx_init(&(_tq)->lock, (_tq)->name, NULL, MTX_DEF); \ 4983c7e78d3SWeongyo Jeong } while (0) 4993c7e78d3SWeongyo Jeong #define MALO_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->lock) 5003c7e78d3SWeongyo Jeong #define MALO_TXQ_LOCK(_tq) mtx_lock(&(_tq)->lock) 5013c7e78d3SWeongyo Jeong #define MALO_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->lock) 5023c7e78d3SWeongyo Jeong #define MALO_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->lock, MA_OWNED) 5033c7e78d3SWeongyo Jeong 5043c7e78d3SWeongyo Jeong /* 5053c7e78d3SWeongyo Jeong * Each packet has fixed front matter: a 2-byte length 5063c7e78d3SWeongyo Jeong * of the payload, followed by a 4-address 802.11 header 5073c7e78d3SWeongyo Jeong * (regardless of the actual header and always w/o any 5083c7e78d3SWeongyo Jeong * QoS header). The payload then follows. 5093c7e78d3SWeongyo Jeong */ 5103c7e78d3SWeongyo Jeong struct malo_txrec { 5113c7e78d3SWeongyo Jeong uint16_t fwlen; 5123c7e78d3SWeongyo Jeong struct ieee80211_frame_addr4 wh; 5133c7e78d3SWeongyo Jeong } __packed; 5143c7e78d3SWeongyo Jeong 515b032f27cSSam Leffler struct malo_vap { 516b032f27cSSam Leffler struct ieee80211vap malo_vap; 517b032f27cSSam Leffler int (*malo_newstate)(struct ieee80211vap *, 518b032f27cSSam Leffler enum ieee80211_state, int); 519b032f27cSSam Leffler }; 520b032f27cSSam Leffler #define MALO_VAP(vap) ((struct malo_vap *)(vap)) 521b032f27cSSam Leffler 5223c7e78d3SWeongyo Jeong struct malo_softc { 5237a79cebfSGleb Smirnoff struct ieee80211com malo_ic; 5247a79cebfSGleb Smirnoff struct mbufq malo_snd; 5253c7e78d3SWeongyo Jeong device_t malo_dev; 5263c7e78d3SWeongyo Jeong struct mtx malo_mtx; /* master lock (recursive) */ 5273c7e78d3SWeongyo Jeong struct taskqueue *malo_tq; /* private task queue */ 5283c7e78d3SWeongyo Jeong 5293c7e78d3SWeongyo Jeong bus_dma_tag_t malo_dmat; /* bus DMA tag */ 5303c7e78d3SWeongyo Jeong bus_space_handle_t malo_io0h; /* BAR 0 */ 5313c7e78d3SWeongyo Jeong bus_space_tag_t malo_io0t; 5323c7e78d3SWeongyo Jeong bus_space_handle_t malo_io1h; /* BAR 1 */ 5333c7e78d3SWeongyo Jeong bus_space_tag_t malo_io1t; 5343c7e78d3SWeongyo Jeong 5353c7e78d3SWeongyo Jeong unsigned int malo_invalid: 1,/* disable hardware accesses */ 5363c7e78d3SWeongyo Jeong malo_recvsetup: 1, /* recv setup */ 5377a79cebfSGleb Smirnoff malo_fixedrate: 1, /* use fixed tx rate */ 5387a79cebfSGleb Smirnoff malo_running: 1; 5393c7e78d3SWeongyo Jeong 5403c7e78d3SWeongyo Jeong struct malo_hal *malo_mh; /* h/w access layer */ 5413c7e78d3SWeongyo Jeong struct malo_hal_hwspec malo_hwspecs; /* h/w capabilities */ 5423c7e78d3SWeongyo Jeong struct malo_hal_txrxdma malo_hwdma; /* h/w dma setup */ 5433c7e78d3SWeongyo Jeong uint32_t malo_imask; /* interrupt mask copy */ 5443c7e78d3SWeongyo Jeong struct malo_hal_channel malo_curchan; 5453c7e78d3SWeongyo Jeong u_int16_t malo_rxantenna; /* rx antenna */ 5463c7e78d3SWeongyo Jeong u_int16_t malo_txantenna; /* tx antenna */ 5473c7e78d3SWeongyo Jeong 5483c7e78d3SWeongyo Jeong struct malo_descdma malo_rxdma; /* rx bus dma resources */ 5493c7e78d3SWeongyo Jeong malo_rxbufhead malo_rxbuf; /* rx buffers */ 5503c7e78d3SWeongyo Jeong struct malo_rxbuf *malo_rxnext; /* next rx buffer to process */ 5513c7e78d3SWeongyo Jeong struct task malo_rxtask; /* rx int processing */ 5523c7e78d3SWeongyo Jeong 5533c7e78d3SWeongyo Jeong struct malo_txq malo_txq[MALO_NUM_TX_QUEUES]; 5543c7e78d3SWeongyo Jeong struct task malo_txtask; /* tx int processing */ 5557cf545d0SJohn Baldwin struct callout malo_watchdog_timer; 5567cf545d0SJohn Baldwin int malo_timer; 5573c7e78d3SWeongyo Jeong 5583c7e78d3SWeongyo Jeong struct malo_tx_radiotap_header malo_tx_th; 5593c7e78d3SWeongyo Jeong struct malo_rx_radiotap_header malo_rx_th; 5603c7e78d3SWeongyo Jeong 5613c7e78d3SWeongyo Jeong struct malo_stats malo_stats; /* interface statistics */ 5623c7e78d3SWeongyo Jeong int malo_debug; 5633c7e78d3SWeongyo Jeong }; 5643c7e78d3SWeongyo Jeong 5653c7e78d3SWeongyo Jeong #define MALO_LOCK_INIT(_sc) \ 5663c7e78d3SWeongyo Jeong mtx_init(&(_sc)->malo_mtx, device_get_nameunit((_sc)->malo_dev), \ 5673c7e78d3SWeongyo Jeong NULL, MTX_DEF | MTX_RECURSE) 5683c7e78d3SWeongyo Jeong #define MALO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->malo_mtx) 5693c7e78d3SWeongyo Jeong #define MALO_LOCK(_sc) mtx_lock(&(_sc)->malo_mtx) 5703c7e78d3SWeongyo Jeong #define MALO_UNLOCK(_sc) mtx_unlock(&(_sc)->malo_mtx) 5713c7e78d3SWeongyo Jeong #define MALO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->malo_mtx, MA_OWNED) 5723c7e78d3SWeongyo Jeong 5733c7e78d3SWeongyo Jeong #define MALO_RXFREE_INIT(_sc) \ 5743c7e78d3SWeongyo Jeong mtx_init(&(_sc)->malo_rxlock, device_get_nameunit((_sc)->malo_dev), \ 5753c7e78d3SWeongyo Jeong NULL, MTX_DEF) 5763c7e78d3SWeongyo Jeong #define MALO_RXFREE_DESTROY(_sc) mtx_destroy(&(_sc)->malo_rxlock) 5773c7e78d3SWeongyo Jeong #define MALO_RXFREE_LOCK(_sc) mtx_lock(&(_sc)->malo_rxlock) 5783c7e78d3SWeongyo Jeong #define MALO_RXFREE_UNLOCK(_sc) mtx_unlock(&(_sc)->malo_rxlock) 5793c7e78d3SWeongyo Jeong #define MALO_RXFREE_ASSERT(_sc) mtx_assert(&(_sc)->malo_rxlock, \ 5803c7e78d3SWeongyo Jeong MA_OWNED) 5813c7e78d3SWeongyo Jeong 5823c7e78d3SWeongyo Jeong int malo_attach(uint16_t, struct malo_softc *); 5833c7e78d3SWeongyo Jeong int malo_intr(void *); 5843c7e78d3SWeongyo Jeong int malo_detach(struct malo_softc *); 5853c7e78d3SWeongyo Jeong void malo_shutdown(struct malo_softc *); 5863c7e78d3SWeongyo Jeong void malo_suspend(struct malo_softc *); 5873c7e78d3SWeongyo Jeong void malo_resume(struct malo_softc *); 5883c7e78d3SWeongyo Jeong 5893c7e78d3SWeongyo Jeong #endif 590