1ce110ea1SWei Hu /*- 2ce110ea1SWei Hu * SPDX-License-Identifier: BSD-2-Clause 3ce110ea1SWei Hu * 4ce110ea1SWei Hu * Copyright (c) 2021 Microsoft Corp. 5ce110ea1SWei Hu * All rights reserved. 6ce110ea1SWei Hu * 7ce110ea1SWei Hu * Redistribution and use in source and binary forms, with or without 8ce110ea1SWei Hu * modification, are permitted provided that the following conditions 9ce110ea1SWei Hu * are met: 10ce110ea1SWei Hu * 11ce110ea1SWei Hu * 1. Redistributions of source code must retain the above copyright 12ce110ea1SWei Hu * notice, this list of conditions and the following disclaimer. 13ce110ea1SWei Hu * 14ce110ea1SWei Hu * 2. Redistributions in binary form must reproduce the above copyright 15ce110ea1SWei Hu * notice, this list of conditions and the following disclaimer in the 16ce110ea1SWei Hu * documentation and/or other materials provided with the distribution. 17ce110ea1SWei Hu * 18ce110ea1SWei Hu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19ce110ea1SWei Hu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20ce110ea1SWei Hu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21ce110ea1SWei Hu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22ce110ea1SWei Hu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23ce110ea1SWei Hu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24ce110ea1SWei Hu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25ce110ea1SWei Hu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26ce110ea1SWei Hu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27ce110ea1SWei Hu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28ce110ea1SWei Hu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29ce110ea1SWei Hu */ 30ce110ea1SWei Hu #include <sys/cdefs.h> 31ce110ea1SWei Hu #include <sys/param.h> 32ce110ea1SWei Hu #include <sys/systm.h> 33ce110ea1SWei Hu #include <sys/bus.h> 34ce110ea1SWei Hu #include <sys/kernel.h> 35ce110ea1SWei Hu #include <sys/kthread.h> 36ce110ea1SWei Hu #include <sys/malloc.h> 37ce110ea1SWei Hu #include <sys/mbuf.h> 38ce110ea1SWei Hu #include <sys/module.h> 39ce110ea1SWei Hu #include <sys/rman.h> 40ce110ea1SWei Hu #include <sys/smp.h> 41ce110ea1SWei Hu #include <sys/socket.h> 42ce110ea1SWei Hu #include <sys/sysctl.h> 43ce110ea1SWei Hu #include <sys/taskqueue.h> 44ce110ea1SWei Hu #include <sys/time.h> 45ce110ea1SWei Hu #include <sys/eventhandler.h> 46ce110ea1SWei Hu 47ce110ea1SWei Hu #include <machine/bus.h> 48ce110ea1SWei Hu #include <machine/resource.h> 49ce110ea1SWei Hu #include <machine/in_cksum.h> 50ce110ea1SWei Hu 51ce110ea1SWei Hu #include <net/if.h> 52ce110ea1SWei Hu #include <net/if_var.h> 53ce110ea1SWei Hu 54ce110ea1SWei Hu #include <dev/pci/pcivar.h> 55ce110ea1SWei Hu #include <dev/pci/pcireg.h> 56ce110ea1SWei Hu 57ce110ea1SWei Hu #include "gdma_util.h" 58ce110ea1SWei Hu #include "mana.h" 59ce110ea1SWei Hu 60ce110ea1SWei Hu 61ce110ea1SWei Hu static mana_vendor_id_t mana_id_table[] = { 62ce110ea1SWei Hu { PCI_VENDOR_ID_MICROSOFT, PCI_DEV_ID_MANA_VF}, 63ce110ea1SWei Hu /* Last entry */ 64ce110ea1SWei Hu { 0, 0} 65ce110ea1SWei Hu }; 66ce110ea1SWei Hu 67ce110ea1SWei Hu static inline uint32_t 68ce110ea1SWei Hu mana_gd_r32(struct gdma_context *g, uint64_t offset) 69ce110ea1SWei Hu { 70ce110ea1SWei Hu uint32_t v = bus_space_read_4(g->gd_bus.bar0_t, 71ce110ea1SWei Hu g->gd_bus.bar0_h, offset); 72ce110ea1SWei Hu rmb(); 73ce110ea1SWei Hu return (v); 74ce110ea1SWei Hu } 75ce110ea1SWei Hu 76ce110ea1SWei Hu #if defined(__amd64__) 77ce110ea1SWei Hu static inline uint64_t 78ce110ea1SWei Hu mana_gd_r64(struct gdma_context *g, uint64_t offset) 79ce110ea1SWei Hu { 80ce110ea1SWei Hu uint64_t v = bus_space_read_8(g->gd_bus.bar0_t, 81ce110ea1SWei Hu g->gd_bus.bar0_h, offset); 82ce110ea1SWei Hu rmb(); 83ce110ea1SWei Hu return (v); 84ce110ea1SWei Hu } 85ce110ea1SWei Hu #else 86ce110ea1SWei Hu static inline uint64_t 87ce110ea1SWei Hu mana_gd_r64(struct gdma_context *g, uint64_t offset) 88ce110ea1SWei Hu { 89ce110ea1SWei Hu uint64_t v; 90ce110ea1SWei Hu uint32_t *vp = (uint32_t *)&v; 91ce110ea1SWei Hu 92ce110ea1SWei Hu *vp = mana_gd_r32(g, offset); 93ce110ea1SWei Hu *(vp + 1) = mana_gd_r32(g, offset + 4); 94ce110ea1SWei Hu rmb(); 95ce110ea1SWei Hu return (v); 96ce110ea1SWei Hu } 97ce110ea1SWei Hu #endif 98ce110ea1SWei Hu 99ce110ea1SWei Hu static int 100ce110ea1SWei Hu mana_gd_query_max_resources(device_t dev) 101ce110ea1SWei Hu { 102ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 103ce110ea1SWei Hu struct gdma_query_max_resources_resp resp = {}; 104ce110ea1SWei Hu struct gdma_general_req req = {}; 105ce110ea1SWei Hu int err; 106ce110ea1SWei Hu 107ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 108ce110ea1SWei Hu sizeof(req), sizeof(resp)); 109ce110ea1SWei Hu 110ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 111ce110ea1SWei Hu if (err || resp.hdr.status) { 112ce110ea1SWei Hu device_printf(gc->dev, 113ce110ea1SWei Hu "Failed to query resource info: %d, 0x%x\n", 114ce110ea1SWei Hu err, resp.hdr.status); 115ce110ea1SWei Hu return err ? err : EPROTO; 116ce110ea1SWei Hu } 117ce110ea1SWei Hu 118ce110ea1SWei Hu mana_dbg(NULL, "max_msix %u, max_eq %u, max_cq %u, " 119ce110ea1SWei Hu "max_sq %u, max_rq %u\n", 120ce110ea1SWei Hu resp.max_msix, resp.max_eq, resp.max_cq, 121ce110ea1SWei Hu resp.max_sq, resp.max_rq); 122ce110ea1SWei Hu 123ce110ea1SWei Hu if (gc->num_msix_usable > resp.max_msix) 124ce110ea1SWei Hu gc->num_msix_usable = resp.max_msix; 125ce110ea1SWei Hu 126ce110ea1SWei Hu if (gc->num_msix_usable <= 1) 127ce110ea1SWei Hu return ENOSPC; 128ce110ea1SWei Hu 129ce110ea1SWei Hu gc->max_num_queues = mp_ncpus; 130ce110ea1SWei Hu if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 131ce110ea1SWei Hu gc->max_num_queues = MANA_MAX_NUM_QUEUES; 132ce110ea1SWei Hu 133ce110ea1SWei Hu if (gc->max_num_queues > resp.max_eq) 134ce110ea1SWei Hu gc->max_num_queues = resp.max_eq; 135ce110ea1SWei Hu 136ce110ea1SWei Hu if (gc->max_num_queues > resp.max_cq) 137ce110ea1SWei Hu gc->max_num_queues = resp.max_cq; 138ce110ea1SWei Hu 139ce110ea1SWei Hu if (gc->max_num_queues > resp.max_sq) 140ce110ea1SWei Hu gc->max_num_queues = resp.max_sq; 141ce110ea1SWei Hu 142ce110ea1SWei Hu if (gc->max_num_queues > resp.max_rq) 143ce110ea1SWei Hu gc->max_num_queues = resp.max_rq; 144ce110ea1SWei Hu 145ce110ea1SWei Hu return 0; 146ce110ea1SWei Hu } 147ce110ea1SWei Hu 148ce110ea1SWei Hu static int 149ce110ea1SWei Hu mana_gd_detect_devices(device_t dev) 150ce110ea1SWei Hu { 151ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 152ce110ea1SWei Hu struct gdma_list_devices_resp resp = {}; 153ce110ea1SWei Hu struct gdma_general_req req = {}; 154ce110ea1SWei Hu struct gdma_dev_id gd_dev; 155ce110ea1SWei Hu uint32_t i, max_num_devs; 156ce110ea1SWei Hu uint16_t dev_type; 157ce110ea1SWei Hu int err; 158ce110ea1SWei Hu 159ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 160ce110ea1SWei Hu sizeof(resp)); 161ce110ea1SWei Hu 162ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 163ce110ea1SWei Hu if (err || resp.hdr.status) { 164ce110ea1SWei Hu device_printf(gc->dev, 165ce110ea1SWei Hu "Failed to detect devices: %d, 0x%x\n", err, 166ce110ea1SWei Hu resp.hdr.status); 167ce110ea1SWei Hu return err ? err : EPROTO; 168ce110ea1SWei Hu } 169ce110ea1SWei Hu 170ce110ea1SWei Hu max_num_devs = min_t(uint32_t, MAX_NUM_GDMA_DEVICES, resp.num_of_devs); 171ce110ea1SWei Hu 172ce110ea1SWei Hu for (i = 0; i < max_num_devs; i++) { 173ce110ea1SWei Hu gd_dev = resp.devs[i]; 174ce110ea1SWei Hu dev_type = gd_dev.type; 175ce110ea1SWei Hu 176ce110ea1SWei Hu mana_dbg(NULL, "gdma dev %d, type %u\n", 177ce110ea1SWei Hu i, dev_type); 178ce110ea1SWei Hu 179ce110ea1SWei Hu /* HWC is already detected in mana_hwc_create_channel(). */ 180ce110ea1SWei Hu if (dev_type == GDMA_DEVICE_HWC) 181ce110ea1SWei Hu continue; 182ce110ea1SWei Hu 183ce110ea1SWei Hu if (dev_type == GDMA_DEVICE_MANA) { 184ce110ea1SWei Hu gc->mana.gdma_context = gc; 185ce110ea1SWei Hu gc->mana.dev_id = gd_dev; 186ce110ea1SWei Hu } 187ce110ea1SWei Hu } 188ce110ea1SWei Hu 189ce110ea1SWei Hu return gc->mana.dev_id.type == 0 ? ENODEV : 0; 190ce110ea1SWei Hu } 191ce110ea1SWei Hu 192ce110ea1SWei Hu int 193ce110ea1SWei Hu mana_gd_send_request(struct gdma_context *gc, uint32_t req_len, 194ce110ea1SWei Hu const void *req, uint32_t resp_len, void *resp) 195ce110ea1SWei Hu { 196ce110ea1SWei Hu struct hw_channel_context *hwc = gc->hwc.driver_data; 197ce110ea1SWei Hu 198ce110ea1SWei Hu return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 199ce110ea1SWei Hu } 200ce110ea1SWei Hu 201ce110ea1SWei Hu void 202ce110ea1SWei Hu mana_gd_dma_map_paddr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 203ce110ea1SWei Hu { 204ce110ea1SWei Hu bus_addr_t *paddr = arg; 205ce110ea1SWei Hu 206ce110ea1SWei Hu if (error) 207ce110ea1SWei Hu return; 208ce110ea1SWei Hu 209ce110ea1SWei Hu KASSERT(nseg == 1, ("too many segments %d!", nseg)); 210ce110ea1SWei Hu *paddr = segs->ds_addr; 211ce110ea1SWei Hu } 212ce110ea1SWei Hu 213ce110ea1SWei Hu int 214ce110ea1SWei Hu mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 215ce110ea1SWei Hu struct gdma_mem_info *gmi) 216ce110ea1SWei Hu { 217ce110ea1SWei Hu bus_addr_t dma_handle; 218ce110ea1SWei Hu void *buf; 219ce110ea1SWei Hu int err; 220ce110ea1SWei Hu 221ce110ea1SWei Hu if (!gc || !gmi) 222ce110ea1SWei Hu return EINVAL; 223ce110ea1SWei Hu 224ce110ea1SWei Hu if (length < PAGE_SIZE || (length != roundup_pow_of_two(length))) 225ce110ea1SWei Hu return EINVAL; 226ce110ea1SWei Hu 227ce110ea1SWei Hu err = bus_dma_tag_create(bus_get_dma_tag(gc->dev), /* parent */ 228ce110ea1SWei Hu PAGE_SIZE, 0, /* alignment, boundary */ 229ce110ea1SWei Hu BUS_SPACE_MAXADDR, /* lowaddr */ 230ce110ea1SWei Hu BUS_SPACE_MAXADDR, /* highaddr */ 231ce110ea1SWei Hu NULL, NULL, /* filter, filterarg */ 232ce110ea1SWei Hu length, /* maxsize */ 233ce110ea1SWei Hu 1, /* nsegments */ 234ce110ea1SWei Hu length, /* maxsegsize */ 235ce110ea1SWei Hu 0, /* flags */ 236ce110ea1SWei Hu NULL, NULL, /* lockfunc, lockfuncarg*/ 237ce110ea1SWei Hu &gmi->dma_tag); 238ce110ea1SWei Hu if (err) { 239ce110ea1SWei Hu device_printf(gc->dev, 240ce110ea1SWei Hu "failed to create dma tag, err: %d\n", err); 241ce110ea1SWei Hu return (err); 242ce110ea1SWei Hu } 243ce110ea1SWei Hu 244ce110ea1SWei Hu /* 245ce110ea1SWei Hu * Must have BUS_DMA_ZERO flag to clear the dma memory. 246ce110ea1SWei Hu * Otherwise the queue overflow detection mechanism does 247ce110ea1SWei Hu * not work. 248ce110ea1SWei Hu */ 249ce110ea1SWei Hu err = bus_dmamem_alloc(gmi->dma_tag, &buf, 250ce110ea1SWei Hu BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &gmi->dma_map); 251ce110ea1SWei Hu if (err) { 252ce110ea1SWei Hu device_printf(gc->dev, 253ce110ea1SWei Hu "failed to alloc dma mem, err: %d\n", err); 254ce110ea1SWei Hu bus_dma_tag_destroy(gmi->dma_tag); 255ce110ea1SWei Hu return (err); 256ce110ea1SWei Hu } 257ce110ea1SWei Hu 258ce110ea1SWei Hu err = bus_dmamap_load(gmi->dma_tag, gmi->dma_map, buf, 259ce110ea1SWei Hu length, mana_gd_dma_map_paddr, &dma_handle, BUS_DMA_NOWAIT); 260ce110ea1SWei Hu if (err) { 261ce110ea1SWei Hu device_printf(gc->dev, 262ce110ea1SWei Hu "failed to load dma mem, err: %d\n", err); 263ce110ea1SWei Hu bus_dmamem_free(gmi->dma_tag, buf, gmi->dma_map); 264ce110ea1SWei Hu bus_dma_tag_destroy(gmi->dma_tag); 265ce110ea1SWei Hu return (err); 266ce110ea1SWei Hu } 267ce110ea1SWei Hu 268ce110ea1SWei Hu gmi->dev = gc->dev; 269ce110ea1SWei Hu gmi->dma_handle = dma_handle; 270ce110ea1SWei Hu gmi->virt_addr = buf; 271ce110ea1SWei Hu gmi->length = length; 272ce110ea1SWei Hu 273ce110ea1SWei Hu return 0; 274ce110ea1SWei Hu } 275ce110ea1SWei Hu 276ce110ea1SWei Hu void 277ce110ea1SWei Hu mana_gd_free_memory(struct gdma_mem_info *gmi) 278ce110ea1SWei Hu { 279ce110ea1SWei Hu bus_dmamap_unload(gmi->dma_tag, gmi->dma_map); 280ce110ea1SWei Hu bus_dmamem_free(gmi->dma_tag, gmi->virt_addr, gmi->dma_map); 281ce110ea1SWei Hu bus_dma_tag_destroy(gmi->dma_tag); 282ce110ea1SWei Hu } 283ce110ea1SWei Hu 284b685df31SWei Hu int 285b685df31SWei Hu mana_gd_destroy_doorbell_page(struct gdma_context *gc, int doorbell_page) 286b685df31SWei Hu { 287b685df31SWei Hu struct gdma_destroy_resource_range_req req = {}; 288b685df31SWei Hu struct gdma_resp_hdr resp = {}; 289b685df31SWei Hu int err; 290b685df31SWei Hu 291b685df31SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_RESOURCE_RANGE, 292b685df31SWei Hu sizeof(req), sizeof(resp)); 293b685df31SWei Hu 294b685df31SWei Hu req.resource_type = GDMA_RESOURCE_DOORBELL_PAGE; 295b685df31SWei Hu req.num_resources = 1; 296b685df31SWei Hu req.allocated_resources = doorbell_page; 297b685df31SWei Hu 298b685df31SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 299b685df31SWei Hu if (err || resp.status) { 300b685df31SWei Hu device_printf(gc->dev, 301b685df31SWei Hu "Failed to destroy doorbell page: ret %d, 0x%x\n", 302b685df31SWei Hu err, resp.status); 303b685df31SWei Hu return err ? err : EPROTO; 304b685df31SWei Hu } 305b685df31SWei Hu 306b685df31SWei Hu return 0; 307b685df31SWei Hu } 308b685df31SWei Hu 309b685df31SWei Hu int 310b685df31SWei Hu mana_gd_allocate_doorbell_page(struct gdma_context *gc, int *doorbell_page) 311b685df31SWei Hu { 312b685df31SWei Hu struct gdma_allocate_resource_range_req req = {}; 313b685df31SWei Hu struct gdma_allocate_resource_range_resp resp = {}; 314b685df31SWei Hu int err; 315b685df31SWei Hu 316b685df31SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_ALLOCATE_RESOURCE_RANGE, 317b685df31SWei Hu sizeof(req), sizeof(resp)); 318b685df31SWei Hu 319b685df31SWei Hu req.resource_type = GDMA_RESOURCE_DOORBELL_PAGE; 320b685df31SWei Hu req.num_resources = 1; 321b685df31SWei Hu req.alignment = 1; 322b685df31SWei Hu 323b685df31SWei Hu /* Have GDMA start searching from 0 */ 324b685df31SWei Hu req.allocated_resources = 0; 325b685df31SWei Hu 326b685df31SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 327b685df31SWei Hu if (err || resp.hdr.status) { 328b685df31SWei Hu device_printf(gc->dev, 329b685df31SWei Hu "Failed to allocate doorbell page: ret %d, 0x%x\n", 330b685df31SWei Hu err, resp.hdr.status); 331b685df31SWei Hu return err ? err : EPROTO; 332b685df31SWei Hu } 333b685df31SWei Hu 334b685df31SWei Hu *doorbell_page = resp.allocated_resources; 335b685df31SWei Hu 336b685df31SWei Hu return 0; 337b685df31SWei Hu } 338b685df31SWei Hu 339ce110ea1SWei Hu static int 340ce110ea1SWei Hu mana_gd_create_hw_eq(struct gdma_context *gc, 341ce110ea1SWei Hu struct gdma_queue *queue) 342ce110ea1SWei Hu { 343ce110ea1SWei Hu struct gdma_create_queue_resp resp = {}; 344ce110ea1SWei Hu struct gdma_create_queue_req req = {}; 345ce110ea1SWei Hu int err; 346ce110ea1SWei Hu 347ce110ea1SWei Hu if (queue->type != GDMA_EQ) 348ce110ea1SWei Hu return EINVAL; 349ce110ea1SWei Hu 350ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 351ce110ea1SWei Hu sizeof(req), sizeof(resp)); 352ce110ea1SWei Hu 353ce110ea1SWei Hu req.hdr.dev_id = queue->gdma_dev->dev_id; 354ce110ea1SWei Hu req.type = queue->type; 355ce110ea1SWei Hu req.pdid = queue->gdma_dev->pdid; 356ce110ea1SWei Hu req.doolbell_id = queue->gdma_dev->doorbell; 357b685df31SWei Hu req.gdma_region = queue->mem_info.dma_region_handle; 358ce110ea1SWei Hu req.queue_size = queue->queue_size; 359ce110ea1SWei Hu req.log2_throttle_limit = queue->eq.log2_throttle_limit; 360ce110ea1SWei Hu req.eq_pci_msix_index = queue->eq.msix_index; 361ce110ea1SWei Hu 362ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 363ce110ea1SWei Hu if (err || resp.hdr.status) { 364ce110ea1SWei Hu device_printf(gc->dev, 365ce110ea1SWei Hu "Failed to create queue: %d, 0x%x\n", 366ce110ea1SWei Hu err, resp.hdr.status); 367ce110ea1SWei Hu return err ? err : EPROTO; 368ce110ea1SWei Hu } 369ce110ea1SWei Hu 370ce110ea1SWei Hu queue->id = resp.queue_index; 371ce110ea1SWei Hu queue->eq.disable_needed = true; 372b685df31SWei Hu queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION; 373ce110ea1SWei Hu return 0; 374ce110ea1SWei Hu } 375ce110ea1SWei Hu 376ce110ea1SWei Hu static 377ce110ea1SWei Hu int mana_gd_disable_queue(struct gdma_queue *queue) 378ce110ea1SWei Hu { 379ce110ea1SWei Hu struct gdma_context *gc = queue->gdma_dev->gdma_context; 380ce110ea1SWei Hu struct gdma_disable_queue_req req = {}; 381ce110ea1SWei Hu struct gdma_general_resp resp = {}; 382ce110ea1SWei Hu int err; 383ce110ea1SWei Hu 384ce110ea1SWei Hu if (queue->type != GDMA_EQ) 385ce110ea1SWei Hu mana_warn(NULL, "Not event queue type 0x%x\n", 386ce110ea1SWei Hu queue->type); 387ce110ea1SWei Hu 388ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 389ce110ea1SWei Hu sizeof(req), sizeof(resp)); 390ce110ea1SWei Hu 391ce110ea1SWei Hu req.hdr.dev_id = queue->gdma_dev->dev_id; 392ce110ea1SWei Hu req.type = queue->type; 393ce110ea1SWei Hu req.queue_index = queue->id; 394ce110ea1SWei Hu req.alloc_res_id_on_creation = 1; 395ce110ea1SWei Hu 396ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 397ce110ea1SWei Hu if (err || resp.hdr.status) { 398ce110ea1SWei Hu device_printf(gc->dev, 399ce110ea1SWei Hu "Failed to disable queue: %d, 0x%x\n", err, 400ce110ea1SWei Hu resp.hdr.status); 401ce110ea1SWei Hu return err ? err : EPROTO; 402ce110ea1SWei Hu } 403ce110ea1SWei Hu 404ce110ea1SWei Hu return 0; 405ce110ea1SWei Hu } 406ce110ea1SWei Hu 407ce110ea1SWei Hu #define DOORBELL_OFFSET_SQ 0x0 408ce110ea1SWei Hu #define DOORBELL_OFFSET_RQ 0x400 409ce110ea1SWei Hu #define DOORBELL_OFFSET_CQ 0x800 410ce110ea1SWei Hu #define DOORBELL_OFFSET_EQ 0xFF8 411ce110ea1SWei Hu 412ce110ea1SWei Hu static void 413ce110ea1SWei Hu mana_gd_ring_doorbell(struct gdma_context *gc, uint32_t db_index, 414ce110ea1SWei Hu enum gdma_queue_type q_type, uint32_t qid, 415ce110ea1SWei Hu uint32_t tail_ptr, uint8_t num_req) 416ce110ea1SWei Hu { 417ce110ea1SWei Hu union gdma_doorbell_entry e = {}; 418ce110ea1SWei Hu void __iomem *addr; 419ce110ea1SWei Hu 420ce110ea1SWei Hu addr = (char *)gc->db_page_base + gc->db_page_size * db_index; 421ce110ea1SWei Hu switch (q_type) { 422ce110ea1SWei Hu case GDMA_EQ: 423ce110ea1SWei Hu e.eq.id = qid; 424ce110ea1SWei Hu e.eq.tail_ptr = tail_ptr; 425ce110ea1SWei Hu e.eq.arm = num_req; 426ce110ea1SWei Hu 427ce110ea1SWei Hu addr = (char *)addr + DOORBELL_OFFSET_EQ; 428ce110ea1SWei Hu break; 429ce110ea1SWei Hu 430ce110ea1SWei Hu case GDMA_CQ: 431ce110ea1SWei Hu e.cq.id = qid; 432ce110ea1SWei Hu e.cq.tail_ptr = tail_ptr; 433ce110ea1SWei Hu e.cq.arm = num_req; 434ce110ea1SWei Hu 435ce110ea1SWei Hu addr = (char *)addr + DOORBELL_OFFSET_CQ; 436ce110ea1SWei Hu break; 437ce110ea1SWei Hu 438ce110ea1SWei Hu case GDMA_RQ: 439ce110ea1SWei Hu e.rq.id = qid; 440ce110ea1SWei Hu e.rq.tail_ptr = tail_ptr; 441ce110ea1SWei Hu e.rq.wqe_cnt = num_req; 442ce110ea1SWei Hu 443ce110ea1SWei Hu addr = (char *)addr + DOORBELL_OFFSET_RQ; 444ce110ea1SWei Hu break; 445ce110ea1SWei Hu 446ce110ea1SWei Hu case GDMA_SQ: 447ce110ea1SWei Hu e.sq.id = qid; 448ce110ea1SWei Hu e.sq.tail_ptr = tail_ptr; 449ce110ea1SWei Hu 450ce110ea1SWei Hu addr = (char *)addr + DOORBELL_OFFSET_SQ; 451ce110ea1SWei Hu break; 452ce110ea1SWei Hu 453ce110ea1SWei Hu default: 454ce110ea1SWei Hu mana_warn(NULL, "Invalid queue type 0x%x\n", q_type); 455ce110ea1SWei Hu return; 456ce110ea1SWei Hu } 457ce110ea1SWei Hu 458ce110ea1SWei Hu /* Ensure all writes are done before ring doorbell */ 459ce110ea1SWei Hu wmb(); 460ce110ea1SWei Hu 461ce110ea1SWei Hu #if defined(__amd64__) 462ce110ea1SWei Hu writeq(addr, e.as_uint64); 463ce110ea1SWei Hu #else 464ce110ea1SWei Hu uint32_t *p = (uint32_t *)&e.as_uint64; 465ce110ea1SWei Hu writel(addr, *p); 466ce110ea1SWei Hu writel((char *)addr + 4, *(p + 1)); 467ce110ea1SWei Hu #endif 468ce110ea1SWei Hu } 469ce110ea1SWei Hu 470ce110ea1SWei Hu void 471ce110ea1SWei Hu mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 472ce110ea1SWei Hu { 473ce110ea1SWei Hu mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 474e4e11c1dSWei Hu queue->id, queue->head * GDMA_WQE_BU_SIZE, 0); 475ce110ea1SWei Hu } 476ce110ea1SWei Hu 477ce110ea1SWei Hu void 4781833cf13SWei Hu mana_gd_ring_cq(struct gdma_queue *cq, uint8_t arm_bit) 479ce110ea1SWei Hu { 480ce110ea1SWei Hu struct gdma_context *gc = cq->gdma_dev->gdma_context; 481ce110ea1SWei Hu 482ce110ea1SWei Hu uint32_t num_cqe = cq->queue_size / GDMA_CQE_SIZE; 483ce110ea1SWei Hu 484ce110ea1SWei Hu uint32_t head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 485ce110ea1SWei Hu 486ce110ea1SWei Hu mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 4871833cf13SWei Hu head, arm_bit); 488ce110ea1SWei Hu } 489ce110ea1SWei Hu 490ce110ea1SWei Hu static void 491ce110ea1SWei Hu mana_gd_process_eqe(struct gdma_queue *eq) 492ce110ea1SWei Hu { 493ce110ea1SWei Hu uint32_t head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 494ce110ea1SWei Hu struct gdma_context *gc = eq->gdma_dev->gdma_context; 495ce110ea1SWei Hu struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 496ce110ea1SWei Hu union gdma_eqe_info eqe_info; 497ce110ea1SWei Hu enum gdma_eqe_type type; 498ce110ea1SWei Hu struct gdma_event event; 499ce110ea1SWei Hu struct gdma_queue *cq; 500ce110ea1SWei Hu struct gdma_eqe *eqe; 501ce110ea1SWei Hu uint32_t cq_id; 502ce110ea1SWei Hu 503ce110ea1SWei Hu eqe = &eq_eqe_ptr[head]; 504ce110ea1SWei Hu eqe_info.as_uint32 = eqe->eqe_info; 505ce110ea1SWei Hu type = eqe_info.type; 506ce110ea1SWei Hu 507ce110ea1SWei Hu switch (type) { 508ce110ea1SWei Hu case GDMA_EQE_COMPLETION: 509ce110ea1SWei Hu cq_id = eqe->details[0] & 0xFFFFFF; 510ce110ea1SWei Hu if (cq_id >= gc->max_num_cqs) { 511ce110ea1SWei Hu mana_warn(NULL, 512ce110ea1SWei Hu "failed: cq_id %u > max_num_cqs %u\n", 513ce110ea1SWei Hu cq_id, gc->max_num_cqs); 514ce110ea1SWei Hu break; 515ce110ea1SWei Hu } 516ce110ea1SWei Hu 517ce110ea1SWei Hu cq = gc->cq_table[cq_id]; 518ce110ea1SWei Hu if (!cq || cq->type != GDMA_CQ || cq->id != cq_id) { 519ce110ea1SWei Hu mana_warn(NULL, 520ce110ea1SWei Hu "failed: invalid cq_id %u\n", cq_id); 521ce110ea1SWei Hu break; 522ce110ea1SWei Hu } 523ce110ea1SWei Hu 524ce110ea1SWei Hu if (cq->cq.callback) 525ce110ea1SWei Hu cq->cq.callback(cq->cq.context, cq); 526ce110ea1SWei Hu 527ce110ea1SWei Hu break; 528ce110ea1SWei Hu 529ce110ea1SWei Hu case GDMA_EQE_TEST_EVENT: 530ce110ea1SWei Hu gc->test_event_eq_id = eq->id; 531ce110ea1SWei Hu 532ce110ea1SWei Hu mana_dbg(NULL, 533ce110ea1SWei Hu "EQE TEST EVENT received for EQ %u\n", eq->id); 534ce110ea1SWei Hu 535ce110ea1SWei Hu complete(&gc->eq_test_event); 536ce110ea1SWei Hu break; 537ce110ea1SWei Hu 538ce110ea1SWei Hu case GDMA_EQE_HWC_INIT_EQ_ID_DB: 539ce110ea1SWei Hu case GDMA_EQE_HWC_INIT_DATA: 540ce110ea1SWei Hu case GDMA_EQE_HWC_INIT_DONE: 541ce110ea1SWei Hu if (!eq->eq.callback) 542ce110ea1SWei Hu break; 543ce110ea1SWei Hu 544ce110ea1SWei Hu event.type = type; 545ce110ea1SWei Hu memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 546ce110ea1SWei Hu eq->eq.callback(eq->eq.context, eq, &event); 547ce110ea1SWei Hu break; 548ce110ea1SWei Hu 549ce110ea1SWei Hu default: 550ce110ea1SWei Hu break; 551ce110ea1SWei Hu } 552ce110ea1SWei Hu } 553ce110ea1SWei Hu 554ce110ea1SWei Hu static void 555ce110ea1SWei Hu mana_gd_process_eq_events(void *arg) 556ce110ea1SWei Hu { 557ce110ea1SWei Hu uint32_t owner_bits, new_bits, old_bits; 558ce110ea1SWei Hu union gdma_eqe_info eqe_info; 559ce110ea1SWei Hu struct gdma_eqe *eq_eqe_ptr; 560ce110ea1SWei Hu struct gdma_queue *eq = arg; 561ce110ea1SWei Hu struct gdma_context *gc; 562ce110ea1SWei Hu uint32_t head, num_eqe; 563ce110ea1SWei Hu struct gdma_eqe *eqe; 564ce110ea1SWei Hu int i, j; 565ce110ea1SWei Hu 566ce110ea1SWei Hu gc = eq->gdma_dev->gdma_context; 567ce110ea1SWei Hu 568ce110ea1SWei Hu num_eqe = eq->queue_size / GDMA_EQE_SIZE; 569ce110ea1SWei Hu eq_eqe_ptr = eq->queue_mem_ptr; 570ce110ea1SWei Hu 571ce110ea1SWei Hu bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 572ce110ea1SWei Hu BUS_DMASYNC_POSTREAD); 573ce110ea1SWei Hu 574ce110ea1SWei Hu /* Process up to 5 EQEs at a time, and update the HW head. */ 575ce110ea1SWei Hu for (i = 0; i < 5; i++) { 576ce110ea1SWei Hu eqe = &eq_eqe_ptr[eq->head % num_eqe]; 577ce110ea1SWei Hu eqe_info.as_uint32 = eqe->eqe_info; 578ce110ea1SWei Hu owner_bits = eqe_info.owner_bits; 579ce110ea1SWei Hu 580ce110ea1SWei Hu old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 581ce110ea1SWei Hu 582ce110ea1SWei Hu /* No more entries */ 583ce110ea1SWei Hu if (owner_bits == old_bits) 584ce110ea1SWei Hu break; 585ce110ea1SWei Hu 586ce110ea1SWei Hu new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 587ce110ea1SWei Hu if (owner_bits != new_bits) { 588ce110ea1SWei Hu /* Something wrong. Log for debugging purpose */ 589ce110ea1SWei Hu device_printf(gc->dev, 590ce110ea1SWei Hu "EQ %d: overflow detected, " 591ce110ea1SWei Hu "i = %d, eq->head = %u " 592ce110ea1SWei Hu "got owner_bits = %u, new_bits = %u " 593ce110ea1SWei Hu "eqe addr %p, eqe->eqe_info 0x%x, " 594ce110ea1SWei Hu "eqe type = %x, reserved1 = %x, client_id = %x, " 595ce110ea1SWei Hu "reserved2 = %x, owner_bits = %x\n", 596ce110ea1SWei Hu eq->id, i, eq->head, 597ce110ea1SWei Hu owner_bits, new_bits, 598ce110ea1SWei Hu eqe, eqe->eqe_info, 599ce110ea1SWei Hu eqe_info.type, eqe_info.reserved1, 600ce110ea1SWei Hu eqe_info.client_id, eqe_info.reserved2, 601ce110ea1SWei Hu eqe_info.owner_bits); 602ce110ea1SWei Hu 603ce110ea1SWei Hu uint32_t *eqe_dump = (uint32_t *) eq_eqe_ptr; 604ce110ea1SWei Hu for (j = 0; j < 20; j++) { 605ce110ea1SWei Hu device_printf(gc->dev, "%p: %x\t%x\t%x\t%x\n", 606ce110ea1SWei Hu &eqe_dump[j * 4], eqe_dump[j * 4], eqe_dump[j * 4 + 1], 607ce110ea1SWei Hu eqe_dump[j * 4 + 2], eqe_dump[j * 4 + 3]); 608ce110ea1SWei Hu } 609ce110ea1SWei Hu break; 610ce110ea1SWei Hu } 611ce110ea1SWei Hu 612fa2d4a22SWei Hu rmb(); 613fa2d4a22SWei Hu 614ce110ea1SWei Hu mana_gd_process_eqe(eq); 615ce110ea1SWei Hu 616ce110ea1SWei Hu eq->head++; 617ce110ea1SWei Hu } 618ce110ea1SWei Hu 619ce110ea1SWei Hu bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 620ce110ea1SWei Hu BUS_DMASYNC_PREREAD); 621ce110ea1SWei Hu 622ce110ea1SWei Hu head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 623ce110ea1SWei Hu 624ce110ea1SWei Hu mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 6251833cf13SWei Hu head, SET_ARM_BIT); 626ce110ea1SWei Hu } 627ce110ea1SWei Hu 628ce110ea1SWei Hu static int 629ce110ea1SWei Hu mana_gd_register_irq(struct gdma_queue *queue, 630ce110ea1SWei Hu const struct gdma_queue_spec *spec) 631ce110ea1SWei Hu { 632ce110ea1SWei Hu struct gdma_dev *gd = queue->gdma_dev; 633ce110ea1SWei Hu struct gdma_irq_context *gic; 634ce110ea1SWei Hu struct gdma_context *gc; 635ce110ea1SWei Hu struct gdma_resource *r; 636ce110ea1SWei Hu unsigned int msi_index; 637ce110ea1SWei Hu int err; 638ce110ea1SWei Hu 639ce110ea1SWei Hu gc = gd->gdma_context; 640ce110ea1SWei Hu r = &gc->msix_resource; 641ce110ea1SWei Hu 642ce110ea1SWei Hu mtx_lock_spin(&r->lock_spin); 643ce110ea1SWei Hu 644ce110ea1SWei Hu msi_index = find_first_zero_bit(r->map, r->size); 645ce110ea1SWei Hu if (msi_index >= r->size) { 646ce110ea1SWei Hu err = ENOSPC; 647ce110ea1SWei Hu } else { 648ce110ea1SWei Hu bitmap_set(r->map, msi_index, 1); 649ce110ea1SWei Hu queue->eq.msix_index = msi_index; 650ce110ea1SWei Hu err = 0; 651ce110ea1SWei Hu } 652ce110ea1SWei Hu 653ce110ea1SWei Hu mtx_unlock_spin(&r->lock_spin); 654ce110ea1SWei Hu 655ce110ea1SWei Hu if (err) 656ce110ea1SWei Hu return err; 657ce110ea1SWei Hu 658ce110ea1SWei Hu if (unlikely(msi_index >= gc->num_msix_usable)) { 659ce110ea1SWei Hu device_printf(gc->dev, 660ce110ea1SWei Hu "chose an invalid msix index %d, usable %d\n", 661ce110ea1SWei Hu msi_index, gc->num_msix_usable); 662ce110ea1SWei Hu return ENOSPC; 663ce110ea1SWei Hu } 664ce110ea1SWei Hu 665ce110ea1SWei Hu gic = &gc->irq_contexts[msi_index]; 666ce110ea1SWei Hu 667ce110ea1SWei Hu if (unlikely(gic->handler || gic->arg)) { 668ce110ea1SWei Hu device_printf(gc->dev, 669ce110ea1SWei Hu "interrupt handler or arg already assigned, " 670ce110ea1SWei Hu "msix index: %d\n", msi_index); 671ce110ea1SWei Hu } 672ce110ea1SWei Hu 673ce110ea1SWei Hu gic->arg = queue; 674ce110ea1SWei Hu 675ce110ea1SWei Hu gic->handler = mana_gd_process_eq_events; 676ce110ea1SWei Hu 677ce110ea1SWei Hu mana_dbg(NULL, "registered msix index %d vector %d irq %ju\n", 678ce110ea1SWei Hu msi_index, gic->msix_e.vector, rman_get_start(gic->res)); 679ce110ea1SWei Hu 680ce110ea1SWei Hu return 0; 681ce110ea1SWei Hu } 682ce110ea1SWei Hu 683ce110ea1SWei Hu static void 684ce110ea1SWei Hu mana_gd_deregiser_irq(struct gdma_queue *queue) 685ce110ea1SWei Hu { 686ce110ea1SWei Hu struct gdma_dev *gd = queue->gdma_dev; 687ce110ea1SWei Hu struct gdma_irq_context *gic; 688ce110ea1SWei Hu struct gdma_context *gc; 689ce110ea1SWei Hu struct gdma_resource *r; 690ce110ea1SWei Hu unsigned int msix_index; 691ce110ea1SWei Hu 692ce110ea1SWei Hu gc = gd->gdma_context; 693ce110ea1SWei Hu r = &gc->msix_resource; 694ce110ea1SWei Hu 695ce110ea1SWei Hu /* At most num_online_cpus() + 1 interrupts are used. */ 696ce110ea1SWei Hu msix_index = queue->eq.msix_index; 697ce110ea1SWei Hu if (unlikely(msix_index >= gc->num_msix_usable)) 698ce110ea1SWei Hu return; 699ce110ea1SWei Hu 700ce110ea1SWei Hu gic = &gc->irq_contexts[msix_index]; 701ce110ea1SWei Hu gic->handler = NULL; 702ce110ea1SWei Hu gic->arg = NULL; 703ce110ea1SWei Hu 704ce110ea1SWei Hu mtx_lock_spin(&r->lock_spin); 705ce110ea1SWei Hu bitmap_clear(r->map, msix_index, 1); 706ce110ea1SWei Hu mtx_unlock_spin(&r->lock_spin); 707ce110ea1SWei Hu 708ce110ea1SWei Hu queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 709ce110ea1SWei Hu 710ce110ea1SWei Hu mana_dbg(NULL, "deregistered msix index %d vector %d irq %ju\n", 711ce110ea1SWei Hu msix_index, gic->msix_e.vector, rman_get_start(gic->res)); 712ce110ea1SWei Hu } 713ce110ea1SWei Hu 714ce110ea1SWei Hu int 715ce110ea1SWei Hu mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 716ce110ea1SWei Hu { 717ce110ea1SWei Hu struct gdma_generate_test_event_req req = {}; 718ce110ea1SWei Hu struct gdma_general_resp resp = {}; 719ce110ea1SWei Hu device_t dev = gc->dev; 720ce110ea1SWei Hu int err; 721ce110ea1SWei Hu 722ce110ea1SWei Hu sx_xlock(&gc->eq_test_event_sx); 723ce110ea1SWei Hu 724ce110ea1SWei Hu init_completion(&gc->eq_test_event); 725ce110ea1SWei Hu gc->test_event_eq_id = INVALID_QUEUE_ID; 726ce110ea1SWei Hu 727ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 728ce110ea1SWei Hu sizeof(req), sizeof(resp)); 729ce110ea1SWei Hu 730ce110ea1SWei Hu req.hdr.dev_id = eq->gdma_dev->dev_id; 731ce110ea1SWei Hu req.queue_index = eq->id; 732ce110ea1SWei Hu 733ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, 734ce110ea1SWei Hu sizeof(resp), &resp); 735ce110ea1SWei Hu if (err) { 736ce110ea1SWei Hu device_printf(dev, "test_eq failed: %d\n", err); 737ce110ea1SWei Hu goto out; 738ce110ea1SWei Hu } 739ce110ea1SWei Hu 740ce110ea1SWei Hu err = EPROTO; 741ce110ea1SWei Hu 742ce110ea1SWei Hu if (resp.hdr.status) { 743ce110ea1SWei Hu device_printf(dev, "test_eq failed: 0x%x\n", 744ce110ea1SWei Hu resp.hdr.status); 745ce110ea1SWei Hu goto out; 746ce110ea1SWei Hu } 747ce110ea1SWei Hu 748ce110ea1SWei Hu if (wait_for_completion_timeout(&gc->eq_test_event, 30 * hz)) { 749ce110ea1SWei Hu device_printf(dev, "test_eq timed out on queue %d\n", 750ce110ea1SWei Hu eq->id); 751ce110ea1SWei Hu goto out; 752ce110ea1SWei Hu } 753ce110ea1SWei Hu 754ce110ea1SWei Hu if (eq->id != gc->test_event_eq_id) { 755ce110ea1SWei Hu device_printf(dev, 756ce110ea1SWei Hu "test_eq got an event on wrong queue %d (%d)\n", 757ce110ea1SWei Hu gc->test_event_eq_id, eq->id); 758ce110ea1SWei Hu goto out; 759ce110ea1SWei Hu } 760ce110ea1SWei Hu 761ce110ea1SWei Hu err = 0; 762ce110ea1SWei Hu out: 763ce110ea1SWei Hu sx_xunlock(&gc->eq_test_event_sx); 764ce110ea1SWei Hu return err; 765ce110ea1SWei Hu } 766ce110ea1SWei Hu 767ce110ea1SWei Hu static void 768ce110ea1SWei Hu mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 769ce110ea1SWei Hu struct gdma_queue *queue) 770ce110ea1SWei Hu { 771ce110ea1SWei Hu int err; 772ce110ea1SWei Hu 773ce110ea1SWei Hu if (flush_evenets) { 774ce110ea1SWei Hu err = mana_gd_test_eq(gc, queue); 775ce110ea1SWei Hu if (err) 776ce110ea1SWei Hu device_printf(gc->dev, 777ce110ea1SWei Hu "Failed to flush EQ: %d\n", err); 778ce110ea1SWei Hu } 779ce110ea1SWei Hu 780ce110ea1SWei Hu mana_gd_deregiser_irq(queue); 781ce110ea1SWei Hu 782ce110ea1SWei Hu if (queue->eq.disable_needed) 783ce110ea1SWei Hu mana_gd_disable_queue(queue); 784ce110ea1SWei Hu } 785ce110ea1SWei Hu 786ce110ea1SWei Hu static int mana_gd_create_eq(struct gdma_dev *gd, 787ce110ea1SWei Hu const struct gdma_queue_spec *spec, 788ce110ea1SWei Hu bool create_hwq, struct gdma_queue *queue) 789ce110ea1SWei Hu { 790ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 791ce110ea1SWei Hu device_t dev = gc->dev; 792ce110ea1SWei Hu uint32_t log2_num_entries; 793ce110ea1SWei Hu int err; 794ce110ea1SWei Hu 795ce110ea1SWei Hu queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 796ce110ea1SWei Hu 797ce110ea1SWei Hu log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 798ce110ea1SWei Hu 799ce110ea1SWei Hu if (spec->eq.log2_throttle_limit > log2_num_entries) { 800ce110ea1SWei Hu device_printf(dev, 801ce110ea1SWei Hu "EQ throttling limit (%lu) > maximum EQE (%u)\n", 802ce110ea1SWei Hu spec->eq.log2_throttle_limit, log2_num_entries); 803ce110ea1SWei Hu return EINVAL; 804ce110ea1SWei Hu } 805ce110ea1SWei Hu 806ce110ea1SWei Hu err = mana_gd_register_irq(queue, spec); 807ce110ea1SWei Hu if (err) { 808ce110ea1SWei Hu device_printf(dev, "Failed to register irq: %d\n", err); 809ce110ea1SWei Hu return err; 810ce110ea1SWei Hu } 811ce110ea1SWei Hu 812ce110ea1SWei Hu queue->eq.callback = spec->eq.callback; 813ce110ea1SWei Hu queue->eq.context = spec->eq.context; 814ce110ea1SWei Hu queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 815ce110ea1SWei Hu queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 816ce110ea1SWei Hu 817ce110ea1SWei Hu if (create_hwq) { 818ce110ea1SWei Hu err = mana_gd_create_hw_eq(gc, queue); 819ce110ea1SWei Hu if (err) 820ce110ea1SWei Hu goto out; 821ce110ea1SWei Hu 822ce110ea1SWei Hu err = mana_gd_test_eq(gc, queue); 823ce110ea1SWei Hu if (err) 824ce110ea1SWei Hu goto out; 825ce110ea1SWei Hu } 826ce110ea1SWei Hu 827ce110ea1SWei Hu return 0; 828ce110ea1SWei Hu out: 829ce110ea1SWei Hu device_printf(dev, "Failed to create EQ: %d\n", err); 830ce110ea1SWei Hu mana_gd_destroy_eq(gc, false, queue); 831ce110ea1SWei Hu return err; 832ce110ea1SWei Hu } 833ce110ea1SWei Hu 834ce110ea1SWei Hu static void 835ce110ea1SWei Hu mana_gd_create_cq(const struct gdma_queue_spec *spec, 836ce110ea1SWei Hu struct gdma_queue *queue) 837ce110ea1SWei Hu { 838ce110ea1SWei Hu uint32_t log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 839ce110ea1SWei Hu 840ce110ea1SWei Hu queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 841ce110ea1SWei Hu queue->cq.parent = spec->cq.parent_eq; 842ce110ea1SWei Hu queue->cq.context = spec->cq.context; 843ce110ea1SWei Hu queue->cq.callback = spec->cq.callback; 844ce110ea1SWei Hu } 845ce110ea1SWei Hu 846ce110ea1SWei Hu static void 847ce110ea1SWei Hu mana_gd_destroy_cq(struct gdma_context *gc, 848ce110ea1SWei Hu struct gdma_queue *queue) 849ce110ea1SWei Hu { 850ce110ea1SWei Hu uint32_t id = queue->id; 851ce110ea1SWei Hu 852ce110ea1SWei Hu if (id >= gc->max_num_cqs) 853ce110ea1SWei Hu return; 854ce110ea1SWei Hu 855ce110ea1SWei Hu if (!gc->cq_table[id]) 856ce110ea1SWei Hu return; 857ce110ea1SWei Hu 858ce110ea1SWei Hu gc->cq_table[id] = NULL; 859ce110ea1SWei Hu } 860ce110ea1SWei Hu 861ce110ea1SWei Hu int mana_gd_create_hwc_queue(struct gdma_dev *gd, 862ce110ea1SWei Hu const struct gdma_queue_spec *spec, 863ce110ea1SWei Hu struct gdma_queue **queue_ptr) 864ce110ea1SWei Hu { 865ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 866ce110ea1SWei Hu struct gdma_mem_info *gmi; 867ce110ea1SWei Hu struct gdma_queue *queue; 868ce110ea1SWei Hu int err; 869ce110ea1SWei Hu 870ce110ea1SWei Hu queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 871ce110ea1SWei Hu if (!queue) 872ce110ea1SWei Hu return ENOMEM; 873ce110ea1SWei Hu 874ce110ea1SWei Hu gmi = &queue->mem_info; 875ce110ea1SWei Hu err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 876ce110ea1SWei Hu if (err) 877ce110ea1SWei Hu goto free_q; 878ce110ea1SWei Hu 879ce110ea1SWei Hu queue->head = 0; 880ce110ea1SWei Hu queue->tail = 0; 881ce110ea1SWei Hu queue->queue_mem_ptr = gmi->virt_addr; 882ce110ea1SWei Hu queue->queue_size = spec->queue_size; 883ce110ea1SWei Hu queue->monitor_avl_buf = spec->monitor_avl_buf; 884ce110ea1SWei Hu queue->type = spec->type; 885ce110ea1SWei Hu queue->gdma_dev = gd; 886ce110ea1SWei Hu 887ce110ea1SWei Hu if (spec->type == GDMA_EQ) 888ce110ea1SWei Hu err = mana_gd_create_eq(gd, spec, false, queue); 889ce110ea1SWei Hu else if (spec->type == GDMA_CQ) 890ce110ea1SWei Hu mana_gd_create_cq(spec, queue); 891ce110ea1SWei Hu 892ce110ea1SWei Hu if (err) 893ce110ea1SWei Hu goto out; 894ce110ea1SWei Hu 895ce110ea1SWei Hu *queue_ptr = queue; 896ce110ea1SWei Hu return 0; 897ce110ea1SWei Hu out: 898ce110ea1SWei Hu mana_gd_free_memory(gmi); 899ce110ea1SWei Hu free_q: 900ce110ea1SWei Hu free(queue, M_DEVBUF); 901ce110ea1SWei Hu return err; 902ce110ea1SWei Hu } 903ce110ea1SWei Hu 904b685df31SWei Hu int 905b685df31SWei Hu mana_gd_destroy_dma_region(struct gdma_context *gc, 906b685df31SWei Hu gdma_obj_handle_t dma_region_handle) 907ce110ea1SWei Hu { 908ce110ea1SWei Hu struct gdma_destroy_dma_region_req req = {}; 909ce110ea1SWei Hu struct gdma_general_resp resp = {}; 910ce110ea1SWei Hu int err; 911ce110ea1SWei Hu 912b685df31SWei Hu if (dma_region_handle == GDMA_INVALID_DMA_REGION) 913b685df31SWei Hu return 0; 914ce110ea1SWei Hu 915ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 916ce110ea1SWei Hu sizeof(resp)); 917b685df31SWei Hu req.dma_region_handle = dma_region_handle; 918ce110ea1SWei Hu 919ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), 920ce110ea1SWei Hu &resp); 921b685df31SWei Hu if (err || resp.hdr.status) { 922ce110ea1SWei Hu device_printf(gc->dev, 923ce110ea1SWei Hu "Failed to destroy DMA region: %d, 0x%x\n", 924ce110ea1SWei Hu err, resp.hdr.status); 925b685df31SWei Hu return EPROTO; 926b685df31SWei Hu } 927b685df31SWei Hu 928b685df31SWei Hu return 0; 929ce110ea1SWei Hu } 930ce110ea1SWei Hu 931ce110ea1SWei Hu static int 932ce110ea1SWei Hu mana_gd_create_dma_region(struct gdma_dev *gd, 933ce110ea1SWei Hu struct gdma_mem_info *gmi) 934ce110ea1SWei Hu { 935ce110ea1SWei Hu unsigned int num_page = gmi->length / PAGE_SIZE; 936ce110ea1SWei Hu struct gdma_create_dma_region_req *req = NULL; 937ce110ea1SWei Hu struct gdma_create_dma_region_resp resp = {}; 938ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 939ce110ea1SWei Hu struct hw_channel_context *hwc; 940ce110ea1SWei Hu uint32_t length = gmi->length; 941ce110ea1SWei Hu uint32_t req_msg_size; 942ce110ea1SWei Hu int err; 943ce110ea1SWei Hu int i; 944ce110ea1SWei Hu 945ce110ea1SWei Hu if (length < PAGE_SIZE || !is_power_of_2(length)) { 946ce110ea1SWei Hu mana_err(NULL, "gmi size incorrect: %u\n", length); 947ce110ea1SWei Hu return EINVAL; 948ce110ea1SWei Hu } 949ce110ea1SWei Hu 950c5eed414SJohn Baldwin if (offset_in_page((uintptr_t)gmi->virt_addr) != 0) { 951ce110ea1SWei Hu mana_err(NULL, "gmi not page aligned: %p\n", 952ce110ea1SWei Hu gmi->virt_addr); 953ce110ea1SWei Hu return EINVAL; 954ce110ea1SWei Hu } 955ce110ea1SWei Hu 956ce110ea1SWei Hu hwc = gc->hwc.driver_data; 957ce110ea1SWei Hu req_msg_size = sizeof(*req) + num_page * sizeof(uint64_t); 958ce110ea1SWei Hu if (req_msg_size > hwc->max_req_msg_size) { 959ce110ea1SWei Hu mana_err(NULL, "req msg size too large: %u, %u\n", 960ce110ea1SWei Hu req_msg_size, hwc->max_req_msg_size); 961ce110ea1SWei Hu return EINVAL; 962ce110ea1SWei Hu } 963ce110ea1SWei Hu 964ce110ea1SWei Hu req = malloc(req_msg_size, M_DEVBUF, M_WAITOK | M_ZERO); 965ce110ea1SWei Hu if (!req) 966ce110ea1SWei Hu return ENOMEM; 967ce110ea1SWei Hu 968ce110ea1SWei Hu mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 969ce110ea1SWei Hu req_msg_size, sizeof(resp)); 970ce110ea1SWei Hu req->length = length; 971ce110ea1SWei Hu req->offset_in_page = 0; 972ce110ea1SWei Hu req->gdma_page_type = GDMA_PAGE_TYPE_4K; 973ce110ea1SWei Hu req->page_count = num_page; 974ce110ea1SWei Hu req->page_addr_list_len = num_page; 975ce110ea1SWei Hu 976ce110ea1SWei Hu for (i = 0; i < num_page; i++) 977ce110ea1SWei Hu req->page_addr_list[i] = gmi->dma_handle + i * PAGE_SIZE; 978ce110ea1SWei Hu 979ce110ea1SWei Hu err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 980ce110ea1SWei Hu if (err) 981ce110ea1SWei Hu goto out; 982ce110ea1SWei Hu 983b685df31SWei Hu if (resp.hdr.status || 984b685df31SWei Hu resp.dma_region_handle == GDMA_INVALID_DMA_REGION) { 985ce110ea1SWei Hu device_printf(gc->dev, "Failed to create DMA region: 0x%x\n", 986ce110ea1SWei Hu resp.hdr.status); 987ce110ea1SWei Hu err = EPROTO; 988ce110ea1SWei Hu goto out; 989ce110ea1SWei Hu } 990ce110ea1SWei Hu 991b685df31SWei Hu gmi->dma_region_handle = resp.dma_region_handle; 992ce110ea1SWei Hu out: 993ce110ea1SWei Hu free(req, M_DEVBUF); 994ce110ea1SWei Hu return err; 995ce110ea1SWei Hu } 996ce110ea1SWei Hu 997ce110ea1SWei Hu int 998ce110ea1SWei Hu mana_gd_create_mana_eq(struct gdma_dev *gd, 999ce110ea1SWei Hu const struct gdma_queue_spec *spec, 1000ce110ea1SWei Hu struct gdma_queue **queue_ptr) 1001ce110ea1SWei Hu { 1002ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 1003ce110ea1SWei Hu struct gdma_mem_info *gmi; 1004ce110ea1SWei Hu struct gdma_queue *queue; 1005ce110ea1SWei Hu int err; 1006ce110ea1SWei Hu 1007ce110ea1SWei Hu if (spec->type != GDMA_EQ) 1008ce110ea1SWei Hu return EINVAL; 1009ce110ea1SWei Hu 1010ce110ea1SWei Hu queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 1011ce110ea1SWei Hu if (!queue) 1012ce110ea1SWei Hu return ENOMEM; 1013ce110ea1SWei Hu 1014ce110ea1SWei Hu gmi = &queue->mem_info; 1015ce110ea1SWei Hu err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1016ce110ea1SWei Hu if (err) 1017ce110ea1SWei Hu goto free_q; 1018ce110ea1SWei Hu 1019ce110ea1SWei Hu err = mana_gd_create_dma_region(gd, gmi); 1020ce110ea1SWei Hu if (err) 1021ce110ea1SWei Hu goto out; 1022ce110ea1SWei Hu 1023ce110ea1SWei Hu queue->head = 0; 1024ce110ea1SWei Hu queue->tail = 0; 1025ce110ea1SWei Hu queue->queue_mem_ptr = gmi->virt_addr; 1026ce110ea1SWei Hu queue->queue_size = spec->queue_size; 1027ce110ea1SWei Hu queue->monitor_avl_buf = spec->monitor_avl_buf; 1028ce110ea1SWei Hu queue->type = spec->type; 1029ce110ea1SWei Hu queue->gdma_dev = gd; 1030ce110ea1SWei Hu 1031ce110ea1SWei Hu err = mana_gd_create_eq(gd, spec, true, queue); 1032ce110ea1SWei Hu if (err) 1033ce110ea1SWei Hu goto out; 1034ce110ea1SWei Hu 1035ce110ea1SWei Hu *queue_ptr = queue; 1036ce110ea1SWei Hu return 0; 1037ce110ea1SWei Hu 1038ce110ea1SWei Hu out: 1039ce110ea1SWei Hu mana_gd_free_memory(gmi); 1040ce110ea1SWei Hu free_q: 1041ce110ea1SWei Hu free(queue, M_DEVBUF); 1042ce110ea1SWei Hu return err; 1043ce110ea1SWei Hu } 1044ce110ea1SWei Hu 1045ce110ea1SWei Hu int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 1046ce110ea1SWei Hu const struct gdma_queue_spec *spec, 1047ce110ea1SWei Hu struct gdma_queue **queue_ptr) 1048ce110ea1SWei Hu { 1049ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 1050ce110ea1SWei Hu struct gdma_mem_info *gmi; 1051ce110ea1SWei Hu struct gdma_queue *queue; 1052ce110ea1SWei Hu int err; 1053ce110ea1SWei Hu 1054ce110ea1SWei Hu if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 1055ce110ea1SWei Hu spec->type != GDMA_RQ) 1056ce110ea1SWei Hu return EINVAL; 1057ce110ea1SWei Hu 1058ce110ea1SWei Hu queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 1059ce110ea1SWei Hu if (!queue) 1060ce110ea1SWei Hu return ENOMEM; 1061ce110ea1SWei Hu 1062ce110ea1SWei Hu gmi = &queue->mem_info; 1063ce110ea1SWei Hu err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1064ce110ea1SWei Hu if (err) 1065ce110ea1SWei Hu goto free_q; 1066ce110ea1SWei Hu 1067ce110ea1SWei Hu err = mana_gd_create_dma_region(gd, gmi); 1068ce110ea1SWei Hu if (err) 1069ce110ea1SWei Hu goto out; 1070ce110ea1SWei Hu 1071ce110ea1SWei Hu queue->head = 0; 1072ce110ea1SWei Hu queue->tail = 0; 1073ce110ea1SWei Hu queue->queue_mem_ptr = gmi->virt_addr; 1074ce110ea1SWei Hu queue->queue_size = spec->queue_size; 1075ce110ea1SWei Hu queue->monitor_avl_buf = spec->monitor_avl_buf; 1076ce110ea1SWei Hu queue->type = spec->type; 1077ce110ea1SWei Hu queue->gdma_dev = gd; 1078ce110ea1SWei Hu 1079ce110ea1SWei Hu if (spec->type == GDMA_CQ) 1080ce110ea1SWei Hu mana_gd_create_cq(spec, queue); 1081ce110ea1SWei Hu 1082ce110ea1SWei Hu *queue_ptr = queue; 1083ce110ea1SWei Hu return 0; 1084ce110ea1SWei Hu 1085ce110ea1SWei Hu out: 1086ce110ea1SWei Hu mana_gd_free_memory(gmi); 1087ce110ea1SWei Hu free_q: 1088ce110ea1SWei Hu free(queue, M_DEVBUF); 1089ce110ea1SWei Hu return err; 1090ce110ea1SWei Hu } 1091ce110ea1SWei Hu 1092ce110ea1SWei Hu void 1093ce110ea1SWei Hu mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 1094ce110ea1SWei Hu { 1095ce110ea1SWei Hu struct gdma_mem_info *gmi = &queue->mem_info; 1096ce110ea1SWei Hu 1097ce110ea1SWei Hu switch (queue->type) { 1098ce110ea1SWei Hu case GDMA_EQ: 1099ce110ea1SWei Hu mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 1100ce110ea1SWei Hu break; 1101ce110ea1SWei Hu 1102ce110ea1SWei Hu case GDMA_CQ: 1103ce110ea1SWei Hu mana_gd_destroy_cq(gc, queue); 1104ce110ea1SWei Hu break; 1105ce110ea1SWei Hu 1106ce110ea1SWei Hu case GDMA_RQ: 1107ce110ea1SWei Hu break; 1108ce110ea1SWei Hu 1109ce110ea1SWei Hu case GDMA_SQ: 1110ce110ea1SWei Hu break; 1111ce110ea1SWei Hu 1112ce110ea1SWei Hu default: 1113ce110ea1SWei Hu device_printf(gc->dev, 1114ce110ea1SWei Hu "Can't destroy unknown queue: type = %d\n", 1115ce110ea1SWei Hu queue->type); 1116ce110ea1SWei Hu return; 1117ce110ea1SWei Hu } 1118ce110ea1SWei Hu 1119b685df31SWei Hu mana_gd_destroy_dma_region(gc, gmi->dma_region_handle); 1120ce110ea1SWei Hu mana_gd_free_memory(gmi); 1121ce110ea1SWei Hu free(queue, M_DEVBUF); 1122ce110ea1SWei Hu } 1123ce110ea1SWei Hu 1124ed65c80aSWei Hu #define OS_MAJOR_DIV 100000 1125ed65c80aSWei Hu #define OS_BUILD_MOD 1000 1126ed65c80aSWei Hu 1127ce110ea1SWei Hu int 1128ce110ea1SWei Hu mana_gd_verify_vf_version(device_t dev) 1129ce110ea1SWei Hu { 1130ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 1131ce110ea1SWei Hu struct gdma_verify_ver_resp resp = {}; 1132ce110ea1SWei Hu struct gdma_verify_ver_req req = {}; 1133ce110ea1SWei Hu int err; 1134ce110ea1SWei Hu 1135ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 1136ce110ea1SWei Hu sizeof(req), sizeof(resp)); 1137ce110ea1SWei Hu 1138ce110ea1SWei Hu req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 1139ce110ea1SWei Hu req.protocol_ver_max = GDMA_PROTOCOL_LAST; 1140ce110ea1SWei Hu 1141ed65c80aSWei Hu req.drv_ver = 0; /* Unused */ 1142ed65c80aSWei Hu req.os_type = 0x30; /* Other */ 1143ed65c80aSWei Hu req.os_ver_major = osreldate / OS_MAJOR_DIV; 1144ed65c80aSWei Hu req.os_ver_minor = (osreldate % OS_MAJOR_DIV) / OS_BUILD_MOD; 1145ed65c80aSWei Hu req.os_ver_build = osreldate % OS_BUILD_MOD; 1146ed65c80aSWei Hu strncpy(req.os_ver_str1, ostype, sizeof(req.os_ver_str1) - 1); 1147ed65c80aSWei Hu strncpy(req.os_ver_str2, osrelease, sizeof(req.os_ver_str2) - 1); 1148ed65c80aSWei Hu 1149ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1150ce110ea1SWei Hu if (err || resp.hdr.status) { 1151ce110ea1SWei Hu device_printf(gc->dev, 1152ce110ea1SWei Hu "VfVerifyVersionOutput: %d, status=0x%x\n", 1153ce110ea1SWei Hu err, resp.hdr.status); 1154ce110ea1SWei Hu return err ? err : EPROTO; 1155ce110ea1SWei Hu } 1156ce110ea1SWei Hu 1157ce110ea1SWei Hu return 0; 1158ce110ea1SWei Hu } 1159ce110ea1SWei Hu 1160ce110ea1SWei Hu int 1161ce110ea1SWei Hu mana_gd_register_device(struct gdma_dev *gd) 1162ce110ea1SWei Hu { 1163ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 1164ce110ea1SWei Hu struct gdma_register_device_resp resp = {}; 1165ce110ea1SWei Hu struct gdma_general_req req = {}; 1166ce110ea1SWei Hu int err; 1167ce110ea1SWei Hu 1168ce110ea1SWei Hu gd->pdid = INVALID_PDID; 1169ce110ea1SWei Hu gd->doorbell = INVALID_DOORBELL; 1170ce110ea1SWei Hu gd->gpa_mkey = INVALID_MEM_KEY; 1171ce110ea1SWei Hu 1172ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 1173ce110ea1SWei Hu sizeof(resp)); 1174ce110ea1SWei Hu 1175ce110ea1SWei Hu req.hdr.dev_id = gd->dev_id; 1176ce110ea1SWei Hu 1177ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1178ce110ea1SWei Hu if (err || resp.hdr.status) { 1179ce110ea1SWei Hu device_printf(gc->dev, 1180ce110ea1SWei Hu "gdma_register_device_resp failed: %d, 0x%x\n", 1181ce110ea1SWei Hu err, resp.hdr.status); 1182ce110ea1SWei Hu return err ? err : -EPROTO; 1183ce110ea1SWei Hu } 1184ce110ea1SWei Hu 1185ce110ea1SWei Hu gd->pdid = resp.pdid; 1186ce110ea1SWei Hu gd->gpa_mkey = resp.gpa_mkey; 1187ce110ea1SWei Hu gd->doorbell = resp.db_id; 1188ce110ea1SWei Hu 1189ce110ea1SWei Hu mana_dbg(NULL, "mana device pdid %u, gpa_mkey %u, doorbell %u \n", 1190ce110ea1SWei Hu gd->pdid, gd->gpa_mkey, gd->doorbell); 1191ce110ea1SWei Hu 1192ce110ea1SWei Hu return 0; 1193ce110ea1SWei Hu } 1194ce110ea1SWei Hu 1195ce110ea1SWei Hu int 1196ce110ea1SWei Hu mana_gd_deregister_device(struct gdma_dev *gd) 1197ce110ea1SWei Hu { 1198ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 1199ce110ea1SWei Hu struct gdma_general_resp resp = {}; 1200ce110ea1SWei Hu struct gdma_general_req req = {}; 1201ce110ea1SWei Hu int err; 1202ce110ea1SWei Hu 1203ce110ea1SWei Hu if (gd->pdid == INVALID_PDID) 1204ce110ea1SWei Hu return EINVAL; 1205ce110ea1SWei Hu 1206ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 1207ce110ea1SWei Hu sizeof(resp)); 1208ce110ea1SWei Hu 1209ce110ea1SWei Hu req.hdr.dev_id = gd->dev_id; 1210ce110ea1SWei Hu 1211ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1212ce110ea1SWei Hu if (err || resp.hdr.status) { 1213ce110ea1SWei Hu device_printf(gc->dev, 1214ce110ea1SWei Hu "Failed to deregister device: %d, 0x%x\n", 1215ce110ea1SWei Hu err, resp.hdr.status); 1216ce110ea1SWei Hu if (!err) 1217ce110ea1SWei Hu err = EPROTO; 1218ce110ea1SWei Hu } 1219ce110ea1SWei Hu 1220ce110ea1SWei Hu gd->pdid = INVALID_PDID; 1221ce110ea1SWei Hu gd->doorbell = INVALID_DOORBELL; 1222ce110ea1SWei Hu gd->gpa_mkey = INVALID_MEM_KEY; 1223ce110ea1SWei Hu 1224ce110ea1SWei Hu return err; 1225ce110ea1SWei Hu } 1226ce110ea1SWei Hu 1227ce110ea1SWei Hu uint32_t 1228ce110ea1SWei Hu mana_gd_wq_avail_space(struct gdma_queue *wq) 1229ce110ea1SWei Hu { 1230ce110ea1SWei Hu uint32_t used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1231ce110ea1SWei Hu uint32_t wq_size = wq->queue_size; 1232ce110ea1SWei Hu 1233ce110ea1SWei Hu if (used_space > wq_size) { 1234ce110ea1SWei Hu mana_warn(NULL, "failed: used space %u > queue size %u\n", 1235ce110ea1SWei Hu used_space, wq_size); 1236ce110ea1SWei Hu } 1237ce110ea1SWei Hu 1238ce110ea1SWei Hu return wq_size - used_space; 1239ce110ea1SWei Hu } 1240ce110ea1SWei Hu 1241ce110ea1SWei Hu uint8_t * 1242ce110ea1SWei Hu mana_gd_get_wqe_ptr(const struct gdma_queue *wq, uint32_t wqe_offset) 1243ce110ea1SWei Hu { 1244ce110ea1SWei Hu uint32_t offset = 1245ce110ea1SWei Hu (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1246ce110ea1SWei Hu 1247ce110ea1SWei Hu if ((offset + GDMA_WQE_BU_SIZE) > wq->queue_size) { 1248ce110ea1SWei Hu mana_warn(NULL, "failed: write end out of queue bound %u, " 1249ce110ea1SWei Hu "queue size %u\n", 1250ce110ea1SWei Hu offset + GDMA_WQE_BU_SIZE, wq->queue_size); 1251ce110ea1SWei Hu } 1252ce110ea1SWei Hu 1253ce110ea1SWei Hu return (uint8_t *)wq->queue_mem_ptr + offset; 1254ce110ea1SWei Hu } 1255ce110ea1SWei Hu 1256ce110ea1SWei Hu static uint32_t 1257ce110ea1SWei Hu mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1258ce110ea1SWei Hu enum gdma_queue_type q_type, 1259ce110ea1SWei Hu uint32_t client_oob_size, uint32_t sgl_data_size, 1260ce110ea1SWei Hu uint8_t *wqe_ptr) 1261ce110ea1SWei Hu { 1262ce110ea1SWei Hu bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1263ce110ea1SWei Hu bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1264ce110ea1SWei Hu struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1265ce110ea1SWei Hu uint8_t *ptr; 1266ce110ea1SWei Hu 1267ce110ea1SWei Hu memset(header, 0, sizeof(struct gdma_wqe)); 1268ce110ea1SWei Hu header->num_sge = wqe_req->num_sge; 1269ce110ea1SWei Hu header->inline_oob_size_div4 = client_oob_size / sizeof(uint32_t); 1270ce110ea1SWei Hu 1271ce110ea1SWei Hu if (oob_in_sgl) { 1272ce110ea1SWei Hu if (!pad_data || wqe_req->num_sge < 2) { 1273ce110ea1SWei Hu mana_warn(NULL, "no pad_data or num_sge < 2\n"); 1274ce110ea1SWei Hu } 1275ce110ea1SWei Hu 1276ce110ea1SWei Hu header->client_oob_in_sgl = 1; 1277ce110ea1SWei Hu 1278ce110ea1SWei Hu if (pad_data) 1279ce110ea1SWei Hu header->last_vbytes = wqe_req->sgl[0].size; 1280ce110ea1SWei Hu } 1281ce110ea1SWei Hu 1282ce110ea1SWei Hu if (q_type == GDMA_SQ) 1283ce110ea1SWei Hu header->client_data_unit = wqe_req->client_data_unit; 1284ce110ea1SWei Hu 1285ce110ea1SWei Hu /* 1286ce110ea1SWei Hu * The size of gdma_wqe + client_oob_size must be less than or equal 1287ce110ea1SWei Hu * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1288ce110ea1SWei Hu * the queue memory buffer boundary. 1289ce110ea1SWei Hu */ 1290ce110ea1SWei Hu ptr = wqe_ptr + sizeof(header); 1291ce110ea1SWei Hu 1292ce110ea1SWei Hu if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1293ce110ea1SWei Hu memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1294ce110ea1SWei Hu 1295ce110ea1SWei Hu if (client_oob_size > wqe_req->inline_oob_size) 1296ce110ea1SWei Hu memset(ptr + wqe_req->inline_oob_size, 0, 1297ce110ea1SWei Hu client_oob_size - wqe_req->inline_oob_size); 1298ce110ea1SWei Hu } 1299ce110ea1SWei Hu 1300ce110ea1SWei Hu return sizeof(header) + client_oob_size; 1301ce110ea1SWei Hu } 1302ce110ea1SWei Hu 1303ce110ea1SWei Hu static void 1304ce110ea1SWei Hu mana_gd_write_sgl(struct gdma_queue *wq, uint8_t *wqe_ptr, 1305ce110ea1SWei Hu const struct gdma_wqe_request *wqe_req) 1306ce110ea1SWei Hu { 1307ce110ea1SWei Hu uint32_t sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1308ce110ea1SWei Hu const uint8_t *address = (uint8_t *)wqe_req->sgl; 1309ce110ea1SWei Hu uint8_t *base_ptr, *end_ptr; 1310ce110ea1SWei Hu uint32_t size_to_end; 1311ce110ea1SWei Hu 1312ce110ea1SWei Hu base_ptr = wq->queue_mem_ptr; 1313ce110ea1SWei Hu end_ptr = base_ptr + wq->queue_size; 1314ce110ea1SWei Hu size_to_end = (uint32_t)(end_ptr - wqe_ptr); 1315ce110ea1SWei Hu 1316ce110ea1SWei Hu if (size_to_end < sgl_size) { 1317ce110ea1SWei Hu memcpy(wqe_ptr, address, size_to_end); 1318ce110ea1SWei Hu 1319ce110ea1SWei Hu wqe_ptr = base_ptr; 1320ce110ea1SWei Hu address += size_to_end; 1321ce110ea1SWei Hu sgl_size -= size_to_end; 1322ce110ea1SWei Hu } 1323ce110ea1SWei Hu 1324ce110ea1SWei Hu memcpy(wqe_ptr, address, sgl_size); 1325ce110ea1SWei Hu } 1326ce110ea1SWei Hu 1327ce110ea1SWei Hu int 1328ce110ea1SWei Hu mana_gd_post_work_request(struct gdma_queue *wq, 1329ce110ea1SWei Hu const struct gdma_wqe_request *wqe_req, 1330ce110ea1SWei Hu struct gdma_posted_wqe_info *wqe_info) 1331ce110ea1SWei Hu { 1332ce110ea1SWei Hu uint32_t client_oob_size = wqe_req->inline_oob_size; 1333ce110ea1SWei Hu struct gdma_context *gc; 1334ce110ea1SWei Hu uint32_t sgl_data_size; 1335ce110ea1SWei Hu uint32_t max_wqe_size; 1336ce110ea1SWei Hu uint32_t wqe_size; 1337ce110ea1SWei Hu uint8_t *wqe_ptr; 1338ce110ea1SWei Hu 1339ce110ea1SWei Hu if (wqe_req->num_sge == 0) 1340ce110ea1SWei Hu return EINVAL; 1341ce110ea1SWei Hu 1342ce110ea1SWei Hu if (wq->type == GDMA_RQ) { 1343ce110ea1SWei Hu if (client_oob_size != 0) 1344ce110ea1SWei Hu return EINVAL; 1345ce110ea1SWei Hu 1346ce110ea1SWei Hu client_oob_size = INLINE_OOB_SMALL_SIZE; 1347ce110ea1SWei Hu 1348ce110ea1SWei Hu max_wqe_size = GDMA_MAX_RQE_SIZE; 1349ce110ea1SWei Hu } else { 1350ce110ea1SWei Hu if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1351ce110ea1SWei Hu client_oob_size != INLINE_OOB_LARGE_SIZE) 1352ce110ea1SWei Hu return EINVAL; 1353ce110ea1SWei Hu 1354ce110ea1SWei Hu max_wqe_size = GDMA_MAX_SQE_SIZE; 1355ce110ea1SWei Hu } 1356ce110ea1SWei Hu 1357ce110ea1SWei Hu sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1358ce110ea1SWei Hu wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1359ce110ea1SWei Hu sgl_data_size, GDMA_WQE_BU_SIZE); 1360ce110ea1SWei Hu if (wqe_size > max_wqe_size) 1361ce110ea1SWei Hu return EINVAL; 1362ce110ea1SWei Hu 1363ce110ea1SWei Hu if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1364ce110ea1SWei Hu gc = wq->gdma_dev->gdma_context; 1365ce110ea1SWei Hu device_printf(gc->dev, "unsuccessful flow control!\n"); 1366ce110ea1SWei Hu return ENOSPC; 1367ce110ea1SWei Hu } 1368ce110ea1SWei Hu 1369ce110ea1SWei Hu if (wqe_info) 1370ce110ea1SWei Hu wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1371ce110ea1SWei Hu 1372ce110ea1SWei Hu wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1373ce110ea1SWei Hu wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1374ce110ea1SWei Hu sgl_data_size, wqe_ptr); 1375ce110ea1SWei Hu if (wqe_ptr >= (uint8_t *)wq->queue_mem_ptr + wq->queue_size) 1376ce110ea1SWei Hu wqe_ptr -= wq->queue_size; 1377ce110ea1SWei Hu 1378ce110ea1SWei Hu mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1379ce110ea1SWei Hu 1380ce110ea1SWei Hu wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1381ce110ea1SWei Hu 1382ce110ea1SWei Hu bus_dmamap_sync(wq->mem_info.dma_tag, wq->mem_info.dma_map, 1383ce110ea1SWei Hu BUS_DMASYNC_PREWRITE); 1384ce110ea1SWei Hu 1385ce110ea1SWei Hu return 0; 1386ce110ea1SWei Hu } 1387ce110ea1SWei Hu 1388ce110ea1SWei Hu int 1389ce110ea1SWei Hu mana_gd_post_and_ring(struct gdma_queue *queue, 1390ce110ea1SWei Hu const struct gdma_wqe_request *wqe_req, 1391ce110ea1SWei Hu struct gdma_posted_wqe_info *wqe_info) 1392ce110ea1SWei Hu { 1393ce110ea1SWei Hu struct gdma_context *gc = queue->gdma_dev->gdma_context; 1394ce110ea1SWei Hu int err; 1395ce110ea1SWei Hu 1396ce110ea1SWei Hu err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1397ce110ea1SWei Hu if (err) 1398ce110ea1SWei Hu return err; 1399ce110ea1SWei Hu 1400ce110ea1SWei Hu mana_gd_wq_ring_doorbell(gc, queue); 1401ce110ea1SWei Hu 1402ce110ea1SWei Hu return 0; 1403ce110ea1SWei Hu } 1404ce110ea1SWei Hu 1405ce110ea1SWei Hu static int 1406ce110ea1SWei Hu mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1407ce110ea1SWei Hu { 1408ce110ea1SWei Hu unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1409ce110ea1SWei Hu struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1410ce110ea1SWei Hu uint32_t owner_bits, new_bits, old_bits; 1411ce110ea1SWei Hu struct gdma_cqe *cqe; 1412ce110ea1SWei Hu 1413ce110ea1SWei Hu cqe = &cq_cqe[cq->head % num_cqe]; 1414ce110ea1SWei Hu owner_bits = cqe->cqe_info.owner_bits; 1415ce110ea1SWei Hu 1416ce110ea1SWei Hu old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1417ce110ea1SWei Hu /* Return 0 if no more entries. */ 1418ce110ea1SWei Hu if (owner_bits == old_bits) 1419ce110ea1SWei Hu return 0; 1420ce110ea1SWei Hu 1421ce110ea1SWei Hu new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1422ce110ea1SWei Hu /* Return -1 if overflow detected. */ 1423027d0c1cSWei Hu if (owner_bits != new_bits) { 1424027d0c1cSWei Hu mana_warn(NULL, 1425027d0c1cSWei Hu "overflow detected! owner_bits %u != new_bits %u\n", 1426027d0c1cSWei Hu owner_bits, new_bits); 1427ce110ea1SWei Hu return -1; 1428027d0c1cSWei Hu } 1429ce110ea1SWei Hu 1430fa2d4a22SWei Hu rmb(); 1431fa2d4a22SWei Hu 1432ce110ea1SWei Hu comp->wq_num = cqe->cqe_info.wq_num; 1433ce110ea1SWei Hu comp->is_sq = cqe->cqe_info.is_sq; 1434ce110ea1SWei Hu memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1435ce110ea1SWei Hu 1436ce110ea1SWei Hu return 1; 1437ce110ea1SWei Hu } 1438ce110ea1SWei Hu 1439ce110ea1SWei Hu int 1440ce110ea1SWei Hu mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1441ce110ea1SWei Hu { 1442ce110ea1SWei Hu int cqe_idx; 1443ce110ea1SWei Hu int ret; 1444ce110ea1SWei Hu 1445ce110ea1SWei Hu bus_dmamap_sync(cq->mem_info.dma_tag, cq->mem_info.dma_map, 1446ce110ea1SWei Hu BUS_DMASYNC_POSTREAD); 1447ce110ea1SWei Hu 1448ce110ea1SWei Hu for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1449ce110ea1SWei Hu ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1450ce110ea1SWei Hu 1451ce110ea1SWei Hu if (ret < 0) { 1452ce110ea1SWei Hu cq->head -= cqe_idx; 1453ce110ea1SWei Hu return ret; 1454ce110ea1SWei Hu } 1455ce110ea1SWei Hu 1456ce110ea1SWei Hu if (ret == 0) 1457ce110ea1SWei Hu break; 1458ce110ea1SWei Hu 1459ce110ea1SWei Hu cq->head++; 1460ce110ea1SWei Hu } 1461ce110ea1SWei Hu 1462ce110ea1SWei Hu return cqe_idx; 1463ce110ea1SWei Hu } 1464ce110ea1SWei Hu 1465ce110ea1SWei Hu static void 1466ce110ea1SWei Hu mana_gd_intr(void *arg) 1467ce110ea1SWei Hu { 1468ce110ea1SWei Hu struct gdma_irq_context *gic = arg; 1469ce110ea1SWei Hu 1470ce110ea1SWei Hu if (gic->handler) { 1471ce110ea1SWei Hu gic->handler(gic->arg); 1472ce110ea1SWei Hu } 1473ce110ea1SWei Hu } 1474ce110ea1SWei Hu 1475ce110ea1SWei Hu int 1476ce110ea1SWei Hu mana_gd_alloc_res_map(uint32_t res_avail, 1477ce110ea1SWei Hu struct gdma_resource *r, const char *lock_name) 1478ce110ea1SWei Hu { 1479ce110ea1SWei Hu int n = howmany(res_avail, BITS_PER_LONG); 1480ce110ea1SWei Hu 1481ce110ea1SWei Hu r->map = 1482ce110ea1SWei Hu malloc(n * sizeof(unsigned long), M_DEVBUF, M_WAITOK | M_ZERO); 1483ce110ea1SWei Hu if (!r->map) 1484ce110ea1SWei Hu return ENOMEM; 1485ce110ea1SWei Hu 1486ce110ea1SWei Hu r->size = res_avail; 1487ce110ea1SWei Hu mtx_init(&r->lock_spin, lock_name, NULL, MTX_SPIN); 1488ce110ea1SWei Hu 1489ce110ea1SWei Hu mana_dbg(NULL, 1490ce110ea1SWei Hu "total res %u, total number of unsigned longs %u\n", 1491ce110ea1SWei Hu r->size, n); 1492ce110ea1SWei Hu return (0); 1493ce110ea1SWei Hu } 1494ce110ea1SWei Hu 1495ce110ea1SWei Hu void 1496ce110ea1SWei Hu mana_gd_free_res_map(struct gdma_resource *r) 1497ce110ea1SWei Hu { 1498ce110ea1SWei Hu if (!r || !r->map) 1499ce110ea1SWei Hu return; 1500ce110ea1SWei Hu 1501ce110ea1SWei Hu free(r->map, M_DEVBUF); 1502ce110ea1SWei Hu r->map = NULL; 1503ce110ea1SWei Hu r->size = 0; 1504ce110ea1SWei Hu } 1505ce110ea1SWei Hu 1506ce110ea1SWei Hu static void 1507ce110ea1SWei Hu mana_gd_init_registers(struct gdma_context *gc) 1508ce110ea1SWei Hu { 1509c5eed414SJohn Baldwin uintptr_t bar0_va = rman_get_bushandle(gc->bar0); 1510b685df31SWei Hu vm_paddr_t bar0_pa = rman_get_start(gc->bar0); 1511ce110ea1SWei Hu 1512ce110ea1SWei Hu gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 1513ce110ea1SWei Hu 1514ce110ea1SWei Hu gc->db_page_base = 1515c5eed414SJohn Baldwin (void *)(bar0_va + (size_t)mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET)); 1516ce110ea1SWei Hu 1517b685df31SWei Hu gc->phys_db_page_base = 1518b685df31SWei Hu bar0_pa + mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 1519b685df31SWei Hu 1520ce110ea1SWei Hu gc->shm_base = 1521c5eed414SJohn Baldwin (void *)(bar0_va + (size_t)mana_gd_r64(gc, GDMA_REG_SHM_OFFSET)); 1522ce110ea1SWei Hu 1523ce110ea1SWei Hu mana_dbg(NULL, "db_page_size 0x%xx, db_page_base %p," 1524ce110ea1SWei Hu " shm_base %p\n", 1525ce110ea1SWei Hu gc->db_page_size, gc->db_page_base, gc->shm_base); 1526ce110ea1SWei Hu } 1527ce110ea1SWei Hu 1528ce110ea1SWei Hu static struct resource * 1529ce110ea1SWei Hu mana_gd_alloc_bar(device_t dev, int bar) 1530ce110ea1SWei Hu { 1531ce110ea1SWei Hu struct resource *res = NULL; 1532ce110ea1SWei Hu struct pci_map *pm; 1533ce110ea1SWei Hu int rid, type; 1534ce110ea1SWei Hu 1535ce110ea1SWei Hu if (bar < 0 || bar > PCIR_MAX_BAR_0) 1536ce110ea1SWei Hu goto alloc_bar_out; 1537ce110ea1SWei Hu 1538ce110ea1SWei Hu pm = pci_find_bar(dev, PCIR_BAR(bar)); 1539ce110ea1SWei Hu if (!pm) 1540ce110ea1SWei Hu goto alloc_bar_out; 1541ce110ea1SWei Hu 1542ce110ea1SWei Hu if (PCI_BAR_IO(pm->pm_value)) 1543ce110ea1SWei Hu type = SYS_RES_IOPORT; 1544ce110ea1SWei Hu else 1545ce110ea1SWei Hu type = SYS_RES_MEMORY; 1546ce110ea1SWei Hu if (type < 0) 1547ce110ea1SWei Hu goto alloc_bar_out; 1548ce110ea1SWei Hu 1549ce110ea1SWei Hu rid = PCIR_BAR(bar); 1550ce110ea1SWei Hu res = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE); 1551ce110ea1SWei Hu #if defined(__amd64__) 1552ce110ea1SWei Hu if (res) 1553ce110ea1SWei Hu mana_dbg(NULL, "bar %d: rid 0x%x, type 0x%jx," 1554ce110ea1SWei Hu " handle 0x%jx\n", 1555ce110ea1SWei Hu bar, rid, res->r_bustag, res->r_bushandle); 1556ce110ea1SWei Hu #endif 1557ce110ea1SWei Hu 1558ce110ea1SWei Hu alloc_bar_out: 1559ce110ea1SWei Hu return (res); 1560ce110ea1SWei Hu } 1561ce110ea1SWei Hu 1562ce110ea1SWei Hu static void 1563ce110ea1SWei Hu mana_gd_free_pci_res(struct gdma_context *gc) 1564ce110ea1SWei Hu { 1565ce110ea1SWei Hu if (!gc || gc->dev) 1566ce110ea1SWei Hu return; 1567ce110ea1SWei Hu 1568ce110ea1SWei Hu if (gc->bar0 != NULL) { 1569ce110ea1SWei Hu bus_release_resource(gc->dev, SYS_RES_MEMORY, 1570ce110ea1SWei Hu PCIR_BAR(GDMA_BAR0), gc->bar0); 1571ce110ea1SWei Hu } 1572ce110ea1SWei Hu 1573ce110ea1SWei Hu if (gc->msix != NULL) { 1574ce110ea1SWei Hu bus_release_resource(gc->dev, SYS_RES_MEMORY, 1575ce110ea1SWei Hu gc->msix_rid, gc->msix); 1576ce110ea1SWei Hu } 1577ce110ea1SWei Hu } 1578ce110ea1SWei Hu 1579ce110ea1SWei Hu static int 1580ce110ea1SWei Hu mana_gd_setup_irqs(device_t dev) 1581ce110ea1SWei Hu { 1582ce110ea1SWei Hu unsigned int max_queues_per_port = mp_ncpus; 1583ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 1584ce110ea1SWei Hu struct gdma_irq_context *gic; 1585ce110ea1SWei Hu unsigned int max_irqs; 1586ce110ea1SWei Hu int nvec; 1587ce110ea1SWei Hu int rc, rcc, i; 1588ce110ea1SWei Hu 1589ce110ea1SWei Hu if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1590ce110ea1SWei Hu max_queues_per_port = MANA_MAX_NUM_QUEUES; 1591ce110ea1SWei Hu 1592ce110ea1SWei Hu /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 15931833cf13SWei Hu max_irqs = max_queues_per_port + 1; 1594ce110ea1SWei Hu 1595ce110ea1SWei Hu nvec = max_irqs; 1596ce110ea1SWei Hu rc = pci_alloc_msix(dev, &nvec); 1597ce110ea1SWei Hu if (unlikely(rc != 0)) { 1598ce110ea1SWei Hu device_printf(dev, 1599ce110ea1SWei Hu "Failed to allocate MSIX, vectors %d, error: %d\n", 1600ce110ea1SWei Hu nvec, rc); 1601ce110ea1SWei Hu rc = ENOSPC; 1602ce110ea1SWei Hu goto err_setup_irq_alloc; 1603ce110ea1SWei Hu } 1604ce110ea1SWei Hu 1605ce110ea1SWei Hu if (nvec != max_irqs) { 1606ce110ea1SWei Hu if (nvec == 1) { 1607ce110ea1SWei Hu device_printf(dev, 1608ce110ea1SWei Hu "Not enough number of MSI-x allocated: %d\n", 1609ce110ea1SWei Hu nvec); 1610ce110ea1SWei Hu rc = ENOSPC; 1611ce110ea1SWei Hu goto err_setup_irq_release; 1612ce110ea1SWei Hu } 1613ce110ea1SWei Hu device_printf(dev, "Allocated only %d MSI-x (%d requested)\n", 1614ce110ea1SWei Hu nvec, max_irqs); 1615ce110ea1SWei Hu } 1616ce110ea1SWei Hu 1617ce110ea1SWei Hu gc->irq_contexts = malloc(nvec * sizeof(struct gdma_irq_context), 1618ce110ea1SWei Hu M_DEVBUF, M_WAITOK | M_ZERO); 1619ce110ea1SWei Hu if (!gc->irq_contexts) { 1620ce110ea1SWei Hu rc = ENOMEM; 1621ce110ea1SWei Hu goto err_setup_irq_release; 1622ce110ea1SWei Hu } 1623ce110ea1SWei Hu 1624ce110ea1SWei Hu for (i = 0; i < nvec; i++) { 1625ce110ea1SWei Hu gic = &gc->irq_contexts[i]; 1626ce110ea1SWei Hu gic->msix_e.entry = i; 1627ce110ea1SWei Hu /* Vector starts from 1. */ 1628ce110ea1SWei Hu gic->msix_e.vector = i + 1; 1629ce110ea1SWei Hu gic->handler = NULL; 1630ce110ea1SWei Hu gic->arg = NULL; 1631ce110ea1SWei Hu 1632ce110ea1SWei Hu gic->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1633ce110ea1SWei Hu &gic->msix_e.vector, RF_ACTIVE | RF_SHAREABLE); 1634ce110ea1SWei Hu if (unlikely(gic->res == NULL)) { 1635ce110ea1SWei Hu rc = ENOMEM; 1636ce110ea1SWei Hu device_printf(dev, "could not allocate resource " 1637ce110ea1SWei Hu "for irq vector %d\n", gic->msix_e.vector); 1638ce110ea1SWei Hu goto err_setup_irq; 1639ce110ea1SWei Hu } 1640ce110ea1SWei Hu 1641ce110ea1SWei Hu rc = bus_setup_intr(dev, gic->res, 1642ce110ea1SWei Hu INTR_TYPE_NET | INTR_MPSAFE, NULL, mana_gd_intr, 1643ce110ea1SWei Hu gic, &gic->cookie); 1644ce110ea1SWei Hu if (unlikely(rc != 0)) { 1645ce110ea1SWei Hu device_printf(dev, "failed to register interrupt " 1646ce110ea1SWei Hu "handler for irq %ju vector %d: error %d\n", 1647ce110ea1SWei Hu rman_get_start(gic->res), gic->msix_e.vector, rc); 1648ce110ea1SWei Hu goto err_setup_irq; 1649ce110ea1SWei Hu } 1650ce110ea1SWei Hu gic->requested = true; 1651ce110ea1SWei Hu 1652ce110ea1SWei Hu mana_dbg(NULL, "added msix vector %d irq %ju\n", 1653ce110ea1SWei Hu gic->msix_e.vector, rman_get_start(gic->res)); 1654ce110ea1SWei Hu } 1655ce110ea1SWei Hu 1656ce110ea1SWei Hu rc = mana_gd_alloc_res_map(nvec, &gc->msix_resource, 1657ce110ea1SWei Hu "gdma msix res lock"); 1658ce110ea1SWei Hu if (rc != 0) { 1659ce110ea1SWei Hu device_printf(dev, "failed to allocate memory " 1660ce110ea1SWei Hu "for msix bitmap\n"); 1661ce110ea1SWei Hu goto err_setup_irq; 1662ce110ea1SWei Hu } 1663ce110ea1SWei Hu 1664ce110ea1SWei Hu gc->max_num_msix = nvec; 1665ce110ea1SWei Hu gc->num_msix_usable = nvec; 1666ce110ea1SWei Hu 1667ce110ea1SWei Hu mana_dbg(NULL, "setup %d msix interrupts\n", nvec); 1668ce110ea1SWei Hu 1669ce110ea1SWei Hu return (0); 1670ce110ea1SWei Hu 1671ce110ea1SWei Hu err_setup_irq: 1672ce110ea1SWei Hu for (; i >= 0; i--) { 1673ce110ea1SWei Hu gic = &gc->irq_contexts[i]; 1674ce110ea1SWei Hu rcc = 0; 1675ce110ea1SWei Hu 1676ce110ea1SWei Hu /* 1677ce110ea1SWei Hu * If gic->requested is true, we need to free both intr and 1678ce110ea1SWei Hu * resources. 1679ce110ea1SWei Hu */ 1680ce110ea1SWei Hu if (gic->requested) 1681ce110ea1SWei Hu rcc = bus_teardown_intr(dev, gic->res, gic->cookie); 1682ce110ea1SWei Hu if (unlikely(rcc != 0)) 1683ce110ea1SWei Hu device_printf(dev, "could not release " 1684ce110ea1SWei Hu "irq vector %d, error: %d\n", 1685ce110ea1SWei Hu gic->msix_e.vector, rcc); 1686ce110ea1SWei Hu 1687ce110ea1SWei Hu rcc = 0; 1688ce110ea1SWei Hu if (gic->res != NULL) { 1689ce110ea1SWei Hu rcc = bus_release_resource(dev, SYS_RES_IRQ, 1690ce110ea1SWei Hu gic->msix_e.vector, gic->res); 1691ce110ea1SWei Hu } 1692ce110ea1SWei Hu if (unlikely(rcc != 0)) 1693ce110ea1SWei Hu device_printf(dev, "dev has no parent while " 1694ce110ea1SWei Hu "releasing resource for irq vector %d\n", 1695ce110ea1SWei Hu gic->msix_e.vector); 1696ce110ea1SWei Hu gic->requested = false; 1697ce110ea1SWei Hu gic->res = NULL; 1698ce110ea1SWei Hu } 1699ce110ea1SWei Hu 1700ce110ea1SWei Hu free(gc->irq_contexts, M_DEVBUF); 1701ce110ea1SWei Hu gc->irq_contexts = NULL; 1702ce110ea1SWei Hu err_setup_irq_release: 1703ce110ea1SWei Hu pci_release_msi(dev); 1704ce110ea1SWei Hu err_setup_irq_alloc: 1705ce110ea1SWei Hu return (rc); 1706ce110ea1SWei Hu } 1707ce110ea1SWei Hu 1708ce110ea1SWei Hu static void 1709ce110ea1SWei Hu mana_gd_remove_irqs(device_t dev) 1710ce110ea1SWei Hu { 1711ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 1712ce110ea1SWei Hu struct gdma_irq_context *gic; 1713ce110ea1SWei Hu int rc, i; 1714ce110ea1SWei Hu 1715ce110ea1SWei Hu mana_gd_free_res_map(&gc->msix_resource); 1716ce110ea1SWei Hu 1717ce110ea1SWei Hu for (i = 0; i < gc->max_num_msix; i++) { 1718ce110ea1SWei Hu gic = &gc->irq_contexts[i]; 1719ce110ea1SWei Hu if (gic->requested) { 1720ce110ea1SWei Hu rc = bus_teardown_intr(dev, gic->res, gic->cookie); 1721ce110ea1SWei Hu if (unlikely(rc != 0)) { 1722ce110ea1SWei Hu device_printf(dev, "failed to tear down " 1723ce110ea1SWei Hu "irq vector %d, error: %d\n", 1724ce110ea1SWei Hu gic->msix_e.vector, rc); 1725ce110ea1SWei Hu } 1726ce110ea1SWei Hu gic->requested = false; 1727ce110ea1SWei Hu } 1728ce110ea1SWei Hu 1729ce110ea1SWei Hu if (gic->res != NULL) { 1730ce110ea1SWei Hu rc = bus_release_resource(dev, SYS_RES_IRQ, 1731ce110ea1SWei Hu gic->msix_e.vector, gic->res); 1732ce110ea1SWei Hu if (unlikely(rc != 0)) { 1733ce110ea1SWei Hu device_printf(dev, "dev has no parent while " 1734ce110ea1SWei Hu "releasing resource for irq vector %d\n", 1735ce110ea1SWei Hu gic->msix_e.vector); 1736ce110ea1SWei Hu } 1737ce110ea1SWei Hu gic->res = NULL; 1738ce110ea1SWei Hu } 1739ce110ea1SWei Hu } 1740ce110ea1SWei Hu 1741ce110ea1SWei Hu gc->max_num_msix = 0; 1742ce110ea1SWei Hu gc->num_msix_usable = 0; 1743ce110ea1SWei Hu free(gc->irq_contexts, M_DEVBUF); 1744ce110ea1SWei Hu gc->irq_contexts = NULL; 1745ce110ea1SWei Hu 1746ce110ea1SWei Hu pci_release_msi(dev); 1747ce110ea1SWei Hu } 1748ce110ea1SWei Hu 1749ce110ea1SWei Hu static int 1750ce110ea1SWei Hu mana_gd_probe(device_t dev) 1751ce110ea1SWei Hu { 1752ce110ea1SWei Hu mana_vendor_id_t *ent; 1753ce110ea1SWei Hu char adapter_name[60]; 1754ce110ea1SWei Hu uint16_t pci_vendor_id = 0; 1755ce110ea1SWei Hu uint16_t pci_device_id = 0; 1756ce110ea1SWei Hu 1757ce110ea1SWei Hu pci_vendor_id = pci_get_vendor(dev); 1758ce110ea1SWei Hu pci_device_id = pci_get_device(dev); 1759ce110ea1SWei Hu 1760ce110ea1SWei Hu ent = mana_id_table; 1761ce110ea1SWei Hu while (ent->vendor_id != 0) { 1762ce110ea1SWei Hu if ((pci_vendor_id == ent->vendor_id) && 1763ce110ea1SWei Hu (pci_device_id == ent->device_id)) { 1764ce110ea1SWei Hu mana_dbg(NULL, "vendor=%x device=%x\n", 1765ce110ea1SWei Hu pci_vendor_id, pci_device_id); 1766ce110ea1SWei Hu 1767ce110ea1SWei Hu sprintf(adapter_name, DEVICE_DESC); 1768ce110ea1SWei Hu device_set_desc_copy(dev, adapter_name); 1769ce110ea1SWei Hu return (BUS_PROBE_DEFAULT); 1770ce110ea1SWei Hu } 1771ce110ea1SWei Hu 1772ce110ea1SWei Hu ent++; 1773ce110ea1SWei Hu } 1774ce110ea1SWei Hu 1775ce110ea1SWei Hu return (ENXIO); 1776ce110ea1SWei Hu } 1777ce110ea1SWei Hu 1778ce110ea1SWei Hu /** 1779ce110ea1SWei Hu * mana_attach - Device Initialization Routine 1780ce110ea1SWei Hu * @dev: device information struct 1781ce110ea1SWei Hu * 1782ce110ea1SWei Hu * Returns 0 on success, otherwise on failure. 1783ce110ea1SWei Hu * 1784ce110ea1SWei Hu * mana_attach initializes a GDMA adapter identified by a device structure. 1785ce110ea1SWei Hu **/ 1786ce110ea1SWei Hu static int 1787ce110ea1SWei Hu mana_gd_attach(device_t dev) 1788ce110ea1SWei Hu { 1789ce110ea1SWei Hu struct gdma_context *gc; 1790ce110ea1SWei Hu int msix_rid; 1791ce110ea1SWei Hu int rc; 1792ce110ea1SWei Hu 1793ce110ea1SWei Hu gc = device_get_softc(dev); 1794ce110ea1SWei Hu gc->dev = dev; 1795ce110ea1SWei Hu 1796ce110ea1SWei Hu pci_enable_io(dev, SYS_RES_IOPORT); 1797ce110ea1SWei Hu pci_enable_io(dev, SYS_RES_MEMORY); 1798ce110ea1SWei Hu 1799ce110ea1SWei Hu pci_enable_busmaster(dev); 1800ce110ea1SWei Hu 1801ce110ea1SWei Hu gc->bar0 = mana_gd_alloc_bar(dev, GDMA_BAR0); 1802ce110ea1SWei Hu if (unlikely(gc->bar0 == NULL)) { 1803ce110ea1SWei Hu device_printf(dev, 1804ce110ea1SWei Hu "unable to allocate bus resource for bar0!\n"); 1805ce110ea1SWei Hu rc = ENOMEM; 1806ce110ea1SWei Hu goto err_disable_dev; 1807ce110ea1SWei Hu } 1808ce110ea1SWei Hu 1809ce110ea1SWei Hu /* Store bar0 tage and handle for quick access */ 1810ce110ea1SWei Hu gc->gd_bus.bar0_t = rman_get_bustag(gc->bar0); 1811ce110ea1SWei Hu gc->gd_bus.bar0_h = rman_get_bushandle(gc->bar0); 1812ce110ea1SWei Hu 1813ce110ea1SWei Hu /* Map MSI-x vector table */ 1814ce110ea1SWei Hu msix_rid = pci_msix_table_bar(dev); 1815ce110ea1SWei Hu 1816ce110ea1SWei Hu mana_dbg(NULL, "msix_rid 0x%x\n", msix_rid); 1817ce110ea1SWei Hu 1818ce110ea1SWei Hu gc->msix = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1819ce110ea1SWei Hu &msix_rid, RF_ACTIVE); 1820ce110ea1SWei Hu if (unlikely(gc->msix == NULL)) { 1821ce110ea1SWei Hu device_printf(dev, 1822ce110ea1SWei Hu "unable to allocate bus resource for msix!\n"); 1823ce110ea1SWei Hu rc = ENOMEM; 1824ce110ea1SWei Hu goto err_free_pci_res; 1825ce110ea1SWei Hu } 1826ce110ea1SWei Hu gc->msix_rid = msix_rid; 1827ce110ea1SWei Hu 1828ce110ea1SWei Hu if (unlikely(gc->gd_bus.bar0_h == 0)) { 1829ce110ea1SWei Hu device_printf(dev, "failed to map bar0!\n"); 1830ce110ea1SWei Hu rc = ENXIO; 1831ce110ea1SWei Hu goto err_free_pci_res; 1832ce110ea1SWei Hu } 1833ce110ea1SWei Hu 1834ce110ea1SWei Hu mana_gd_init_registers(gc); 1835ce110ea1SWei Hu 1836ce110ea1SWei Hu mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1837ce110ea1SWei Hu 1838ce110ea1SWei Hu rc = mana_gd_setup_irqs(dev); 1839ce110ea1SWei Hu if (rc) { 1840ce110ea1SWei Hu goto err_free_pci_res; 1841ce110ea1SWei Hu } 1842ce110ea1SWei Hu 1843ce110ea1SWei Hu sx_init(&gc->eq_test_event_sx, "gdma test event sx"); 1844ce110ea1SWei Hu 1845ce110ea1SWei Hu rc = mana_hwc_create_channel(gc); 1846ce110ea1SWei Hu if (rc) { 1847ce110ea1SWei Hu mana_dbg(NULL, "Failed to create hwc channel\n"); 1848ce110ea1SWei Hu if (rc == EIO) 1849ce110ea1SWei Hu goto err_clean_up_gdma; 1850ce110ea1SWei Hu else 1851ce110ea1SWei Hu goto err_remove_irq; 1852ce110ea1SWei Hu } 1853ce110ea1SWei Hu 1854ce110ea1SWei Hu rc = mana_gd_verify_vf_version(dev); 1855ce110ea1SWei Hu if (rc) { 1856ce110ea1SWei Hu mana_dbg(NULL, "Failed to verify vf\n"); 1857ce110ea1SWei Hu goto err_clean_up_gdma; 1858ce110ea1SWei Hu } 1859ce110ea1SWei Hu 1860ce110ea1SWei Hu rc = mana_gd_query_max_resources(dev); 1861ce110ea1SWei Hu if (rc) { 1862ce110ea1SWei Hu mana_dbg(NULL, "Failed to query max resources\n"); 1863ce110ea1SWei Hu goto err_clean_up_gdma; 1864ce110ea1SWei Hu } 1865ce110ea1SWei Hu 1866ce110ea1SWei Hu rc = mana_gd_detect_devices(dev); 1867ce110ea1SWei Hu if (rc) { 1868ce110ea1SWei Hu mana_dbg(NULL, "Failed to detect mana device\n"); 1869ce110ea1SWei Hu goto err_clean_up_gdma; 1870ce110ea1SWei Hu } 1871ce110ea1SWei Hu 1872ce110ea1SWei Hu rc = mana_probe(&gc->mana); 1873ce110ea1SWei Hu if (rc) { 1874ce110ea1SWei Hu mana_dbg(NULL, "Failed to probe mana device\n"); 1875ce110ea1SWei Hu goto err_clean_up_gdma; 1876ce110ea1SWei Hu } 1877ce110ea1SWei Hu 1878ce110ea1SWei Hu return (0); 1879ce110ea1SWei Hu 1880ce110ea1SWei Hu err_clean_up_gdma: 1881ce110ea1SWei Hu mana_hwc_destroy_channel(gc); 1882ce110ea1SWei Hu err_remove_irq: 1883ce110ea1SWei Hu mana_gd_remove_irqs(dev); 1884ce110ea1SWei Hu err_free_pci_res: 1885ce110ea1SWei Hu mana_gd_free_pci_res(gc); 1886ce110ea1SWei Hu err_disable_dev: 1887ce110ea1SWei Hu pci_disable_busmaster(dev); 1888ce110ea1SWei Hu 1889ce110ea1SWei Hu return(rc); 1890ce110ea1SWei Hu } 1891ce110ea1SWei Hu 1892ce110ea1SWei Hu /** 1893ce110ea1SWei Hu * mana_detach - Device Removal Routine 1894ce110ea1SWei Hu * @pdev: device information struct 1895ce110ea1SWei Hu * 1896ce110ea1SWei Hu * mana_detach is called by the device subsystem to alert the driver 1897ce110ea1SWei Hu * that it should release a PCI device. 1898ce110ea1SWei Hu **/ 1899ce110ea1SWei Hu static int 1900ce110ea1SWei Hu mana_gd_detach(device_t dev) 1901ce110ea1SWei Hu { 1902ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 1903ce110ea1SWei Hu 1904ce110ea1SWei Hu mana_remove(&gc->mana); 1905ce110ea1SWei Hu 1906ce110ea1SWei Hu mana_hwc_destroy_channel(gc); 1907ce110ea1SWei Hu 1908ce110ea1SWei Hu mana_gd_remove_irqs(dev); 1909ce110ea1SWei Hu 1910ce110ea1SWei Hu mana_gd_free_pci_res(gc); 1911ce110ea1SWei Hu 1912ce110ea1SWei Hu pci_disable_busmaster(dev); 1913ce110ea1SWei Hu 1914ce110ea1SWei Hu return (bus_generic_detach(dev)); 1915ce110ea1SWei Hu } 1916ce110ea1SWei Hu 1917ce110ea1SWei Hu 1918ce110ea1SWei Hu /********************************************************************* 1919ce110ea1SWei Hu * FreeBSD Device Interface Entry Points 1920ce110ea1SWei Hu *********************************************************************/ 1921ce110ea1SWei Hu 1922ce110ea1SWei Hu static device_method_t mana_methods[] = { 1923ce110ea1SWei Hu /* Device interface */ 1924ce110ea1SWei Hu DEVMETHOD(device_probe, mana_gd_probe), 1925ce110ea1SWei Hu DEVMETHOD(device_attach, mana_gd_attach), 1926ce110ea1SWei Hu DEVMETHOD(device_detach, mana_gd_detach), 1927ce110ea1SWei Hu DEVMETHOD_END 1928ce110ea1SWei Hu }; 1929ce110ea1SWei Hu 1930ce110ea1SWei Hu static driver_t mana_driver = { 1931ce110ea1SWei Hu "mana", mana_methods, sizeof(struct gdma_context), 1932ce110ea1SWei Hu }; 1933ce110ea1SWei Hu 1934825718a3SJohn Baldwin DRIVER_MODULE(mana, pci, mana_driver, 0, 0); 1935ce110ea1SWei Hu MODULE_PNP_INFO("U16:vendor;U16:device", pci, mana, mana_id_table, 1936ce110ea1SWei Hu nitems(mana_id_table) - 1); 1937ce110ea1SWei Hu MODULE_DEPEND(mana, pci, 1, 1, 1); 1938ce110ea1SWei Hu MODULE_DEPEND(mana, ether, 1, 1, 1); 1939ce110ea1SWei Hu 1940ce110ea1SWei Hu /*********************************************************************/ 1941