1ce110ea1SWei Hu /*- 2ce110ea1SWei Hu * SPDX-License-Identifier: BSD-2-Clause 3ce110ea1SWei Hu * 4ce110ea1SWei Hu * Copyright (c) 2021 Microsoft Corp. 5ce110ea1SWei Hu * All rights reserved. 6ce110ea1SWei Hu * 7ce110ea1SWei Hu * Redistribution and use in source and binary forms, with or without 8ce110ea1SWei Hu * modification, are permitted provided that the following conditions 9ce110ea1SWei Hu * are met: 10ce110ea1SWei Hu * 11ce110ea1SWei Hu * 1. Redistributions of source code must retain the above copyright 12ce110ea1SWei Hu * notice, this list of conditions and the following disclaimer. 13ce110ea1SWei Hu * 14ce110ea1SWei Hu * 2. Redistributions in binary form must reproduce the above copyright 15ce110ea1SWei Hu * notice, this list of conditions and the following disclaimer in the 16ce110ea1SWei Hu * documentation and/or other materials provided with the distribution. 17ce110ea1SWei Hu * 18ce110ea1SWei Hu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19ce110ea1SWei Hu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20ce110ea1SWei Hu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21ce110ea1SWei Hu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22ce110ea1SWei Hu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23ce110ea1SWei Hu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24ce110ea1SWei Hu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25ce110ea1SWei Hu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26ce110ea1SWei Hu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27ce110ea1SWei Hu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28ce110ea1SWei Hu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29ce110ea1SWei Hu */ 30ce110ea1SWei Hu #include <sys/cdefs.h> 31ce110ea1SWei Hu __FBSDID("$FreeBSD$"); 32ce110ea1SWei Hu 33ce110ea1SWei Hu #include <sys/param.h> 34ce110ea1SWei Hu #include <sys/systm.h> 35ce110ea1SWei Hu #include <sys/bus.h> 36ce110ea1SWei Hu #include <sys/kernel.h> 37ce110ea1SWei Hu #include <sys/kthread.h> 38ce110ea1SWei Hu #include <sys/malloc.h> 39ce110ea1SWei Hu #include <sys/mbuf.h> 40ce110ea1SWei Hu #include <sys/module.h> 41ce110ea1SWei Hu #include <sys/rman.h> 42ce110ea1SWei Hu #include <sys/smp.h> 43ce110ea1SWei Hu #include <sys/socket.h> 44ce110ea1SWei Hu #include <sys/sysctl.h> 45ce110ea1SWei Hu #include <sys/taskqueue.h> 46ce110ea1SWei Hu #include <sys/time.h> 47ce110ea1SWei Hu #include <sys/eventhandler.h> 48ce110ea1SWei Hu 49ce110ea1SWei Hu #include <machine/bus.h> 50ce110ea1SWei Hu #include <machine/resource.h> 51ce110ea1SWei Hu #include <machine/in_cksum.h> 52ce110ea1SWei Hu 53ce110ea1SWei Hu #include <net/if.h> 54ce110ea1SWei Hu #include <net/if_var.h> 55ce110ea1SWei Hu 56ce110ea1SWei Hu #include <dev/pci/pcivar.h> 57ce110ea1SWei Hu #include <dev/pci/pcireg.h> 58ce110ea1SWei Hu 59ce110ea1SWei Hu #include "gdma_util.h" 60ce110ea1SWei Hu #include "mana.h" 61ce110ea1SWei Hu 62ce110ea1SWei Hu 63ce110ea1SWei Hu static mana_vendor_id_t mana_id_table[] = { 64ce110ea1SWei Hu { PCI_VENDOR_ID_MICROSOFT, PCI_DEV_ID_MANA_VF}, 65ce110ea1SWei Hu /* Last entry */ 66ce110ea1SWei Hu { 0, 0} 67ce110ea1SWei Hu }; 68ce110ea1SWei Hu 69ce110ea1SWei Hu static inline uint32_t 70ce110ea1SWei Hu mana_gd_r32(struct gdma_context *g, uint64_t offset) 71ce110ea1SWei Hu { 72ce110ea1SWei Hu uint32_t v = bus_space_read_4(g->gd_bus.bar0_t, 73ce110ea1SWei Hu g->gd_bus.bar0_h, offset); 74ce110ea1SWei Hu rmb(); 75ce110ea1SWei Hu return (v); 76ce110ea1SWei Hu } 77ce110ea1SWei Hu 78ce110ea1SWei Hu #if defined(__amd64__) 79ce110ea1SWei Hu static inline uint64_t 80ce110ea1SWei Hu mana_gd_r64(struct gdma_context *g, uint64_t offset) 81ce110ea1SWei Hu { 82ce110ea1SWei Hu uint64_t v = bus_space_read_8(g->gd_bus.bar0_t, 83ce110ea1SWei Hu g->gd_bus.bar0_h, offset); 84ce110ea1SWei Hu rmb(); 85ce110ea1SWei Hu return (v); 86ce110ea1SWei Hu } 87ce110ea1SWei Hu #else 88ce110ea1SWei Hu static inline uint64_t 89ce110ea1SWei Hu mana_gd_r64(struct gdma_context *g, uint64_t offset) 90ce110ea1SWei Hu { 91ce110ea1SWei Hu uint64_t v; 92ce110ea1SWei Hu uint32_t *vp = (uint32_t *)&v; 93ce110ea1SWei Hu 94ce110ea1SWei Hu *vp = mana_gd_r32(g, offset); 95ce110ea1SWei Hu *(vp + 1) = mana_gd_r32(g, offset + 4); 96ce110ea1SWei Hu rmb(); 97ce110ea1SWei Hu return (v); 98ce110ea1SWei Hu } 99ce110ea1SWei Hu #endif 100ce110ea1SWei Hu 101ce110ea1SWei Hu static int 102ce110ea1SWei Hu mana_gd_query_max_resources(device_t dev) 103ce110ea1SWei Hu { 104ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 105ce110ea1SWei Hu struct gdma_query_max_resources_resp resp = {}; 106ce110ea1SWei Hu struct gdma_general_req req = {}; 107ce110ea1SWei Hu int err; 108ce110ea1SWei Hu 109ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 110ce110ea1SWei Hu sizeof(req), sizeof(resp)); 111ce110ea1SWei Hu 112ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 113ce110ea1SWei Hu if (err || resp.hdr.status) { 114ce110ea1SWei Hu device_printf(gc->dev, 115ce110ea1SWei Hu "Failed to query resource info: %d, 0x%x\n", 116ce110ea1SWei Hu err, resp.hdr.status); 117ce110ea1SWei Hu return err ? err : EPROTO; 118ce110ea1SWei Hu } 119ce110ea1SWei Hu 120ce110ea1SWei Hu mana_dbg(NULL, "max_msix %u, max_eq %u, max_cq %u, " 121ce110ea1SWei Hu "max_sq %u, max_rq %u\n", 122ce110ea1SWei Hu resp.max_msix, resp.max_eq, resp.max_cq, 123ce110ea1SWei Hu resp.max_sq, resp.max_rq); 124ce110ea1SWei Hu 125ce110ea1SWei Hu if (gc->num_msix_usable > resp.max_msix) 126ce110ea1SWei Hu gc->num_msix_usable = resp.max_msix; 127ce110ea1SWei Hu 128ce110ea1SWei Hu if (gc->num_msix_usable <= 1) 129ce110ea1SWei Hu return ENOSPC; 130ce110ea1SWei Hu 131ce110ea1SWei Hu gc->max_num_queues = mp_ncpus; 132ce110ea1SWei Hu if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 133ce110ea1SWei Hu gc->max_num_queues = MANA_MAX_NUM_QUEUES; 134ce110ea1SWei Hu 135ce110ea1SWei Hu if (gc->max_num_queues > resp.max_eq) 136ce110ea1SWei Hu gc->max_num_queues = resp.max_eq; 137ce110ea1SWei Hu 138ce110ea1SWei Hu if (gc->max_num_queues > resp.max_cq) 139ce110ea1SWei Hu gc->max_num_queues = resp.max_cq; 140ce110ea1SWei Hu 141ce110ea1SWei Hu if (gc->max_num_queues > resp.max_sq) 142ce110ea1SWei Hu gc->max_num_queues = resp.max_sq; 143ce110ea1SWei Hu 144ce110ea1SWei Hu if (gc->max_num_queues > resp.max_rq) 145ce110ea1SWei Hu gc->max_num_queues = resp.max_rq; 146ce110ea1SWei Hu 147ce110ea1SWei Hu return 0; 148ce110ea1SWei Hu } 149ce110ea1SWei Hu 150ce110ea1SWei Hu static int 151ce110ea1SWei Hu mana_gd_detect_devices(device_t dev) 152ce110ea1SWei Hu { 153ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 154ce110ea1SWei Hu struct gdma_list_devices_resp resp = {}; 155ce110ea1SWei Hu struct gdma_general_req req = {}; 156ce110ea1SWei Hu struct gdma_dev_id gd_dev; 157ce110ea1SWei Hu uint32_t i, max_num_devs; 158ce110ea1SWei Hu uint16_t dev_type; 159ce110ea1SWei Hu int err; 160ce110ea1SWei Hu 161ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 162ce110ea1SWei Hu sizeof(resp)); 163ce110ea1SWei Hu 164ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 165ce110ea1SWei Hu if (err || resp.hdr.status) { 166ce110ea1SWei Hu device_printf(gc->dev, 167ce110ea1SWei Hu "Failed to detect devices: %d, 0x%x\n", err, 168ce110ea1SWei Hu resp.hdr.status); 169ce110ea1SWei Hu return err ? err : EPROTO; 170ce110ea1SWei Hu } 171ce110ea1SWei Hu 172ce110ea1SWei Hu max_num_devs = min_t(uint32_t, MAX_NUM_GDMA_DEVICES, resp.num_of_devs); 173ce110ea1SWei Hu 174ce110ea1SWei Hu for (i = 0; i < max_num_devs; i++) { 175ce110ea1SWei Hu gd_dev = resp.devs[i]; 176ce110ea1SWei Hu dev_type = gd_dev.type; 177ce110ea1SWei Hu 178ce110ea1SWei Hu mana_dbg(NULL, "gdma dev %d, type %u\n", 179ce110ea1SWei Hu i, dev_type); 180ce110ea1SWei Hu 181ce110ea1SWei Hu /* HWC is already detected in mana_hwc_create_channel(). */ 182ce110ea1SWei Hu if (dev_type == GDMA_DEVICE_HWC) 183ce110ea1SWei Hu continue; 184ce110ea1SWei Hu 185ce110ea1SWei Hu if (dev_type == GDMA_DEVICE_MANA) { 186ce110ea1SWei Hu gc->mana.gdma_context = gc; 187ce110ea1SWei Hu gc->mana.dev_id = gd_dev; 188ce110ea1SWei Hu } 189ce110ea1SWei Hu } 190ce110ea1SWei Hu 191ce110ea1SWei Hu return gc->mana.dev_id.type == 0 ? ENODEV : 0; 192ce110ea1SWei Hu } 193ce110ea1SWei Hu 194ce110ea1SWei Hu int 195ce110ea1SWei Hu mana_gd_send_request(struct gdma_context *gc, uint32_t req_len, 196ce110ea1SWei Hu const void *req, uint32_t resp_len, void *resp) 197ce110ea1SWei Hu { 198ce110ea1SWei Hu struct hw_channel_context *hwc = gc->hwc.driver_data; 199ce110ea1SWei Hu 200ce110ea1SWei Hu return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 201ce110ea1SWei Hu } 202ce110ea1SWei Hu 203ce110ea1SWei Hu void 204ce110ea1SWei Hu mana_gd_dma_map_paddr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 205ce110ea1SWei Hu { 206ce110ea1SWei Hu bus_addr_t *paddr = arg; 207ce110ea1SWei Hu 208ce110ea1SWei Hu if (error) 209ce110ea1SWei Hu return; 210ce110ea1SWei Hu 211ce110ea1SWei Hu KASSERT(nseg == 1, ("too many segments %d!", nseg)); 212ce110ea1SWei Hu *paddr = segs->ds_addr; 213ce110ea1SWei Hu } 214ce110ea1SWei Hu 215ce110ea1SWei Hu int 216ce110ea1SWei Hu mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 217ce110ea1SWei Hu struct gdma_mem_info *gmi) 218ce110ea1SWei Hu { 219ce110ea1SWei Hu bus_addr_t dma_handle; 220ce110ea1SWei Hu void *buf; 221ce110ea1SWei Hu int err; 222ce110ea1SWei Hu 223ce110ea1SWei Hu if (!gc || !gmi) 224ce110ea1SWei Hu return EINVAL; 225ce110ea1SWei Hu 226ce110ea1SWei Hu if (length < PAGE_SIZE || (length != roundup_pow_of_two(length))) 227ce110ea1SWei Hu return EINVAL; 228ce110ea1SWei Hu 229ce110ea1SWei Hu err = bus_dma_tag_create(bus_get_dma_tag(gc->dev), /* parent */ 230ce110ea1SWei Hu PAGE_SIZE, 0, /* alignment, boundary */ 231ce110ea1SWei Hu BUS_SPACE_MAXADDR, /* lowaddr */ 232ce110ea1SWei Hu BUS_SPACE_MAXADDR, /* highaddr */ 233ce110ea1SWei Hu NULL, NULL, /* filter, filterarg */ 234ce110ea1SWei Hu length, /* maxsize */ 235ce110ea1SWei Hu 1, /* nsegments */ 236ce110ea1SWei Hu length, /* maxsegsize */ 237ce110ea1SWei Hu 0, /* flags */ 238ce110ea1SWei Hu NULL, NULL, /* lockfunc, lockfuncarg*/ 239ce110ea1SWei Hu &gmi->dma_tag); 240ce110ea1SWei Hu if (err) { 241ce110ea1SWei Hu device_printf(gc->dev, 242ce110ea1SWei Hu "failed to create dma tag, err: %d\n", err); 243ce110ea1SWei Hu return (err); 244ce110ea1SWei Hu } 245ce110ea1SWei Hu 246ce110ea1SWei Hu /* 247ce110ea1SWei Hu * Must have BUS_DMA_ZERO flag to clear the dma memory. 248ce110ea1SWei Hu * Otherwise the queue overflow detection mechanism does 249ce110ea1SWei Hu * not work. 250ce110ea1SWei Hu */ 251ce110ea1SWei Hu err = bus_dmamem_alloc(gmi->dma_tag, &buf, 252ce110ea1SWei Hu BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &gmi->dma_map); 253ce110ea1SWei Hu if (err) { 254ce110ea1SWei Hu device_printf(gc->dev, 255ce110ea1SWei Hu "failed to alloc dma mem, err: %d\n", err); 256ce110ea1SWei Hu bus_dma_tag_destroy(gmi->dma_tag); 257ce110ea1SWei Hu return (err); 258ce110ea1SWei Hu } 259ce110ea1SWei Hu 260ce110ea1SWei Hu err = bus_dmamap_load(gmi->dma_tag, gmi->dma_map, buf, 261ce110ea1SWei Hu length, mana_gd_dma_map_paddr, &dma_handle, BUS_DMA_NOWAIT); 262ce110ea1SWei Hu if (err) { 263ce110ea1SWei Hu device_printf(gc->dev, 264ce110ea1SWei Hu "failed to load dma mem, err: %d\n", err); 265ce110ea1SWei Hu bus_dmamem_free(gmi->dma_tag, buf, gmi->dma_map); 266ce110ea1SWei Hu bus_dma_tag_destroy(gmi->dma_tag); 267ce110ea1SWei Hu return (err); 268ce110ea1SWei Hu } 269ce110ea1SWei Hu 270ce110ea1SWei Hu gmi->dev = gc->dev; 271ce110ea1SWei Hu gmi->dma_handle = dma_handle; 272ce110ea1SWei Hu gmi->virt_addr = buf; 273ce110ea1SWei Hu gmi->length = length; 274ce110ea1SWei Hu 275ce110ea1SWei Hu return 0; 276ce110ea1SWei Hu } 277ce110ea1SWei Hu 278ce110ea1SWei Hu void 279ce110ea1SWei Hu mana_gd_free_memory(struct gdma_mem_info *gmi) 280ce110ea1SWei Hu { 281ce110ea1SWei Hu bus_dmamap_unload(gmi->dma_tag, gmi->dma_map); 282ce110ea1SWei Hu bus_dmamem_free(gmi->dma_tag, gmi->virt_addr, gmi->dma_map); 283ce110ea1SWei Hu bus_dma_tag_destroy(gmi->dma_tag); 284ce110ea1SWei Hu } 285ce110ea1SWei Hu 286ce110ea1SWei Hu static int 287ce110ea1SWei Hu mana_gd_create_hw_eq(struct gdma_context *gc, 288ce110ea1SWei Hu struct gdma_queue *queue) 289ce110ea1SWei Hu { 290ce110ea1SWei Hu struct gdma_create_queue_resp resp = {}; 291ce110ea1SWei Hu struct gdma_create_queue_req req = {}; 292ce110ea1SWei Hu int err; 293ce110ea1SWei Hu 294ce110ea1SWei Hu if (queue->type != GDMA_EQ) 295ce110ea1SWei Hu return EINVAL; 296ce110ea1SWei Hu 297ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 298ce110ea1SWei Hu sizeof(req), sizeof(resp)); 299ce110ea1SWei Hu 300ce110ea1SWei Hu req.hdr.dev_id = queue->gdma_dev->dev_id; 301ce110ea1SWei Hu req.type = queue->type; 302ce110ea1SWei Hu req.pdid = queue->gdma_dev->pdid; 303ce110ea1SWei Hu req.doolbell_id = queue->gdma_dev->doorbell; 304ce110ea1SWei Hu req.gdma_region = queue->mem_info.gdma_region; 305ce110ea1SWei Hu req.queue_size = queue->queue_size; 306ce110ea1SWei Hu req.log2_throttle_limit = queue->eq.log2_throttle_limit; 307ce110ea1SWei Hu req.eq_pci_msix_index = queue->eq.msix_index; 308ce110ea1SWei Hu 309ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 310ce110ea1SWei Hu if (err || resp.hdr.status) { 311ce110ea1SWei Hu device_printf(gc->dev, 312ce110ea1SWei Hu "Failed to create queue: %d, 0x%x\n", 313ce110ea1SWei Hu err, resp.hdr.status); 314ce110ea1SWei Hu return err ? err : EPROTO; 315ce110ea1SWei Hu } 316ce110ea1SWei Hu 317ce110ea1SWei Hu queue->id = resp.queue_index; 318ce110ea1SWei Hu queue->eq.disable_needed = true; 319ce110ea1SWei Hu queue->mem_info.gdma_region = GDMA_INVALID_DMA_REGION; 320ce110ea1SWei Hu return 0; 321ce110ea1SWei Hu } 322ce110ea1SWei Hu 323ce110ea1SWei Hu static 324ce110ea1SWei Hu int mana_gd_disable_queue(struct gdma_queue *queue) 325ce110ea1SWei Hu { 326ce110ea1SWei Hu struct gdma_context *gc = queue->gdma_dev->gdma_context; 327ce110ea1SWei Hu struct gdma_disable_queue_req req = {}; 328ce110ea1SWei Hu struct gdma_general_resp resp = {}; 329ce110ea1SWei Hu int err; 330ce110ea1SWei Hu 331ce110ea1SWei Hu if (queue->type != GDMA_EQ) 332ce110ea1SWei Hu mana_warn(NULL, "Not event queue type 0x%x\n", 333ce110ea1SWei Hu queue->type); 334ce110ea1SWei Hu 335ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 336ce110ea1SWei Hu sizeof(req), sizeof(resp)); 337ce110ea1SWei Hu 338ce110ea1SWei Hu req.hdr.dev_id = queue->gdma_dev->dev_id; 339ce110ea1SWei Hu req.type = queue->type; 340ce110ea1SWei Hu req.queue_index = queue->id; 341ce110ea1SWei Hu req.alloc_res_id_on_creation = 1; 342ce110ea1SWei Hu 343ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 344ce110ea1SWei Hu if (err || resp.hdr.status) { 345ce110ea1SWei Hu device_printf(gc->dev, 346ce110ea1SWei Hu "Failed to disable queue: %d, 0x%x\n", err, 347ce110ea1SWei Hu resp.hdr.status); 348ce110ea1SWei Hu return err ? err : EPROTO; 349ce110ea1SWei Hu } 350ce110ea1SWei Hu 351ce110ea1SWei Hu return 0; 352ce110ea1SWei Hu } 353ce110ea1SWei Hu 354ce110ea1SWei Hu #define DOORBELL_OFFSET_SQ 0x0 355ce110ea1SWei Hu #define DOORBELL_OFFSET_RQ 0x400 356ce110ea1SWei Hu #define DOORBELL_OFFSET_CQ 0x800 357ce110ea1SWei Hu #define DOORBELL_OFFSET_EQ 0xFF8 358ce110ea1SWei Hu 359ce110ea1SWei Hu static void 360ce110ea1SWei Hu mana_gd_ring_doorbell(struct gdma_context *gc, uint32_t db_index, 361ce110ea1SWei Hu enum gdma_queue_type q_type, uint32_t qid, 362ce110ea1SWei Hu uint32_t tail_ptr, uint8_t num_req) 363ce110ea1SWei Hu { 364ce110ea1SWei Hu union gdma_doorbell_entry e = {}; 365ce110ea1SWei Hu void __iomem *addr; 366ce110ea1SWei Hu 367ce110ea1SWei Hu addr = (char *)gc->db_page_base + gc->db_page_size * db_index; 368ce110ea1SWei Hu switch (q_type) { 369ce110ea1SWei Hu case GDMA_EQ: 370ce110ea1SWei Hu e.eq.id = qid; 371ce110ea1SWei Hu e.eq.tail_ptr = tail_ptr; 372ce110ea1SWei Hu e.eq.arm = num_req; 373ce110ea1SWei Hu 374ce110ea1SWei Hu addr = (char *)addr + DOORBELL_OFFSET_EQ; 375ce110ea1SWei Hu break; 376ce110ea1SWei Hu 377ce110ea1SWei Hu case GDMA_CQ: 378ce110ea1SWei Hu e.cq.id = qid; 379ce110ea1SWei Hu e.cq.tail_ptr = tail_ptr; 380ce110ea1SWei Hu e.cq.arm = num_req; 381ce110ea1SWei Hu 382ce110ea1SWei Hu addr = (char *)addr + DOORBELL_OFFSET_CQ; 383ce110ea1SWei Hu break; 384ce110ea1SWei Hu 385ce110ea1SWei Hu case GDMA_RQ: 386ce110ea1SWei Hu e.rq.id = qid; 387ce110ea1SWei Hu e.rq.tail_ptr = tail_ptr; 388ce110ea1SWei Hu e.rq.wqe_cnt = num_req; 389ce110ea1SWei Hu 390ce110ea1SWei Hu addr = (char *)addr + DOORBELL_OFFSET_RQ; 391ce110ea1SWei Hu break; 392ce110ea1SWei Hu 393ce110ea1SWei Hu case GDMA_SQ: 394ce110ea1SWei Hu e.sq.id = qid; 395ce110ea1SWei Hu e.sq.tail_ptr = tail_ptr; 396ce110ea1SWei Hu 397ce110ea1SWei Hu addr = (char *)addr + DOORBELL_OFFSET_SQ; 398ce110ea1SWei Hu break; 399ce110ea1SWei Hu 400ce110ea1SWei Hu default: 401ce110ea1SWei Hu mana_warn(NULL, "Invalid queue type 0x%x\n", q_type); 402ce110ea1SWei Hu return; 403ce110ea1SWei Hu } 404ce110ea1SWei Hu 405ce110ea1SWei Hu /* Ensure all writes are done before ring doorbell */ 406ce110ea1SWei Hu wmb(); 407ce110ea1SWei Hu 408ce110ea1SWei Hu #if defined(__amd64__) 409ce110ea1SWei Hu writeq(addr, e.as_uint64); 410ce110ea1SWei Hu #else 411ce110ea1SWei Hu uint32_t *p = (uint32_t *)&e.as_uint64; 412ce110ea1SWei Hu writel(addr, *p); 413ce110ea1SWei Hu writel((char *)addr + 4, *(p + 1)); 414ce110ea1SWei Hu #endif 415ce110ea1SWei Hu } 416ce110ea1SWei Hu 417ce110ea1SWei Hu void 418ce110ea1SWei Hu mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 419ce110ea1SWei Hu { 420ce110ea1SWei Hu mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 421ce110ea1SWei Hu queue->id, queue->head * GDMA_WQE_BU_SIZE, 1); 422ce110ea1SWei Hu } 423ce110ea1SWei Hu 424ce110ea1SWei Hu void 4251833cf13SWei Hu mana_gd_ring_cq(struct gdma_queue *cq, uint8_t arm_bit) 426ce110ea1SWei Hu { 427ce110ea1SWei Hu struct gdma_context *gc = cq->gdma_dev->gdma_context; 428ce110ea1SWei Hu 429ce110ea1SWei Hu uint32_t num_cqe = cq->queue_size / GDMA_CQE_SIZE; 430ce110ea1SWei Hu 431ce110ea1SWei Hu uint32_t head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 432ce110ea1SWei Hu 433ce110ea1SWei Hu mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 4341833cf13SWei Hu head, arm_bit); 435ce110ea1SWei Hu } 436ce110ea1SWei Hu 437ce110ea1SWei Hu static void 438ce110ea1SWei Hu mana_gd_process_eqe(struct gdma_queue *eq) 439ce110ea1SWei Hu { 440ce110ea1SWei Hu uint32_t head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 441ce110ea1SWei Hu struct gdma_context *gc = eq->gdma_dev->gdma_context; 442ce110ea1SWei Hu struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 443ce110ea1SWei Hu union gdma_eqe_info eqe_info; 444ce110ea1SWei Hu enum gdma_eqe_type type; 445ce110ea1SWei Hu struct gdma_event event; 446ce110ea1SWei Hu struct gdma_queue *cq; 447ce110ea1SWei Hu struct gdma_eqe *eqe; 448ce110ea1SWei Hu uint32_t cq_id; 449ce110ea1SWei Hu 450ce110ea1SWei Hu eqe = &eq_eqe_ptr[head]; 451ce110ea1SWei Hu eqe_info.as_uint32 = eqe->eqe_info; 452ce110ea1SWei Hu type = eqe_info.type; 453ce110ea1SWei Hu 454ce110ea1SWei Hu switch (type) { 455ce110ea1SWei Hu case GDMA_EQE_COMPLETION: 456ce110ea1SWei Hu cq_id = eqe->details[0] & 0xFFFFFF; 457ce110ea1SWei Hu if (cq_id >= gc->max_num_cqs) { 458ce110ea1SWei Hu mana_warn(NULL, 459ce110ea1SWei Hu "failed: cq_id %u > max_num_cqs %u\n", 460ce110ea1SWei Hu cq_id, gc->max_num_cqs); 461ce110ea1SWei Hu break; 462ce110ea1SWei Hu } 463ce110ea1SWei Hu 464ce110ea1SWei Hu cq = gc->cq_table[cq_id]; 465ce110ea1SWei Hu if (!cq || cq->type != GDMA_CQ || cq->id != cq_id) { 466ce110ea1SWei Hu mana_warn(NULL, 467ce110ea1SWei Hu "failed: invalid cq_id %u\n", cq_id); 468ce110ea1SWei Hu break; 469ce110ea1SWei Hu } 470ce110ea1SWei Hu 471ce110ea1SWei Hu if (cq->cq.callback) 472ce110ea1SWei Hu cq->cq.callback(cq->cq.context, cq); 473ce110ea1SWei Hu 474ce110ea1SWei Hu break; 475ce110ea1SWei Hu 476ce110ea1SWei Hu case GDMA_EQE_TEST_EVENT: 477ce110ea1SWei Hu gc->test_event_eq_id = eq->id; 478ce110ea1SWei Hu 479ce110ea1SWei Hu mana_dbg(NULL, 480ce110ea1SWei Hu "EQE TEST EVENT received for EQ %u\n", eq->id); 481ce110ea1SWei Hu 482ce110ea1SWei Hu complete(&gc->eq_test_event); 483ce110ea1SWei Hu break; 484ce110ea1SWei Hu 485ce110ea1SWei Hu case GDMA_EQE_HWC_INIT_EQ_ID_DB: 486ce110ea1SWei Hu case GDMA_EQE_HWC_INIT_DATA: 487ce110ea1SWei Hu case GDMA_EQE_HWC_INIT_DONE: 488ce110ea1SWei Hu if (!eq->eq.callback) 489ce110ea1SWei Hu break; 490ce110ea1SWei Hu 491ce110ea1SWei Hu event.type = type; 492ce110ea1SWei Hu memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 493ce110ea1SWei Hu eq->eq.callback(eq->eq.context, eq, &event); 494ce110ea1SWei Hu break; 495ce110ea1SWei Hu 496ce110ea1SWei Hu default: 497ce110ea1SWei Hu break; 498ce110ea1SWei Hu } 499ce110ea1SWei Hu } 500ce110ea1SWei Hu 501ce110ea1SWei Hu static void 502ce110ea1SWei Hu mana_gd_process_eq_events(void *arg) 503ce110ea1SWei Hu { 504ce110ea1SWei Hu uint32_t owner_bits, new_bits, old_bits; 505ce110ea1SWei Hu union gdma_eqe_info eqe_info; 506ce110ea1SWei Hu struct gdma_eqe *eq_eqe_ptr; 507ce110ea1SWei Hu struct gdma_queue *eq = arg; 508ce110ea1SWei Hu struct gdma_context *gc; 509ce110ea1SWei Hu uint32_t head, num_eqe; 510ce110ea1SWei Hu struct gdma_eqe *eqe; 511ce110ea1SWei Hu int i, j; 512ce110ea1SWei Hu 513ce110ea1SWei Hu gc = eq->gdma_dev->gdma_context; 514ce110ea1SWei Hu 515ce110ea1SWei Hu num_eqe = eq->queue_size / GDMA_EQE_SIZE; 516ce110ea1SWei Hu eq_eqe_ptr = eq->queue_mem_ptr; 517ce110ea1SWei Hu 518ce110ea1SWei Hu bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 519ce110ea1SWei Hu BUS_DMASYNC_POSTREAD); 520ce110ea1SWei Hu 521ce110ea1SWei Hu /* Process up to 5 EQEs at a time, and update the HW head. */ 522ce110ea1SWei Hu for (i = 0; i < 5; i++) { 523ce110ea1SWei Hu eqe = &eq_eqe_ptr[eq->head % num_eqe]; 524ce110ea1SWei Hu eqe_info.as_uint32 = eqe->eqe_info; 525ce110ea1SWei Hu owner_bits = eqe_info.owner_bits; 526ce110ea1SWei Hu 527ce110ea1SWei Hu old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 528ce110ea1SWei Hu 529ce110ea1SWei Hu /* No more entries */ 530ce110ea1SWei Hu if (owner_bits == old_bits) 531ce110ea1SWei Hu break; 532ce110ea1SWei Hu 533ce110ea1SWei Hu new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 534ce110ea1SWei Hu if (owner_bits != new_bits) { 535ce110ea1SWei Hu /* Something wrong. Log for debugging purpose */ 536ce110ea1SWei Hu device_printf(gc->dev, 537ce110ea1SWei Hu "EQ %d: overflow detected, " 538ce110ea1SWei Hu "i = %d, eq->head = %u " 539ce110ea1SWei Hu "got owner_bits = %u, new_bits = %u " 540ce110ea1SWei Hu "eqe addr %p, eqe->eqe_info 0x%x, " 541ce110ea1SWei Hu "eqe type = %x, reserved1 = %x, client_id = %x, " 542ce110ea1SWei Hu "reserved2 = %x, owner_bits = %x\n", 543ce110ea1SWei Hu eq->id, i, eq->head, 544ce110ea1SWei Hu owner_bits, new_bits, 545ce110ea1SWei Hu eqe, eqe->eqe_info, 546ce110ea1SWei Hu eqe_info.type, eqe_info.reserved1, 547ce110ea1SWei Hu eqe_info.client_id, eqe_info.reserved2, 548ce110ea1SWei Hu eqe_info.owner_bits); 549ce110ea1SWei Hu 550ce110ea1SWei Hu uint32_t *eqe_dump = (uint32_t *) eq_eqe_ptr; 551ce110ea1SWei Hu for (j = 0; j < 20; j++) { 552ce110ea1SWei Hu device_printf(gc->dev, "%p: %x\t%x\t%x\t%x\n", 553ce110ea1SWei Hu &eqe_dump[j * 4], eqe_dump[j * 4], eqe_dump[j * 4 + 1], 554ce110ea1SWei Hu eqe_dump[j * 4 + 2], eqe_dump[j * 4 + 3]); 555ce110ea1SWei Hu } 556ce110ea1SWei Hu break; 557ce110ea1SWei Hu } 558ce110ea1SWei Hu 559ce110ea1SWei Hu mana_gd_process_eqe(eq); 560ce110ea1SWei Hu 561ce110ea1SWei Hu eq->head++; 562ce110ea1SWei Hu } 563ce110ea1SWei Hu 564ce110ea1SWei Hu bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 565ce110ea1SWei Hu BUS_DMASYNC_PREREAD); 566ce110ea1SWei Hu 567ce110ea1SWei Hu head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 568ce110ea1SWei Hu 569ce110ea1SWei Hu mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 5701833cf13SWei Hu head, SET_ARM_BIT); 571ce110ea1SWei Hu } 572ce110ea1SWei Hu 573ce110ea1SWei Hu static int 574ce110ea1SWei Hu mana_gd_register_irq(struct gdma_queue *queue, 575ce110ea1SWei Hu const struct gdma_queue_spec *spec) 576ce110ea1SWei Hu { 577ce110ea1SWei Hu struct gdma_dev *gd = queue->gdma_dev; 578ce110ea1SWei Hu struct gdma_irq_context *gic; 579ce110ea1SWei Hu struct gdma_context *gc; 580ce110ea1SWei Hu struct gdma_resource *r; 581ce110ea1SWei Hu unsigned int msi_index; 582ce110ea1SWei Hu int err; 583ce110ea1SWei Hu 584ce110ea1SWei Hu gc = gd->gdma_context; 585ce110ea1SWei Hu r = &gc->msix_resource; 586ce110ea1SWei Hu 587ce110ea1SWei Hu mtx_lock_spin(&r->lock_spin); 588ce110ea1SWei Hu 589ce110ea1SWei Hu msi_index = find_first_zero_bit(r->map, r->size); 590ce110ea1SWei Hu if (msi_index >= r->size) { 591ce110ea1SWei Hu err = ENOSPC; 592ce110ea1SWei Hu } else { 593ce110ea1SWei Hu bitmap_set(r->map, msi_index, 1); 594ce110ea1SWei Hu queue->eq.msix_index = msi_index; 595ce110ea1SWei Hu err = 0; 596ce110ea1SWei Hu } 597ce110ea1SWei Hu 598ce110ea1SWei Hu mtx_unlock_spin(&r->lock_spin); 599ce110ea1SWei Hu 600ce110ea1SWei Hu if (err) 601ce110ea1SWei Hu return err; 602ce110ea1SWei Hu 603ce110ea1SWei Hu if (unlikely(msi_index >= gc->num_msix_usable)) { 604ce110ea1SWei Hu device_printf(gc->dev, 605ce110ea1SWei Hu "chose an invalid msix index %d, usable %d\n", 606ce110ea1SWei Hu msi_index, gc->num_msix_usable); 607ce110ea1SWei Hu return ENOSPC; 608ce110ea1SWei Hu } 609ce110ea1SWei Hu 610ce110ea1SWei Hu gic = &gc->irq_contexts[msi_index]; 611ce110ea1SWei Hu 612ce110ea1SWei Hu if (unlikely(gic->handler || gic->arg)) { 613ce110ea1SWei Hu device_printf(gc->dev, 614ce110ea1SWei Hu "interrupt handler or arg already assigned, " 615ce110ea1SWei Hu "msix index: %d\n", msi_index); 616ce110ea1SWei Hu } 617ce110ea1SWei Hu 618ce110ea1SWei Hu gic->arg = queue; 619ce110ea1SWei Hu 620ce110ea1SWei Hu gic->handler = mana_gd_process_eq_events; 621ce110ea1SWei Hu 622ce110ea1SWei Hu mana_dbg(NULL, "registered msix index %d vector %d irq %ju\n", 623ce110ea1SWei Hu msi_index, gic->msix_e.vector, rman_get_start(gic->res)); 624ce110ea1SWei Hu 625ce110ea1SWei Hu return 0; 626ce110ea1SWei Hu } 627ce110ea1SWei Hu 628ce110ea1SWei Hu static void 629ce110ea1SWei Hu mana_gd_deregiser_irq(struct gdma_queue *queue) 630ce110ea1SWei Hu { 631ce110ea1SWei Hu struct gdma_dev *gd = queue->gdma_dev; 632ce110ea1SWei Hu struct gdma_irq_context *gic; 633ce110ea1SWei Hu struct gdma_context *gc; 634ce110ea1SWei Hu struct gdma_resource *r; 635ce110ea1SWei Hu unsigned int msix_index; 636ce110ea1SWei Hu 637ce110ea1SWei Hu gc = gd->gdma_context; 638ce110ea1SWei Hu r = &gc->msix_resource; 639ce110ea1SWei Hu 640ce110ea1SWei Hu /* At most num_online_cpus() + 1 interrupts are used. */ 641ce110ea1SWei Hu msix_index = queue->eq.msix_index; 642ce110ea1SWei Hu if (unlikely(msix_index >= gc->num_msix_usable)) 643ce110ea1SWei Hu return; 644ce110ea1SWei Hu 645ce110ea1SWei Hu gic = &gc->irq_contexts[msix_index]; 646ce110ea1SWei Hu gic->handler = NULL; 647ce110ea1SWei Hu gic->arg = NULL; 648ce110ea1SWei Hu 649ce110ea1SWei Hu mtx_lock_spin(&r->lock_spin); 650ce110ea1SWei Hu bitmap_clear(r->map, msix_index, 1); 651ce110ea1SWei Hu mtx_unlock_spin(&r->lock_spin); 652ce110ea1SWei Hu 653ce110ea1SWei Hu queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 654ce110ea1SWei Hu 655ce110ea1SWei Hu mana_dbg(NULL, "deregistered msix index %d vector %d irq %ju\n", 656ce110ea1SWei Hu msix_index, gic->msix_e.vector, rman_get_start(gic->res)); 657ce110ea1SWei Hu } 658ce110ea1SWei Hu 659ce110ea1SWei Hu int 660ce110ea1SWei Hu mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 661ce110ea1SWei Hu { 662ce110ea1SWei Hu struct gdma_generate_test_event_req req = {}; 663ce110ea1SWei Hu struct gdma_general_resp resp = {}; 664ce110ea1SWei Hu device_t dev = gc->dev; 665ce110ea1SWei Hu int err; 666ce110ea1SWei Hu 667ce110ea1SWei Hu sx_xlock(&gc->eq_test_event_sx); 668ce110ea1SWei Hu 669ce110ea1SWei Hu init_completion(&gc->eq_test_event); 670ce110ea1SWei Hu gc->test_event_eq_id = INVALID_QUEUE_ID; 671ce110ea1SWei Hu 672ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 673ce110ea1SWei Hu sizeof(req), sizeof(resp)); 674ce110ea1SWei Hu 675ce110ea1SWei Hu req.hdr.dev_id = eq->gdma_dev->dev_id; 676ce110ea1SWei Hu req.queue_index = eq->id; 677ce110ea1SWei Hu 678ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, 679ce110ea1SWei Hu sizeof(resp), &resp); 680ce110ea1SWei Hu if (err) { 681ce110ea1SWei Hu device_printf(dev, "test_eq failed: %d\n", err); 682ce110ea1SWei Hu goto out; 683ce110ea1SWei Hu } 684ce110ea1SWei Hu 685ce110ea1SWei Hu err = EPROTO; 686ce110ea1SWei Hu 687ce110ea1SWei Hu if (resp.hdr.status) { 688ce110ea1SWei Hu device_printf(dev, "test_eq failed: 0x%x\n", 689ce110ea1SWei Hu resp.hdr.status); 690ce110ea1SWei Hu goto out; 691ce110ea1SWei Hu } 692ce110ea1SWei Hu 693ce110ea1SWei Hu if (wait_for_completion_timeout(&gc->eq_test_event, 30 * hz)) { 694ce110ea1SWei Hu device_printf(dev, "test_eq timed out on queue %d\n", 695ce110ea1SWei Hu eq->id); 696ce110ea1SWei Hu goto out; 697ce110ea1SWei Hu } 698ce110ea1SWei Hu 699ce110ea1SWei Hu if (eq->id != gc->test_event_eq_id) { 700ce110ea1SWei Hu device_printf(dev, 701ce110ea1SWei Hu "test_eq got an event on wrong queue %d (%d)\n", 702ce110ea1SWei Hu gc->test_event_eq_id, eq->id); 703ce110ea1SWei Hu goto out; 704ce110ea1SWei Hu } 705ce110ea1SWei Hu 706ce110ea1SWei Hu err = 0; 707ce110ea1SWei Hu out: 708ce110ea1SWei Hu sx_xunlock(&gc->eq_test_event_sx); 709ce110ea1SWei Hu return err; 710ce110ea1SWei Hu } 711ce110ea1SWei Hu 712ce110ea1SWei Hu static void 713ce110ea1SWei Hu mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 714ce110ea1SWei Hu struct gdma_queue *queue) 715ce110ea1SWei Hu { 716ce110ea1SWei Hu int err; 717ce110ea1SWei Hu 718ce110ea1SWei Hu if (flush_evenets) { 719ce110ea1SWei Hu err = mana_gd_test_eq(gc, queue); 720ce110ea1SWei Hu if (err) 721ce110ea1SWei Hu device_printf(gc->dev, 722ce110ea1SWei Hu "Failed to flush EQ: %d\n", err); 723ce110ea1SWei Hu } 724ce110ea1SWei Hu 725ce110ea1SWei Hu mana_gd_deregiser_irq(queue); 726ce110ea1SWei Hu 727ce110ea1SWei Hu if (queue->eq.disable_needed) 728ce110ea1SWei Hu mana_gd_disable_queue(queue); 729ce110ea1SWei Hu } 730ce110ea1SWei Hu 731ce110ea1SWei Hu static int mana_gd_create_eq(struct gdma_dev *gd, 732ce110ea1SWei Hu const struct gdma_queue_spec *spec, 733ce110ea1SWei Hu bool create_hwq, struct gdma_queue *queue) 734ce110ea1SWei Hu { 735ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 736ce110ea1SWei Hu device_t dev = gc->dev; 737ce110ea1SWei Hu uint32_t log2_num_entries; 738ce110ea1SWei Hu int err; 739ce110ea1SWei Hu 740ce110ea1SWei Hu queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 741ce110ea1SWei Hu 742ce110ea1SWei Hu log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 743ce110ea1SWei Hu 744ce110ea1SWei Hu if (spec->eq.log2_throttle_limit > log2_num_entries) { 745ce110ea1SWei Hu device_printf(dev, 746ce110ea1SWei Hu "EQ throttling limit (%lu) > maximum EQE (%u)\n", 747ce110ea1SWei Hu spec->eq.log2_throttle_limit, log2_num_entries); 748ce110ea1SWei Hu return EINVAL; 749ce110ea1SWei Hu } 750ce110ea1SWei Hu 751ce110ea1SWei Hu err = mana_gd_register_irq(queue, spec); 752ce110ea1SWei Hu if (err) { 753ce110ea1SWei Hu device_printf(dev, "Failed to register irq: %d\n", err); 754ce110ea1SWei Hu return err; 755ce110ea1SWei Hu } 756ce110ea1SWei Hu 757ce110ea1SWei Hu queue->eq.callback = spec->eq.callback; 758ce110ea1SWei Hu queue->eq.context = spec->eq.context; 759ce110ea1SWei Hu queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 760ce110ea1SWei Hu queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 761ce110ea1SWei Hu 762ce110ea1SWei Hu if (create_hwq) { 763ce110ea1SWei Hu err = mana_gd_create_hw_eq(gc, queue); 764ce110ea1SWei Hu if (err) 765ce110ea1SWei Hu goto out; 766ce110ea1SWei Hu 767ce110ea1SWei Hu err = mana_gd_test_eq(gc, queue); 768ce110ea1SWei Hu if (err) 769ce110ea1SWei Hu goto out; 770ce110ea1SWei Hu } 771ce110ea1SWei Hu 772ce110ea1SWei Hu return 0; 773ce110ea1SWei Hu out: 774ce110ea1SWei Hu device_printf(dev, "Failed to create EQ: %d\n", err); 775ce110ea1SWei Hu mana_gd_destroy_eq(gc, false, queue); 776ce110ea1SWei Hu return err; 777ce110ea1SWei Hu } 778ce110ea1SWei Hu 779ce110ea1SWei Hu static void 780ce110ea1SWei Hu mana_gd_create_cq(const struct gdma_queue_spec *spec, 781ce110ea1SWei Hu struct gdma_queue *queue) 782ce110ea1SWei Hu { 783ce110ea1SWei Hu uint32_t log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 784ce110ea1SWei Hu 785ce110ea1SWei Hu queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 786ce110ea1SWei Hu queue->cq.parent = spec->cq.parent_eq; 787ce110ea1SWei Hu queue->cq.context = spec->cq.context; 788ce110ea1SWei Hu queue->cq.callback = spec->cq.callback; 789ce110ea1SWei Hu } 790ce110ea1SWei Hu 791ce110ea1SWei Hu static void 792ce110ea1SWei Hu mana_gd_destroy_cq(struct gdma_context *gc, 793ce110ea1SWei Hu struct gdma_queue *queue) 794ce110ea1SWei Hu { 795ce110ea1SWei Hu uint32_t id = queue->id; 796ce110ea1SWei Hu 797ce110ea1SWei Hu if (id >= gc->max_num_cqs) 798ce110ea1SWei Hu return; 799ce110ea1SWei Hu 800ce110ea1SWei Hu if (!gc->cq_table[id]) 801ce110ea1SWei Hu return; 802ce110ea1SWei Hu 803ce110ea1SWei Hu gc->cq_table[id] = NULL; 804ce110ea1SWei Hu } 805ce110ea1SWei Hu 806ce110ea1SWei Hu int mana_gd_create_hwc_queue(struct gdma_dev *gd, 807ce110ea1SWei Hu const struct gdma_queue_spec *spec, 808ce110ea1SWei Hu struct gdma_queue **queue_ptr) 809ce110ea1SWei Hu { 810ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 811ce110ea1SWei Hu struct gdma_mem_info *gmi; 812ce110ea1SWei Hu struct gdma_queue *queue; 813ce110ea1SWei Hu int err; 814ce110ea1SWei Hu 815ce110ea1SWei Hu queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 816ce110ea1SWei Hu if (!queue) 817ce110ea1SWei Hu return ENOMEM; 818ce110ea1SWei Hu 819ce110ea1SWei Hu gmi = &queue->mem_info; 820ce110ea1SWei Hu err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 821ce110ea1SWei Hu if (err) 822ce110ea1SWei Hu goto free_q; 823ce110ea1SWei Hu 824ce110ea1SWei Hu queue->head = 0; 825ce110ea1SWei Hu queue->tail = 0; 826ce110ea1SWei Hu queue->queue_mem_ptr = gmi->virt_addr; 827ce110ea1SWei Hu queue->queue_size = spec->queue_size; 828ce110ea1SWei Hu queue->monitor_avl_buf = spec->monitor_avl_buf; 829ce110ea1SWei Hu queue->type = spec->type; 830ce110ea1SWei Hu queue->gdma_dev = gd; 831ce110ea1SWei Hu 832ce110ea1SWei Hu if (spec->type == GDMA_EQ) 833ce110ea1SWei Hu err = mana_gd_create_eq(gd, spec, false, queue); 834ce110ea1SWei Hu else if (spec->type == GDMA_CQ) 835ce110ea1SWei Hu mana_gd_create_cq(spec, queue); 836ce110ea1SWei Hu 837ce110ea1SWei Hu if (err) 838ce110ea1SWei Hu goto out; 839ce110ea1SWei Hu 840ce110ea1SWei Hu *queue_ptr = queue; 841ce110ea1SWei Hu return 0; 842ce110ea1SWei Hu out: 843ce110ea1SWei Hu mana_gd_free_memory(gmi); 844ce110ea1SWei Hu free_q: 845ce110ea1SWei Hu free(queue, M_DEVBUF); 846ce110ea1SWei Hu return err; 847ce110ea1SWei Hu } 848ce110ea1SWei Hu 849ce110ea1SWei Hu static void 850ce110ea1SWei Hu mana_gd_destroy_dma_region(struct gdma_context *gc, uint64_t gdma_region) 851ce110ea1SWei Hu { 852ce110ea1SWei Hu struct gdma_destroy_dma_region_req req = {}; 853ce110ea1SWei Hu struct gdma_general_resp resp = {}; 854ce110ea1SWei Hu int err; 855ce110ea1SWei Hu 856ce110ea1SWei Hu if (gdma_region == GDMA_INVALID_DMA_REGION) 857ce110ea1SWei Hu return; 858ce110ea1SWei Hu 859ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 860ce110ea1SWei Hu sizeof(resp)); 861ce110ea1SWei Hu req.gdma_region = gdma_region; 862ce110ea1SWei Hu 863ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), 864ce110ea1SWei Hu &resp); 865ce110ea1SWei Hu if (err || resp.hdr.status) 866ce110ea1SWei Hu device_printf(gc->dev, 867ce110ea1SWei Hu "Failed to destroy DMA region: %d, 0x%x\n", 868ce110ea1SWei Hu err, resp.hdr.status); 869ce110ea1SWei Hu } 870ce110ea1SWei Hu 871ce110ea1SWei Hu static int 872ce110ea1SWei Hu mana_gd_create_dma_region(struct gdma_dev *gd, 873ce110ea1SWei Hu struct gdma_mem_info *gmi) 874ce110ea1SWei Hu { 875ce110ea1SWei Hu unsigned int num_page = gmi->length / PAGE_SIZE; 876ce110ea1SWei Hu struct gdma_create_dma_region_req *req = NULL; 877ce110ea1SWei Hu struct gdma_create_dma_region_resp resp = {}; 878ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 879ce110ea1SWei Hu struct hw_channel_context *hwc; 880ce110ea1SWei Hu uint32_t length = gmi->length; 881ce110ea1SWei Hu uint32_t req_msg_size; 882ce110ea1SWei Hu int err; 883ce110ea1SWei Hu int i; 884ce110ea1SWei Hu 885ce110ea1SWei Hu if (length < PAGE_SIZE || !is_power_of_2(length)) { 886ce110ea1SWei Hu mana_err(NULL, "gmi size incorrect: %u\n", length); 887ce110ea1SWei Hu return EINVAL; 888ce110ea1SWei Hu } 889ce110ea1SWei Hu 890ce110ea1SWei Hu if (offset_in_page((uint64_t)gmi->virt_addr) != 0) { 891ce110ea1SWei Hu mana_err(NULL, "gmi not page aligned: %p\n", 892ce110ea1SWei Hu gmi->virt_addr); 893ce110ea1SWei Hu return EINVAL; 894ce110ea1SWei Hu } 895ce110ea1SWei Hu 896ce110ea1SWei Hu hwc = gc->hwc.driver_data; 897ce110ea1SWei Hu req_msg_size = sizeof(*req) + num_page * sizeof(uint64_t); 898ce110ea1SWei Hu if (req_msg_size > hwc->max_req_msg_size) { 899ce110ea1SWei Hu mana_err(NULL, "req msg size too large: %u, %u\n", 900ce110ea1SWei Hu req_msg_size, hwc->max_req_msg_size); 901ce110ea1SWei Hu return EINVAL; 902ce110ea1SWei Hu } 903ce110ea1SWei Hu 904ce110ea1SWei Hu req = malloc(req_msg_size, M_DEVBUF, M_WAITOK | M_ZERO); 905ce110ea1SWei Hu if (!req) 906ce110ea1SWei Hu return ENOMEM; 907ce110ea1SWei Hu 908ce110ea1SWei Hu mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 909ce110ea1SWei Hu req_msg_size, sizeof(resp)); 910ce110ea1SWei Hu req->length = length; 911ce110ea1SWei Hu req->offset_in_page = 0; 912ce110ea1SWei Hu req->gdma_page_type = GDMA_PAGE_TYPE_4K; 913ce110ea1SWei Hu req->page_count = num_page; 914ce110ea1SWei Hu req->page_addr_list_len = num_page; 915ce110ea1SWei Hu 916ce110ea1SWei Hu for (i = 0; i < num_page; i++) 917ce110ea1SWei Hu req->page_addr_list[i] = gmi->dma_handle + i * PAGE_SIZE; 918ce110ea1SWei Hu 919ce110ea1SWei Hu err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 920ce110ea1SWei Hu if (err) 921ce110ea1SWei Hu goto out; 922ce110ea1SWei Hu 923ce110ea1SWei Hu if (resp.hdr.status || resp.gdma_region == GDMA_INVALID_DMA_REGION) { 924ce110ea1SWei Hu device_printf(gc->dev, "Failed to create DMA region: 0x%x\n", 925ce110ea1SWei Hu resp.hdr.status); 926ce110ea1SWei Hu err = EPROTO; 927ce110ea1SWei Hu goto out; 928ce110ea1SWei Hu } 929ce110ea1SWei Hu 930ce110ea1SWei Hu gmi->gdma_region = resp.gdma_region; 931ce110ea1SWei Hu out: 932ce110ea1SWei Hu free(req, M_DEVBUF); 933ce110ea1SWei Hu return err; 934ce110ea1SWei Hu } 935ce110ea1SWei Hu 936ce110ea1SWei Hu int 937ce110ea1SWei Hu mana_gd_create_mana_eq(struct gdma_dev *gd, 938ce110ea1SWei Hu const struct gdma_queue_spec *spec, 939ce110ea1SWei Hu struct gdma_queue **queue_ptr) 940ce110ea1SWei Hu { 941ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 942ce110ea1SWei Hu struct gdma_mem_info *gmi; 943ce110ea1SWei Hu struct gdma_queue *queue; 944ce110ea1SWei Hu int err; 945ce110ea1SWei Hu 946ce110ea1SWei Hu if (spec->type != GDMA_EQ) 947ce110ea1SWei Hu return EINVAL; 948ce110ea1SWei Hu 949ce110ea1SWei Hu queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 950ce110ea1SWei Hu if (!queue) 951ce110ea1SWei Hu return ENOMEM; 952ce110ea1SWei Hu 953ce110ea1SWei Hu gmi = &queue->mem_info; 954ce110ea1SWei Hu err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 955ce110ea1SWei Hu if (err) 956ce110ea1SWei Hu goto free_q; 957ce110ea1SWei Hu 958ce110ea1SWei Hu err = mana_gd_create_dma_region(gd, gmi); 959ce110ea1SWei Hu if (err) 960ce110ea1SWei Hu goto out; 961ce110ea1SWei Hu 962ce110ea1SWei Hu queue->head = 0; 963ce110ea1SWei Hu queue->tail = 0; 964ce110ea1SWei Hu queue->queue_mem_ptr = gmi->virt_addr; 965ce110ea1SWei Hu queue->queue_size = spec->queue_size; 966ce110ea1SWei Hu queue->monitor_avl_buf = spec->monitor_avl_buf; 967ce110ea1SWei Hu queue->type = spec->type; 968ce110ea1SWei Hu queue->gdma_dev = gd; 969ce110ea1SWei Hu 970ce110ea1SWei Hu err = mana_gd_create_eq(gd, spec, true, queue); 971ce110ea1SWei Hu if (err) 972ce110ea1SWei Hu goto out; 973ce110ea1SWei Hu 974ce110ea1SWei Hu *queue_ptr = queue; 975ce110ea1SWei Hu return 0; 976ce110ea1SWei Hu 977ce110ea1SWei Hu out: 978ce110ea1SWei Hu mana_gd_free_memory(gmi); 979ce110ea1SWei Hu free_q: 980ce110ea1SWei Hu free(queue, M_DEVBUF); 981ce110ea1SWei Hu return err; 982ce110ea1SWei Hu } 983ce110ea1SWei Hu 984ce110ea1SWei Hu int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 985ce110ea1SWei Hu const struct gdma_queue_spec *spec, 986ce110ea1SWei Hu struct gdma_queue **queue_ptr) 987ce110ea1SWei Hu { 988ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 989ce110ea1SWei Hu struct gdma_mem_info *gmi; 990ce110ea1SWei Hu struct gdma_queue *queue; 991ce110ea1SWei Hu int err; 992ce110ea1SWei Hu 993ce110ea1SWei Hu if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 994ce110ea1SWei Hu spec->type != GDMA_RQ) 995ce110ea1SWei Hu return EINVAL; 996ce110ea1SWei Hu 997ce110ea1SWei Hu queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 998ce110ea1SWei Hu if (!queue) 999ce110ea1SWei Hu return ENOMEM; 1000ce110ea1SWei Hu 1001ce110ea1SWei Hu gmi = &queue->mem_info; 1002ce110ea1SWei Hu err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1003ce110ea1SWei Hu if (err) 1004ce110ea1SWei Hu goto free_q; 1005ce110ea1SWei Hu 1006ce110ea1SWei Hu err = mana_gd_create_dma_region(gd, gmi); 1007ce110ea1SWei Hu if (err) 1008ce110ea1SWei Hu goto out; 1009ce110ea1SWei Hu 1010ce110ea1SWei Hu queue->head = 0; 1011ce110ea1SWei Hu queue->tail = 0; 1012ce110ea1SWei Hu queue->queue_mem_ptr = gmi->virt_addr; 1013ce110ea1SWei Hu queue->queue_size = spec->queue_size; 1014ce110ea1SWei Hu queue->monitor_avl_buf = spec->monitor_avl_buf; 1015ce110ea1SWei Hu queue->type = spec->type; 1016ce110ea1SWei Hu queue->gdma_dev = gd; 1017ce110ea1SWei Hu 1018ce110ea1SWei Hu if (spec->type == GDMA_CQ) 1019ce110ea1SWei Hu mana_gd_create_cq(spec, queue); 1020ce110ea1SWei Hu 1021ce110ea1SWei Hu *queue_ptr = queue; 1022ce110ea1SWei Hu return 0; 1023ce110ea1SWei Hu 1024ce110ea1SWei Hu out: 1025ce110ea1SWei Hu mana_gd_free_memory(gmi); 1026ce110ea1SWei Hu free_q: 1027ce110ea1SWei Hu free(queue, M_DEVBUF); 1028ce110ea1SWei Hu return err; 1029ce110ea1SWei Hu } 1030ce110ea1SWei Hu 1031ce110ea1SWei Hu void 1032ce110ea1SWei Hu mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 1033ce110ea1SWei Hu { 1034ce110ea1SWei Hu struct gdma_mem_info *gmi = &queue->mem_info; 1035ce110ea1SWei Hu 1036ce110ea1SWei Hu switch (queue->type) { 1037ce110ea1SWei Hu case GDMA_EQ: 1038ce110ea1SWei Hu mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 1039ce110ea1SWei Hu break; 1040ce110ea1SWei Hu 1041ce110ea1SWei Hu case GDMA_CQ: 1042ce110ea1SWei Hu mana_gd_destroy_cq(gc, queue); 1043ce110ea1SWei Hu break; 1044ce110ea1SWei Hu 1045ce110ea1SWei Hu case GDMA_RQ: 1046ce110ea1SWei Hu break; 1047ce110ea1SWei Hu 1048ce110ea1SWei Hu case GDMA_SQ: 1049ce110ea1SWei Hu break; 1050ce110ea1SWei Hu 1051ce110ea1SWei Hu default: 1052ce110ea1SWei Hu device_printf(gc->dev, 1053ce110ea1SWei Hu "Can't destroy unknown queue: type = %d\n", 1054ce110ea1SWei Hu queue->type); 1055ce110ea1SWei Hu return; 1056ce110ea1SWei Hu } 1057ce110ea1SWei Hu 1058ce110ea1SWei Hu mana_gd_destroy_dma_region(gc, gmi->gdma_region); 1059ce110ea1SWei Hu mana_gd_free_memory(gmi); 1060ce110ea1SWei Hu free(queue, M_DEVBUF); 1061ce110ea1SWei Hu } 1062ce110ea1SWei Hu 1063ed65c80aSWei Hu #define OS_MAJOR_DIV 100000 1064ed65c80aSWei Hu #define OS_BUILD_MOD 1000 1065ed65c80aSWei Hu 1066ce110ea1SWei Hu int 1067ce110ea1SWei Hu mana_gd_verify_vf_version(device_t dev) 1068ce110ea1SWei Hu { 1069ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 1070ce110ea1SWei Hu struct gdma_verify_ver_resp resp = {}; 1071ce110ea1SWei Hu struct gdma_verify_ver_req req = {}; 1072ce110ea1SWei Hu int err; 1073ce110ea1SWei Hu 1074ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 1075ce110ea1SWei Hu sizeof(req), sizeof(resp)); 1076ce110ea1SWei Hu 1077ce110ea1SWei Hu req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 1078ce110ea1SWei Hu req.protocol_ver_max = GDMA_PROTOCOL_LAST; 1079ce110ea1SWei Hu 1080ed65c80aSWei Hu req.drv_ver = 0; /* Unused */ 1081ed65c80aSWei Hu req.os_type = 0x30; /* Other */ 1082ed65c80aSWei Hu req.os_ver_major = osreldate / OS_MAJOR_DIV; 1083ed65c80aSWei Hu req.os_ver_minor = (osreldate % OS_MAJOR_DIV) / OS_BUILD_MOD; 1084ed65c80aSWei Hu req.os_ver_build = osreldate % OS_BUILD_MOD; 1085ed65c80aSWei Hu strncpy(req.os_ver_str1, ostype, sizeof(req.os_ver_str1) - 1); 1086ed65c80aSWei Hu strncpy(req.os_ver_str2, osrelease, sizeof(req.os_ver_str2) - 1); 1087ed65c80aSWei Hu 1088ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1089ce110ea1SWei Hu if (err || resp.hdr.status) { 1090ce110ea1SWei Hu device_printf(gc->dev, 1091ce110ea1SWei Hu "VfVerifyVersionOutput: %d, status=0x%x\n", 1092ce110ea1SWei Hu err, resp.hdr.status); 1093ce110ea1SWei Hu return err ? err : EPROTO; 1094ce110ea1SWei Hu } 1095ce110ea1SWei Hu 1096ce110ea1SWei Hu return 0; 1097ce110ea1SWei Hu } 1098ce110ea1SWei Hu 1099ce110ea1SWei Hu int 1100ce110ea1SWei Hu mana_gd_register_device(struct gdma_dev *gd) 1101ce110ea1SWei Hu { 1102ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 1103ce110ea1SWei Hu struct gdma_register_device_resp resp = {}; 1104ce110ea1SWei Hu struct gdma_general_req req = {}; 1105ce110ea1SWei Hu int err; 1106ce110ea1SWei Hu 1107ce110ea1SWei Hu gd->pdid = INVALID_PDID; 1108ce110ea1SWei Hu gd->doorbell = INVALID_DOORBELL; 1109ce110ea1SWei Hu gd->gpa_mkey = INVALID_MEM_KEY; 1110ce110ea1SWei Hu 1111ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 1112ce110ea1SWei Hu sizeof(resp)); 1113ce110ea1SWei Hu 1114ce110ea1SWei Hu req.hdr.dev_id = gd->dev_id; 1115ce110ea1SWei Hu 1116ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1117ce110ea1SWei Hu if (err || resp.hdr.status) { 1118ce110ea1SWei Hu device_printf(gc->dev, 1119ce110ea1SWei Hu "gdma_register_device_resp failed: %d, 0x%x\n", 1120ce110ea1SWei Hu err, resp.hdr.status); 1121ce110ea1SWei Hu return err ? err : -EPROTO; 1122ce110ea1SWei Hu } 1123ce110ea1SWei Hu 1124ce110ea1SWei Hu gd->pdid = resp.pdid; 1125ce110ea1SWei Hu gd->gpa_mkey = resp.gpa_mkey; 1126ce110ea1SWei Hu gd->doorbell = resp.db_id; 1127ce110ea1SWei Hu 1128ce110ea1SWei Hu mana_dbg(NULL, "mana device pdid %u, gpa_mkey %u, doorbell %u \n", 1129ce110ea1SWei Hu gd->pdid, gd->gpa_mkey, gd->doorbell); 1130ce110ea1SWei Hu 1131ce110ea1SWei Hu return 0; 1132ce110ea1SWei Hu } 1133ce110ea1SWei Hu 1134ce110ea1SWei Hu int 1135ce110ea1SWei Hu mana_gd_deregister_device(struct gdma_dev *gd) 1136ce110ea1SWei Hu { 1137ce110ea1SWei Hu struct gdma_context *gc = gd->gdma_context; 1138ce110ea1SWei Hu struct gdma_general_resp resp = {}; 1139ce110ea1SWei Hu struct gdma_general_req req = {}; 1140ce110ea1SWei Hu int err; 1141ce110ea1SWei Hu 1142ce110ea1SWei Hu if (gd->pdid == INVALID_PDID) 1143ce110ea1SWei Hu return EINVAL; 1144ce110ea1SWei Hu 1145ce110ea1SWei Hu mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 1146ce110ea1SWei Hu sizeof(resp)); 1147ce110ea1SWei Hu 1148ce110ea1SWei Hu req.hdr.dev_id = gd->dev_id; 1149ce110ea1SWei Hu 1150ce110ea1SWei Hu err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1151ce110ea1SWei Hu if (err || resp.hdr.status) { 1152ce110ea1SWei Hu device_printf(gc->dev, 1153ce110ea1SWei Hu "Failed to deregister device: %d, 0x%x\n", 1154ce110ea1SWei Hu err, resp.hdr.status); 1155ce110ea1SWei Hu if (!err) 1156ce110ea1SWei Hu err = EPROTO; 1157ce110ea1SWei Hu } 1158ce110ea1SWei Hu 1159ce110ea1SWei Hu gd->pdid = INVALID_PDID; 1160ce110ea1SWei Hu gd->doorbell = INVALID_DOORBELL; 1161ce110ea1SWei Hu gd->gpa_mkey = INVALID_MEM_KEY; 1162ce110ea1SWei Hu 1163ce110ea1SWei Hu return err; 1164ce110ea1SWei Hu } 1165ce110ea1SWei Hu 1166ce110ea1SWei Hu uint32_t 1167ce110ea1SWei Hu mana_gd_wq_avail_space(struct gdma_queue *wq) 1168ce110ea1SWei Hu { 1169ce110ea1SWei Hu uint32_t used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1170ce110ea1SWei Hu uint32_t wq_size = wq->queue_size; 1171ce110ea1SWei Hu 1172ce110ea1SWei Hu if (used_space > wq_size) { 1173ce110ea1SWei Hu mana_warn(NULL, "failed: used space %u > queue size %u\n", 1174ce110ea1SWei Hu used_space, wq_size); 1175ce110ea1SWei Hu } 1176ce110ea1SWei Hu 1177ce110ea1SWei Hu return wq_size - used_space; 1178ce110ea1SWei Hu } 1179ce110ea1SWei Hu 1180ce110ea1SWei Hu uint8_t * 1181ce110ea1SWei Hu mana_gd_get_wqe_ptr(const struct gdma_queue *wq, uint32_t wqe_offset) 1182ce110ea1SWei Hu { 1183ce110ea1SWei Hu uint32_t offset = 1184ce110ea1SWei Hu (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1185ce110ea1SWei Hu 1186ce110ea1SWei Hu if ((offset + GDMA_WQE_BU_SIZE) > wq->queue_size) { 1187ce110ea1SWei Hu mana_warn(NULL, "failed: write end out of queue bound %u, " 1188ce110ea1SWei Hu "queue size %u\n", 1189ce110ea1SWei Hu offset + GDMA_WQE_BU_SIZE, wq->queue_size); 1190ce110ea1SWei Hu } 1191ce110ea1SWei Hu 1192ce110ea1SWei Hu return (uint8_t *)wq->queue_mem_ptr + offset; 1193ce110ea1SWei Hu } 1194ce110ea1SWei Hu 1195ce110ea1SWei Hu static uint32_t 1196ce110ea1SWei Hu mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1197ce110ea1SWei Hu enum gdma_queue_type q_type, 1198ce110ea1SWei Hu uint32_t client_oob_size, uint32_t sgl_data_size, 1199ce110ea1SWei Hu uint8_t *wqe_ptr) 1200ce110ea1SWei Hu { 1201ce110ea1SWei Hu bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1202ce110ea1SWei Hu bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1203ce110ea1SWei Hu struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1204ce110ea1SWei Hu uint8_t *ptr; 1205ce110ea1SWei Hu 1206ce110ea1SWei Hu memset(header, 0, sizeof(struct gdma_wqe)); 1207ce110ea1SWei Hu header->num_sge = wqe_req->num_sge; 1208ce110ea1SWei Hu header->inline_oob_size_div4 = client_oob_size / sizeof(uint32_t); 1209ce110ea1SWei Hu 1210ce110ea1SWei Hu if (oob_in_sgl) { 1211ce110ea1SWei Hu if (!pad_data || wqe_req->num_sge < 2) { 1212ce110ea1SWei Hu mana_warn(NULL, "no pad_data or num_sge < 2\n"); 1213ce110ea1SWei Hu } 1214ce110ea1SWei Hu 1215ce110ea1SWei Hu header->client_oob_in_sgl = 1; 1216ce110ea1SWei Hu 1217ce110ea1SWei Hu if (pad_data) 1218ce110ea1SWei Hu header->last_vbytes = wqe_req->sgl[0].size; 1219ce110ea1SWei Hu } 1220ce110ea1SWei Hu 1221ce110ea1SWei Hu if (q_type == GDMA_SQ) 1222ce110ea1SWei Hu header->client_data_unit = wqe_req->client_data_unit; 1223ce110ea1SWei Hu 1224ce110ea1SWei Hu /* 1225ce110ea1SWei Hu * The size of gdma_wqe + client_oob_size must be less than or equal 1226ce110ea1SWei Hu * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1227ce110ea1SWei Hu * the queue memory buffer boundary. 1228ce110ea1SWei Hu */ 1229ce110ea1SWei Hu ptr = wqe_ptr + sizeof(header); 1230ce110ea1SWei Hu 1231ce110ea1SWei Hu if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1232ce110ea1SWei Hu memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1233ce110ea1SWei Hu 1234ce110ea1SWei Hu if (client_oob_size > wqe_req->inline_oob_size) 1235ce110ea1SWei Hu memset(ptr + wqe_req->inline_oob_size, 0, 1236ce110ea1SWei Hu client_oob_size - wqe_req->inline_oob_size); 1237ce110ea1SWei Hu } 1238ce110ea1SWei Hu 1239ce110ea1SWei Hu return sizeof(header) + client_oob_size; 1240ce110ea1SWei Hu } 1241ce110ea1SWei Hu 1242ce110ea1SWei Hu static void 1243ce110ea1SWei Hu mana_gd_write_sgl(struct gdma_queue *wq, uint8_t *wqe_ptr, 1244ce110ea1SWei Hu const struct gdma_wqe_request *wqe_req) 1245ce110ea1SWei Hu { 1246ce110ea1SWei Hu uint32_t sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1247ce110ea1SWei Hu const uint8_t *address = (uint8_t *)wqe_req->sgl; 1248ce110ea1SWei Hu uint8_t *base_ptr, *end_ptr; 1249ce110ea1SWei Hu uint32_t size_to_end; 1250ce110ea1SWei Hu 1251ce110ea1SWei Hu base_ptr = wq->queue_mem_ptr; 1252ce110ea1SWei Hu end_ptr = base_ptr + wq->queue_size; 1253ce110ea1SWei Hu size_to_end = (uint32_t)(end_ptr - wqe_ptr); 1254ce110ea1SWei Hu 1255ce110ea1SWei Hu if (size_to_end < sgl_size) { 1256ce110ea1SWei Hu memcpy(wqe_ptr, address, size_to_end); 1257ce110ea1SWei Hu 1258ce110ea1SWei Hu wqe_ptr = base_ptr; 1259ce110ea1SWei Hu address += size_to_end; 1260ce110ea1SWei Hu sgl_size -= size_to_end; 1261ce110ea1SWei Hu } 1262ce110ea1SWei Hu 1263ce110ea1SWei Hu memcpy(wqe_ptr, address, sgl_size); 1264ce110ea1SWei Hu } 1265ce110ea1SWei Hu 1266ce110ea1SWei Hu int 1267ce110ea1SWei Hu mana_gd_post_work_request(struct gdma_queue *wq, 1268ce110ea1SWei Hu const struct gdma_wqe_request *wqe_req, 1269ce110ea1SWei Hu struct gdma_posted_wqe_info *wqe_info) 1270ce110ea1SWei Hu { 1271ce110ea1SWei Hu uint32_t client_oob_size = wqe_req->inline_oob_size; 1272ce110ea1SWei Hu struct gdma_context *gc; 1273ce110ea1SWei Hu uint32_t sgl_data_size; 1274ce110ea1SWei Hu uint32_t max_wqe_size; 1275ce110ea1SWei Hu uint32_t wqe_size; 1276ce110ea1SWei Hu uint8_t *wqe_ptr; 1277ce110ea1SWei Hu 1278ce110ea1SWei Hu if (wqe_req->num_sge == 0) 1279ce110ea1SWei Hu return EINVAL; 1280ce110ea1SWei Hu 1281ce110ea1SWei Hu if (wq->type == GDMA_RQ) { 1282ce110ea1SWei Hu if (client_oob_size != 0) 1283ce110ea1SWei Hu return EINVAL; 1284ce110ea1SWei Hu 1285ce110ea1SWei Hu client_oob_size = INLINE_OOB_SMALL_SIZE; 1286ce110ea1SWei Hu 1287ce110ea1SWei Hu max_wqe_size = GDMA_MAX_RQE_SIZE; 1288ce110ea1SWei Hu } else { 1289ce110ea1SWei Hu if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1290ce110ea1SWei Hu client_oob_size != INLINE_OOB_LARGE_SIZE) 1291ce110ea1SWei Hu return EINVAL; 1292ce110ea1SWei Hu 1293ce110ea1SWei Hu max_wqe_size = GDMA_MAX_SQE_SIZE; 1294ce110ea1SWei Hu } 1295ce110ea1SWei Hu 1296ce110ea1SWei Hu sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1297ce110ea1SWei Hu wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1298ce110ea1SWei Hu sgl_data_size, GDMA_WQE_BU_SIZE); 1299ce110ea1SWei Hu if (wqe_size > max_wqe_size) 1300ce110ea1SWei Hu return EINVAL; 1301ce110ea1SWei Hu 1302ce110ea1SWei Hu if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1303ce110ea1SWei Hu gc = wq->gdma_dev->gdma_context; 1304ce110ea1SWei Hu device_printf(gc->dev, "unsuccessful flow control!\n"); 1305ce110ea1SWei Hu return ENOSPC; 1306ce110ea1SWei Hu } 1307ce110ea1SWei Hu 1308ce110ea1SWei Hu if (wqe_info) 1309ce110ea1SWei Hu wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1310ce110ea1SWei Hu 1311ce110ea1SWei Hu wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1312ce110ea1SWei Hu wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1313ce110ea1SWei Hu sgl_data_size, wqe_ptr); 1314ce110ea1SWei Hu if (wqe_ptr >= (uint8_t *)wq->queue_mem_ptr + wq->queue_size) 1315ce110ea1SWei Hu wqe_ptr -= wq->queue_size; 1316ce110ea1SWei Hu 1317ce110ea1SWei Hu mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1318ce110ea1SWei Hu 1319ce110ea1SWei Hu wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1320ce110ea1SWei Hu 1321ce110ea1SWei Hu bus_dmamap_sync(wq->mem_info.dma_tag, wq->mem_info.dma_map, 1322ce110ea1SWei Hu BUS_DMASYNC_PREWRITE); 1323ce110ea1SWei Hu 1324ce110ea1SWei Hu return 0; 1325ce110ea1SWei Hu } 1326ce110ea1SWei Hu 1327ce110ea1SWei Hu int 1328ce110ea1SWei Hu mana_gd_post_and_ring(struct gdma_queue *queue, 1329ce110ea1SWei Hu const struct gdma_wqe_request *wqe_req, 1330ce110ea1SWei Hu struct gdma_posted_wqe_info *wqe_info) 1331ce110ea1SWei Hu { 1332ce110ea1SWei Hu struct gdma_context *gc = queue->gdma_dev->gdma_context; 1333ce110ea1SWei Hu int err; 1334ce110ea1SWei Hu 1335ce110ea1SWei Hu err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1336ce110ea1SWei Hu if (err) 1337ce110ea1SWei Hu return err; 1338ce110ea1SWei Hu 1339ce110ea1SWei Hu mana_gd_wq_ring_doorbell(gc, queue); 1340ce110ea1SWei Hu 1341ce110ea1SWei Hu return 0; 1342ce110ea1SWei Hu } 1343ce110ea1SWei Hu 1344ce110ea1SWei Hu static int 1345ce110ea1SWei Hu mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1346ce110ea1SWei Hu { 1347ce110ea1SWei Hu unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1348ce110ea1SWei Hu struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1349ce110ea1SWei Hu uint32_t owner_bits, new_bits, old_bits; 1350ce110ea1SWei Hu struct gdma_cqe *cqe; 1351ce110ea1SWei Hu 1352ce110ea1SWei Hu cqe = &cq_cqe[cq->head % num_cqe]; 1353ce110ea1SWei Hu owner_bits = cqe->cqe_info.owner_bits; 1354ce110ea1SWei Hu 1355ce110ea1SWei Hu old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1356ce110ea1SWei Hu /* Return 0 if no more entries. */ 1357ce110ea1SWei Hu if (owner_bits == old_bits) 1358ce110ea1SWei Hu return 0; 1359ce110ea1SWei Hu 1360ce110ea1SWei Hu new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1361ce110ea1SWei Hu /* Return -1 if overflow detected. */ 1362ce110ea1SWei Hu if (owner_bits != new_bits) 1363ce110ea1SWei Hu return -1; 1364ce110ea1SWei Hu 1365ce110ea1SWei Hu comp->wq_num = cqe->cqe_info.wq_num; 1366ce110ea1SWei Hu comp->is_sq = cqe->cqe_info.is_sq; 1367ce110ea1SWei Hu memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1368ce110ea1SWei Hu 1369ce110ea1SWei Hu return 1; 1370ce110ea1SWei Hu } 1371ce110ea1SWei Hu 1372ce110ea1SWei Hu int 1373ce110ea1SWei Hu mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1374ce110ea1SWei Hu { 1375ce110ea1SWei Hu int cqe_idx; 1376ce110ea1SWei Hu int ret; 1377ce110ea1SWei Hu 1378ce110ea1SWei Hu bus_dmamap_sync(cq->mem_info.dma_tag, cq->mem_info.dma_map, 1379ce110ea1SWei Hu BUS_DMASYNC_POSTREAD); 1380ce110ea1SWei Hu 1381ce110ea1SWei Hu for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1382ce110ea1SWei Hu ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1383ce110ea1SWei Hu 1384ce110ea1SWei Hu if (ret < 0) { 1385ce110ea1SWei Hu cq->head -= cqe_idx; 1386ce110ea1SWei Hu return ret; 1387ce110ea1SWei Hu } 1388ce110ea1SWei Hu 1389ce110ea1SWei Hu if (ret == 0) 1390ce110ea1SWei Hu break; 1391ce110ea1SWei Hu 1392ce110ea1SWei Hu cq->head++; 1393ce110ea1SWei Hu } 1394ce110ea1SWei Hu 1395ce110ea1SWei Hu return cqe_idx; 1396ce110ea1SWei Hu } 1397ce110ea1SWei Hu 1398ce110ea1SWei Hu static void 1399ce110ea1SWei Hu mana_gd_intr(void *arg) 1400ce110ea1SWei Hu { 1401ce110ea1SWei Hu struct gdma_irq_context *gic = arg; 1402ce110ea1SWei Hu 1403ce110ea1SWei Hu if (gic->handler) { 1404ce110ea1SWei Hu gic->handler(gic->arg); 1405ce110ea1SWei Hu } 1406ce110ea1SWei Hu } 1407ce110ea1SWei Hu 1408ce110ea1SWei Hu int 1409ce110ea1SWei Hu mana_gd_alloc_res_map(uint32_t res_avail, 1410ce110ea1SWei Hu struct gdma_resource *r, const char *lock_name) 1411ce110ea1SWei Hu { 1412ce110ea1SWei Hu int n = howmany(res_avail, BITS_PER_LONG); 1413ce110ea1SWei Hu 1414ce110ea1SWei Hu r->map = 1415ce110ea1SWei Hu malloc(n * sizeof(unsigned long), M_DEVBUF, M_WAITOK | M_ZERO); 1416ce110ea1SWei Hu if (!r->map) 1417ce110ea1SWei Hu return ENOMEM; 1418ce110ea1SWei Hu 1419ce110ea1SWei Hu r->size = res_avail; 1420ce110ea1SWei Hu mtx_init(&r->lock_spin, lock_name, NULL, MTX_SPIN); 1421ce110ea1SWei Hu 1422ce110ea1SWei Hu mana_dbg(NULL, 1423ce110ea1SWei Hu "total res %u, total number of unsigned longs %u\n", 1424ce110ea1SWei Hu r->size, n); 1425ce110ea1SWei Hu return (0); 1426ce110ea1SWei Hu } 1427ce110ea1SWei Hu 1428ce110ea1SWei Hu void 1429ce110ea1SWei Hu mana_gd_free_res_map(struct gdma_resource *r) 1430ce110ea1SWei Hu { 1431ce110ea1SWei Hu if (!r || !r->map) 1432ce110ea1SWei Hu return; 1433ce110ea1SWei Hu 1434ce110ea1SWei Hu free(r->map, M_DEVBUF); 1435ce110ea1SWei Hu r->map = NULL; 1436ce110ea1SWei Hu r->size = 0; 1437ce110ea1SWei Hu } 1438ce110ea1SWei Hu 1439ce110ea1SWei Hu static void 1440ce110ea1SWei Hu mana_gd_init_registers(struct gdma_context *gc) 1441ce110ea1SWei Hu { 1442ce110ea1SWei Hu uint64_t bar0_va = rman_get_bushandle(gc->bar0); 1443ce110ea1SWei Hu 1444ce110ea1SWei Hu gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 1445ce110ea1SWei Hu 1446ce110ea1SWei Hu gc->db_page_base = 1447ce110ea1SWei Hu (void *) (bar0_va + mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET)); 1448ce110ea1SWei Hu 1449ce110ea1SWei Hu gc->shm_base = 1450ce110ea1SWei Hu (void *) (bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET)); 1451ce110ea1SWei Hu 1452ce110ea1SWei Hu mana_dbg(NULL, "db_page_size 0x%xx, db_page_base %p," 1453ce110ea1SWei Hu " shm_base %p\n", 1454ce110ea1SWei Hu gc->db_page_size, gc->db_page_base, gc->shm_base); 1455ce110ea1SWei Hu } 1456ce110ea1SWei Hu 1457ce110ea1SWei Hu static struct resource * 1458ce110ea1SWei Hu mana_gd_alloc_bar(device_t dev, int bar) 1459ce110ea1SWei Hu { 1460ce110ea1SWei Hu struct resource *res = NULL; 1461ce110ea1SWei Hu struct pci_map *pm; 1462ce110ea1SWei Hu int rid, type; 1463ce110ea1SWei Hu 1464ce110ea1SWei Hu if (bar < 0 || bar > PCIR_MAX_BAR_0) 1465ce110ea1SWei Hu goto alloc_bar_out; 1466ce110ea1SWei Hu 1467ce110ea1SWei Hu pm = pci_find_bar(dev, PCIR_BAR(bar)); 1468ce110ea1SWei Hu if (!pm) 1469ce110ea1SWei Hu goto alloc_bar_out; 1470ce110ea1SWei Hu 1471ce110ea1SWei Hu if (PCI_BAR_IO(pm->pm_value)) 1472ce110ea1SWei Hu type = SYS_RES_IOPORT; 1473ce110ea1SWei Hu else 1474ce110ea1SWei Hu type = SYS_RES_MEMORY; 1475ce110ea1SWei Hu if (type < 0) 1476ce110ea1SWei Hu goto alloc_bar_out; 1477ce110ea1SWei Hu 1478ce110ea1SWei Hu rid = PCIR_BAR(bar); 1479ce110ea1SWei Hu res = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE); 1480ce110ea1SWei Hu #if defined(__amd64__) 1481ce110ea1SWei Hu if (res) 1482ce110ea1SWei Hu mana_dbg(NULL, "bar %d: rid 0x%x, type 0x%jx," 1483ce110ea1SWei Hu " handle 0x%jx\n", 1484ce110ea1SWei Hu bar, rid, res->r_bustag, res->r_bushandle); 1485ce110ea1SWei Hu #endif 1486ce110ea1SWei Hu 1487ce110ea1SWei Hu alloc_bar_out: 1488ce110ea1SWei Hu return (res); 1489ce110ea1SWei Hu } 1490ce110ea1SWei Hu 1491ce110ea1SWei Hu static void 1492ce110ea1SWei Hu mana_gd_free_pci_res(struct gdma_context *gc) 1493ce110ea1SWei Hu { 1494ce110ea1SWei Hu if (!gc || gc->dev) 1495ce110ea1SWei Hu return; 1496ce110ea1SWei Hu 1497ce110ea1SWei Hu if (gc->bar0 != NULL) { 1498ce110ea1SWei Hu bus_release_resource(gc->dev, SYS_RES_MEMORY, 1499ce110ea1SWei Hu PCIR_BAR(GDMA_BAR0), gc->bar0); 1500ce110ea1SWei Hu } 1501ce110ea1SWei Hu 1502ce110ea1SWei Hu if (gc->msix != NULL) { 1503ce110ea1SWei Hu bus_release_resource(gc->dev, SYS_RES_MEMORY, 1504ce110ea1SWei Hu gc->msix_rid, gc->msix); 1505ce110ea1SWei Hu } 1506ce110ea1SWei Hu } 1507ce110ea1SWei Hu 1508ce110ea1SWei Hu static int 1509ce110ea1SWei Hu mana_gd_setup_irqs(device_t dev) 1510ce110ea1SWei Hu { 1511ce110ea1SWei Hu unsigned int max_queues_per_port = mp_ncpus; 1512ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 1513ce110ea1SWei Hu struct gdma_irq_context *gic; 1514ce110ea1SWei Hu unsigned int max_irqs; 1515ce110ea1SWei Hu int nvec; 1516ce110ea1SWei Hu int rc, rcc, i; 1517ce110ea1SWei Hu 1518ce110ea1SWei Hu if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1519ce110ea1SWei Hu max_queues_per_port = MANA_MAX_NUM_QUEUES; 1520ce110ea1SWei Hu 1521ce110ea1SWei Hu /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 15221833cf13SWei Hu max_irqs = max_queues_per_port + 1; 1523ce110ea1SWei Hu 1524ce110ea1SWei Hu nvec = max_irqs; 1525ce110ea1SWei Hu rc = pci_alloc_msix(dev, &nvec); 1526ce110ea1SWei Hu if (unlikely(rc != 0)) { 1527ce110ea1SWei Hu device_printf(dev, 1528ce110ea1SWei Hu "Failed to allocate MSIX, vectors %d, error: %d\n", 1529ce110ea1SWei Hu nvec, rc); 1530ce110ea1SWei Hu rc = ENOSPC; 1531ce110ea1SWei Hu goto err_setup_irq_alloc; 1532ce110ea1SWei Hu } 1533ce110ea1SWei Hu 1534ce110ea1SWei Hu if (nvec != max_irqs) { 1535ce110ea1SWei Hu if (nvec == 1) { 1536ce110ea1SWei Hu device_printf(dev, 1537ce110ea1SWei Hu "Not enough number of MSI-x allocated: %d\n", 1538ce110ea1SWei Hu nvec); 1539ce110ea1SWei Hu rc = ENOSPC; 1540ce110ea1SWei Hu goto err_setup_irq_release; 1541ce110ea1SWei Hu } 1542ce110ea1SWei Hu device_printf(dev, "Allocated only %d MSI-x (%d requested)\n", 1543ce110ea1SWei Hu nvec, max_irqs); 1544ce110ea1SWei Hu } 1545ce110ea1SWei Hu 1546ce110ea1SWei Hu gc->irq_contexts = malloc(nvec * sizeof(struct gdma_irq_context), 1547ce110ea1SWei Hu M_DEVBUF, M_WAITOK | M_ZERO); 1548ce110ea1SWei Hu if (!gc->irq_contexts) { 1549ce110ea1SWei Hu rc = ENOMEM; 1550ce110ea1SWei Hu goto err_setup_irq_release; 1551ce110ea1SWei Hu } 1552ce110ea1SWei Hu 1553ce110ea1SWei Hu for (i = 0; i < nvec; i++) { 1554ce110ea1SWei Hu gic = &gc->irq_contexts[i]; 1555ce110ea1SWei Hu gic->msix_e.entry = i; 1556ce110ea1SWei Hu /* Vector starts from 1. */ 1557ce110ea1SWei Hu gic->msix_e.vector = i + 1; 1558ce110ea1SWei Hu gic->handler = NULL; 1559ce110ea1SWei Hu gic->arg = NULL; 1560ce110ea1SWei Hu 1561ce110ea1SWei Hu gic->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1562ce110ea1SWei Hu &gic->msix_e.vector, RF_ACTIVE | RF_SHAREABLE); 1563ce110ea1SWei Hu if (unlikely(gic->res == NULL)) { 1564ce110ea1SWei Hu rc = ENOMEM; 1565ce110ea1SWei Hu device_printf(dev, "could not allocate resource " 1566ce110ea1SWei Hu "for irq vector %d\n", gic->msix_e.vector); 1567ce110ea1SWei Hu goto err_setup_irq; 1568ce110ea1SWei Hu } 1569ce110ea1SWei Hu 1570ce110ea1SWei Hu rc = bus_setup_intr(dev, gic->res, 1571ce110ea1SWei Hu INTR_TYPE_NET | INTR_MPSAFE, NULL, mana_gd_intr, 1572ce110ea1SWei Hu gic, &gic->cookie); 1573ce110ea1SWei Hu if (unlikely(rc != 0)) { 1574ce110ea1SWei Hu device_printf(dev, "failed to register interrupt " 1575ce110ea1SWei Hu "handler for irq %ju vector %d: error %d\n", 1576ce110ea1SWei Hu rman_get_start(gic->res), gic->msix_e.vector, rc); 1577ce110ea1SWei Hu goto err_setup_irq; 1578ce110ea1SWei Hu } 1579ce110ea1SWei Hu gic->requested = true; 1580ce110ea1SWei Hu 1581ce110ea1SWei Hu mana_dbg(NULL, "added msix vector %d irq %ju\n", 1582ce110ea1SWei Hu gic->msix_e.vector, rman_get_start(gic->res)); 1583ce110ea1SWei Hu } 1584ce110ea1SWei Hu 1585ce110ea1SWei Hu rc = mana_gd_alloc_res_map(nvec, &gc->msix_resource, 1586ce110ea1SWei Hu "gdma msix res lock"); 1587ce110ea1SWei Hu if (rc != 0) { 1588ce110ea1SWei Hu device_printf(dev, "failed to allocate memory " 1589ce110ea1SWei Hu "for msix bitmap\n"); 1590ce110ea1SWei Hu goto err_setup_irq; 1591ce110ea1SWei Hu } 1592ce110ea1SWei Hu 1593ce110ea1SWei Hu gc->max_num_msix = nvec; 1594ce110ea1SWei Hu gc->num_msix_usable = nvec; 1595ce110ea1SWei Hu 1596ce110ea1SWei Hu mana_dbg(NULL, "setup %d msix interrupts\n", nvec); 1597ce110ea1SWei Hu 1598ce110ea1SWei Hu return (0); 1599ce110ea1SWei Hu 1600ce110ea1SWei Hu err_setup_irq: 1601ce110ea1SWei Hu for (; i >= 0; i--) { 1602ce110ea1SWei Hu gic = &gc->irq_contexts[i]; 1603ce110ea1SWei Hu rcc = 0; 1604ce110ea1SWei Hu 1605ce110ea1SWei Hu /* 1606ce110ea1SWei Hu * If gic->requested is true, we need to free both intr and 1607ce110ea1SWei Hu * resources. 1608ce110ea1SWei Hu */ 1609ce110ea1SWei Hu if (gic->requested) 1610ce110ea1SWei Hu rcc = bus_teardown_intr(dev, gic->res, gic->cookie); 1611ce110ea1SWei Hu if (unlikely(rcc != 0)) 1612ce110ea1SWei Hu device_printf(dev, "could not release " 1613ce110ea1SWei Hu "irq vector %d, error: %d\n", 1614ce110ea1SWei Hu gic->msix_e.vector, rcc); 1615ce110ea1SWei Hu 1616ce110ea1SWei Hu rcc = 0; 1617ce110ea1SWei Hu if (gic->res != NULL) { 1618ce110ea1SWei Hu rcc = bus_release_resource(dev, SYS_RES_IRQ, 1619ce110ea1SWei Hu gic->msix_e.vector, gic->res); 1620ce110ea1SWei Hu } 1621ce110ea1SWei Hu if (unlikely(rcc != 0)) 1622ce110ea1SWei Hu device_printf(dev, "dev has no parent while " 1623ce110ea1SWei Hu "releasing resource for irq vector %d\n", 1624ce110ea1SWei Hu gic->msix_e.vector); 1625ce110ea1SWei Hu gic->requested = false; 1626ce110ea1SWei Hu gic->res = NULL; 1627ce110ea1SWei Hu } 1628ce110ea1SWei Hu 1629ce110ea1SWei Hu free(gc->irq_contexts, M_DEVBUF); 1630ce110ea1SWei Hu gc->irq_contexts = NULL; 1631ce110ea1SWei Hu err_setup_irq_release: 1632ce110ea1SWei Hu pci_release_msi(dev); 1633ce110ea1SWei Hu err_setup_irq_alloc: 1634ce110ea1SWei Hu return (rc); 1635ce110ea1SWei Hu } 1636ce110ea1SWei Hu 1637ce110ea1SWei Hu static void 1638ce110ea1SWei Hu mana_gd_remove_irqs(device_t dev) 1639ce110ea1SWei Hu { 1640ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 1641ce110ea1SWei Hu struct gdma_irq_context *gic; 1642ce110ea1SWei Hu int rc, i; 1643ce110ea1SWei Hu 1644ce110ea1SWei Hu mana_gd_free_res_map(&gc->msix_resource); 1645ce110ea1SWei Hu 1646ce110ea1SWei Hu for (i = 0; i < gc->max_num_msix; i++) { 1647ce110ea1SWei Hu gic = &gc->irq_contexts[i]; 1648ce110ea1SWei Hu if (gic->requested) { 1649ce110ea1SWei Hu rc = bus_teardown_intr(dev, gic->res, gic->cookie); 1650ce110ea1SWei Hu if (unlikely(rc != 0)) { 1651ce110ea1SWei Hu device_printf(dev, "failed to tear down " 1652ce110ea1SWei Hu "irq vector %d, error: %d\n", 1653ce110ea1SWei Hu gic->msix_e.vector, rc); 1654ce110ea1SWei Hu } 1655ce110ea1SWei Hu gic->requested = false; 1656ce110ea1SWei Hu } 1657ce110ea1SWei Hu 1658ce110ea1SWei Hu if (gic->res != NULL) { 1659ce110ea1SWei Hu rc = bus_release_resource(dev, SYS_RES_IRQ, 1660ce110ea1SWei Hu gic->msix_e.vector, gic->res); 1661ce110ea1SWei Hu if (unlikely(rc != 0)) { 1662ce110ea1SWei Hu device_printf(dev, "dev has no parent while " 1663ce110ea1SWei Hu "releasing resource for irq vector %d\n", 1664ce110ea1SWei Hu gic->msix_e.vector); 1665ce110ea1SWei Hu } 1666ce110ea1SWei Hu gic->res = NULL; 1667ce110ea1SWei Hu } 1668ce110ea1SWei Hu } 1669ce110ea1SWei Hu 1670ce110ea1SWei Hu gc->max_num_msix = 0; 1671ce110ea1SWei Hu gc->num_msix_usable = 0; 1672ce110ea1SWei Hu free(gc->irq_contexts, M_DEVBUF); 1673ce110ea1SWei Hu gc->irq_contexts = NULL; 1674ce110ea1SWei Hu 1675ce110ea1SWei Hu pci_release_msi(dev); 1676ce110ea1SWei Hu } 1677ce110ea1SWei Hu 1678ce110ea1SWei Hu static int 1679ce110ea1SWei Hu mana_gd_probe(device_t dev) 1680ce110ea1SWei Hu { 1681ce110ea1SWei Hu mana_vendor_id_t *ent; 1682ce110ea1SWei Hu char adapter_name[60]; 1683ce110ea1SWei Hu uint16_t pci_vendor_id = 0; 1684ce110ea1SWei Hu uint16_t pci_device_id = 0; 1685ce110ea1SWei Hu 1686ce110ea1SWei Hu pci_vendor_id = pci_get_vendor(dev); 1687ce110ea1SWei Hu pci_device_id = pci_get_device(dev); 1688ce110ea1SWei Hu 1689ce110ea1SWei Hu ent = mana_id_table; 1690ce110ea1SWei Hu while (ent->vendor_id != 0) { 1691ce110ea1SWei Hu if ((pci_vendor_id == ent->vendor_id) && 1692ce110ea1SWei Hu (pci_device_id == ent->device_id)) { 1693ce110ea1SWei Hu mana_dbg(NULL, "vendor=%x device=%x\n", 1694ce110ea1SWei Hu pci_vendor_id, pci_device_id); 1695ce110ea1SWei Hu 1696ce110ea1SWei Hu sprintf(adapter_name, DEVICE_DESC); 1697ce110ea1SWei Hu device_set_desc_copy(dev, adapter_name); 1698ce110ea1SWei Hu return (BUS_PROBE_DEFAULT); 1699ce110ea1SWei Hu } 1700ce110ea1SWei Hu 1701ce110ea1SWei Hu ent++; 1702ce110ea1SWei Hu } 1703ce110ea1SWei Hu 1704ce110ea1SWei Hu return (ENXIO); 1705ce110ea1SWei Hu } 1706ce110ea1SWei Hu 1707ce110ea1SWei Hu /** 1708ce110ea1SWei Hu * mana_attach - Device Initialization Routine 1709ce110ea1SWei Hu * @dev: device information struct 1710ce110ea1SWei Hu * 1711ce110ea1SWei Hu * Returns 0 on success, otherwise on failure. 1712ce110ea1SWei Hu * 1713ce110ea1SWei Hu * mana_attach initializes a GDMA adapter identified by a device structure. 1714ce110ea1SWei Hu **/ 1715ce110ea1SWei Hu static int 1716ce110ea1SWei Hu mana_gd_attach(device_t dev) 1717ce110ea1SWei Hu { 1718ce110ea1SWei Hu struct gdma_context *gc; 1719ce110ea1SWei Hu int msix_rid; 1720ce110ea1SWei Hu int rc; 1721ce110ea1SWei Hu 1722ce110ea1SWei Hu gc = device_get_softc(dev); 1723ce110ea1SWei Hu gc->dev = dev; 1724ce110ea1SWei Hu 1725ce110ea1SWei Hu pci_enable_io(dev, SYS_RES_IOPORT); 1726ce110ea1SWei Hu pci_enable_io(dev, SYS_RES_MEMORY); 1727ce110ea1SWei Hu 1728ce110ea1SWei Hu pci_enable_busmaster(dev); 1729ce110ea1SWei Hu 1730ce110ea1SWei Hu gc->bar0 = mana_gd_alloc_bar(dev, GDMA_BAR0); 1731ce110ea1SWei Hu if (unlikely(gc->bar0 == NULL)) { 1732ce110ea1SWei Hu device_printf(dev, 1733ce110ea1SWei Hu "unable to allocate bus resource for bar0!\n"); 1734ce110ea1SWei Hu rc = ENOMEM; 1735ce110ea1SWei Hu goto err_disable_dev; 1736ce110ea1SWei Hu } 1737ce110ea1SWei Hu 1738ce110ea1SWei Hu /* Store bar0 tage and handle for quick access */ 1739ce110ea1SWei Hu gc->gd_bus.bar0_t = rman_get_bustag(gc->bar0); 1740ce110ea1SWei Hu gc->gd_bus.bar0_h = rman_get_bushandle(gc->bar0); 1741ce110ea1SWei Hu 1742ce110ea1SWei Hu /* Map MSI-x vector table */ 1743ce110ea1SWei Hu msix_rid = pci_msix_table_bar(dev); 1744ce110ea1SWei Hu 1745ce110ea1SWei Hu mana_dbg(NULL, "msix_rid 0x%x\n", msix_rid); 1746ce110ea1SWei Hu 1747ce110ea1SWei Hu gc->msix = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1748ce110ea1SWei Hu &msix_rid, RF_ACTIVE); 1749ce110ea1SWei Hu if (unlikely(gc->msix == NULL)) { 1750ce110ea1SWei Hu device_printf(dev, 1751ce110ea1SWei Hu "unable to allocate bus resource for msix!\n"); 1752ce110ea1SWei Hu rc = ENOMEM; 1753ce110ea1SWei Hu goto err_free_pci_res; 1754ce110ea1SWei Hu } 1755ce110ea1SWei Hu gc->msix_rid = msix_rid; 1756ce110ea1SWei Hu 1757ce110ea1SWei Hu if (unlikely(gc->gd_bus.bar0_h == 0)) { 1758ce110ea1SWei Hu device_printf(dev, "failed to map bar0!\n"); 1759ce110ea1SWei Hu rc = ENXIO; 1760ce110ea1SWei Hu goto err_free_pci_res; 1761ce110ea1SWei Hu } 1762ce110ea1SWei Hu 1763ce110ea1SWei Hu mana_gd_init_registers(gc); 1764ce110ea1SWei Hu 1765ce110ea1SWei Hu mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1766ce110ea1SWei Hu 1767ce110ea1SWei Hu rc = mana_gd_setup_irqs(dev); 1768ce110ea1SWei Hu if (rc) { 1769ce110ea1SWei Hu goto err_free_pci_res; 1770ce110ea1SWei Hu } 1771ce110ea1SWei Hu 1772ce110ea1SWei Hu sx_init(&gc->eq_test_event_sx, "gdma test event sx"); 1773ce110ea1SWei Hu 1774ce110ea1SWei Hu rc = mana_hwc_create_channel(gc); 1775ce110ea1SWei Hu if (rc) { 1776ce110ea1SWei Hu mana_dbg(NULL, "Failed to create hwc channel\n"); 1777ce110ea1SWei Hu if (rc == EIO) 1778ce110ea1SWei Hu goto err_clean_up_gdma; 1779ce110ea1SWei Hu else 1780ce110ea1SWei Hu goto err_remove_irq; 1781ce110ea1SWei Hu } 1782ce110ea1SWei Hu 1783ce110ea1SWei Hu rc = mana_gd_verify_vf_version(dev); 1784ce110ea1SWei Hu if (rc) { 1785ce110ea1SWei Hu mana_dbg(NULL, "Failed to verify vf\n"); 1786ce110ea1SWei Hu goto err_clean_up_gdma; 1787ce110ea1SWei Hu } 1788ce110ea1SWei Hu 1789ce110ea1SWei Hu rc = mana_gd_query_max_resources(dev); 1790ce110ea1SWei Hu if (rc) { 1791ce110ea1SWei Hu mana_dbg(NULL, "Failed to query max resources\n"); 1792ce110ea1SWei Hu goto err_clean_up_gdma; 1793ce110ea1SWei Hu } 1794ce110ea1SWei Hu 1795ce110ea1SWei Hu rc = mana_gd_detect_devices(dev); 1796ce110ea1SWei Hu if (rc) { 1797ce110ea1SWei Hu mana_dbg(NULL, "Failed to detect mana device\n"); 1798ce110ea1SWei Hu goto err_clean_up_gdma; 1799ce110ea1SWei Hu } 1800ce110ea1SWei Hu 1801ce110ea1SWei Hu rc = mana_probe(&gc->mana); 1802ce110ea1SWei Hu if (rc) { 1803ce110ea1SWei Hu mana_dbg(NULL, "Failed to probe mana device\n"); 1804ce110ea1SWei Hu goto err_clean_up_gdma; 1805ce110ea1SWei Hu } 1806ce110ea1SWei Hu 1807ce110ea1SWei Hu return (0); 1808ce110ea1SWei Hu 1809ce110ea1SWei Hu err_clean_up_gdma: 1810ce110ea1SWei Hu mana_hwc_destroy_channel(gc); 1811ce110ea1SWei Hu if (gc->cq_table) 1812ce110ea1SWei Hu free(gc->cq_table, M_DEVBUF); 1813ce110ea1SWei Hu gc->cq_table = NULL; 1814ce110ea1SWei Hu err_remove_irq: 1815ce110ea1SWei Hu mana_gd_remove_irqs(dev); 1816ce110ea1SWei Hu err_free_pci_res: 1817ce110ea1SWei Hu mana_gd_free_pci_res(gc); 1818ce110ea1SWei Hu err_disable_dev: 1819ce110ea1SWei Hu pci_disable_busmaster(dev); 1820ce110ea1SWei Hu 1821ce110ea1SWei Hu return(rc); 1822ce110ea1SWei Hu } 1823ce110ea1SWei Hu 1824ce110ea1SWei Hu /** 1825ce110ea1SWei Hu * mana_detach - Device Removal Routine 1826ce110ea1SWei Hu * @pdev: device information struct 1827ce110ea1SWei Hu * 1828ce110ea1SWei Hu * mana_detach is called by the device subsystem to alert the driver 1829ce110ea1SWei Hu * that it should release a PCI device. 1830ce110ea1SWei Hu **/ 1831ce110ea1SWei Hu static int 1832ce110ea1SWei Hu mana_gd_detach(device_t dev) 1833ce110ea1SWei Hu { 1834ce110ea1SWei Hu struct gdma_context *gc = device_get_softc(dev); 1835ce110ea1SWei Hu 1836ce110ea1SWei Hu mana_remove(&gc->mana); 1837ce110ea1SWei Hu 1838ce110ea1SWei Hu mana_hwc_destroy_channel(gc); 1839ce110ea1SWei Hu free(gc->cq_table, M_DEVBUF); 1840ce110ea1SWei Hu gc->cq_table = NULL; 1841ce110ea1SWei Hu 1842ce110ea1SWei Hu mana_gd_remove_irqs(dev); 1843ce110ea1SWei Hu 1844ce110ea1SWei Hu mana_gd_free_pci_res(gc); 1845ce110ea1SWei Hu 1846ce110ea1SWei Hu pci_disable_busmaster(dev); 1847ce110ea1SWei Hu 1848ce110ea1SWei Hu return (bus_generic_detach(dev)); 1849ce110ea1SWei Hu } 1850ce110ea1SWei Hu 1851ce110ea1SWei Hu 1852ce110ea1SWei Hu /********************************************************************* 1853ce110ea1SWei Hu * FreeBSD Device Interface Entry Points 1854ce110ea1SWei Hu *********************************************************************/ 1855ce110ea1SWei Hu 1856ce110ea1SWei Hu static device_method_t mana_methods[] = { 1857ce110ea1SWei Hu /* Device interface */ 1858ce110ea1SWei Hu DEVMETHOD(device_probe, mana_gd_probe), 1859ce110ea1SWei Hu DEVMETHOD(device_attach, mana_gd_attach), 1860ce110ea1SWei Hu DEVMETHOD(device_detach, mana_gd_detach), 1861ce110ea1SWei Hu DEVMETHOD_END 1862ce110ea1SWei Hu }; 1863ce110ea1SWei Hu 1864ce110ea1SWei Hu static driver_t mana_driver = { 1865ce110ea1SWei Hu "mana", mana_methods, sizeof(struct gdma_context), 1866ce110ea1SWei Hu }; 1867ce110ea1SWei Hu 1868ce110ea1SWei Hu devclass_t mana_devclass; 1869ce110ea1SWei Hu DRIVER_MODULE(mana, pci, mana_driver, mana_devclass, 0, 0); 1870ce110ea1SWei Hu MODULE_PNP_INFO("U16:vendor;U16:device", pci, mana, mana_id_table, 1871ce110ea1SWei Hu nitems(mana_id_table) - 1); 1872ce110ea1SWei Hu MODULE_DEPEND(mana, pci, 1, 1, 1); 1873ce110ea1SWei Hu MODULE_DEPEND(mana, ether, 1, 1, 1); 1874ce110ea1SWei Hu 1875ce110ea1SWei Hu /*********************************************************************/ 1876