1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 IronPort Systems 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /*- 29 * Copyright (c) 2007 LSI Corp. 30 * Copyright (c) 2007 Rajesh Prabhakaran. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 52 * SUCH DAMAGE. 53 */ 54 55 #ifndef _MFIREG_H 56 #define _MFIREG_H 57 58 #include <sys/cdefs.h> 59 __FBSDID("$FreeBSD$"); 60 61 /* 62 * MegaRAID SAS MFI firmware definitions 63 * 64 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 65 * new firmware interface from the old AMI MegaRAID one, and there is no 66 * reason why this interface should be limited to just SAS. In any case, LSI 67 * seems to also call this interface 'MFI', so that will be used here. 68 */ 69 #define MEGAMFI_FRAME_SIZE 64 70 /* 71 * Start with the register set. All registers are 32 bits wide. 72 * The usual Intel IOP style setup. 73 */ 74 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 75 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 76 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 77 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 78 #define MFI_IDB 0x20 /* Inbound doorbell */ 79 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 80 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 81 #define MFI_ODB 0x2c /* Outbound doorbell */ 82 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 83 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 84 #define MFI_IQP 0x40 /* Inbound queue port */ 85 #define MFI_OQP 0x44 /* Outbound queue port */ 86 87 /* 88 * ThunderBolt specific Register 89 */ 90 91 #define MFI_RFPI 0x48 /* reply_free_post_host_index */ 92 #define MFI_RPI 0x6c /* reply_post_host_index */ 93 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 94 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 95 96 /* 97 * 1078 specific related register 98 */ 99 #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 100 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 101 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 102 #define MFI_1078_EIM 0x80000004 /* 1078 enable interrupt mask */ 103 #define MFI_RMI 0x2 /* reply message interrupt */ 104 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 105 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 106 107 /* OCR registers */ 108 #define MFI_WSR 0x004 /* write sequence register */ 109 #define MFI_HDR 0x008 /* host diagnostic register */ 110 #define MFI_RSR 0x3c3 /* Reset Status Register */ 111 112 /* 113 * GEN2 specific changes 114 */ 115 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 116 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 117 118 /* 119 * skinny specific changes 120 */ 121 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 122 #define MFI_IQPL 0x000000c0 123 #define MFI_IQPH 0x000000c4 124 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 125 126 /* Bits for MFI_OSTS */ 127 #define MFI_OSTS_INTR_VALID 0x00000002 128 129 /* OCR specific flags */ 130 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 131 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 132 133 /* 134 * Firmware state values. Found in OMSG0 during initialization. 135 */ 136 #define MFI_FWSTATE_MASK 0xf0000000 137 #define MFI_FWSTATE_UNDEFINED 0x00000000 138 #define MFI_FWSTATE_BB_INIT 0x10000000 139 #define MFI_FWSTATE_FW_INIT 0x40000000 140 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 141 #define MFI_FWSTATE_FW_INIT_2 0x70000000 142 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 143 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 144 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 145 #define MFI_FWSTATE_READY 0xb0000000 146 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 147 #define MFI_FWSTATE_FAULT 0xf0000000 148 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 149 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 150 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 151 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 152 #define MFI_RESET_REQUIRED 0x00000001 153 154 /* ThunderBolt Support */ 155 #define MFI_FWSTATE_TB_MASK 0xf0000000 156 #define MFI_FWSTATE_TB_RESET 0x00000000 157 #define MFI_FWSTATE_TB_READY 0x10000000 158 #define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 159 #define MFI_FWSTATE_TB_FAULT 0x40000000 160 161 /* 162 * Control bits to drive the card to ready state. These go into the IDB 163 * register. 164 */ 165 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 166 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 167 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 168 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 169 #define MFI_FWINIT_HOTPLUG 0x00000010 170 171 /* ADP reset flags */ 172 #define MFI_STOP_ADP 0x00000020 173 #define MFI_ADP_RESET 0x00000040 174 #define DIAG_WRITE_ENABLE 0x00000080 175 #define DIAG_RESET_ADAPTER 0x00000004 176 177 /* MFI Commands */ 178 typedef enum { 179 MFI_CMD_INIT = 0x00, 180 MFI_CMD_LD_READ, 181 MFI_CMD_LD_WRITE, 182 MFI_CMD_LD_SCSI_IO, 183 MFI_CMD_PD_SCSI_IO, 184 MFI_CMD_DCMD, 185 MFI_CMD_ABORT, 186 MFI_CMD_SMP, 187 MFI_CMD_STP 188 } mfi_cmd_t; 189 190 /* Direct commands */ 191 typedef enum { 192 MFI_DCMD_CTRL_GETINFO = 0x01010000, 193 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 194 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 195 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 196 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 197 MFI_DCMD_CTRL_GET_PROPS = 0x01020100, 198 MFI_DCMD_CTRL_SET_PROPS = 0x01020200, 199 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 200 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 201 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 202 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 203 MFI_DCMD_PR_GET_STATUS = 0x01070100, 204 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 205 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 206 MFI_DCMD_PR_START = 0x01070400, 207 MFI_DCMD_PR_STOP = 0x01070500, 208 MFI_DCMD_TIME_SECS_GET = 0x01080201, 209 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 210 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 211 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 212 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 213 MFI_DCMD_PD_GET_LIST = 0x02010000, 214 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 215 MFI_DCMD_PD_GET_INFO = 0x02020000, 216 MFI_DCMD_PD_STATE_SET = 0x02030100, 217 MFI_DCMD_PD_REBUILD_START = 0x02040100, 218 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 219 MFI_DCMD_PD_CLEAR_START = 0x02050100, 220 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 221 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 222 MFI_DCMD_PD_LOCATE_START = 0x02070100, 223 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 224 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 225 MFI_DCMD_LD_SYNC = 0x0300e102, 226 MFI_DCMD_LD_GET_LIST = 0x03010000, 227 MFI_DCMD_LD_GET_INFO = 0x03020000, 228 MFI_DCMD_LD_GET_PROP = 0x03030000, 229 MFI_DCMD_LD_SET_PROP = 0x03040000, 230 MFI_DCMD_LD_INIT_START = 0x03060100, 231 MFI_DCMD_LD_DELETE = 0x03090000, 232 MFI_DCMD_CFG_READ = 0x04010000, 233 MFI_DCMD_CFG_ADD = 0x04020000, 234 MFI_DCMD_CFG_CLEAR = 0x04030000, 235 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 236 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 237 MFI_DCMD_CFG_FOREIGN_SCAN = 0x04060100, 238 MFI_DCMD_CFG_FOREIGN_DISPLAY = 0x04060200, 239 MFI_DCMD_CFG_FOREIGN_PREVIEW = 0x04060300, 240 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 241 MFI_DCMD_CFG_FOREIGN_CLEAR = 0x04060500, 242 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 243 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 244 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 245 MFI_DCMD_BBU_START_LEARN = 0x05040000, 246 MFI_DCMD_BBU_GET_PROP = 0x05050100, 247 MFI_DCMD_BBU_SET_PROP = 0x05050200, 248 MFI_DCMD_CLUSTER = 0x08000000, 249 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 250 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 251 } mfi_dcmd_t; 252 253 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 254 #define MFI_FLUSHCACHE_CTRL 0x01 255 #define MFI_FLUSHCACHE_DISK 0x02 256 257 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 258 #define MFI_SHUTDOWN_SPINDOWN 0x01 259 260 /* 261 * MFI Frame flags 262 */ 263 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 264 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 265 #define MFI_FRAME_SGL32 0x0000 266 #define MFI_FRAME_SGL64 0x0002 267 #define MFI_FRAME_SENSE32 0x0000 268 #define MFI_FRAME_SENSE64 0x0004 269 #define MFI_FRAME_DIR_NONE 0x0000 270 #define MFI_FRAME_DIR_WRITE 0x0008 271 #define MFI_FRAME_DIR_READ 0x0010 272 #define MFI_FRAME_DIR_BOTH 0x0018 273 #define MFI_FRAME_IEEE_SGL 0x0020 274 #define MFI_FRAME_FMT "\20" \ 275 "\1NOPOST" \ 276 "\2SGL64" \ 277 "\3SENSE64" \ 278 "\4WRITE" \ 279 "\5READ" \ 280 "\6IEEESGL" 281 282 /* ThunderBolt Specific */ 283 284 /* 285 * Pre-TB command size and TB command size. 286 * We will be checking it at the load time for the time being 287 */ 288 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 289 290 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 291 /* 292 * We are defining only 128 byte message to reduce memory move over head 293 * and also it will reduce the SRB extension size by 128byte compared with 294 * 256 message size 295 */ 296 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 297 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 298 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 299 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 300 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 301 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 302 303 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 304 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 305 306 #define MR_INTERNAL_MFI_FRAMES_SMID 1 307 #define MR_CTRL_EVENT_WAIT_SMID 2 308 #define MR_INTERNAL_DRIVER_RESET_SMID 3 309 310 /* MFI Status codes */ 311 typedef enum { 312 MFI_STAT_OK = 0x00, 313 MFI_STAT_INVALID_CMD, 314 MFI_STAT_INVALID_DCMD, 315 MFI_STAT_INVALID_PARAMETER, 316 MFI_STAT_INVALID_SEQUENCE_NUMBER, 317 MFI_STAT_ABORT_NOT_POSSIBLE, 318 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 319 MFI_STAT_APP_IN_USE, 320 MFI_STAT_APP_NOT_INITIALIZED, 321 MFI_STAT_ARRAY_INDEX_INVALID, 322 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 323 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 324 MFI_STAT_DEVICE_NOT_FOUND, 325 MFI_STAT_DRIVE_TOO_SMALL, 326 MFI_STAT_FLASH_ALLOC_FAIL, 327 MFI_STAT_FLASH_BUSY, 328 MFI_STAT_FLASH_ERROR = 0x10, 329 MFI_STAT_FLASH_IMAGE_BAD, 330 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 331 MFI_STAT_FLASH_NOT_OPEN, 332 MFI_STAT_FLASH_NOT_STARTED, 333 MFI_STAT_FLUSH_FAILED, 334 MFI_STAT_HOST_CODE_NOT_FOUNT, 335 MFI_STAT_LD_CC_IN_PROGRESS, 336 MFI_STAT_LD_INIT_IN_PROGRESS, 337 MFI_STAT_LD_LBA_OUT_OF_RANGE, 338 MFI_STAT_LD_MAX_CONFIGURED, 339 MFI_STAT_LD_NOT_OPTIMAL, 340 MFI_STAT_LD_RBLD_IN_PROGRESS, 341 MFI_STAT_LD_RECON_IN_PROGRESS, 342 MFI_STAT_LD_WRONG_RAID_LEVEL, 343 MFI_STAT_MAX_SPARES_EXCEEDED, 344 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 345 MFI_STAT_MFC_HW_ERROR, 346 MFI_STAT_NO_HW_PRESENT, 347 MFI_STAT_NOT_FOUND, 348 MFI_STAT_NOT_IN_ENCL, 349 MFI_STAT_PD_CLEAR_IN_PROGRESS, 350 MFI_STAT_PD_TYPE_WRONG, 351 MFI_STAT_PR_DISABLED, 352 MFI_STAT_ROW_INDEX_INVALID, 353 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 354 MFI_STAT_SAS_CONFIG_INVALID_DATA, 355 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 356 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 357 MFI_STAT_SCSI_DONE_WITH_ERROR, 358 MFI_STAT_SCSI_IO_FAILED, 359 MFI_STAT_SCSI_RESERVATION_CONFLICT, 360 MFI_STAT_SHUTDOWN_FAILED = 0x30, 361 MFI_STAT_TIME_NOT_SET, 362 MFI_STAT_WRONG_STATE, 363 MFI_STAT_LD_OFFLINE, 364 MFI_STAT_PEER_NOTIFICATION_REJECTED, 365 MFI_STAT_PEER_NOTIFICATION_FAILED, 366 MFI_STAT_RESERVATION_IN_PROGRESS, 367 MFI_STAT_I2C_ERRORS_DETECTED, 368 MFI_STAT_PCI_ERRORS_DETECTED, 369 MFI_STAT_DIAG_FAILED, 370 MFI_STAT_BOOT_MSG_PENDING, 371 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 372 MFI_STAT_INVALID_STATUS = 0xFF 373 } mfi_status_t; 374 375 typedef enum { 376 MFI_EVT_CLASS_DEBUG = -2, 377 MFI_EVT_CLASS_PROGRESS = -1, 378 MFI_EVT_CLASS_INFO = 0, 379 MFI_EVT_CLASS_WARNING = 1, 380 MFI_EVT_CLASS_CRITICAL = 2, 381 MFI_EVT_CLASS_FATAL = 3, 382 MFI_EVT_CLASS_DEAD = 4 383 } mfi_evt_class_t; 384 385 typedef enum { 386 MFI_EVT_LOCALE_LD = 0x0001, 387 MFI_EVT_LOCALE_PD = 0x0002, 388 MFI_EVT_LOCALE_ENCL = 0x0004, 389 MFI_EVT_LOCALE_BBU = 0x0008, 390 MFI_EVT_LOCALE_SAS = 0x0010, 391 MFI_EVT_LOCALE_CTRL = 0x0020, 392 MFI_EVT_LOCALE_CONFIG = 0x0040, 393 MFI_EVT_LOCALE_CLUSTER = 0x0080, 394 MFI_EVT_LOCALE_ALL = 0xffff 395 } mfi_evt_locale_t; 396 397 typedef enum { 398 MR_EVT_ARGS_NONE = 0x00, 399 MR_EVT_ARGS_CDB_SENSE, 400 MR_EVT_ARGS_LD, 401 MR_EVT_ARGS_LD_COUNT, 402 MR_EVT_ARGS_LD_LBA, 403 MR_EVT_ARGS_LD_OWNER, 404 MR_EVT_ARGS_LD_LBA_PD_LBA, 405 MR_EVT_ARGS_LD_PROG, 406 MR_EVT_ARGS_LD_STATE, 407 MR_EVT_ARGS_LD_STRIP, 408 MR_EVT_ARGS_PD, 409 MR_EVT_ARGS_PD_ERR, 410 MR_EVT_ARGS_PD_LBA, 411 MR_EVT_ARGS_PD_LBA_LD, 412 MR_EVT_ARGS_PD_PROG, 413 MR_EVT_ARGS_PD_STATE, 414 MR_EVT_ARGS_PCI, 415 MR_EVT_ARGS_RATE, 416 MR_EVT_ARGS_STR, 417 MR_EVT_ARGS_TIME, 418 MR_EVT_ARGS_ECC 419 } mfi_evt_args; 420 421 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 422 #define MR_EVT_PD_REMOVED 0x0070 423 #define MR_EVT_PD_INSERTED 0x005b 424 #define MR_EVT_LD_CHANGE 0x0051 425 426 typedef enum { 427 MR_LD_CACHE_WRITE_BACK = 0x01, 428 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 429 MR_LD_CACHE_READ_AHEAD = 0x04, 430 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 431 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 432 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 433 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 434 } mfi_ld_cache; 435 #define MR_LD_CACHE_MASK 0x7f 436 437 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 438 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 439 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 440 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 441 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 442 #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 443 #define MR_LD_CACHE_POLICY_IO_CACHED \ 444 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 445 #define MR_LD_CACHE_POLICY_IO_DIRECT 0 446 447 typedef enum { 448 MR_PD_CACHE_UNCHANGED = 0, 449 MR_PD_CACHE_ENABLE = 1, 450 MR_PD_CACHE_DISABLE = 2 451 } mfi_pd_cache; 452 453 typedef enum { 454 MR_PD_QUERY_TYPE_ALL = 0, 455 MR_PD_QUERY_TYPE_STATE = 1, 456 MR_PD_QUERY_TYPE_POWER_STATE = 2, 457 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 458 MR_PD_QUERY_TYPE_SPEED = 4, 459 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 460 } mfi_pd_query_type; 461 462 /* 463 * Other propertities and definitions 464 */ 465 #define MFI_MAX_PD_CHANNELS 2 466 #define MFI_MAX_LD_CHANNELS 2 467 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 468 #define MFI_MAX_CHANNEL_DEVS 128 469 #define MFI_DEFAULT_ID -1 470 #define MFI_MAX_LUN 8 471 #define MFI_MAX_LD 64 472 #define MFI_MAX_PD 256 473 474 #define MFI_FRAME_SIZE 64 475 #define MFI_MBOX_SIZE 12 476 477 /* Firmware flashing can take 50+ seconds */ 478 #define MFI_POLL_TIMEOUT_SECS 60 479 480 /* Allow for speedier math calculations */ 481 #define MFI_SECTOR_LEN 512 482 483 /* Scatter Gather elements */ 484 struct mfi_sg32 { 485 uint32_t addr; 486 uint32_t len; 487 } __packed; 488 489 struct mfi_sg64 { 490 uint64_t addr; 491 uint32_t len; 492 } __packed; 493 494 struct mfi_sg_skinny { 495 uint64_t addr; 496 uint32_t len; 497 uint32_t flag; 498 } __packed; 499 500 union mfi_sgl { 501 struct mfi_sg32 sg32[1]; 502 struct mfi_sg64 sg64[1]; 503 struct mfi_sg_skinny sg_skinny[1]; 504 } __packed; 505 506 /* Message frames. All messages have a common header */ 507 struct mfi_frame_header { 508 uint8_t cmd; 509 uint8_t sense_len; 510 uint8_t cmd_status; 511 uint8_t scsi_status; 512 uint8_t target_id; 513 uint8_t lun_id; 514 uint8_t cdb_len; 515 uint8_t sg_count; 516 uint32_t context; 517 /* 518 * pad0 is MSI Specific. Not used by Driver. Zero the value before 519 * sending the command to f/w. 520 */ 521 uint32_t pad0; 522 uint16_t flags; 523 #define MFI_FRAME_DATAOUT 0x08 524 #define MFI_FRAME_DATAIN 0x10 525 uint16_t timeout; 526 uint32_t data_len; 527 } __packed; 528 529 struct mfi_init_frame { 530 struct mfi_frame_header header; 531 uint32_t qinfo_new_addr_lo; 532 uint32_t qinfo_new_addr_hi; 533 uint32_t qinfo_old_addr_lo; 534 uint32_t qinfo_old_addr_hi; 535 // Start LSIP200113393 536 uint32_t driver_ver_lo; /*28h */ 537 uint32_t driver_ver_hi; /*2Ch */ 538 539 uint32_t reserved[4]; 540 // End LSIP200113393 541 } __packed; 542 543 /* 544 * Define MFI Address Context union. 545 */ 546 #ifdef MFI_ADDRESS_IS_uint64_t 547 typedef uint64_t MFI_ADDRESS; 548 #else 549 typedef union _MFI_ADDRESS { 550 struct { 551 uint32_t addressLow; 552 uint32_t addressHigh; 553 } u; 554 uint64_t address; 555 } MFI_ADDRESS, *PMFI_ADDRESS; 556 #endif 557 558 #define MFI_IO_FRAME_SIZE 40 559 struct mfi_io_frame { 560 struct mfi_frame_header header; 561 uint32_t sense_addr_lo; 562 uint32_t sense_addr_hi; 563 uint32_t lba_lo; 564 uint32_t lba_hi; 565 union mfi_sgl sgl; 566 } __packed; 567 568 #define MFI_PASS_FRAME_SIZE 48 569 struct mfi_pass_frame { 570 struct mfi_frame_header header; 571 uint32_t sense_addr_lo; 572 uint32_t sense_addr_hi; 573 uint8_t cdb[16]; 574 union mfi_sgl sgl; 575 } __packed; 576 577 #define MFI_DCMD_FRAME_SIZE 40 578 struct mfi_dcmd_frame { 579 struct mfi_frame_header header; 580 uint32_t opcode; 581 uint8_t mbox[MFI_MBOX_SIZE]; 582 union mfi_sgl sgl; 583 } __packed; 584 585 struct mfi_abort_frame { 586 struct mfi_frame_header header; 587 uint32_t abort_context; 588 /* pad is changed to reserved.*/ 589 uint32_t reserved0; 590 uint32_t abort_mfi_addr_lo; 591 uint32_t abort_mfi_addr_hi; 592 uint32_t reserved1[6]; 593 } __packed; 594 595 struct mfi_smp_frame { 596 struct mfi_frame_header header; 597 uint64_t sas_addr; 598 union { 599 struct mfi_sg32 sg32[2]; 600 struct mfi_sg64 sg64[2]; 601 } sgl; 602 } __packed; 603 604 struct mfi_stp_frame { 605 struct mfi_frame_header header; 606 uint16_t fis[10]; 607 uint32_t stp_flags; 608 union { 609 struct mfi_sg32 sg32[2]; 610 struct mfi_sg64 sg64[2]; 611 } sgl; 612 } __packed; 613 614 union mfi_frame { 615 struct mfi_frame_header header; 616 struct mfi_init_frame init; 617 /* ThunderBolt Initialization */ 618 struct mfi_io_frame io; 619 struct mfi_pass_frame pass; 620 struct mfi_dcmd_frame dcmd; 621 struct mfi_abort_frame abort; 622 struct mfi_smp_frame smp; 623 struct mfi_stp_frame stp; 624 uint8_t bytes[MFI_FRAME_SIZE]; 625 }; 626 627 #define MFI_SENSE_LEN 128 628 struct mfi_sense { 629 uint8_t data[MFI_SENSE_LEN]; 630 }; 631 632 /* The queue init structure that is passed with the init message */ 633 struct mfi_init_qinfo { 634 uint32_t flags; 635 uint32_t rq_entries; 636 uint32_t rq_addr_lo; 637 uint32_t rq_addr_hi; 638 uint32_t pi_addr_lo; 639 uint32_t pi_addr_hi; 640 uint32_t ci_addr_lo; 641 uint32_t ci_addr_hi; 642 } __packed; 643 644 /* SAS (?) controller properties, part of mfi_ctrl_info */ 645 struct mfi_ctrl_props { 646 uint16_t seq_num; 647 uint16_t pred_fail_poll_interval; 648 uint16_t intr_throttle_cnt; 649 uint16_t intr_throttle_timeout; 650 uint8_t rebuild_rate; 651 uint8_t patrol_read_rate; 652 uint8_t bgi_rate; 653 uint8_t cc_rate; 654 uint8_t recon_rate; 655 uint8_t cache_flush_interval; 656 uint8_t spinup_drv_cnt; 657 uint8_t spinup_delay; 658 uint8_t cluster_enable; 659 uint8_t coercion_mode; 660 uint8_t alarm_enable; 661 uint8_t disable_auto_rebuild; 662 uint8_t disable_battery_warn; 663 uint8_t ecc_bucket_size; 664 uint16_t ecc_bucket_leak_rate; 665 uint8_t restore_hotspare_on_insertion; 666 uint8_t expose_encl_devices; 667 uint8_t maintainPdFailHistory; 668 uint8_t disallowHostRequestReordering; 669 /* set TRUE to abort CC on detecting an inconsistency */ 670 uint8_t abortCCOnError; 671 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 672 uint8_t loadBalanceMode; 673 /* 674 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 675 * h/w mechansim like GPIO pins 676 * 1 - disable auto detect SGPIO, 677 * 2 - disable i2c SEP auto detect 678 * 3 - disable both auto detect 679 */ 680 uint8_t disableAutoDetectBackplane; 681 /* 682 * % of source LD to be reserved for a VDs snapshot in snapshot 683 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 684 */ 685 uint8_t snapVDSpace; 686 687 /* 688 * Add properties that can be controlled by a bit in the following 689 * structure. 690 */ 691 struct { 692 /* set TRUE to disable copyBack (0=copback enabled) */ 693 uint32_t copyBackDisabled :1; 694 uint32_t SMARTerEnabled :1; 695 uint32_t prCorrectUnconfiguredAreas :1; 696 uint32_t useFdeOnly :1; 697 uint32_t disableNCQ :1; 698 uint32_t SSDSMARTerEnabled :1; 699 uint32_t SSDPatrolReadEnabled :1; 700 uint32_t enableSpinDownUnconfigured :1; 701 uint32_t autoEnhancedImport :1; 702 uint32_t enableSecretKeyControl :1; 703 uint32_t disableOnlineCtrlReset :1; 704 uint32_t allowBootWithPinnedCache :1; 705 uint32_t disableSpinDownHS :1; 706 uint32_t enableJBOD :1; 707 uint32_t reserved :18; 708 } OnOffProperties; 709 /* 710 * % of source LD to be reserved for auto snapshot in snapshot 711 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 712 */ 713 uint8_t autoSnapVDSpace; 714 /* 715 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 716 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 717 */ 718 uint8_t viewSpace; 719 /* # of idle minutes before device is spun down (0=use FW defaults) */ 720 uint16_t spinDownTime; 721 uint8_t reserved[24]; 722 } __packed; 723 724 /* PCI information about the card. */ 725 struct mfi_info_pci { 726 uint16_t vendor; 727 uint16_t device; 728 uint16_t subvendor; 729 uint16_t subdevice; 730 uint8_t reserved[24]; 731 } __packed; 732 733 /* Host (front end) interface information */ 734 struct mfi_info_host { 735 uint8_t type; 736 #define MFI_INFO_HOST_PCIX 0x01 737 #define MFI_INFO_HOST_PCIE 0x02 738 #define MFI_INFO_HOST_ISCSI 0x04 739 #define MFI_INFO_HOST_SAS3G 0x08 740 uint8_t reserved[6]; 741 uint8_t port_count; 742 uint64_t port_addr[8]; 743 } __packed; 744 745 /* Device (back end) interface information */ 746 struct mfi_info_device { 747 uint8_t type; 748 #define MFI_INFO_DEV_SPI 0x01 749 #define MFI_INFO_DEV_SAS3G 0x02 750 #define MFI_INFO_DEV_SATA1 0x04 751 #define MFI_INFO_DEV_SATA3G 0x08 752 uint8_t reserved[6]; 753 uint8_t port_count; 754 uint64_t port_addr[8]; 755 } __packed; 756 757 /* Firmware component information */ 758 struct mfi_info_component { 759 char name[8]; 760 char version[32]; 761 char build_date[16]; 762 char build_time[16]; 763 } __packed; 764 765 /* Controller default settings */ 766 struct mfi_defaults { 767 uint64_t sas_addr; 768 uint8_t phy_polarity; 769 uint8_t background_rate; 770 uint8_t stripe_size; 771 uint8_t flush_time; 772 uint8_t write_back; 773 uint8_t read_ahead; 774 uint8_t cache_when_bbu_bad; 775 uint8_t cached_io; 776 uint8_t smart_mode; 777 uint8_t alarm_disable; 778 uint8_t coercion; 779 uint8_t zrc_config; 780 uint8_t dirty_led_shows_drive_activity; 781 uint8_t bios_continue_on_error; 782 uint8_t spindown_mode; 783 uint8_t allowed_device_types; 784 uint8_t allow_mix_in_enclosure; 785 uint8_t allow_mix_in_ld; 786 uint8_t allow_sata_in_cluster; 787 uint8_t max_chained_enclosures; 788 uint8_t disable_ctrl_r; 789 uint8_t enabel_web_bios; 790 uint8_t phy_polarity_split; 791 uint8_t direct_pd_mapping; 792 uint8_t bios_enumerate_lds; 793 uint8_t restored_hot_spare_on_insertion; 794 uint8_t expose_enclosure_devices; 795 uint8_t maintain_pd_fail_history; 796 uint8_t resv[28]; 797 } __packed; 798 799 /* Controller default settings */ 800 struct mfi_bios_data { 801 uint16_t boot_target_id; 802 uint8_t do_not_int_13; 803 uint8_t continue_on_error; 804 uint8_t verbose; 805 uint8_t geometry; 806 uint8_t expose_all_drives; 807 uint8_t reserved[56]; 808 uint8_t check_sum; 809 } __packed; 810 811 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 812 struct mfi_ctrl_info { 813 struct mfi_info_pci pci; 814 struct mfi_info_host host; 815 struct mfi_info_device device; 816 817 /* Firmware components that are present and active. */ 818 uint32_t image_check_word; 819 uint32_t image_component_count; 820 struct mfi_info_component image_component[8]; 821 822 /* Firmware components that have been flashed but are inactive */ 823 uint32_t pending_image_component_count; 824 struct mfi_info_component pending_image_component[8]; 825 826 uint8_t max_arms; 827 uint8_t max_spans; 828 uint8_t max_arrays; 829 uint8_t max_lds; 830 char product_name[80]; 831 char serial_number[32]; 832 uint32_t hw_present; 833 #define MFI_INFO_HW_BBU 0x01 834 #define MFI_INFO_HW_ALARM 0x02 835 #define MFI_INFO_HW_NVRAM 0x04 836 #define MFI_INFO_HW_UART 0x08 837 uint32_t current_fw_time; 838 uint16_t max_cmds; 839 uint16_t max_sg_elements; 840 uint32_t max_request_size; 841 uint16_t lds_present; 842 uint16_t lds_degraded; 843 uint16_t lds_offline; 844 uint16_t pd_present; 845 uint16_t pd_disks_present; 846 uint16_t pd_disks_pred_failure; 847 uint16_t pd_disks_failed; 848 uint16_t nvram_size; 849 uint16_t memory_size; 850 uint16_t flash_size; 851 uint16_t ram_correctable_errors; 852 uint16_t ram_uncorrectable_errors; 853 uint8_t cluster_allowed; 854 uint8_t cluster_active; 855 uint16_t max_strips_per_io; 856 857 uint32_t raid_levels; 858 #define MFI_INFO_RAID_0 0x01 859 #define MFI_INFO_RAID_1 0x02 860 #define MFI_INFO_RAID_5 0x04 861 #define MFI_INFO_RAID_1E 0x08 862 #define MFI_INFO_RAID_6 0x10 863 864 uint32_t adapter_ops; 865 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 866 #define MFI_INFO_AOPS_CC_RATE 0x0002 867 #define MFI_INFO_AOPS_BGI_RATE 0x0004 868 #define MFI_INFO_AOPS_RECON_RATE 0x0008 869 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 870 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 871 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 872 #define MFI_INFO_AOPS_BBU 0x0080 873 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 874 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 875 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 876 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 877 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 878 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 879 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 880 881 uint32_t ld_ops; 882 #define MFI_INFO_LDOPS_READ_POLICY 0x01 883 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 884 #define MFI_INFO_LDOPS_IO_POLICY 0x04 885 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 886 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 887 888 struct { 889 uint8_t min; 890 uint8_t max; 891 uint8_t reserved[2]; 892 } __packed stripe_sz_ops; 893 894 uint32_t pd_ops; 895 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 896 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 897 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 898 899 uint32_t pd_mix_support; 900 #define MFI_INFO_PDMIX_SAS 0x01 901 #define MFI_INFO_PDMIX_SATA 0x02 902 #define MFI_INFO_PDMIX_ENCL 0x04 903 #define MFI_INFO_PDMIX_LD 0x08 904 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 905 906 uint8_t ecc_bucket_count; 907 uint8_t reserved2[11]; 908 struct mfi_ctrl_props properties; 909 char package_version[0x60]; 910 uint8_t pad[0x800 - 0x6a0]; 911 } __packed; 912 913 /* keep track of an event. */ 914 union mfi_evt { 915 struct { 916 uint16_t locale; 917 uint8_t reserved; 918 int8_t evt_class; 919 } members; 920 uint32_t word; 921 } __packed; 922 923 /* event log state. */ 924 struct mfi_evt_log_state { 925 uint32_t newest_seq_num; 926 uint32_t oldest_seq_num; 927 uint32_t clear_seq_num; 928 uint32_t shutdown_seq_num; 929 uint32_t boot_seq_num; 930 } __packed; 931 932 struct mfi_progress { 933 uint16_t progress; 934 uint16_t elapsed_seconds; 935 } __packed; 936 937 struct mfi_evt_ld { 938 uint16_t target_id; 939 uint8_t ld_index; 940 uint8_t reserved; 941 } __packed; 942 943 struct mfi_evt_pd { 944 uint16_t device_id; 945 uint8_t enclosure_index; 946 uint8_t slot_number; 947 } __packed; 948 949 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 950 struct mfi_evt_detail { 951 uint32_t seq; 952 uint32_t time; 953 uint32_t code; 954 union mfi_evt evt_class; 955 uint8_t arg_type; 956 uint8_t reserved1[15]; 957 958 union { 959 struct { 960 struct mfi_evt_pd pd; 961 uint8_t cdb_len; 962 uint8_t sense_len; 963 uint8_t reserved[2]; 964 uint8_t cdb[16]; 965 uint8_t sense[64]; 966 } cdb_sense; 967 968 struct mfi_evt_ld ld; 969 970 struct { 971 struct mfi_evt_ld ld; 972 uint64_t count; 973 } ld_count; 974 975 struct { 976 uint64_t lba; 977 struct mfi_evt_ld ld; 978 } ld_lba; 979 980 struct { 981 struct mfi_evt_ld ld; 982 uint32_t pre_owner; 983 uint32_t new_owner; 984 } ld_owner; 985 986 struct { 987 uint64_t ld_lba; 988 uint64_t pd_lba; 989 struct mfi_evt_ld ld; 990 struct mfi_evt_pd pd; 991 } ld_lba_pd_lba; 992 993 struct { 994 struct mfi_evt_ld ld; 995 struct mfi_progress prog; 996 } ld_prog; 997 998 struct { 999 struct mfi_evt_ld ld; 1000 uint32_t prev_state; 1001 uint32_t new_state; 1002 } ld_state; 1003 1004 struct { 1005 uint64_t strip; 1006 struct mfi_evt_ld ld; 1007 } ld_strip; 1008 1009 struct mfi_evt_pd pd; 1010 1011 struct { 1012 struct mfi_evt_pd pd; 1013 uint32_t err; 1014 } pd_err; 1015 1016 struct { 1017 uint64_t lba; 1018 struct mfi_evt_pd pd; 1019 } pd_lba; 1020 1021 struct { 1022 uint64_t lba; 1023 struct mfi_evt_pd pd; 1024 struct mfi_evt_ld ld; 1025 } pd_lba_ld; 1026 1027 struct { 1028 struct mfi_evt_pd pd; 1029 struct mfi_progress prog; 1030 } pd_prog; 1031 1032 struct { 1033 struct mfi_evt_pd ld; 1034 uint32_t prev_state; 1035 uint32_t new_state; 1036 } pd_state; 1037 1038 struct { 1039 uint16_t venderId; 1040 uint16_t deviceId; 1041 uint16_t subVenderId; 1042 uint16_t subDeviceId; 1043 } pci; 1044 1045 uint32_t rate; 1046 1047 char str[96]; 1048 1049 struct { 1050 uint32_t rtc; 1051 uint16_t elapsedSeconds; 1052 } time; 1053 1054 struct { 1055 uint32_t ecar; 1056 uint32_t elog; 1057 char str[64]; 1058 } ecc; 1059 1060 uint8_t b[96]; 1061 uint16_t s[48]; 1062 uint32_t w[24]; 1063 uint64_t d[12]; 1064 } args; 1065 1066 char description[128]; 1067 } __packed; 1068 1069 struct mfi_evt_list { 1070 uint32_t count; 1071 uint32_t reserved; 1072 struct mfi_evt_detail event[1]; 1073 } __packed; 1074 1075 union mfi_pd_ref { 1076 struct { 1077 uint16_t device_id; 1078 uint16_t seq_num; 1079 } v; 1080 uint32_t ref; 1081 } __packed; 1082 1083 union mfi_pd_ddf_type { 1084 struct { 1085 union { 1086 struct { 1087 uint16_t forced_pd_guid : 1; 1088 uint16_t in_vd : 1; 1089 uint16_t is_global_spare : 1; 1090 uint16_t is_spare : 1; 1091 uint16_t is_foreign : 1; 1092 uint16_t reserved : 7; 1093 uint16_t intf : 4; 1094 } pd_type; 1095 uint16_t type; 1096 } v; 1097 uint16_t reserved; 1098 } ddf; 1099 struct { 1100 uint32_t reserved; 1101 } non_disk; 1102 uint32_t type; 1103 } __packed; 1104 1105 struct mfi_pd_progress { 1106 uint32_t active; 1107 #define MFI_PD_PROGRESS_REBUILD (1<<0) 1108 #define MFI_PD_PROGRESS_PATROL (1<<1) 1109 #define MFI_PD_PROGRESS_CLEAR (1<<2) 1110 struct mfi_progress rbld; 1111 struct mfi_progress patrol; 1112 struct mfi_progress clear; 1113 struct mfi_progress reserved[4]; 1114 } __packed; 1115 1116 struct mfi_pd_info { 1117 union mfi_pd_ref ref; 1118 uint8_t inquiry_data[96]; 1119 uint8_t vpd_page83[64]; 1120 uint8_t not_supported; 1121 uint8_t scsi_dev_type; 1122 uint8_t connected_port_bitmap; 1123 uint8_t device_speed; 1124 uint32_t media_err_count; 1125 uint32_t other_err_count; 1126 uint32_t pred_fail_count; 1127 uint32_t last_pred_fail_event_seq_num; 1128 uint16_t fw_state; /* MFI_PD_STATE_* */ 1129 uint8_t disabled_for_removal; 1130 uint8_t link_speed; 1131 union mfi_pd_ddf_type state; 1132 struct { 1133 uint8_t count; 1134 uint8_t is_path_broken; 1135 uint8_t reserved[6]; 1136 uint64_t sas_addr[4]; 1137 } path_info; 1138 uint64_t raw_size; 1139 uint64_t non_coerced_size; 1140 uint64_t coerced_size; 1141 uint16_t encl_device_id; 1142 uint8_t encl_index; 1143 uint8_t slot_number; 1144 struct mfi_pd_progress prog_info; 1145 uint8_t bad_block_table_full; 1146 uint8_t unusable_in_current_config; 1147 uint8_t vpd_page83_ext[64]; 1148 uint8_t reserved[512-358]; 1149 } __packed; 1150 1151 struct mfi_pd_address { 1152 uint16_t device_id; 1153 uint16_t encl_device_id; 1154 uint8_t encl_index; 1155 uint8_t slot_number; 1156 uint8_t scsi_dev_type; /* 0 = disk */ 1157 uint8_t connect_port_bitmap; 1158 uint64_t sas_addr[2]; 1159 } __packed; 1160 1161 #define MAX_SYS_PDS 240 1162 struct mfi_pd_list { 1163 uint32_t size; 1164 uint32_t count; 1165 struct mfi_pd_address addr[MAX_SYS_PDS]; 1166 } __packed; 1167 1168 enum mfi_pd_state { 1169 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1170 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1171 MFI_PD_STATE_HOT_SPARE = 0x02, 1172 MFI_PD_STATE_OFFLINE = 0x10, 1173 MFI_PD_STATE_FAILED = 0x11, 1174 MFI_PD_STATE_REBUILD = 0x14, 1175 MFI_PD_STATE_ONLINE = 0x18, 1176 MFI_PD_STATE_COPYBACK = 0x20, 1177 MFI_PD_STATE_SYSTEM = 0x40 1178 }; 1179 1180 /* 1181 * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1182 * Adding a #define to denote this. 1183 */ 1184 #define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1185 1186 union mfi_ld_ref { 1187 struct { 1188 uint8_t target_id; 1189 uint8_t reserved; 1190 uint16_t seq; 1191 } v; 1192 uint32_t ref; 1193 } __packed; 1194 1195 struct mfi_ld_list { 1196 uint32_t ld_count; 1197 uint32_t reserved1; 1198 struct { 1199 union mfi_ld_ref ld; 1200 uint8_t state; 1201 uint8_t reserved2[3]; 1202 uint64_t size; 1203 } ld_list[MFI_MAX_LD]; 1204 } __packed; 1205 1206 enum mfi_ld_access { 1207 MFI_LD_ACCESS_RW = 0, 1208 MFI_LD_ACCSSS_RO = 2, 1209 MFI_LD_ACCESS_BLOCKED = 3, 1210 }; 1211 #define MFI_LD_ACCESS_MASK 3 1212 1213 enum mfi_ld_state { 1214 MFI_LD_STATE_OFFLINE = 0, 1215 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1216 MFI_LD_STATE_DEGRADED = 2, 1217 MFI_LD_STATE_OPTIMAL = 3 1218 }; 1219 1220 struct mfi_ld_props { 1221 union mfi_ld_ref ld; 1222 char name[16]; 1223 uint8_t default_cache_policy; 1224 uint8_t access_policy; 1225 uint8_t disk_cache_policy; 1226 uint8_t current_cache_policy; 1227 uint8_t no_bgi; 1228 uint8_t reserved[7]; 1229 } __packed; 1230 1231 struct mfi_ld_params { 1232 uint8_t primary_raid_level; 1233 uint8_t raid_level_qualifier; 1234 uint8_t secondary_raid_level; 1235 uint8_t stripe_size; 1236 uint8_t num_drives; 1237 uint8_t span_depth; 1238 uint8_t state; 1239 uint8_t init_state; 1240 #define MFI_LD_PARAMS_INIT_NO 0 1241 #define MFI_LD_PARAMS_INIT_QUICK 1 1242 #define MFI_LD_PARAMS_INIT_FULL 2 1243 uint8_t is_consistent; 1244 uint8_t reserved1[6]; 1245 uint8_t isSSCD; 1246 uint8_t reserved2[16]; 1247 } __packed; 1248 1249 struct mfi_ld_progress { 1250 uint32_t active; 1251 #define MFI_LD_PROGRESS_CC (1<<0) 1252 #define MFI_LD_PROGRESS_BGI (1<<1) 1253 #define MFI_LD_PROGRESS_FGI (1<<2) 1254 #define MFI_LD_PROGRESS_RECON (1<<3) 1255 struct mfi_progress cc; 1256 struct mfi_progress bgi; 1257 struct mfi_progress fgi; 1258 struct mfi_progress recon; 1259 struct mfi_progress reserved[4]; 1260 } __packed; 1261 1262 struct mfi_span { 1263 uint64_t start_block; 1264 uint64_t num_blocks; 1265 uint16_t array_ref; 1266 uint8_t reserved[6]; 1267 } __packed; 1268 1269 #define MFI_MAX_SPAN_DEPTH 8 1270 struct mfi_ld_config { 1271 struct mfi_ld_props properties; 1272 struct mfi_ld_params params; 1273 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1274 } __packed; 1275 1276 struct mfi_ld_info { 1277 struct mfi_ld_config ld_config; 1278 uint64_t size; 1279 struct mfi_ld_progress progress; 1280 uint16_t cluster_owner; 1281 uint8_t reconstruct_active; 1282 uint8_t reserved1[1]; 1283 uint8_t vpd_page83[64]; 1284 uint8_t reserved2[16]; 1285 } __packed; 1286 1287 #define MFI_MAX_ARRAYS 16 1288 struct mfi_spare { 1289 union mfi_pd_ref ref; 1290 uint8_t spare_type; 1291 #define MFI_SPARE_DEDICATED (1 << 0) 1292 #define MFI_SPARE_REVERTIBLE (1 << 1) 1293 #define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1294 uint8_t reserved[2]; 1295 uint8_t array_count; 1296 uint16_t array_ref[MFI_MAX_ARRAYS]; 1297 } __packed; 1298 1299 #define MFI_MAX_ROW_SIZE 32 1300 struct mfi_array { 1301 uint64_t size; 1302 uint8_t num_drives; 1303 uint8_t reserved; 1304 uint16_t array_ref; 1305 uint8_t pad[20]; 1306 struct { 1307 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1308 uint16_t fw_state; /* MFI_PD_STATE_* */ 1309 struct { 1310 uint8_t pd; 1311 uint8_t slot; 1312 } encl; 1313 } pd[MFI_MAX_ROW_SIZE]; 1314 } __packed; 1315 1316 struct mfi_config_data { 1317 uint32_t size; 1318 uint16_t array_count; 1319 uint16_t array_size; 1320 uint16_t log_drv_count; 1321 uint16_t log_drv_size; 1322 uint16_t spares_count; 1323 uint16_t spares_size; 1324 uint8_t reserved[16]; 1325 struct mfi_array array[0]; 1326 struct mfi_ld_config ld[0]; 1327 struct mfi_spare spare[0]; 1328 } __packed; 1329 1330 struct mfi_bbu_capacity_info { 1331 uint16_t relative_charge; 1332 uint16_t absolute_charge; 1333 uint16_t remaining_capacity; 1334 uint16_t full_charge_capacity; 1335 uint16_t run_time_to_empty; 1336 uint16_t average_time_to_empty; 1337 uint16_t average_time_to_full; 1338 uint16_t cycle_count; 1339 uint16_t max_error; 1340 uint16_t remaining_capacity_alarm; 1341 uint16_t remaining_time_alarm; 1342 uint8_t reserved[26]; 1343 } __packed; 1344 1345 struct mfi_bbu_design_info { 1346 uint32_t mfg_date; 1347 uint16_t design_capacity; 1348 uint16_t design_voltage; 1349 uint16_t spec_info; 1350 uint16_t serial_number; 1351 uint16_t pack_stat_config; 1352 uint8_t mfg_name[12]; 1353 uint8_t device_name[8]; 1354 uint8_t device_chemistry[8]; 1355 uint8_t mfg_data[8]; 1356 uint8_t reserved[17]; 1357 } __packed; 1358 1359 struct mfi_ibbu_state { 1360 uint16_t gas_guage_status; 1361 uint16_t relative_charge; 1362 uint16_t charger_system_state; 1363 uint16_t charger_system_ctrl; 1364 uint16_t charging_current; 1365 uint16_t absolute_charge; 1366 uint16_t max_error; 1367 uint8_t reserved[18]; 1368 } __packed; 1369 1370 struct mfi_bbu_state { 1371 uint16_t gas_guage_status; 1372 uint16_t relative_charge; 1373 uint16_t charger_status; 1374 uint16_t remaining_capacity; 1375 uint16_t full_charge_capacity; 1376 uint8_t is_SOH_good; 1377 uint8_t reserved[21]; 1378 } __packed; 1379 1380 struct mfi_bbu_properties { 1381 uint32_t auto_learn_period; 1382 uint32_t next_learn_time; 1383 uint8_t learn_delay_interval; 1384 uint8_t auto_learn_mode; 1385 uint8_t bbu_mode; 1386 uint8_t reserved[21]; 1387 } __packed; 1388 1389 union mfi_bbu_status_detail { 1390 struct mfi_ibbu_state ibbu; 1391 struct mfi_bbu_state bbu; 1392 }; 1393 1394 struct mfi_bbu_status { 1395 uint8_t battery_type; 1396 #define MFI_BBU_TYPE_NONE 0 1397 #define MFI_BBU_TYPE_IBBU 1 1398 #define MFI_BBU_TYPE_BBU 2 1399 uint8_t reserved; 1400 uint16_t voltage; 1401 int16_t current; 1402 uint16_t temperature; 1403 uint32_t fw_status; 1404 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1405 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1406 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1407 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1408 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1409 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1410 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1411 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1412 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1413 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1414 uint8_t pad[20]; 1415 union mfi_bbu_status_detail detail; 1416 } __packed; 1417 1418 enum mfi_pr_state { 1419 MFI_PR_STATE_STOPPED = 0, 1420 MFI_PR_STATE_READY = 1, 1421 MFI_PR_STATE_ACTIVE = 2, 1422 MFI_PR_STATE_ABORTED = 0xff 1423 }; 1424 1425 struct mfi_pr_status { 1426 uint32_t num_iteration; 1427 uint8_t state; 1428 uint8_t num_pd_done; 1429 uint8_t reserved[10]; 1430 }; 1431 1432 enum mfi_pr_opmode { 1433 MFI_PR_OPMODE_AUTO = 0, 1434 MFI_PR_OPMODE_MANUAL = 1, 1435 MFI_PR_OPMODE_DISABLED = 2 1436 }; 1437 1438 struct mfi_pr_properties { 1439 uint8_t op_mode; 1440 uint8_t max_pd; 1441 uint8_t reserved; 1442 uint8_t exclude_ld_count; 1443 uint16_t excluded_ld[MFI_MAX_LD]; 1444 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1445 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1446 uint32_t next_exec; 1447 uint32_t exec_freq; 1448 uint32_t clear_freq; 1449 }; 1450 1451 /* ThunderBolt support */ 1452 1453 /* 1454 * Raid Context structure which describes MegaRAID specific IO Paramenters 1455 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1456 */ 1457 typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1458 uint16_t resvd0; /* 0x00 - 0x01 */ 1459 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1460 uint8_t regLockFlags; 1461 uint8_t armId; 1462 uint16_t TargetID; /* 0x06 - 0x07 */ 1463 1464 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1465 1466 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1467 1468 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1469 uint8_t exStatus; /* 0x16 */ 1470 uint8_t Status; /* 0x17 status */ 1471 1472 uint8_t RAIDFlags; /* 0x18 */ 1473 uint8_t numSGE; /* 0x19 numSge */ 1474 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1475 uint8_t spanArm; /* 0x1C */ 1476 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1477 } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1478 1479 /***************************************************************************** 1480 * 1481 * Message Functions 1482 * 1483 *****************************************************************************/ 1484 1485 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1486 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1487 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1488 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1489 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1490 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1491 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1492 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1493 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1494 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1495 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1496 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1497 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1498 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1499 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1500 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1501 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1502 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1503 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1504 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1505 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1506 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1507 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1508 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1509 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1510 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1511 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1512 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1513 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1514 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1515 1516 /* Doorbell functions */ 1517 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1518 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1519 1520 /***************************************************************************** 1521 * 1522 * MPI Version Definitions 1523 * 1524 *****************************************************************************/ 1525 1526 #define MPI2_VERSION_MAJOR (0x02) 1527 #define MPI2_VERSION_MINOR (0x00) 1528 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1529 #define MPI2_VERSION_MAJOR_SHIFT (8) 1530 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1531 #define MPI2_VERSION_MINOR_SHIFT (0) 1532 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1533 MPI2_VERSION_MINOR) 1534 1535 #define MPI2_VERSION_02_00 (0x0200) 1536 1537 /* versioning for this MPI header set */ 1538 #define MPI2_HEADER_VERSION_UNIT (0x10) 1539 #define MPI2_HEADER_VERSION_DEV (0x00) 1540 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1541 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1542 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1543 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1544 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1545 MPI2_HEADER_VERSION_DEV) 1546 1547 /* IOCInit Request message */ 1548 struct MPI2_IOC_INIT_REQUEST { 1549 uint8_t WhoInit; /* 0x00 */ 1550 uint8_t Reserved1; /* 0x01 */ 1551 uint8_t ChainOffset; /* 0x02 */ 1552 uint8_t Function; /* 0x03 */ 1553 uint16_t Reserved2; /* 0x04 */ 1554 uint8_t Reserved3; /* 0x06 */ 1555 uint8_t MsgFlags; /* 0x07 */ 1556 uint8_t VP_ID; /* 0x08 */ 1557 uint8_t VF_ID; /* 0x09 */ 1558 uint16_t Reserved4; /* 0x0A */ 1559 uint16_t MsgVersion; /* 0x0C */ 1560 uint16_t HeaderVersion; /* 0x0E */ 1561 uint32_t Reserved5; /* 0x10 */ 1562 uint16_t Reserved6; /* 0x14 */ 1563 uint8_t Reserved7; /* 0x16 */ 1564 uint8_t HostMSIxVectors; /* 0x17 */ 1565 uint16_t Reserved8; /* 0x18 */ 1566 uint16_t SystemRequestFrameSize; /* 0x1A */ 1567 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1568 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1569 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1570 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1571 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1572 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1573 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1574 uint64_t TimeStamp; /* 0x40 */ 1575 }; 1576 1577 /* WhoInit values */ 1578 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1579 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1580 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1581 #define MPI2_WHOINIT_PCI_PEER (0x03) 1582 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1583 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1584 1585 struct MPI2_SGE_CHAIN_UNION { 1586 uint16_t Length; 1587 uint8_t NextChainOffset; 1588 uint8_t Flags; 1589 union { 1590 uint32_t Address32; 1591 uint64_t Address64; 1592 } u; 1593 }; 1594 1595 struct MPI2_IEEE_SGE_SIMPLE32 { 1596 uint32_t Address; 1597 uint32_t FlagsLength; 1598 }; 1599 1600 struct MPI2_IEEE_SGE_SIMPLE64 { 1601 uint64_t Address; 1602 uint32_t Length; 1603 uint16_t Reserved1; 1604 uint8_t Reserved2; 1605 uint8_t Flags; 1606 }; 1607 1608 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1609 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1610 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1611 } MPI2_IEEE_SGE_SIMPLE_UNION; 1612 1613 typedef struct _MPI2_SGE_SIMPLE_UNION { 1614 uint32_t FlagsLength; 1615 union { 1616 uint32_t Address32; 1617 uint64_t Address64; 1618 } u; 1619 } MPI2_SGE_SIMPLE_UNION; 1620 1621 /**************************************************************************** 1622 * IEEE SGE field definitions and masks 1623 ****************************************************************************/ 1624 1625 /* Flags field bit definitions */ 1626 1627 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1628 1629 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1630 1631 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1632 1633 /* Element Type */ 1634 1635 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1636 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1637 1638 /* Data Location Address Space */ 1639 1640 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1641 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1642 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1643 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1644 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1645 1646 /* Address Size */ 1647 1648 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1649 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1650 1651 /*******************/ 1652 /* SCSI IO Control bits */ 1653 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1654 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1655 1656 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1657 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1658 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1659 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1660 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1661 1662 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1663 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1664 1665 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1666 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1667 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1668 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1669 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1670 1671 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1672 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1673 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1674 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1675 1676 /*******************/ 1677 1678 typedef struct { 1679 uint8_t CDB[20]; /* 0x00 */ 1680 uint32_t PrimaryReferenceTag; /* 0x14 */ 1681 uint16_t PrimaryApplicationTag; /* 0x18 */ 1682 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1683 uint32_t TransferLength; /* 0x1C */ 1684 } MPI2_SCSI_IO_CDB_EEDP32; 1685 1686 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1687 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1688 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1689 } MPI2_IEEE_SGE_CHAIN_UNION; 1690 1691 typedef union _MPI2_SIMPLE_SGE_UNION { 1692 MPI2_SGE_SIMPLE_UNION MpiSimple; 1693 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1694 } MPI2_SIMPLE_SGE_UNION; 1695 1696 typedef union _MPI2_SGE_IO_UNION { 1697 MPI2_SGE_SIMPLE_UNION MpiSimple; 1698 struct MPI2_SGE_CHAIN_UNION MpiChain; 1699 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1700 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1701 } MPI2_SGE_IO_UNION; 1702 1703 typedef union { 1704 uint8_t CDB32[32]; 1705 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1706 MPI2_SGE_SIMPLE_UNION SGE; 1707 } MPI2_SCSI_IO_CDB_UNION; 1708 1709 /* MPI 2.5 SGLs */ 1710 1711 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1712 1713 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1714 uint64_t Address; 1715 uint32_t Length; 1716 uint16_t Reserved1; 1717 uint8_t NextChainOffset; 1718 uint8_t Flags; 1719 } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1720 1721 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1722 1723 /********/ 1724 1725 /* 1726 * RAID SCSI IO Request Message 1727 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1728 */ 1729 struct mfi_mpi2_request_raid_scsi_io { 1730 uint16_t DevHandle; /* 0x00 */ 1731 uint8_t ChainOffset; /* 0x02 */ 1732 uint8_t Function; /* 0x03 */ 1733 uint16_t Reserved1; /* 0x04 */ 1734 uint8_t Reserved2; /* 0x06 */ 1735 uint8_t MsgFlags; /* 0x07 */ 1736 uint8_t VP_ID; /* 0x08 */ 1737 uint8_t VF_ID; /* 0x09 */ 1738 uint16_t Reserved3; /* 0x0A */ 1739 uint32_t SenseBufferLowAddress; /* 0x0C */ 1740 uint16_t SGLFlags; /* 0x10 */ 1741 uint8_t SenseBufferLength; /* 0x12 */ 1742 uint8_t Reserved4; /* 0x13 */ 1743 uint8_t SGLOffset0; /* 0x14 */ 1744 uint8_t SGLOffset1; /* 0x15 */ 1745 uint8_t SGLOffset2; /* 0x16 */ 1746 uint8_t SGLOffset3; /* 0x17 */ 1747 uint32_t SkipCount; /* 0x18 */ 1748 uint32_t DataLength; /* 0x1C */ 1749 uint32_t BidirectionalDataLength; /* 0x20 */ 1750 uint16_t IoFlags; /* 0x24 */ 1751 uint16_t EEDPFlags; /* 0x26 */ 1752 uint32_t EEDPBlockSize; /* 0x28 */ 1753 uint32_t SecondaryReferenceTag; /* 0x2C */ 1754 uint16_t SecondaryApplicationTag; /* 0x30 */ 1755 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1756 uint8_t LUN[8]; /* 0x34 */ 1757 uint32_t Control; /* 0x3C */ 1758 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1759 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1760 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1761 } __packed; 1762 1763 /* 1764 * MPT RAID MFA IO Descriptor. 1765 */ 1766 typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1767 uint32_t RequestFlags : 8; 1768 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1769 uint32_t MessageAddress2; /* bits 61:32 */ 1770 } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1771 1772 struct mfi_mpi2_request_header { 1773 uint8_t RequestFlags; /* 0x00 */ 1774 uint8_t MSIxIndex; /* 0x01 */ 1775 uint16_t SMID; /* 0x02 */ 1776 uint16_t LMID; /* 0x04 */ 1777 }; 1778 1779 /* defines for the RequestFlags field */ 1780 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1781 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1782 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1783 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1784 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1785 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1786 1787 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1788 1789 struct mfi_mpi2_request_high_priority { 1790 struct mfi_mpi2_request_header header; 1791 uint16_t reserved; 1792 }; 1793 1794 struct mfi_mpi2_request_scsi_io { 1795 struct mfi_mpi2_request_header header; 1796 uint16_t scsi_io_dev_handle; 1797 }; 1798 1799 struct mfi_mpi2_request_scsi_target { 1800 struct mfi_mpi2_request_header header; 1801 uint16_t scsi_target_io_index; 1802 }; 1803 1804 /* Request Descriptors */ 1805 union mfi_mpi2_request_descriptor { 1806 struct mfi_mpi2_request_header header; 1807 struct mfi_mpi2_request_high_priority high_priority; 1808 struct mfi_mpi2_request_scsi_io scsi_io; 1809 struct mfi_mpi2_request_scsi_target scsi_target; 1810 uint64_t words; 1811 }; 1812 1813 struct mfi_mpi2_reply_header { 1814 uint8_t ReplyFlags; /* 0x00 */ 1815 uint8_t MSIxIndex; /* 0x01 */ 1816 uint16_t SMID; /* 0x02 */ 1817 }; 1818 1819 /* defines for the ReplyFlags field */ 1820 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1821 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1822 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1823 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1824 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1825 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1826 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1827 1828 /* values for marking a reply descriptor as unused */ 1829 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1830 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1831 1832 struct mfi_mpi2_reply_default { 1833 struct mfi_mpi2_reply_header header; 1834 uint32_t DescriptorTypeDependent2; 1835 }; 1836 1837 struct mfi_mpi2_reply_address { 1838 struct mfi_mpi2_reply_header header; 1839 uint32_t ReplyFrameAddress; 1840 }; 1841 1842 struct mfi_mpi2_reply_scsi_io { 1843 struct mfi_mpi2_reply_header header; 1844 uint16_t TaskTag; /* 0x04 */ 1845 uint16_t Reserved1; /* 0x06 */ 1846 }; 1847 1848 struct mfi_mpi2_reply_target_assist { 1849 struct mfi_mpi2_reply_header header; 1850 uint8_t SequenceNumber; /* 0x04 */ 1851 uint8_t Reserved1; /* 0x04 */ 1852 uint16_t IoIndex; /* 0x06 */ 1853 }; 1854 1855 struct mfi_mpi2_reply_target_cmd_buffer { 1856 struct mfi_mpi2_reply_header header; 1857 uint8_t SequenceNumber; /* 0x04 */ 1858 uint8_t Flags; /* 0x04 */ 1859 uint16_t InitiatorDevHandle; /* 0x06 */ 1860 uint16_t IoIndex; /* 0x06 */ 1861 }; 1862 1863 struct mfi_mpi2_reply_raid_accel { 1864 struct mfi_mpi2_reply_header header; 1865 uint8_t SequenceNumber; /* 0x04 */ 1866 uint32_t Reserved; /* 0x04 */ 1867 }; 1868 1869 /* union of Reply Descriptors */ 1870 union mfi_mpi2_reply_descriptor { 1871 struct mfi_mpi2_reply_header header; 1872 struct mfi_mpi2_reply_scsi_io scsi_io; 1873 struct mfi_mpi2_reply_target_assist target_assist; 1874 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1875 struct mfi_mpi2_reply_raid_accel raid_accel; 1876 struct mfi_mpi2_reply_default reply_default; 1877 uint64_t words; 1878 }; 1879 1880 struct IO_REQUEST_INFO { 1881 uint64_t ldStartBlock; 1882 uint32_t numBlocks; 1883 uint16_t ldTgtId; 1884 uint8_t isRead; 1885 uint16_t devHandle; 1886 uint64_t pdBlock; 1887 uint8_t fpOkForIo; 1888 }; 1889 1890 #define MFI_SCSI_MAX_TARGETS 128 1891 #define MFI_SCSI_MAX_LUNS 8 1892 #define MFI_SCSI_INITIATOR_ID 255 1893 #define MFI_SCSI_MAX_CMDS 8 1894 #define MFI_SCSI_MAX_CDB_LEN 16 1895 1896 #endif /* _MFIREG_H */ 1897