1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/ethernet.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/brgphyreg.h> 58 #include <net/if_arp.h> 59 #include <machine/bus.h> 60 #include <dev/bge/if_bgereg.h> 61 #include <dev/bce/if_bcereg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 66 #include "miibus_if.h" 67 68 static int brgphy_probe(device_t); 69 static int brgphy_attach(device_t); 70 71 struct brgphy_softc { 72 struct mii_softc mii_sc; 73 int serdes_flags; /* Keeps track of the serdes type used */ 74 #define BRGPHY_5706S 0x0001 75 #define BRGPHY_5708S 0x0002 76 #define BRGPHY_NOANWAIT 0x0004 77 #define BRGPHY_5709S 0x0008 78 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 79 }; 80 81 static device_method_t brgphy_methods[] = { 82 /* device interface */ 83 DEVMETHOD(device_probe, brgphy_probe), 84 DEVMETHOD(device_attach, brgphy_attach), 85 DEVMETHOD(device_detach, mii_phy_detach), 86 DEVMETHOD(device_shutdown, bus_generic_shutdown), 87 DEVMETHOD_END 88 }; 89 90 static devclass_t brgphy_devclass; 91 92 static driver_t brgphy_driver = { 93 "brgphy", 94 brgphy_methods, 95 sizeof(struct brgphy_softc) 96 }; 97 98 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 99 100 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 101 static void brgphy_setmedia(struct mii_softc *, int); 102 static void brgphy_status(struct mii_softc *); 103 static void brgphy_mii_phy_auto(struct mii_softc *, int); 104 static void brgphy_reset(struct mii_softc *); 105 static void brgphy_enable_loopback(struct mii_softc *); 106 static void bcm5401_load_dspcode(struct mii_softc *); 107 static void bcm5411_load_dspcode(struct mii_softc *); 108 static void bcm54k2_load_dspcode(struct mii_softc *); 109 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 110 static void brgphy_fixup_adc_bug(struct mii_softc *); 111 static void brgphy_fixup_adjust_trim(struct mii_softc *); 112 static void brgphy_fixup_ber_bug(struct mii_softc *); 113 static void brgphy_fixup_crc_bug(struct mii_softc *); 114 static void brgphy_fixup_jitter_bug(struct mii_softc *); 115 static void brgphy_ethernet_wirespeed(struct mii_softc *); 116 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 117 118 static const struct mii_phydesc brgphys[] = { 119 MII_PHY_DESC(BROADCOM, BCM5400), 120 MII_PHY_DESC(BROADCOM, BCM5401), 121 MII_PHY_DESC(BROADCOM, BCM5411), 122 MII_PHY_DESC(BROADCOM, BCM54K2), 123 MII_PHY_DESC(BROADCOM, BCM5701), 124 MII_PHY_DESC(BROADCOM, BCM5703), 125 MII_PHY_DESC(BROADCOM, BCM5704), 126 MII_PHY_DESC(BROADCOM, BCM5705), 127 MII_PHY_DESC(BROADCOM, BCM5706), 128 MII_PHY_DESC(BROADCOM, BCM5714), 129 MII_PHY_DESC(BROADCOM, BCM5421), 130 MII_PHY_DESC(BROADCOM, BCM5750), 131 MII_PHY_DESC(BROADCOM, BCM5752), 132 MII_PHY_DESC(BROADCOM, BCM5780), 133 MII_PHY_DESC(BROADCOM, BCM5708C), 134 MII_PHY_DESC(BROADCOM2, BCM5482), 135 MII_PHY_DESC(BROADCOM2, BCM5708S), 136 MII_PHY_DESC(BROADCOM2, BCM5709C), 137 MII_PHY_DESC(BROADCOM2, BCM5709S), 138 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 139 MII_PHY_DESC(BROADCOM2, BCM5722), 140 MII_PHY_DESC(BROADCOM2, BCM5755), 141 MII_PHY_DESC(BROADCOM2, BCM5754), 142 MII_PHY_DESC(BROADCOM2, BCM5761), 143 MII_PHY_DESC(BROADCOM2, BCM5784), 144 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 145 MII_PHY_DESC(BROADCOM2, BCM5785), 146 #endif 147 MII_PHY_DESC(BROADCOM3, BCM5717C), 148 MII_PHY_DESC(BROADCOM3, BCM5719C), 149 MII_PHY_DESC(BROADCOM3, BCM5720C), 150 MII_PHY_DESC(BROADCOM3, BCM57765), 151 MII_PHY_DESC(BROADCOM3, BCM57780), 152 MII_PHY_DESC(BROADCOM4, BCM5725C), 153 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 154 MII_PHY_END 155 }; 156 157 static const struct mii_phy_funcs brgphy_funcs = { 158 brgphy_service, 159 brgphy_status, 160 brgphy_reset 161 }; 162 163 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 164 #define HS21_BCM_CHIPID 0x57081021 165 166 static int 167 detect_hs21(struct bce_softc *bce_sc) 168 { 169 char *sysenv; 170 int found; 171 172 found = 0; 173 if (bce_sc->bce_chipid == HS21_BCM_CHIPID) { 174 sysenv = kern_getenv("smbios.system.product"); 175 if (sysenv != NULL) { 176 if (strncmp(sysenv, HS21_PRODUCT_ID, 177 strlen(HS21_PRODUCT_ID)) == 0) 178 found = 1; 179 freeenv(sysenv); 180 } 181 } 182 return (found); 183 } 184 185 /* Search for our PHY in the list of known PHYs */ 186 static int 187 brgphy_probe(device_t dev) 188 { 189 190 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 191 } 192 193 /* Attach the PHY to the MII bus */ 194 static int 195 brgphy_attach(device_t dev) 196 { 197 struct brgphy_softc *bsc; 198 struct bge_softc *bge_sc = NULL; 199 struct bce_softc *bce_sc = NULL; 200 struct mii_softc *sc; 201 202 bsc = device_get_softc(dev); 203 sc = &bsc->mii_sc; 204 205 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 206 &brgphy_funcs, 0); 207 208 bsc->serdes_flags = 0; 209 210 /* Find the MAC driver associated with this PHY. */ 211 if (mii_dev_mac_match(dev, "bge")) 212 bge_sc = mii_dev_mac_softc(dev); 213 else if (mii_dev_mac_match(dev, "bce")) 214 bce_sc = mii_dev_mac_softc(dev); 215 216 /* Handle any special cases based on the PHY ID */ 217 switch (sc->mii_mpd_oui) { 218 case MII_OUI_BROADCOM: 219 switch (sc->mii_mpd_model) { 220 case MII_MODEL_BROADCOM_BCM5706: 221 case MII_MODEL_BROADCOM_BCM5714: 222 /* 223 * The 5464 PHY used in the 5706 supports both copper 224 * and fiber interfaces over GMII. Need to check the 225 * shadow registers to see which mode is actually 226 * in effect, and therefore whether we have 5706C or 227 * 5706S. 228 */ 229 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 230 BRGPHY_SHADOW_1C_MODE_CTRL); 231 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 232 BRGPHY_SHADOW_1C_ENA_1000X) { 233 bsc->serdes_flags |= BRGPHY_5706S; 234 sc->mii_flags |= MIIF_HAVEFIBER; 235 } 236 break; 237 } 238 break; 239 case MII_OUI_BROADCOM2: 240 switch (sc->mii_mpd_model) { 241 case MII_MODEL_BROADCOM2_BCM5708S: 242 bsc->serdes_flags |= BRGPHY_5708S; 243 sc->mii_flags |= MIIF_HAVEFIBER; 244 break; 245 case MII_MODEL_BROADCOM2_BCM5709S: 246 /* 247 * XXX 248 * 5720S and 5709S shares the same PHY id. 249 * Assume 5720S PHY if parent device is bge(4). 250 */ 251 if (bge_sc != NULL) 252 bsc->serdes_flags |= BRGPHY_5708S; 253 else 254 bsc->serdes_flags |= BRGPHY_5709S; 255 sc->mii_flags |= MIIF_HAVEFIBER; 256 break; 257 } 258 break; 259 } 260 261 PHY_RESET(sc); 262 263 /* Read the PHY's capabilities. */ 264 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 265 if (sc->mii_capabilities & BMSR_EXTSTAT) 266 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 267 device_printf(dev, " "); 268 269 #define ADD(m, c) ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL) 270 271 /* Add the supported media types */ 272 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 273 mii_phy_add_media(sc); 274 printf("\n"); 275 } else { 276 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 277 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 278 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 279 printf("1000baseSX-FDX, "); 280 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 281 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 282 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 283 printf("2500baseSX-FDX, "); 284 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 285 (detect_hs21(bce_sc) != 0)) { 286 /* 287 * There appears to be certain silicon revision 288 * in IBM HS21 blades that is having issues with 289 * this driver wating for the auto-negotiation to 290 * complete. This happens with a specific chip id 291 * only and when the 1000baseSX-FDX is the only 292 * mode. Workaround this issue since it's unlikely 293 * to be ever addressed. 294 */ 295 printf("auto-neg workaround, "); 296 bsc->serdes_flags |= BRGPHY_NOANWAIT; 297 } 298 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 299 printf("auto\n"); 300 } 301 302 #undef ADD 303 MIIBUS_MEDIAINIT(sc->mii_dev); 304 return (0); 305 } 306 307 static int 308 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 309 { 310 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 311 int val; 312 313 switch (cmd) { 314 case MII_POLLSTAT: 315 break; 316 case MII_MEDIACHG: 317 /* Todo: Why is this here? Is it really needed? */ 318 PHY_RESET(sc); /* XXX hardware bug work-around */ 319 320 switch (IFM_SUBTYPE(ife->ifm_media)) { 321 case IFM_AUTO: 322 brgphy_mii_phy_auto(sc, ife->ifm_media); 323 break; 324 case IFM_2500_SX: 325 case IFM_1000_SX: 326 case IFM_1000_T: 327 case IFM_100_TX: 328 case IFM_10_T: 329 brgphy_setmedia(sc, ife->ifm_media); 330 break; 331 default: 332 return (EINVAL); 333 } 334 break; 335 case MII_TICK: 336 /* Bail if autoneg isn't in process. */ 337 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 338 sc->mii_ticks = 0; 339 break; 340 } 341 342 /* 343 * Check to see if we have link. If we do, we don't 344 * need to restart the autonegotiation process. 345 */ 346 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 347 if (val & BMSR_LINK) { 348 sc->mii_ticks = 0; /* Reset autoneg timer. */ 349 break; 350 } 351 352 /* Announce link loss right after it happens. */ 353 if (sc->mii_ticks++ == 0) 354 break; 355 356 /* Only retry autonegotiation every mii_anegticks seconds. */ 357 if (sc->mii_ticks <= sc->mii_anegticks) 358 break; 359 360 361 /* Retry autonegotiation */ 362 sc->mii_ticks = 0; 363 brgphy_mii_phy_auto(sc, ife->ifm_media); 364 break; 365 } 366 367 /* Update the media status. */ 368 PHY_STATUS(sc); 369 370 /* 371 * Callback if something changed. Note that we need to poke 372 * the DSP on the Broadcom PHYs if the media changes. 373 */ 374 if (sc->mii_media_active != mii->mii_media_active || 375 sc->mii_media_status != mii->mii_media_status || 376 cmd == MII_MEDIACHG) { 377 switch (sc->mii_mpd_oui) { 378 case MII_OUI_BROADCOM: 379 switch (sc->mii_mpd_model) { 380 case MII_MODEL_BROADCOM_BCM5400: 381 bcm5401_load_dspcode(sc); 382 break; 383 case MII_MODEL_BROADCOM_BCM5401: 384 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 385 bcm5401_load_dspcode(sc); 386 break; 387 case MII_MODEL_BROADCOM_BCM5411: 388 bcm5411_load_dspcode(sc); 389 break; 390 case MII_MODEL_BROADCOM_BCM54K2: 391 bcm54k2_load_dspcode(sc); 392 break; 393 } 394 break; 395 } 396 } 397 mii_phy_update(sc, cmd); 398 return (0); 399 } 400 401 /****************************************************************************/ 402 /* Sets the PHY link speed. */ 403 /* */ 404 /* Returns: */ 405 /* None */ 406 /****************************************************************************/ 407 static void 408 brgphy_setmedia(struct mii_softc *sc, int media) 409 { 410 int bmcr = 0, gig; 411 412 switch (IFM_SUBTYPE(media)) { 413 case IFM_2500_SX: 414 break; 415 case IFM_1000_SX: 416 case IFM_1000_T: 417 bmcr = BRGPHY_S1000; 418 break; 419 case IFM_100_TX: 420 bmcr = BRGPHY_S100; 421 break; 422 case IFM_10_T: 423 default: 424 bmcr = BRGPHY_S10; 425 break; 426 } 427 428 if ((media & IFM_FDX) != 0) { 429 bmcr |= BRGPHY_BMCR_FDX; 430 gig = BRGPHY_1000CTL_AFD; 431 } else { 432 gig = BRGPHY_1000CTL_AHD; 433 } 434 435 /* Force loopback to disconnect PHY from Ethernet medium. */ 436 brgphy_enable_loopback(sc); 437 438 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 439 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 440 441 if (IFM_SUBTYPE(media) != IFM_1000_T && 442 IFM_SUBTYPE(media) != IFM_1000_SX) { 443 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 444 return; 445 } 446 447 if (IFM_SUBTYPE(media) == IFM_1000_T) { 448 gig |= BRGPHY_1000CTL_MSE; 449 if ((media & IFM_ETH_MASTER) != 0) 450 gig |= BRGPHY_1000CTL_MSC; 451 } 452 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 453 PHY_WRITE(sc, BRGPHY_MII_BMCR, 454 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 455 } 456 457 /****************************************************************************/ 458 /* Set the media status based on the PHY settings. */ 459 /* */ 460 /* Returns: */ 461 /* None */ 462 /****************************************************************************/ 463 static void 464 brgphy_status(struct mii_softc *sc) 465 { 466 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 467 struct mii_data *mii = sc->mii_pdata; 468 int aux, bmcr, bmsr, val, xstat; 469 u_int flowstat; 470 471 mii->mii_media_status = IFM_AVALID; 472 mii->mii_media_active = IFM_ETHER; 473 474 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 475 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 476 477 if (bmcr & BRGPHY_BMCR_LOOP) { 478 mii->mii_media_active |= IFM_LOOP; 479 } 480 481 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 482 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 483 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 484 /* Erg, still trying, I guess... */ 485 mii->mii_media_active |= IFM_NONE; 486 return; 487 } 488 489 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 490 /* 491 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 492 * wedges at least the PHY of BCM5704 (but not others). 493 */ 494 flowstat = mii_phy_flowstatus(sc); 495 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 496 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 497 498 /* If copper link is up, get the negotiated speed/duplex. */ 499 if (aux & BRGPHY_AUXSTS_LINK) { 500 mii->mii_media_status |= IFM_ACTIVE; 501 switch (aux & BRGPHY_AUXSTS_AN_RES) { 502 case BRGPHY_RES_1000FD: 503 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 504 case BRGPHY_RES_1000HD: 505 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 506 case BRGPHY_RES_100FD: 507 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 508 case BRGPHY_RES_100T4: 509 mii->mii_media_active |= IFM_100_T4; break; 510 case BRGPHY_RES_100HD: 511 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 512 case BRGPHY_RES_10FD: 513 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 514 case BRGPHY_RES_10HD: 515 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 516 default: 517 mii->mii_media_active |= IFM_NONE; break; 518 } 519 520 if ((mii->mii_media_active & IFM_FDX) != 0) 521 mii->mii_media_active |= flowstat; 522 523 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 524 (xstat & BRGPHY_1000STS_MSR) != 0) 525 mii->mii_media_active |= IFM_ETH_MASTER; 526 } 527 } else { 528 /* Todo: Add support for flow control. */ 529 /* If serdes link is up, get the negotiated speed/duplex. */ 530 if (bmsr & BRGPHY_BMSR_LINK) { 531 mii->mii_media_status |= IFM_ACTIVE; 532 } 533 534 /* Check the link speed/duplex based on the PHY type. */ 535 if (bsc->serdes_flags & BRGPHY_5706S) { 536 mii->mii_media_active |= IFM_1000_SX; 537 538 /* If autoneg enabled, read negotiated duplex settings */ 539 if (bmcr & BRGPHY_BMCR_AUTOEN) { 540 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 541 if (val & BRGPHY_SERDES_ANAR_FDX) 542 mii->mii_media_active |= IFM_FDX; 543 else 544 mii->mii_media_active |= IFM_HDX; 545 } 546 } else if (bsc->serdes_flags & BRGPHY_5708S) { 547 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 548 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 549 550 /* Check for MRBE auto-negotiated speed results. */ 551 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 552 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 553 mii->mii_media_active |= IFM_10_FL; break; 554 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 555 mii->mii_media_active |= IFM_100_FX; break; 556 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 557 mii->mii_media_active |= IFM_1000_SX; break; 558 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 559 mii->mii_media_active |= IFM_2500_SX; break; 560 } 561 562 /* Check for MRBE auto-negotiated duplex results. */ 563 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 564 mii->mii_media_active |= IFM_FDX; 565 else 566 mii->mii_media_active |= IFM_HDX; 567 } else if (bsc->serdes_flags & BRGPHY_5709S) { 568 /* Select GP Status Block of the AN MMD, get autoneg results. */ 569 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 570 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 571 572 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 573 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 574 575 /* Check for MRBE auto-negotiated speed results. */ 576 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 577 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 578 mii->mii_media_active |= IFM_10_FL; break; 579 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 580 mii->mii_media_active |= IFM_100_FX; break; 581 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 582 mii->mii_media_active |= IFM_1000_SX; break; 583 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 584 mii->mii_media_active |= IFM_2500_SX; break; 585 } 586 587 /* Check for MRBE auto-negotiated duplex results. */ 588 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 589 mii->mii_media_active |= IFM_FDX; 590 else 591 mii->mii_media_active |= IFM_HDX; 592 } 593 } 594 } 595 596 static void 597 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 598 { 599 int anar, ktcr = 0; 600 601 PHY_RESET(sc); 602 603 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 604 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 605 if ((media & IFM_FLOW) != 0 || 606 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 607 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 608 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 609 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 610 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 611 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 612 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 613 PHY_READ(sc, BRGPHY_MII_1000CTL); 614 } else { 615 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 616 if ((media & IFM_FLOW) != 0 || 617 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 618 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 619 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 620 } 621 622 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 623 BRGPHY_BMCR_STARTNEG); 624 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 625 } 626 627 /* Enable loopback to force the link down. */ 628 static void 629 brgphy_enable_loopback(struct mii_softc *sc) 630 { 631 int i; 632 633 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 634 for (i = 0; i < 15000; i++) { 635 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 636 break; 637 DELAY(10); 638 } 639 } 640 641 /* Turn off tap power management on 5401. */ 642 static void 643 bcm5401_load_dspcode(struct mii_softc *sc) 644 { 645 static const struct { 646 int reg; 647 uint16_t val; 648 } dspcode[] = { 649 { BRGPHY_MII_AUXCTL, 0x0c20 }, 650 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 651 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 652 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 653 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 654 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 655 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 656 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 657 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 658 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 659 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 660 { 0, 0 }, 661 }; 662 int i; 663 664 for (i = 0; dspcode[i].reg != 0; i++) 665 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 666 DELAY(40); 667 } 668 669 static void 670 bcm5411_load_dspcode(struct mii_softc *sc) 671 { 672 static const struct { 673 int reg; 674 uint16_t val; 675 } dspcode[] = { 676 { 0x1c, 0x8c23 }, 677 { 0x1c, 0x8ca3 }, 678 { 0x1c, 0x8c23 }, 679 { 0, 0 }, 680 }; 681 int i; 682 683 for (i = 0; dspcode[i].reg != 0; i++) 684 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 685 } 686 687 void 688 bcm54k2_load_dspcode(struct mii_softc *sc) 689 { 690 static const struct { 691 int reg; 692 uint16_t val; 693 } dspcode[] = { 694 { 4, 0x01e1 }, 695 { 9, 0x0300 }, 696 { 0, 0 }, 697 }; 698 int i; 699 700 for (i = 0; dspcode[i].reg != 0; i++) 701 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 702 703 } 704 705 static void 706 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 707 { 708 static const struct { 709 int reg; 710 uint16_t val; 711 } dspcode[] = { 712 { 0x1c, 0x8d68 }, 713 { 0x1c, 0x8d68 }, 714 { 0, 0 }, 715 }; 716 int i; 717 718 for (i = 0; dspcode[i].reg != 0; i++) 719 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 720 } 721 722 static void 723 brgphy_fixup_adc_bug(struct mii_softc *sc) 724 { 725 static const struct { 726 int reg; 727 uint16_t val; 728 } dspcode[] = { 729 { BRGPHY_MII_AUXCTL, 0x0c00 }, 730 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 731 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 732 { 0, 0 }, 733 }; 734 int i; 735 736 for (i = 0; dspcode[i].reg != 0; i++) 737 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 738 } 739 740 static void 741 brgphy_fixup_adjust_trim(struct mii_softc *sc) 742 { 743 static const struct { 744 int reg; 745 uint16_t val; 746 } dspcode[] = { 747 { BRGPHY_MII_AUXCTL, 0x0c00 }, 748 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 749 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 750 { BRGPHY_MII_TEST1, 0x0014 }, 751 { BRGPHY_MII_AUXCTL, 0x0400 }, 752 { 0, 0 }, 753 }; 754 int i; 755 756 for (i = 0; dspcode[i].reg != 0; i++) 757 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 758 } 759 760 static void 761 brgphy_fixup_ber_bug(struct mii_softc *sc) 762 { 763 static const struct { 764 int reg; 765 uint16_t val; 766 } dspcode[] = { 767 { BRGPHY_MII_AUXCTL, 0x0c00 }, 768 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 769 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 770 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 771 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 772 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 773 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 774 { BRGPHY_MII_AUXCTL, 0x0400 }, 775 { 0, 0 }, 776 }; 777 int i; 778 779 for (i = 0; dspcode[i].reg != 0; i++) 780 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 781 } 782 783 static void 784 brgphy_fixup_crc_bug(struct mii_softc *sc) 785 { 786 static const struct { 787 int reg; 788 uint16_t val; 789 } dspcode[] = { 790 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 791 { 0x1c, 0x8c68 }, 792 { 0x1c, 0x8d68 }, 793 { 0x1c, 0x8c68 }, 794 { 0, 0 }, 795 }; 796 int i; 797 798 for (i = 0; dspcode[i].reg != 0; i++) 799 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 800 } 801 802 static void 803 brgphy_fixup_jitter_bug(struct mii_softc *sc) 804 { 805 static const struct { 806 int reg; 807 uint16_t val; 808 } dspcode[] = { 809 { BRGPHY_MII_AUXCTL, 0x0c00 }, 810 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 811 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 812 { BRGPHY_MII_AUXCTL, 0x0400 }, 813 { 0, 0 }, 814 }; 815 int i; 816 817 for (i = 0; dspcode[i].reg != 0; i++) 818 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 819 } 820 821 static void 822 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 823 { 824 uint32_t val; 825 826 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 827 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 828 val &= ~(1 << 8); 829 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 830 831 } 832 833 static void 834 brgphy_ethernet_wirespeed(struct mii_softc *sc) 835 { 836 uint32_t val; 837 838 /* Enable Ethernet@WireSpeed. */ 839 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 840 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 841 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 842 } 843 844 static void 845 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 846 { 847 uint32_t val; 848 849 /* Set or clear jumbo frame settings in the PHY. */ 850 if (mtu > ETHER_MAX_LEN) { 851 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 852 /* BCM5401 PHY cannot read-modify-write. */ 853 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 854 } else { 855 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 856 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 857 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 858 val | BRGPHY_AUXCTL_LONG_PKT); 859 } 860 861 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 862 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 863 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 864 } else { 865 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 866 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 867 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 868 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 869 870 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 871 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 872 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 873 } 874 } 875 876 static void 877 brgphy_reset(struct mii_softc *sc) 878 { 879 struct bge_softc *bge_sc = NULL; 880 struct bce_softc *bce_sc = NULL; 881 if_t ifp; 882 int i, val; 883 884 /* 885 * Perform a reset. Note that at least some Broadcom PHYs default to 886 * being powered down as well as isolated after a reset but don't work 887 * if one or both of these bits are cleared. However, they just work 888 * fine if both bits remain set, so we don't use mii_phy_reset() here. 889 */ 890 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 891 892 /* Wait 100ms for it to complete. */ 893 for (i = 0; i < 100; i++) { 894 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 895 break; 896 DELAY(1000); 897 } 898 899 /* Handle any PHY specific procedures following the reset. */ 900 switch (sc->mii_mpd_oui) { 901 case MII_OUI_BROADCOM: 902 switch (sc->mii_mpd_model) { 903 case MII_MODEL_BROADCOM_BCM5400: 904 bcm5401_load_dspcode(sc); 905 break; 906 case MII_MODEL_BROADCOM_BCM5401: 907 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 908 bcm5401_load_dspcode(sc); 909 break; 910 case MII_MODEL_BROADCOM_BCM5411: 911 bcm5411_load_dspcode(sc); 912 break; 913 case MII_MODEL_BROADCOM_BCM54K2: 914 bcm54k2_load_dspcode(sc); 915 break; 916 } 917 break; 918 case MII_OUI_BROADCOM3: 919 switch (sc->mii_mpd_model) { 920 case MII_MODEL_BROADCOM3_BCM5717C: 921 case MII_MODEL_BROADCOM3_BCM5719C: 922 case MII_MODEL_BROADCOM3_BCM5720C: 923 case MII_MODEL_BROADCOM3_BCM57765: 924 return; 925 } 926 break; 927 case MII_OUI_BROADCOM4: 928 return; 929 } 930 931 ifp = sc->mii_pdata->mii_ifp; 932 933 /* Find the driver associated with this PHY. */ 934 if (mii_phy_mac_match(sc, "bge")) 935 bge_sc = mii_phy_mac_softc(sc); 936 else if (mii_phy_mac_match(sc, "bce")) 937 bce_sc = mii_phy_mac_softc(sc); 938 939 if (bge_sc) { 940 /* Fix up various bugs */ 941 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 942 brgphy_fixup_5704_a0_bug(sc); 943 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 944 brgphy_fixup_adc_bug(sc); 945 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 946 brgphy_fixup_adjust_trim(sc); 947 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 948 brgphy_fixup_ber_bug(sc); 949 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 950 brgphy_fixup_crc_bug(sc); 951 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 952 brgphy_fixup_jitter_bug(sc); 953 954 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 955 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 956 957 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 958 brgphy_ethernet_wirespeed(sc); 959 960 /* Enable Link LED on Dell boxes */ 961 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 962 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 963 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 964 ~BRGPHY_PHY_EXTCTL_3_LED); 965 } 966 967 /* Adjust output voltage (From Linux driver) */ 968 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 969 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 970 } else if (bce_sc) { 971 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 972 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 973 974 /* Store autoneg capabilities/results in digital block (Page 0) */ 975 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 976 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 977 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 978 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 979 980 /* Enable fiber mode and autodetection */ 981 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 982 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 983 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 984 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 985 986 /* Enable parallel detection */ 987 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 988 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 989 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 990 991 /* Advertise 2.5G support through next page during autoneg */ 992 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 993 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 994 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 995 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 996 997 /* Increase TX signal amplitude */ 998 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 999 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1000 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1001 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1002 BRGPHY_5708S_TX_MISC_PG5); 1003 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1004 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1005 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1006 BRGPHY_5708S_DIG_PG0); 1007 } 1008 1009 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1010 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1011 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1012 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1013 BRGPHY_5708S_TX_MISC_PG5); 1014 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1015 bce_sc->bce_port_hw_cfg & 1016 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1017 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1018 BRGPHY_5708S_DIG_PG0); 1019 } 1020 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1021 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1022 1023 /* Select the SerDes Digital block of the AN MMD. */ 1024 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1025 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1026 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1027 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1028 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1029 1030 /* Select the Over 1G block of the AN MMD. */ 1031 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1032 1033 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1034 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1035 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1036 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1037 else 1038 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1039 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1040 1041 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1042 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1043 1044 /* Enable MRBE speed autoneg. */ 1045 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1046 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1047 BRGPHY_MRBE_MSG_PG5_NP_T2; 1048 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1049 1050 /* Select the Clause 73 User B0 block of the AN MMD. */ 1051 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1052 1053 /* Enable MRBE speed autoneg. */ 1054 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1055 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1056 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1057 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1058 1059 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1060 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1061 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1062 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1063 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1064 brgphy_fixup_disable_early_dac(sc); 1065 1066 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1067 brgphy_ethernet_wirespeed(sc); 1068 } else { 1069 brgphy_fixup_ber_bug(sc); 1070 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1071 brgphy_ethernet_wirespeed(sc); 1072 } 1073 } 1074 } 1075