1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/ethernet.h> 53 #include <net/if_media.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include "miidevs.h" 58 59 #include <dev/mii/brgphyreg.h> 60 #include <net/if_arp.h> 61 #include <machine/bus.h> 62 #include <dev/bge/if_bgereg.h> 63 #include <dev/bce/if_bcereg.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include "miibus_if.h" 69 70 static int brgphy_probe(device_t); 71 static int brgphy_attach(device_t); 72 73 struct brgphy_softc { 74 struct mii_softc mii_sc; 75 int serdes_flags; /* Keeps track of the serdes type used */ 76 #define BRGPHY_5706S 0x0001 77 #define BRGPHY_5708S 0x0002 78 #define BRGPHY_NOANWAIT 0x0004 79 #define BRGPHY_5709S 0x0008 80 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 81 }; 82 83 static device_method_t brgphy_methods[] = { 84 /* device interface */ 85 DEVMETHOD(device_probe, brgphy_probe), 86 DEVMETHOD(device_attach, brgphy_attach), 87 DEVMETHOD(device_detach, mii_phy_detach), 88 DEVMETHOD(device_shutdown, bus_generic_shutdown), 89 DEVMETHOD_END 90 }; 91 92 static driver_t brgphy_driver = { 93 "brgphy", 94 brgphy_methods, 95 sizeof(struct brgphy_softc) 96 }; 97 98 DRIVER_MODULE(brgphy, miibus, brgphy_driver, 0, 0); 99 100 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 101 static void brgphy_setmedia(struct mii_softc *, int); 102 static void brgphy_status(struct mii_softc *); 103 static void brgphy_mii_phy_auto(struct mii_softc *, int); 104 static void brgphy_reset(struct mii_softc *); 105 static void brgphy_enable_loopback(struct mii_softc *); 106 static void bcm5401_load_dspcode(struct mii_softc *); 107 static void bcm5411_load_dspcode(struct mii_softc *); 108 static void bcm54k2_load_dspcode(struct mii_softc *); 109 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 110 static void brgphy_fixup_adc_bug(struct mii_softc *); 111 static void brgphy_fixup_adjust_trim(struct mii_softc *); 112 static void brgphy_fixup_ber_bug(struct mii_softc *); 113 static void brgphy_fixup_crc_bug(struct mii_softc *); 114 static void brgphy_fixup_jitter_bug(struct mii_softc *); 115 static void brgphy_ethernet_wirespeed(struct mii_softc *); 116 static void brgphy_bcm54xx_clock_delay(struct mii_softc *); 117 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 118 119 static const struct mii_phydesc brgphys[] = { 120 MII_PHY_DESC(BROADCOM, BCM5400), 121 MII_PHY_DESC(BROADCOM, BCM5401), 122 MII_PHY_DESC(BROADCOM, BCM5402), 123 MII_PHY_DESC(BROADCOM, BCM5411), 124 MII_PHY_DESC(BROADCOM, BCM5404), 125 MII_PHY_DESC(BROADCOM, BCM5424), 126 MII_PHY_DESC(BROADCOM, BCM54K2), 127 MII_PHY_DESC(BROADCOM, BCM5701), 128 MII_PHY_DESC(BROADCOM, BCM5703), 129 MII_PHY_DESC(BROADCOM, BCM5704), 130 MII_PHY_DESC(BROADCOM, BCM5705), 131 MII_PHY_DESC(BROADCOM, BCM5706), 132 MII_PHY_DESC(BROADCOM, BCM5714), 133 MII_PHY_DESC(BROADCOM, BCM5421), 134 MII_PHY_DESC(BROADCOM, BCM5750), 135 MII_PHY_DESC(BROADCOM, BCM5752), 136 MII_PHY_DESC(BROADCOM, BCM5780), 137 MII_PHY_DESC(BROADCOM, BCM5708C), 138 MII_PHY_DESC(BROADCOM, BCM5466), 139 MII_PHY_DESC(BROADCOM2, BCM5478), 140 MII_PHY_DESC(BROADCOM2, BCM5488), 141 MII_PHY_DESC(BROADCOM2, BCM5482), 142 MII_PHY_DESC(BROADCOM2, BCM5708S), 143 MII_PHY_DESC(BROADCOM2, BCM5709C), 144 MII_PHY_DESC(BROADCOM2, BCM5709S), 145 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 146 MII_PHY_DESC(BROADCOM2, BCM5722), 147 MII_PHY_DESC(BROADCOM2, BCM5755), 148 MII_PHY_DESC(BROADCOM2, BCM5754), 149 MII_PHY_DESC(BROADCOM2, BCM5761), 150 MII_PHY_DESC(BROADCOM2, BCM5784), 151 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 152 MII_PHY_DESC(BROADCOM2, BCM5785), 153 #endif 154 MII_PHY_DESC(BROADCOM3, BCM54618SE), 155 MII_PHY_DESC(BROADCOM3, BCM5717C), 156 MII_PHY_DESC(BROADCOM3, BCM5719C), 157 MII_PHY_DESC(BROADCOM3, BCM5720C), 158 MII_PHY_DESC(BROADCOM3, BCM57765), 159 MII_PHY_DESC(BROADCOM3, BCM57780), 160 MII_PHY_DESC(BROADCOM4, BCM54213PE), 161 MII_PHY_DESC(BROADCOM4, BCM5725C), 162 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 163 MII_PHY_END 164 }; 165 166 static const struct mii_phy_funcs brgphy_funcs = { 167 brgphy_service, 168 brgphy_status, 169 brgphy_reset 170 }; 171 172 static const struct hs21_type { 173 const uint32_t id; 174 const char *prod; 175 } hs21_type_lists[] = { 176 { 0x57081021, "IBM eServer BladeCenter HS21" }, 177 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" }, 178 }; 179 180 static int 181 detect_hs21(struct bce_softc *bce_sc) 182 { 183 char *sysenv; 184 int found, i; 185 186 found = 0; 187 sysenv = kern_getenv("smbios.system.product"); 188 if (sysenv == NULL) 189 return (found); 190 for (i = 0; i < nitems(hs21_type_lists); i++) { 191 if (bce_sc->bce_chipid == hs21_type_lists[i].id && 192 strncmp(sysenv, hs21_type_lists[i].prod, 193 strlen(hs21_type_lists[i].prod)) == 0) { 194 found++; 195 break; 196 } 197 } 198 freeenv(sysenv); 199 return (found); 200 } 201 202 /* Search for our PHY in the list of known PHYs */ 203 static int 204 brgphy_probe(device_t dev) 205 { 206 207 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 208 } 209 210 /* Attach the PHY to the MII bus */ 211 static int 212 brgphy_attach(device_t dev) 213 { 214 struct brgphy_softc *bsc; 215 struct bge_softc *bge_sc = NULL; 216 struct bce_softc *bce_sc = NULL; 217 struct mii_softc *sc; 218 219 bsc = device_get_softc(dev); 220 sc = &bsc->mii_sc; 221 222 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 223 &brgphy_funcs, 0); 224 225 bsc->serdes_flags = 0; 226 227 /* Find the MAC driver associated with this PHY. */ 228 if (mii_dev_mac_match(dev, "bge")) 229 bge_sc = mii_dev_mac_softc(dev); 230 else if (mii_dev_mac_match(dev, "bce")) 231 bce_sc = mii_dev_mac_softc(dev); 232 233 /* Handle any special cases based on the PHY ID */ 234 switch (sc->mii_mpd_oui) { 235 case MII_OUI_BROADCOM: 236 switch (sc->mii_mpd_model) { 237 case MII_MODEL_BROADCOM_BCM5706: 238 case MII_MODEL_BROADCOM_BCM5714: 239 /* 240 * The 5464 PHY used in the 5706 supports both copper 241 * and fiber interfaces over GMII. Need to check the 242 * shadow registers to see which mode is actually 243 * in effect, and therefore whether we have 5706C or 244 * 5706S. 245 */ 246 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 247 BRGPHY_SHADOW_1C_MODE_CTRL); 248 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 249 BRGPHY_SHADOW_1C_ENA_1000X) { 250 bsc->serdes_flags |= BRGPHY_5706S; 251 sc->mii_flags |= MIIF_HAVEFIBER; 252 } 253 break; 254 } 255 break; 256 case MII_OUI_BROADCOM2: 257 switch (sc->mii_mpd_model) { 258 case MII_MODEL_BROADCOM2_BCM5708S: 259 bsc->serdes_flags |= BRGPHY_5708S; 260 sc->mii_flags |= MIIF_HAVEFIBER; 261 break; 262 case MII_MODEL_BROADCOM2_BCM5709S: 263 /* 264 * XXX 265 * 5720S and 5709S shares the same PHY id. 266 * Assume 5720S PHY if parent device is bge(4). 267 */ 268 if (bge_sc != NULL) 269 bsc->serdes_flags |= BRGPHY_5708S; 270 else 271 bsc->serdes_flags |= BRGPHY_5709S; 272 sc->mii_flags |= MIIF_HAVEFIBER; 273 break; 274 } 275 break; 276 } 277 278 PHY_RESET(sc); 279 280 /* Read the PHY's capabilities. */ 281 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 282 if (sc->mii_capabilities & BMSR_EXTSTAT) 283 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 284 device_printf(dev, " "); 285 286 /* Add the supported media types */ 287 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 288 mii_phy_add_media(sc); 289 printf("\n"); 290 } else { 291 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 292 ifmedia_add(&sc->mii_pdata->mii_media, 293 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 294 0, NULL); 295 printf("1000baseSX-FDX, "); 296 /* 297 * 2.5G support is a software enabled feature 298 * on the 5708S and 5709S. 299 */ 300 if (bce_sc && (bce_sc->bce_phy_flags & 301 BCE_PHY_2_5G_CAPABLE_FLAG)) { 302 ifmedia_add(&sc->mii_pdata->mii_media, 303 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, 304 sc->mii_inst), 0, NULL); 305 printf("2500baseSX-FDX, "); 306 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 307 (detect_hs21(bce_sc) != 0)) { 308 /* 309 * There appears to be certain silicon revision 310 * in IBM HS21 blades that is having issues with 311 * this driver wating for the auto-negotiation to 312 * complete. This happens with a specific chip id 313 * only and when the 1000baseSX-FDX is the only 314 * mode. Workaround this issue since it's unlikely 315 * to be ever addressed. 316 */ 317 printf("auto-neg workaround, "); 318 bsc->serdes_flags |= BRGPHY_NOANWAIT; 319 } 320 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER, 321 IFM_AUTO, 0, sc->mii_inst), 0, NULL); 322 printf("auto\n"); 323 } 324 325 MIIBUS_MEDIAINIT(sc->mii_dev); 326 return (0); 327 } 328 329 static int 330 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 331 { 332 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 333 int val; 334 335 switch (cmd) { 336 case MII_POLLSTAT: 337 break; 338 case MII_MEDIACHG: 339 /* Todo: Why is this here? Is it really needed? */ 340 PHY_RESET(sc); /* XXX hardware bug work-around */ 341 342 switch (IFM_SUBTYPE(ife->ifm_media)) { 343 case IFM_AUTO: 344 brgphy_mii_phy_auto(sc, ife->ifm_media); 345 break; 346 case IFM_2500_SX: 347 case IFM_1000_SX: 348 case IFM_1000_T: 349 case IFM_100_TX: 350 case IFM_10_T: 351 brgphy_setmedia(sc, ife->ifm_media); 352 break; 353 default: 354 return (EINVAL); 355 } 356 break; 357 case MII_TICK: 358 /* Bail if autoneg isn't in process. */ 359 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 360 sc->mii_ticks = 0; 361 break; 362 } 363 364 /* 365 * Check to see if we have link. If we do, we don't 366 * need to restart the autonegotiation process. 367 */ 368 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 369 if (val & BMSR_LINK) { 370 sc->mii_ticks = 0; /* Reset autoneg timer. */ 371 break; 372 } 373 374 /* Announce link loss right after it happens. */ 375 if (sc->mii_ticks++ == 0) 376 break; 377 378 /* Only retry autonegotiation every mii_anegticks seconds. */ 379 if (sc->mii_ticks <= sc->mii_anegticks) 380 break; 381 382 /* Retry autonegotiation */ 383 sc->mii_ticks = 0; 384 brgphy_mii_phy_auto(sc, ife->ifm_media); 385 break; 386 } 387 388 /* Update the media status. */ 389 PHY_STATUS(sc); 390 391 /* 392 * Callback if something changed. Note that we need to poke 393 * the DSP on the Broadcom PHYs if the media changes. 394 */ 395 if (sc->mii_media_active != mii->mii_media_active || 396 sc->mii_media_status != mii->mii_media_status || 397 cmd == MII_MEDIACHG) { 398 switch (sc->mii_mpd_oui) { 399 case MII_OUI_BROADCOM: 400 switch (sc->mii_mpd_model) { 401 case MII_MODEL_BROADCOM_BCM5400: 402 bcm5401_load_dspcode(sc); 403 break; 404 case MII_MODEL_BROADCOM_BCM5401: 405 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 406 bcm5401_load_dspcode(sc); 407 break; 408 case MII_MODEL_BROADCOM_BCM5411: 409 bcm5411_load_dspcode(sc); 410 break; 411 case MII_MODEL_BROADCOM_BCM54K2: 412 bcm54k2_load_dspcode(sc); 413 break; 414 } 415 break; 416 case MII_OUI_BROADCOM4: 417 switch (sc->mii_mpd_model) { 418 case MII_MODEL_BROADCOM4_BCM54213PE: 419 brgphy_bcm54xx_clock_delay(sc); 420 break; 421 } 422 } 423 } 424 mii_phy_update(sc, cmd); 425 return (0); 426 } 427 428 /****************************************************************************/ 429 /* Sets the PHY link speed. */ 430 /* */ 431 /* Returns: */ 432 /* None */ 433 /****************************************************************************/ 434 static void 435 brgphy_setmedia(struct mii_softc *sc, int media) 436 { 437 int bmcr = 0, gig; 438 439 switch (IFM_SUBTYPE(media)) { 440 case IFM_2500_SX: 441 break; 442 case IFM_1000_SX: 443 case IFM_1000_T: 444 bmcr = BRGPHY_S1000; 445 break; 446 case IFM_100_TX: 447 bmcr = BRGPHY_S100; 448 break; 449 case IFM_10_T: 450 default: 451 bmcr = BRGPHY_S10; 452 break; 453 } 454 455 if ((media & IFM_FDX) != 0) { 456 bmcr |= BRGPHY_BMCR_FDX; 457 gig = BRGPHY_1000CTL_AFD; 458 } else { 459 gig = BRGPHY_1000CTL_AHD; 460 } 461 462 /* Force loopback to disconnect PHY from Ethernet medium. */ 463 brgphy_enable_loopback(sc); 464 465 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 466 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 467 468 if (IFM_SUBTYPE(media) != IFM_1000_T && 469 IFM_SUBTYPE(media) != IFM_1000_SX) { 470 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 471 return; 472 } 473 474 if (IFM_SUBTYPE(media) == IFM_1000_T) { 475 gig |= BRGPHY_1000CTL_MSE; 476 if ((media & IFM_ETH_MASTER) != 0) 477 gig |= BRGPHY_1000CTL_MSC; 478 } 479 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 480 PHY_WRITE(sc, BRGPHY_MII_BMCR, 481 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 482 } 483 484 /****************************************************************************/ 485 /* Set the media status based on the PHY settings. */ 486 /* */ 487 /* Returns: */ 488 /* None */ 489 /****************************************************************************/ 490 static void 491 brgphy_status(struct mii_softc *sc) 492 { 493 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 494 struct mii_data *mii = sc->mii_pdata; 495 int aux, bmcr, bmsr, val, xstat; 496 u_int flowstat; 497 498 mii->mii_media_status = IFM_AVALID; 499 mii->mii_media_active = IFM_ETHER; 500 501 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 502 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 503 504 if (bmcr & BRGPHY_BMCR_LOOP) { 505 mii->mii_media_active |= IFM_LOOP; 506 } 507 508 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 509 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 510 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 511 /* Erg, still trying, I guess... */ 512 mii->mii_media_active |= IFM_NONE; 513 return; 514 } 515 516 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 517 /* 518 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 519 * wedges at least the PHY of BCM5704 (but not others). 520 */ 521 flowstat = mii_phy_flowstatus(sc); 522 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 523 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 524 525 /* If copper link is up, get the negotiated speed/duplex. */ 526 if (aux & BRGPHY_AUXSTS_LINK) { 527 mii->mii_media_status |= IFM_ACTIVE; 528 switch (aux & BRGPHY_AUXSTS_AN_RES) { 529 case BRGPHY_RES_1000FD: 530 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 531 case BRGPHY_RES_1000HD: 532 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 533 case BRGPHY_RES_100FD: 534 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 535 case BRGPHY_RES_100T4: 536 mii->mii_media_active |= IFM_100_T4; break; 537 case BRGPHY_RES_100HD: 538 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 539 case BRGPHY_RES_10FD: 540 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 541 case BRGPHY_RES_10HD: 542 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 543 default: 544 mii->mii_media_active |= IFM_NONE; break; 545 } 546 547 if ((mii->mii_media_active & IFM_FDX) != 0) 548 mii->mii_media_active |= flowstat; 549 550 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 551 (xstat & BRGPHY_1000STS_MSR) != 0) 552 mii->mii_media_active |= IFM_ETH_MASTER; 553 } 554 } else { 555 /* Todo: Add support for flow control. */ 556 /* If serdes link is up, get the negotiated speed/duplex. */ 557 if (bmsr & BRGPHY_BMSR_LINK) { 558 mii->mii_media_status |= IFM_ACTIVE; 559 } 560 561 /* Check the link speed/duplex based on the PHY type. */ 562 if (bsc->serdes_flags & BRGPHY_5706S) { 563 mii->mii_media_active |= IFM_1000_SX; 564 565 /* If autoneg enabled, read negotiated duplex settings */ 566 if (bmcr & BRGPHY_BMCR_AUTOEN) { 567 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 568 if (val & BRGPHY_SERDES_ANAR_FDX) 569 mii->mii_media_active |= IFM_FDX; 570 else 571 mii->mii_media_active |= IFM_HDX; 572 } 573 } else if (bsc->serdes_flags & BRGPHY_5708S) { 574 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 575 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 576 577 /* Check for MRBE auto-negotiated speed results. */ 578 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 579 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 580 mii->mii_media_active |= IFM_10_FL; break; 581 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 582 mii->mii_media_active |= IFM_100_FX; break; 583 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 584 mii->mii_media_active |= IFM_1000_SX; break; 585 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 586 mii->mii_media_active |= IFM_2500_SX; break; 587 } 588 589 /* Check for MRBE auto-negotiated duplex results. */ 590 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 591 mii->mii_media_active |= IFM_FDX; 592 else 593 mii->mii_media_active |= IFM_HDX; 594 } else if (bsc->serdes_flags & BRGPHY_5709S) { 595 /* Select GP Status Block of the AN MMD, get autoneg results. */ 596 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 597 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 598 599 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 600 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 601 602 /* Check for MRBE auto-negotiated speed results. */ 603 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 604 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 605 mii->mii_media_active |= IFM_10_FL; break; 606 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 607 mii->mii_media_active |= IFM_100_FX; break; 608 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 609 mii->mii_media_active |= IFM_1000_SX; break; 610 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 611 mii->mii_media_active |= IFM_2500_SX; break; 612 } 613 614 /* Check for MRBE auto-negotiated duplex results. */ 615 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 616 mii->mii_media_active |= IFM_FDX; 617 else 618 mii->mii_media_active |= IFM_HDX; 619 } 620 } 621 } 622 623 static void 624 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 625 { 626 int anar, ktcr = 0; 627 628 PHY_RESET(sc); 629 630 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 631 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 632 if ((media & IFM_FLOW) != 0 || 633 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 634 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 635 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 636 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 637 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 638 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 639 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 640 PHY_READ(sc, BRGPHY_MII_1000CTL); 641 } else { 642 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 643 if ((media & IFM_FLOW) != 0 || 644 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 645 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 646 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 647 } 648 649 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 650 BRGPHY_BMCR_STARTNEG); 651 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 652 } 653 654 /* Enable loopback to force the link down. */ 655 static void 656 brgphy_enable_loopback(struct mii_softc *sc) 657 { 658 int i; 659 660 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 661 for (i = 0; i < 15000; i++) { 662 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 663 break; 664 DELAY(10); 665 } 666 } 667 668 /* Turn off tap power management on 5401. */ 669 static void 670 bcm5401_load_dspcode(struct mii_softc *sc) 671 { 672 static const struct { 673 int reg; 674 uint16_t val; 675 } dspcode[] = { 676 { BRGPHY_MII_AUXCTL, 0x0c20 }, 677 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 678 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 679 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 680 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 681 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 682 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 683 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 684 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 685 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 686 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 687 { 0, 0 }, 688 }; 689 int i; 690 691 for (i = 0; dspcode[i].reg != 0; i++) 692 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 693 DELAY(40); 694 } 695 696 static void 697 bcm5411_load_dspcode(struct mii_softc *sc) 698 { 699 static const struct { 700 int reg; 701 uint16_t val; 702 } dspcode[] = { 703 { 0x1c, 0x8c23 }, 704 { 0x1c, 0x8ca3 }, 705 { 0x1c, 0x8c23 }, 706 { 0, 0 }, 707 }; 708 int i; 709 710 for (i = 0; dspcode[i].reg != 0; i++) 711 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 712 } 713 714 void 715 bcm54k2_load_dspcode(struct mii_softc *sc) 716 { 717 static const struct { 718 int reg; 719 uint16_t val; 720 } dspcode[] = { 721 { 4, 0x01e1 }, 722 { 9, 0x0300 }, 723 { 0, 0 }, 724 }; 725 int i; 726 727 for (i = 0; dspcode[i].reg != 0; i++) 728 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 729 730 } 731 732 static void 733 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 734 { 735 static const struct { 736 int reg; 737 uint16_t val; 738 } dspcode[] = { 739 { 0x1c, 0x8d68 }, 740 { 0x1c, 0x8d68 }, 741 { 0, 0 }, 742 }; 743 int i; 744 745 for (i = 0; dspcode[i].reg != 0; i++) 746 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 747 } 748 749 static void 750 brgphy_fixup_adc_bug(struct mii_softc *sc) 751 { 752 static const struct { 753 int reg; 754 uint16_t val; 755 } dspcode[] = { 756 { BRGPHY_MII_AUXCTL, 0x0c00 }, 757 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 758 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 759 { 0, 0 }, 760 }; 761 int i; 762 763 for (i = 0; dspcode[i].reg != 0; i++) 764 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 765 } 766 767 static void 768 brgphy_fixup_adjust_trim(struct mii_softc *sc) 769 { 770 static const struct { 771 int reg; 772 uint16_t val; 773 } dspcode[] = { 774 { BRGPHY_MII_AUXCTL, 0x0c00 }, 775 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 776 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 777 { BRGPHY_MII_TEST1, 0x0014 }, 778 { BRGPHY_MII_AUXCTL, 0x0400 }, 779 { 0, 0 }, 780 }; 781 int i; 782 783 for (i = 0; dspcode[i].reg != 0; i++) 784 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 785 } 786 787 static void 788 brgphy_fixup_ber_bug(struct mii_softc *sc) 789 { 790 static const struct { 791 int reg; 792 uint16_t val; 793 } dspcode[] = { 794 { BRGPHY_MII_AUXCTL, 0x0c00 }, 795 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 796 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 797 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 798 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 799 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 800 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 801 { BRGPHY_MII_AUXCTL, 0x0400 }, 802 { 0, 0 }, 803 }; 804 int i; 805 806 for (i = 0; dspcode[i].reg != 0; i++) 807 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 808 } 809 810 static void 811 brgphy_fixup_crc_bug(struct mii_softc *sc) 812 { 813 static const struct { 814 int reg; 815 uint16_t val; 816 } dspcode[] = { 817 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 818 { 0x1c, 0x8c68 }, 819 { 0x1c, 0x8d68 }, 820 { 0x1c, 0x8c68 }, 821 { 0, 0 }, 822 }; 823 int i; 824 825 for (i = 0; dspcode[i].reg != 0; i++) 826 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 827 } 828 829 static void 830 brgphy_fixup_jitter_bug(struct mii_softc *sc) 831 { 832 static const struct { 833 int reg; 834 uint16_t val; 835 } dspcode[] = { 836 { BRGPHY_MII_AUXCTL, 0x0c00 }, 837 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 838 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 839 { BRGPHY_MII_AUXCTL, 0x0400 }, 840 { 0, 0 }, 841 }; 842 int i; 843 844 for (i = 0; dspcode[i].reg != 0; i++) 845 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 846 } 847 848 static void 849 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 850 { 851 uint32_t val; 852 853 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 854 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 855 val &= ~(1 << 8); 856 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 857 858 } 859 860 static void 861 brgphy_ethernet_wirespeed(struct mii_softc *sc) 862 { 863 uint32_t val; 864 865 /* Enable Ethernet@WireSpeed. */ 866 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 867 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 868 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 869 } 870 871 static void 872 brgphy_bcm54xx_clock_delay(struct mii_softc *sc) 873 { 874 uint16_t val; 875 876 if (!(sc->mii_flags & (MIIF_RX_DELAY | MIIF_TX_DELAY))) 877 /* Adjusting the clocks in rgmii mode causes packet losses. */ 878 return; 879 880 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC | 881 BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT); 882 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 883 val &= BRGPHY_AUXCTL_MISC_DATA_MASK; 884 if (sc->mii_flags & MIIF_RX_DELAY) 885 val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; 886 else 887 val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; 888 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN | 889 BRGPHY_AUXCTL_SHADOW_MISC | val); 890 891 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL); 892 val = PHY_READ(sc, BRGPHY_MII_SHADOW_1C); 893 val &= BRGPHY_SHADOW_1C_DATA_MASK; 894 if (sc->mii_flags & MIIF_TX_DELAY) 895 val |= BRGPHY_SHADOW_1C_GTXCLK_EN; 896 else 897 val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN; 898 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN | 899 BRGPHY_SHADOW_1C_CLK_CTRL | val); 900 } 901 902 static void 903 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 904 { 905 uint32_t val; 906 907 /* Set or clear jumbo frame settings in the PHY. */ 908 if (mtu > ETHER_MAX_LEN) { 909 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 910 /* BCM5401 PHY cannot read-modify-write. */ 911 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 912 } else { 913 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 914 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 915 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 916 val | BRGPHY_AUXCTL_LONG_PKT); 917 } 918 919 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 920 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 921 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 922 } else { 923 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 924 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 925 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 926 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 927 928 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 929 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 930 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 931 } 932 } 933 934 static void 935 brgphy_reset(struct mii_softc *sc) 936 { 937 struct bge_softc *bge_sc = NULL; 938 struct bce_softc *bce_sc = NULL; 939 if_t ifp; 940 int i, val; 941 942 /* 943 * Perform a reset. Note that at least some Broadcom PHYs default to 944 * being powered down as well as isolated after a reset but don't work 945 * if one or both of these bits are cleared. However, they just work 946 * fine if both bits remain set, so we don't use mii_phy_reset() here. 947 */ 948 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 949 950 /* Wait 100ms for it to complete. */ 951 for (i = 0; i < 100; i++) { 952 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 953 break; 954 DELAY(1000); 955 } 956 957 /* Handle any PHY specific procedures following the reset. */ 958 switch (sc->mii_mpd_oui) { 959 case MII_OUI_BROADCOM: 960 switch (sc->mii_mpd_model) { 961 case MII_MODEL_BROADCOM_BCM5400: 962 bcm5401_load_dspcode(sc); 963 break; 964 case MII_MODEL_BROADCOM_BCM5401: 965 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 966 bcm5401_load_dspcode(sc); 967 break; 968 case MII_MODEL_BROADCOM_BCM5411: 969 bcm5411_load_dspcode(sc); 970 break; 971 case MII_MODEL_BROADCOM_BCM54K2: 972 bcm54k2_load_dspcode(sc); 973 break; 974 } 975 break; 976 case MII_OUI_BROADCOM3: 977 switch (sc->mii_mpd_model) { 978 case MII_MODEL_BROADCOM3_BCM5717C: 979 case MII_MODEL_BROADCOM3_BCM5719C: 980 case MII_MODEL_BROADCOM3_BCM5720C: 981 case MII_MODEL_BROADCOM3_BCM57765: 982 return; 983 } 984 break; 985 case MII_OUI_BROADCOM4: 986 return; 987 } 988 989 ifp = sc->mii_pdata->mii_ifp; 990 991 /* Find the driver associated with this PHY. */ 992 if (mii_phy_mac_match(sc, "bge")) 993 bge_sc = mii_phy_mac_softc(sc); 994 else if (mii_phy_mac_match(sc, "bce")) 995 bce_sc = mii_phy_mac_softc(sc); 996 997 if (bge_sc) { 998 /* Fix up various bugs */ 999 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 1000 brgphy_fixup_5704_a0_bug(sc); 1001 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 1002 brgphy_fixup_adc_bug(sc); 1003 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 1004 brgphy_fixup_adjust_trim(sc); 1005 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 1006 brgphy_fixup_ber_bug(sc); 1007 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 1008 brgphy_fixup_crc_bug(sc); 1009 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 1010 brgphy_fixup_jitter_bug(sc); 1011 1012 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 1013 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1014 1015 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 1016 brgphy_ethernet_wirespeed(sc); 1017 1018 /* Enable Link LED on Dell boxes */ 1019 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 1020 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1021 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 1022 ~BRGPHY_PHY_EXTCTL_3_LED); 1023 } 1024 1025 /* Adjust output voltage (From Linux driver) */ 1026 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 1027 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 1028 } else if (bce_sc) { 1029 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 1030 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1031 /* Store autoneg capabilities/results in digital block (Page 0) */ 1032 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 1033 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 1034 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 1035 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 1036 1037 /* Enable fiber mode and autodetection */ 1038 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1039 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1040 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1041 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1042 1043 /* Enable parallel detection */ 1044 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1045 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1046 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1047 1048 /* Advertise 2.5G support through next page during autoneg */ 1049 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1050 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1051 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1052 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1053 1054 /* Increase TX signal amplitude */ 1055 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1056 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1057 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1058 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1059 BRGPHY_5708S_TX_MISC_PG5); 1060 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1061 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1062 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1063 BRGPHY_5708S_DIG_PG0); 1064 } 1065 1066 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1067 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1068 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1069 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1070 BRGPHY_5708S_TX_MISC_PG5); 1071 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1072 bce_sc->bce_port_hw_cfg & 1073 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1074 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1075 BRGPHY_5708S_DIG_PG0); 1076 } 1077 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1078 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1079 /* Select the SerDes Digital block of the AN MMD. */ 1080 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1081 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1082 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1083 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1084 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1085 1086 /* Select the Over 1G block of the AN MMD. */ 1087 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1088 1089 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1090 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1091 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1092 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1093 else 1094 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1095 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1096 1097 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1098 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1099 1100 /* Enable MRBE speed autoneg. */ 1101 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1102 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1103 BRGPHY_MRBE_MSG_PG5_NP_T2; 1104 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1105 1106 /* Select the Clause 73 User B0 block of the AN MMD. */ 1107 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1108 1109 /* Enable MRBE speed autoneg. */ 1110 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1111 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1112 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1113 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1114 1115 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1116 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1117 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1118 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1119 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1120 brgphy_fixup_disable_early_dac(sc); 1121 1122 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1123 brgphy_ethernet_wirespeed(sc); 1124 } else { 1125 brgphy_fixup_ber_bug(sc); 1126 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1127 brgphy_ethernet_wirespeed(sc); 1128 } 1129 } 1130 } 1131