1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additonal Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 struct e1000phy_softc { 69 struct mii_softc mii_sc; 70 int mii_model; 71 }; 72 73 static device_method_t e1000phy_methods[] = { 74 /* device interface */ 75 DEVMETHOD(device_probe, e1000phy_probe), 76 DEVMETHOD(device_attach, e1000phy_attach), 77 DEVMETHOD(device_detach, mii_phy_detach), 78 DEVMETHOD(device_shutdown, bus_generic_shutdown), 79 { 0, 0 } 80 }; 81 82 static devclass_t e1000phy_devclass; 83 static driver_t e1000phy_driver = { 84 "e1000phy", 85 e1000phy_methods, 86 sizeof(struct e1000phy_softc) 87 }; 88 89 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 90 91 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 92 static void e1000phy_status(struct mii_softc *); 93 static void e1000phy_reset(struct mii_softc *); 94 static int e1000phy_mii_phy_auto(struct e1000phy_softc *, int); 95 96 static const struct mii_phydesc e1000phys[] = { 97 MII_PHY_DESC(MARVELL, E1000), 98 MII_PHY_DESC(MARVELL, E1011), 99 MII_PHY_DESC(MARVELL, E1000_3), 100 MII_PHY_DESC(MARVELL, E1000S), 101 MII_PHY_DESC(MARVELL, E1000_5), 102 MII_PHY_DESC(MARVELL, E1101), 103 MII_PHY_DESC(MARVELL, E3082), 104 MII_PHY_DESC(MARVELL, E1112), 105 MII_PHY_DESC(MARVELL, E1149), 106 MII_PHY_DESC(MARVELL, E1111), 107 MII_PHY_DESC(MARVELL, E1116), 108 MII_PHY_DESC(MARVELL, E1116R), 109 MII_PHY_DESC(MARVELL, E1118), 110 MII_PHY_DESC(MARVELL, E3016), 111 MII_PHY_DESC(MARVELL, PHYG65G), 112 MII_PHY_DESC(xxMARVELL, E1000), 113 MII_PHY_DESC(xxMARVELL, E1011), 114 MII_PHY_DESC(xxMARVELL, E1000_3), 115 MII_PHY_DESC(xxMARVELL, E1000_5), 116 MII_PHY_DESC(xxMARVELL, E1111), 117 MII_PHY_END 118 }; 119 120 static int 121 e1000phy_probe(device_t dev) 122 { 123 124 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 125 } 126 127 static int 128 e1000phy_attach(device_t dev) 129 { 130 struct e1000phy_softc *esc; 131 struct mii_softc *sc; 132 struct mii_attach_args *ma; 133 struct mii_data *mii; 134 struct ifnet *ifp; 135 136 esc = device_get_softc(dev); 137 sc = &esc->mii_sc; 138 ma = device_get_ivars(dev); 139 sc->mii_dev = device_get_parent(dev); 140 mii = ma->mii_data; 141 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 142 143 sc->mii_flags = miibus_get_flags(dev); 144 sc->mii_inst = mii->mii_instance++; 145 sc->mii_phy = ma->mii_phyno; 146 sc->mii_service = e1000phy_service; 147 sc->mii_pdata = mii; 148 149 sc->mii_flags |= MIIF_NOMANPAUSE; 150 151 esc->mii_model = MII_MODEL(ma->mii_id2); 152 ifp = sc->mii_pdata->mii_ifp; 153 if (strcmp(ifp->if_dname, "msk") == 0 && 154 (sc->mii_flags & MIIF_MACPRIV0) != 0) 155 sc->mii_flags |= MIIF_PHYPRIV0; 156 157 switch (esc->mii_model) { 158 case MII_MODEL_MARVELL_E1011: 159 case MII_MODEL_MARVELL_E1112: 160 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 161 sc->mii_flags |= MIIF_HAVEFIBER; 162 break; 163 case MII_MODEL_MARVELL_E1149: 164 /* 165 * Some 88E1149 PHY's page select is initialized to 166 * point to other bank instead of copper/fiber bank 167 * which in turn resulted in wrong registers were 168 * accessed during PHY operation. It is believed that 169 * page 0 should be used for copper PHY so reinitialize 170 * E1000_EADR to select default copper PHY. If parent 171 * device know the type of PHY(either copper or fiber), 172 * that information should be used to select default 173 * type of PHY. 174 */ 175 PHY_WRITE(sc, E1000_EADR, 0); 176 break; 177 } 178 179 e1000phy_reset(sc); 180 181 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 182 if (sc->mii_capabilities & BMSR_EXTSTAT) 183 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 184 device_printf(dev, " "); 185 mii_phy_add_media(sc); 186 printf("\n"); 187 188 MIIBUS_MEDIAINIT(sc->mii_dev); 189 return (0); 190 } 191 192 static void 193 e1000phy_reset(struct mii_softc *sc) 194 { 195 struct e1000phy_softc *esc; 196 uint16_t reg, page; 197 198 esc = (struct e1000phy_softc *)sc; 199 reg = PHY_READ(sc, E1000_SCR); 200 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 201 reg &= ~E1000_SCR_AUTO_X_MODE; 202 PHY_WRITE(sc, E1000_SCR, reg); 203 if (esc->mii_model == MII_MODEL_MARVELL_E1112) { 204 /* Select 1000BASE-X only mode. */ 205 page = PHY_READ(sc, E1000_EADR); 206 PHY_WRITE(sc, E1000_EADR, 2); 207 reg = PHY_READ(sc, E1000_SCR); 208 reg &= ~E1000_SCR_MODE_MASK; 209 reg |= E1000_SCR_MODE_1000BX; 210 PHY_WRITE(sc, E1000_SCR, reg); 211 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) { 212 /* Set SIGDET polarity low for SFP module. */ 213 PHY_WRITE(sc, E1000_EADR, 1); 214 reg = PHY_READ(sc, E1000_SCR); 215 reg |= E1000_SCR_FIB_SIGDET_POLARITY; 216 PHY_WRITE(sc, E1000_SCR, reg); 217 } 218 PHY_WRITE(sc, E1000_EADR, page); 219 } 220 } else { 221 switch (esc->mii_model) { 222 case MII_MODEL_MARVELL_E1111: 223 case MII_MODEL_MARVELL_E1112: 224 case MII_MODEL_MARVELL_E1116: 225 case MII_MODEL_MARVELL_E1118: 226 case MII_MODEL_MARVELL_E1149: 227 case MII_MODEL_MARVELL_PHYG65G: 228 /* Disable energy detect mode. */ 229 reg &= ~E1000_SCR_EN_DETECT_MASK; 230 reg |= E1000_SCR_AUTO_X_MODE; 231 if (esc->mii_model == MII_MODEL_MARVELL_E1116) 232 reg &= ~E1000_SCR_POWER_DOWN; 233 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 234 break; 235 case MII_MODEL_MARVELL_E3082: 236 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 237 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 238 break; 239 case MII_MODEL_MARVELL_E3016: 240 reg |= E1000_SCR_AUTO_MDIX; 241 reg &= ~(E1000_SCR_EN_DETECT | 242 E1000_SCR_SCRAMBLER_DISABLE); 243 reg |= E1000_SCR_LPNP; 244 /* XXX Enable class A driver for Yukon FE+ A0. */ 245 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 246 break; 247 default: 248 reg &= ~E1000_SCR_AUTO_X_MODE; 249 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 250 break; 251 } 252 if (esc->mii_model != MII_MODEL_MARVELL_E3016) { 253 /* Auto correction for reversed cable polarity. */ 254 reg &= ~E1000_SCR_POLARITY_REVERSAL; 255 } 256 PHY_WRITE(sc, E1000_SCR, reg); 257 258 if (esc->mii_model == MII_MODEL_MARVELL_E1116 || 259 esc->mii_model == MII_MODEL_MARVELL_E1149) { 260 PHY_WRITE(sc, E1000_EADR, 2); 261 reg = PHY_READ(sc, E1000_SCR); 262 reg |= E1000_SCR_RGMII_POWER_UP; 263 PHY_WRITE(sc, E1000_SCR, reg); 264 PHY_WRITE(sc, E1000_EADR, 0); 265 } 266 } 267 268 switch (esc->mii_model) { 269 case MII_MODEL_MARVELL_E3082: 270 case MII_MODEL_MARVELL_E1112: 271 case MII_MODEL_MARVELL_E1118: 272 break; 273 case MII_MODEL_MARVELL_E1116: 274 page = PHY_READ(sc, E1000_EADR); 275 /* Select page 3, LED control register. */ 276 PHY_WRITE(sc, E1000_EADR, 3); 277 PHY_WRITE(sc, E1000_SCR, 278 E1000_SCR_LED_LOS(1) | /* Link/Act */ 279 E1000_SCR_LED_INIT(8) | /* 10Mbps */ 280 E1000_SCR_LED_STAT1(7) | /* 100Mbps */ 281 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ 282 /* Set blink rate. */ 283 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | 284 E1000_BLINK_RATE(E1000_BLINK_84MS)); 285 PHY_WRITE(sc, E1000_EADR, page); 286 break; 287 case MII_MODEL_MARVELL_E3016: 288 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 289 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 290 /* Integrated register calibration workaround. */ 291 PHY_WRITE(sc, 0x1D, 17); 292 PHY_WRITE(sc, 0x1E, 0x3F60); 293 break; 294 default: 295 /* Force TX_CLK to 25MHz clock. */ 296 reg = PHY_READ(sc, E1000_ESCR); 297 reg |= E1000_ESCR_TX_CLK_25; 298 PHY_WRITE(sc, E1000_ESCR, reg); 299 break; 300 } 301 302 /* Reset the PHY so all changes take effect. */ 303 reg = PHY_READ(sc, E1000_CR); 304 reg |= E1000_CR_RESET; 305 PHY_WRITE(sc, E1000_CR, reg); 306 } 307 308 static int 309 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 310 { 311 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 312 struct e1000phy_softc *esc = (struct e1000phy_softc *)sc; 313 uint16_t speed, gig; 314 int reg; 315 316 switch (cmd) { 317 case MII_POLLSTAT: 318 break; 319 320 case MII_MEDIACHG: 321 /* 322 * If the interface is not up, don't do anything. 323 */ 324 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 325 break; 326 327 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 328 e1000phy_mii_phy_auto(esc, ife->ifm_media); 329 break; 330 } 331 332 speed = 0; 333 switch (IFM_SUBTYPE(ife->ifm_media)) { 334 case IFM_1000_T: 335 if ((sc->mii_extcapabilities & 336 (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) 337 return (EINVAL); 338 speed = E1000_CR_SPEED_1000; 339 break; 340 case IFM_1000_SX: 341 if ((sc->mii_extcapabilities & 342 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 343 return (EINVAL); 344 speed = E1000_CR_SPEED_1000; 345 break; 346 case IFM_100_TX: 347 speed = E1000_CR_SPEED_100; 348 break; 349 case IFM_10_T: 350 speed = E1000_CR_SPEED_10; 351 break; 352 case IFM_NONE: 353 reg = PHY_READ(sc, E1000_CR); 354 PHY_WRITE(sc, E1000_CR, 355 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 356 goto done; 357 default: 358 return (EINVAL); 359 } 360 361 if ((ife->ifm_media & IFM_FDX) != 0) { 362 speed |= E1000_CR_FULL_DUPLEX; 363 gig = E1000_1GCR_1000T_FD; 364 } else 365 gig = E1000_1GCR_1000T; 366 367 reg = PHY_READ(sc, E1000_CR); 368 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 369 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 370 371 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 372 gig |= E1000_1GCR_MS_ENABLE; 373 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 374 gig |= E1000_1GCR_MS_VALUE; 375 } else if ((sc->mii_extcapabilities & 376 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 377 gig = 0; 378 PHY_WRITE(sc, E1000_1GCR, gig); 379 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 380 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 381 done: 382 break; 383 case MII_TICK: 384 /* 385 * Is the interface even up? 386 */ 387 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 388 return (0); 389 390 /* 391 * Only used for autonegotiation. 392 */ 393 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 394 sc->mii_ticks = 0; 395 break; 396 } 397 398 /* 399 * check for link. 400 * Read the status register twice; BMSR_LINK is latch-low. 401 */ 402 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 403 if (reg & BMSR_LINK) { 404 sc->mii_ticks = 0; 405 break; 406 } 407 408 /* Announce link loss right after it happens. */ 409 if (sc->mii_ticks++ == 0) 410 break; 411 if (sc->mii_ticks <= sc->mii_anegticks) 412 break; 413 414 sc->mii_ticks = 0; 415 e1000phy_reset(sc); 416 e1000phy_mii_phy_auto(esc, ife->ifm_media); 417 break; 418 } 419 420 /* Update the media status. */ 421 e1000phy_status(sc); 422 423 /* Callback if something changed. */ 424 mii_phy_update(sc, cmd); 425 return (0); 426 } 427 428 static void 429 e1000phy_status(struct mii_softc *sc) 430 { 431 struct mii_data *mii = sc->mii_pdata; 432 int bmcr, bmsr, ssr; 433 434 mii->mii_media_status = IFM_AVALID; 435 mii->mii_media_active = IFM_ETHER; 436 437 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 438 bmcr = PHY_READ(sc, E1000_CR); 439 ssr = PHY_READ(sc, E1000_SSR); 440 441 if (bmsr & E1000_SR_LINK_STATUS) 442 mii->mii_media_status |= IFM_ACTIVE; 443 444 if (bmcr & E1000_CR_LOOPBACK) 445 mii->mii_media_active |= IFM_LOOP; 446 447 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 448 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 449 /* Erg, still trying, I guess... */ 450 mii->mii_media_active |= IFM_NONE; 451 return; 452 } 453 454 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 455 switch (ssr & E1000_SSR_SPEED) { 456 case E1000_SSR_1000MBS: 457 mii->mii_media_active |= IFM_1000_T; 458 break; 459 case E1000_SSR_100MBS: 460 mii->mii_media_active |= IFM_100_TX; 461 break; 462 case E1000_SSR_10MBS: 463 mii->mii_media_active |= IFM_10_T; 464 break; 465 default: 466 mii->mii_media_active |= IFM_NONE; 467 return; 468 } 469 } else { 470 /* 471 * Some fiber PHY(88E1112) does not seem to set resolved 472 * speed so always assume we've got IFM_1000_SX. 473 */ 474 mii->mii_media_active |= IFM_1000_SX; 475 } 476 477 if (ssr & E1000_SSR_DUPLEX) { 478 mii->mii_media_active |= IFM_FDX; 479 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) 480 mii->mii_media_active |= mii_phy_flowstatus(sc); 481 } else 482 mii->mii_media_active |= IFM_HDX; 483 484 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 485 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) & 486 E1000_1GSR_MS_CONFIG_RES) != 0) 487 mii->mii_media_active |= IFM_ETH_MASTER; 488 } 489 } 490 491 static int 492 e1000phy_mii_phy_auto(struct e1000phy_softc *esc, int media) 493 { 494 struct mii_softc *sc; 495 uint16_t reg; 496 497 sc = &esc->mii_sc; 498 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 499 reg = PHY_READ(sc, E1000_AR); 500 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR); 501 reg |= E1000_AR_10T | E1000_AR_10T_FD | 502 E1000_AR_100TX | E1000_AR_100TX_FD; 503 if ((media & IFM_FLOW) != 0 || 504 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 505 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR; 506 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 507 } else 508 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); 509 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 510 PHY_WRITE(sc, E1000_1GCR, 511 E1000_1GCR_1000T_FD | E1000_1GCR_1000T); 512 PHY_WRITE(sc, E1000_CR, 513 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 514 515 return (EJUSTRETURN); 516 } 517