18c1093fcSMarius Strobl /* $NetBSD: mii_bitbang.c,v 1.12 2008/05/04 17:06:09 xtraeme Exp $ */
28c1093fcSMarius Strobl
38c1093fcSMarius Strobl /*-
4b61a5730SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
5718cf2ccSPedro F. Giffuni *
68c1093fcSMarius Strobl * Copyright (c) 1999 The NetBSD Foundation, Inc.
78c1093fcSMarius Strobl * All rights reserved.
88c1093fcSMarius Strobl *
98c1093fcSMarius Strobl * This code is derived from software contributed to The NetBSD Foundation
108c1093fcSMarius Strobl * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
118c1093fcSMarius Strobl * NASA Ames Research Center.
128c1093fcSMarius Strobl *
138c1093fcSMarius Strobl * Redistribution and use in source and binary forms, with or without
148c1093fcSMarius Strobl * modification, are permitted provided that the following conditions
158c1093fcSMarius Strobl * are met:
168c1093fcSMarius Strobl * 1. Redistributions of source code must retain the above copyright
178c1093fcSMarius Strobl * notice, this list of conditions and the following didevlaimer.
188c1093fcSMarius Strobl * 2. Redistributions in binary form must reproduce the above copyright
198c1093fcSMarius Strobl * notice, this list of conditions and the following didevlaimer in the
208c1093fcSMarius Strobl * documentation and/or other materials provided with the distribution.
218c1093fcSMarius Strobl *
228c1093fcSMarius Strobl * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
238c1093fcSMarius Strobl * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
248c1093fcSMarius Strobl * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
258c1093fcSMarius Strobl * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
268c1093fcSMarius Strobl * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
278c1093fcSMarius Strobl * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
288c1093fcSMarius Strobl * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
298c1093fcSMarius Strobl * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
308c1093fcSMarius Strobl * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
318c1093fcSMarius Strobl * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
328c1093fcSMarius Strobl * POSSIBILITY OF SUCH DAMAGE.
338c1093fcSMarius Strobl */
348c1093fcSMarius Strobl
358c1093fcSMarius Strobl /*
368c1093fcSMarius Strobl * Common module for bit-bang'ing the MII.
378c1093fcSMarius Strobl */
388c1093fcSMarius Strobl
398c1093fcSMarius Strobl #include <sys/param.h>
408c1093fcSMarius Strobl #include <sys/systm.h>
418c1093fcSMarius Strobl #include <sys/module.h>
428c1093fcSMarius Strobl
438c1093fcSMarius Strobl #include <dev/mii/mii.h>
448c1093fcSMarius Strobl #include <dev/mii/mii_bitbang.h>
458c1093fcSMarius Strobl
468c1093fcSMarius Strobl MODULE_VERSION(mii_bitbang, 1);
478c1093fcSMarius Strobl
488c1093fcSMarius Strobl static void mii_bitbang_sendbits(device_t dev, mii_bitbang_ops_t ops,
498c1093fcSMarius Strobl uint32_t data, int nbits);
508c1093fcSMarius Strobl
518c1093fcSMarius Strobl #define MWRITE(x) \
528c1093fcSMarius Strobl do { \
538c1093fcSMarius Strobl ops->mbo_write(dev, (x)); \
548c1093fcSMarius Strobl DELAY(1); \
558c1093fcSMarius Strobl } while (/* CONSTCOND */ 0)
568c1093fcSMarius Strobl
578c1093fcSMarius Strobl #define MREAD ops->mbo_read(dev)
588c1093fcSMarius Strobl
598c1093fcSMarius Strobl #define MDO ops->mbo_bits[MII_BIT_MDO]
608c1093fcSMarius Strobl #define MDI ops->mbo_bits[MII_BIT_MDI]
618c1093fcSMarius Strobl #define MDC ops->mbo_bits[MII_BIT_MDC]
628c1093fcSMarius Strobl #define MDIRPHY ops->mbo_bits[MII_BIT_DIR_HOST_PHY]
638c1093fcSMarius Strobl #define MDIRHOST ops->mbo_bits[MII_BIT_DIR_PHY_HOST]
648c1093fcSMarius Strobl
658c1093fcSMarius Strobl /*
668c1093fcSMarius Strobl * mii_bitbang_sync:
678c1093fcSMarius Strobl *
688c1093fcSMarius Strobl * Synchronize the MII.
698c1093fcSMarius Strobl */
708c1093fcSMarius Strobl void
mii_bitbang_sync(device_t dev,mii_bitbang_ops_t ops)718c1093fcSMarius Strobl mii_bitbang_sync(device_t dev, mii_bitbang_ops_t ops)
728c1093fcSMarius Strobl {
738c1093fcSMarius Strobl int i;
748c1093fcSMarius Strobl uint32_t v;
758c1093fcSMarius Strobl
768c1093fcSMarius Strobl v = MDIRPHY | MDO;
778c1093fcSMarius Strobl
788c1093fcSMarius Strobl MWRITE(v);
798c1093fcSMarius Strobl for (i = 0; i < 32; i++) {
808c1093fcSMarius Strobl MWRITE(v | MDC);
818c1093fcSMarius Strobl MWRITE(v);
828c1093fcSMarius Strobl }
838c1093fcSMarius Strobl }
848c1093fcSMarius Strobl
858c1093fcSMarius Strobl /*
868c1093fcSMarius Strobl * mii_bitbang_sendbits:
878c1093fcSMarius Strobl *
888c1093fcSMarius Strobl * Send a series of bits to the MII.
898c1093fcSMarius Strobl */
908c1093fcSMarius Strobl static void
mii_bitbang_sendbits(device_t dev,mii_bitbang_ops_t ops,uint32_t data,int nbits)918c1093fcSMarius Strobl mii_bitbang_sendbits(device_t dev, mii_bitbang_ops_t ops, uint32_t data,
928c1093fcSMarius Strobl int nbits)
938c1093fcSMarius Strobl {
948c1093fcSMarius Strobl int i;
958c1093fcSMarius Strobl uint32_t v;
968c1093fcSMarius Strobl
978c1093fcSMarius Strobl v = MDIRPHY;
988c1093fcSMarius Strobl MWRITE(v);
998c1093fcSMarius Strobl
1008c1093fcSMarius Strobl for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
1018c1093fcSMarius Strobl if (data & i)
1028c1093fcSMarius Strobl v |= MDO;
1038c1093fcSMarius Strobl else
1048c1093fcSMarius Strobl v &= ~MDO;
1058c1093fcSMarius Strobl MWRITE(v);
1068c1093fcSMarius Strobl MWRITE(v | MDC);
1078c1093fcSMarius Strobl MWRITE(v);
1088c1093fcSMarius Strobl }
1098c1093fcSMarius Strobl }
1108c1093fcSMarius Strobl
1118c1093fcSMarius Strobl /*
1128c1093fcSMarius Strobl * mii_bitbang_readreg:
1138c1093fcSMarius Strobl *
1148c1093fcSMarius Strobl * Read a PHY register by bit-bang'ing the MII.
1158c1093fcSMarius Strobl */
1168c1093fcSMarius Strobl int
mii_bitbang_readreg(device_t dev,mii_bitbang_ops_t ops,int phy,int reg)1178c1093fcSMarius Strobl mii_bitbang_readreg(device_t dev, mii_bitbang_ops_t ops, int phy, int reg)
1188c1093fcSMarius Strobl {
1198c1093fcSMarius Strobl int i, error, val;
1208c1093fcSMarius Strobl
1218c1093fcSMarius Strobl mii_bitbang_sync(dev, ops);
1228c1093fcSMarius Strobl
1238c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, MII_COMMAND_START, 2);
1248c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, MII_COMMAND_READ, 2);
1258c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, phy, 5);
1268c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, reg, 5);
1278c1093fcSMarius Strobl
1288c1093fcSMarius Strobl /* Switch direction to PHY->host, without a clock transition. */
1298c1093fcSMarius Strobl MWRITE(MDIRHOST);
1308c1093fcSMarius Strobl
1318c1093fcSMarius Strobl /* Turnaround clock. */
1328c1093fcSMarius Strobl MWRITE(MDIRHOST | MDC);
1338c1093fcSMarius Strobl MWRITE(MDIRHOST);
1348c1093fcSMarius Strobl
1358c1093fcSMarius Strobl /* Check for error. */
1368c1093fcSMarius Strobl error = MREAD & MDI;
1378c1093fcSMarius Strobl
1388c1093fcSMarius Strobl /* Idle clock. */
1398c1093fcSMarius Strobl MWRITE(MDIRHOST | MDC);
1408c1093fcSMarius Strobl MWRITE(MDIRHOST);
1418c1093fcSMarius Strobl
1428c1093fcSMarius Strobl val = 0;
1438c1093fcSMarius Strobl for (i = 0; i < 16; i++) {
1448c1093fcSMarius Strobl val <<= 1;
1458c1093fcSMarius Strobl /* Read data prior to clock low-high transition. */
1468c1093fcSMarius Strobl if (error == 0 && (MREAD & MDI) != 0)
1478c1093fcSMarius Strobl val |= 1;
1488c1093fcSMarius Strobl
1498c1093fcSMarius Strobl MWRITE(MDIRHOST | MDC);
1508c1093fcSMarius Strobl MWRITE(MDIRHOST);
1518c1093fcSMarius Strobl }
1528c1093fcSMarius Strobl
1538c1093fcSMarius Strobl /* Set direction to host->PHY, without a clock transition. */
1548c1093fcSMarius Strobl MWRITE(MDIRPHY);
1558c1093fcSMarius Strobl
1568c1093fcSMarius Strobl return (error != 0 ? 0 : val);
1578c1093fcSMarius Strobl }
1588c1093fcSMarius Strobl
1598c1093fcSMarius Strobl /*
1608c1093fcSMarius Strobl * mii_bitbang_writereg:
1618c1093fcSMarius Strobl *
1628c1093fcSMarius Strobl * Write a PHY register by bit-bang'ing the MII.
1638c1093fcSMarius Strobl */
1648c1093fcSMarius Strobl void
mii_bitbang_writereg(device_t dev,mii_bitbang_ops_t ops,int phy,int reg,int val)1658c1093fcSMarius Strobl mii_bitbang_writereg(device_t dev, mii_bitbang_ops_t ops, int phy, int reg,
1668c1093fcSMarius Strobl int val)
1678c1093fcSMarius Strobl {
1688c1093fcSMarius Strobl
1698c1093fcSMarius Strobl mii_bitbang_sync(dev, ops);
1708c1093fcSMarius Strobl
1718c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, MII_COMMAND_START, 2);
1728c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, MII_COMMAND_WRITE, 2);
1738c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, phy, 5);
1748c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, reg, 5);
1758c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, MII_COMMAND_ACK, 2);
1768c1093fcSMarius Strobl mii_bitbang_sendbits(dev, ops, val, 16);
1778c1093fcSMarius Strobl
1788c1093fcSMarius Strobl MWRITE(MDIRPHY);
1798c1093fcSMarius Strobl }
180