1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/rgephyreg.h> 56 57 #include "miibus_if.h" 58 59 #include <machine/bus.h> 60 #include <pci/if_rlreg.h> 61 62 static int rgephy_probe(device_t); 63 static int rgephy_attach(device_t); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 int mii_model; 68 int mii_revision; 69 }; 70 71 static device_method_t rgephy_methods[] = { 72 /* device interface */ 73 DEVMETHOD(device_probe, rgephy_probe), 74 DEVMETHOD(device_attach, rgephy_attach), 75 DEVMETHOD(device_detach, mii_phy_detach), 76 DEVMETHOD(device_shutdown, bus_generic_shutdown), 77 { 0, 0 } 78 }; 79 80 static devclass_t rgephy_devclass; 81 82 static driver_t rgephy_driver = { 83 "rgephy", 84 rgephy_methods, 85 sizeof(struct rgephy_softc) 86 }; 87 88 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 89 90 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 91 static void rgephy_status(struct mii_softc *); 92 static int rgephy_mii_phy_auto(struct mii_softc *, int); 93 static void rgephy_reset(struct mii_softc *); 94 static void rgephy_loop(struct mii_softc *); 95 static void rgephy_load_dspcode(struct mii_softc *); 96 97 static const struct mii_phydesc rgephys[] = { 98 MII_PHY_DESC(xxREALTEK, RTL8169S), 99 MII_PHY_END 100 }; 101 102 static int 103 rgephy_probe(device_t dev) 104 { 105 106 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 107 } 108 109 static int 110 rgephy_attach(device_t dev) 111 { 112 struct rgephy_softc *rsc; 113 struct mii_softc *sc; 114 struct mii_attach_args *ma; 115 struct mii_data *mii; 116 117 rsc = device_get_softc(dev); 118 sc = &rsc->mii_sc; 119 ma = device_get_ivars(dev); 120 sc->mii_dev = device_get_parent(dev); 121 mii = ma->mii_data; 122 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 123 124 sc->mii_flags = miibus_get_flags(dev); 125 sc->mii_inst = mii->mii_instance++; 126 sc->mii_phy = ma->mii_phyno; 127 sc->mii_service = rgephy_service; 128 sc->mii_pdata = mii; 129 130 rsc->mii_model = MII_MODEL(ma->mii_id2); 131 rsc->mii_revision = MII_REV(ma->mii_id2); 132 133 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 134 135 #if 0 136 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 137 MII_MEDIA_100_TX); 138 #endif 139 140 /* RTL8169S do not report auto-sense; add manually. */ 141 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 142 ma->mii_capmask; 143 if (sc->mii_capabilities & BMSR_EXTSTAT) 144 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 145 device_printf(dev, " "); 146 mii_phy_add_media(sc); 147 printf("\n"); 148 #undef ADD 149 /* 150 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 151 * manual configuration, which is used to work around issues with 152 * certain setups by default, should not be triggered as it may in 153 * turn cause harm in some edge cases. 154 */ 155 mii->mii_media.ifm_mask |= IFM_FLAG0; 156 157 rgephy_reset(sc); 158 MIIBUS_MEDIAINIT(sc->mii_dev); 159 return (0); 160 } 161 162 static int 163 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 164 { 165 struct rgephy_softc *rsc; 166 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 167 int reg, speed, gig, anar; 168 169 rsc = (struct rgephy_softc *)sc; 170 171 switch (cmd) { 172 case MII_POLLSTAT: 173 break; 174 175 case MII_MEDIACHG: 176 /* 177 * If the interface is not up, don't do anything. 178 */ 179 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 180 break; 181 182 rgephy_reset(sc); /* XXX hardware bug work-around */ 183 184 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 185 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 186 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 187 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 188 189 switch (IFM_SUBTYPE(ife->ifm_media)) { 190 case IFM_AUTO: 191 #ifdef foo 192 /* 193 * If we're already in auto mode, just return. 194 */ 195 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 196 return (0); 197 #endif 198 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 199 break; 200 case IFM_1000_T: 201 speed = RGEPHY_S1000; 202 goto setit; 203 case IFM_100_TX: 204 speed = RGEPHY_S100; 205 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 206 goto setit; 207 case IFM_10_T: 208 speed = RGEPHY_S10; 209 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 210 setit: 211 if ((ife->ifm_media & IFM_FLOW) != 0 && 212 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 213 return (EINVAL); 214 215 if ((ife->ifm_media & IFM_FDX) != 0) { 216 speed |= RGEPHY_BMCR_FDX; 217 gig = RGEPHY_1000CTL_AFD; 218 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 219 if ((ife->ifm_media & IFM_FLOW) != 0 || 220 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 221 anar |= 222 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 223 } else { 224 gig = RGEPHY_1000CTL_AHD; 225 anar &= 226 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 227 } 228 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 229 gig |= RGEPHY_1000CTL_MSE; 230 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 231 gig |= RGEPHY_1000CTL_MSC; 232 } else { 233 gig = 0; 234 anar &= ~RGEPHY_ANAR_ASP; 235 } 236 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 237 speed |= 238 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 239 rgephy_loop(sc); 240 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 241 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 242 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 243 break; 244 case IFM_NONE: 245 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 246 break; 247 default: 248 return (EINVAL); 249 } 250 break; 251 252 case MII_TICK: 253 /* 254 * Is the interface even up? 255 */ 256 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 257 return (0); 258 259 /* 260 * Only used for autonegotiation. 261 */ 262 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 263 sc->mii_ticks = 0; 264 break; 265 } 266 267 /* 268 * Check to see if we have link. If we do, we don't 269 * need to restart the autonegotiation process. 270 */ 271 if (rsc->mii_revision >= 2) { 272 /* RTL8211B(L) */ 273 reg = PHY_READ(sc, RGEPHY_MII_SSR); 274 if (reg & RGEPHY_SSR_LINK) { 275 sc->mii_ticks = 0; 276 break; 277 } 278 } else { 279 reg = PHY_READ(sc, RL_GMEDIASTAT); 280 if (reg & RL_GMEDIASTAT_LINK) { 281 sc->mii_ticks = 0; 282 break; 283 } 284 } 285 286 /* Announce link loss right after it happens. */ 287 if (sc->mii_ticks++ == 0) 288 break; 289 290 /* Only retry autonegotiation every mii_anegticks seconds. */ 291 if (sc->mii_ticks <= sc->mii_anegticks) 292 return (0); 293 294 sc->mii_ticks = 0; 295 rgephy_mii_phy_auto(sc, ife->ifm_media); 296 break; 297 } 298 299 /* Update the media status. */ 300 rgephy_status(sc); 301 302 /* 303 * Callback if something changed. Note that we need to poke 304 * the DSP on the RealTek PHYs if the media changes. 305 * 306 */ 307 if (sc->mii_media_active != mii->mii_media_active || 308 sc->mii_media_status != mii->mii_media_status || 309 cmd == MII_MEDIACHG) { 310 rgephy_load_dspcode(sc); 311 } 312 mii_phy_update(sc, cmd); 313 return (0); 314 } 315 316 static void 317 rgephy_status(struct mii_softc *sc) 318 { 319 struct rgephy_softc *rsc; 320 struct mii_data *mii = sc->mii_pdata; 321 int bmsr, bmcr; 322 uint16_t ssr; 323 324 mii->mii_media_status = IFM_AVALID; 325 mii->mii_media_active = IFM_ETHER; 326 327 rsc = (struct rgephy_softc *)sc; 328 if (rsc->mii_revision >= 2) { 329 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 330 if (ssr & RGEPHY_SSR_LINK) 331 mii->mii_media_status |= IFM_ACTIVE; 332 } else { 333 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 334 if (bmsr & RL_GMEDIASTAT_LINK) 335 mii->mii_media_status |= IFM_ACTIVE; 336 } 337 338 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 339 340 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 341 if (bmcr & RGEPHY_BMCR_ISO) { 342 mii->mii_media_active |= IFM_NONE; 343 mii->mii_media_status = 0; 344 return; 345 } 346 347 if (bmcr & RGEPHY_BMCR_LOOP) 348 mii->mii_media_active |= IFM_LOOP; 349 350 if (bmcr & RGEPHY_BMCR_AUTOEN) { 351 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 352 /* Erg, still trying, I guess... */ 353 mii->mii_media_active |= IFM_NONE; 354 return; 355 } 356 } 357 358 if (rsc->mii_revision >= 2) { 359 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 360 switch (ssr & RGEPHY_SSR_SPD_MASK) { 361 case RGEPHY_SSR_S1000: 362 mii->mii_media_active |= IFM_1000_T; 363 break; 364 case RGEPHY_SSR_S100: 365 mii->mii_media_active |= IFM_100_TX; 366 break; 367 case RGEPHY_SSR_S10: 368 mii->mii_media_active |= IFM_10_T; 369 break; 370 default: 371 mii->mii_media_active |= IFM_NONE; 372 break; 373 } 374 if (ssr & RGEPHY_SSR_FDX) 375 mii->mii_media_active |= IFM_FDX; 376 else 377 mii->mii_media_active |= IFM_HDX; 378 } else { 379 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 380 if (bmsr & RL_GMEDIASTAT_1000MBPS) 381 mii->mii_media_active |= IFM_1000_T; 382 else if (bmsr & RL_GMEDIASTAT_100MBPS) 383 mii->mii_media_active |= IFM_100_TX; 384 else if (bmsr & RL_GMEDIASTAT_10MBPS) 385 mii->mii_media_active |= IFM_10_T; 386 else 387 mii->mii_media_active |= IFM_NONE; 388 if (bmsr & RL_GMEDIASTAT_FDX) 389 mii->mii_media_active |= IFM_FDX; 390 else 391 mii->mii_media_active |= IFM_HDX; 392 } 393 394 if ((mii->mii_media_active & IFM_FDX) != 0) 395 mii->mii_media_active |= mii_phy_flowstatus(sc); 396 397 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 398 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 399 mii->mii_media_active |= IFM_ETH_MASTER; 400 } 401 402 static int 403 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 404 { 405 int anar; 406 407 rgephy_loop(sc); 408 rgephy_reset(sc); 409 410 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 411 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 412 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 413 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 414 DELAY(1000); 415 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 416 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 417 DELAY(1000); 418 PHY_WRITE(sc, RGEPHY_MII_BMCR, 419 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 420 DELAY(100); 421 422 return (EJUSTRETURN); 423 } 424 425 static void 426 rgephy_loop(struct mii_softc *sc) 427 { 428 struct rgephy_softc *rsc; 429 int i; 430 431 rsc = (struct rgephy_softc *)sc; 432 if (rsc->mii_revision < 2) { 433 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 434 DELAY(1000); 435 } 436 437 for (i = 0; i < 15000; i++) { 438 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 439 #if 0 440 device_printf(sc->mii_dev, "looped %d\n", i); 441 #endif 442 break; 443 } 444 DELAY(10); 445 } 446 } 447 448 #define PHY_SETBIT(x, y, z) \ 449 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 450 #define PHY_CLRBIT(x, y, z) \ 451 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 452 453 /* 454 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 455 * existing revisions of the 8169S/8110S chips need to be tuned in 456 * order to reliably negotiate a 1000Mbps link. This is only needed 457 * for rev 0 and rev 1 of the PHY. Later versions work without 458 * any fixups. 459 */ 460 static void 461 rgephy_load_dspcode(struct mii_softc *sc) 462 { 463 struct rgephy_softc *rsc; 464 int val; 465 466 rsc = (struct rgephy_softc *)sc; 467 if (rsc->mii_revision >= 2) 468 return; 469 470 PHY_WRITE(sc, 31, 0x0001); 471 PHY_WRITE(sc, 21, 0x1000); 472 PHY_WRITE(sc, 24, 0x65C7); 473 PHY_CLRBIT(sc, 4, 0x0800); 474 val = PHY_READ(sc, 4) & 0xFFF; 475 PHY_WRITE(sc, 4, val); 476 PHY_WRITE(sc, 3, 0x00A1); 477 PHY_WRITE(sc, 2, 0x0008); 478 PHY_WRITE(sc, 1, 0x1020); 479 PHY_WRITE(sc, 0, 0x1000); 480 PHY_SETBIT(sc, 4, 0x0800); 481 PHY_CLRBIT(sc, 4, 0x0800); 482 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 483 PHY_WRITE(sc, 4, val); 484 PHY_WRITE(sc, 3, 0xFF41); 485 PHY_WRITE(sc, 2, 0xDE60); 486 PHY_WRITE(sc, 1, 0x0140); 487 PHY_WRITE(sc, 0, 0x0077); 488 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 489 PHY_WRITE(sc, 4, val); 490 PHY_WRITE(sc, 3, 0xDF01); 491 PHY_WRITE(sc, 2, 0xDF20); 492 PHY_WRITE(sc, 1, 0xFF95); 493 PHY_WRITE(sc, 0, 0xFA00); 494 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 495 PHY_WRITE(sc, 4, val); 496 PHY_WRITE(sc, 3, 0xFF41); 497 PHY_WRITE(sc, 2, 0xDE20); 498 PHY_WRITE(sc, 1, 0x0140); 499 PHY_WRITE(sc, 0, 0x00BB); 500 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 501 PHY_WRITE(sc, 4, val); 502 PHY_WRITE(sc, 3, 0xDF01); 503 PHY_WRITE(sc, 2, 0xDF20); 504 PHY_WRITE(sc, 1, 0xFF95); 505 PHY_WRITE(sc, 0, 0xBF00); 506 PHY_SETBIT(sc, 4, 0x0800); 507 PHY_CLRBIT(sc, 4, 0x0800); 508 PHY_WRITE(sc, 31, 0x0000); 509 510 DELAY(40); 511 } 512 513 static void 514 rgephy_reset(struct mii_softc *sc) 515 { 516 struct rgephy_softc *rsc; 517 uint16_t ssr; 518 519 rsc = (struct rgephy_softc *)sc; 520 if (rsc->mii_revision == 3) { 521 /* RTL8211C(L) */ 522 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 523 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 524 ssr &= ~RGEPHY_SSR_ALDPS; 525 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 526 } 527 } 528 529 mii_phy_reset(sc); 530 DELAY(1000); 531 rgephy_load_dspcode(sc); 532 } 533